4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, Version 1.0 only
6 * (the "License"). You may not use this file except in compliance
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
27 #pragma ident "%Z%%M% %I% %E% SMI"
29 #include <sys/types.h>
30 #include <sys/sysmacros.h>
31 #include <sys/isa_defs.h>
40 #include <dt_grammar.h>
41 #include <dt_parser.h>
42 #include <dt_provider.h>
44 static void dt_cg_node(dt_node_t *, dt_irlist_t *, dt_regset_t *);
47 dt_cg_node_alloc(uint_t label, dif_instr_t instr)
49 dt_irnode_t *dip = malloc(sizeof (dt_irnode_t));
52 longjmp(yypcb->pcb_jmpbuf, EDT_NOMEM);
54 dip->di_label = label;
55 dip->di_instr = instr;
56 dip->di_extern = NULL;
63 * Code generator wrapper function for ctf_member_info. If we are given a
64 * reference to a forward declaration tag, search the entire type space for
65 * the actual definition and then call ctf_member_info on the result.
68 dt_cg_membinfo(ctf_file_t *fp, ctf_id_t type, const char *s, ctf_membinfo_t *mp)
70 while (ctf_type_kind(fp, type) == CTF_K_FORWARD) {
71 char n[DT_TYPE_NAMELEN];
72 dtrace_typeinfo_t dtt;
74 if (ctf_type_name(fp, type, n, sizeof (n)) == NULL ||
75 dt_type_lookup(n, &dtt) == -1 || (
76 dtt.dtt_ctfp == fp && dtt.dtt_type == type))
77 break; /* unable to improve our position */
80 type = ctf_type_resolve(fp, dtt.dtt_type);
83 if (ctf_member_info(fp, type, s, mp) == CTF_ERR)
84 return (NULL); /* ctf_errno is set for us */
90 dt_cg_xsetx(dt_irlist_t *dlp, dt_ident_t *idp, uint_t lbl, int reg, uint64_t x)
92 int flag = idp != NULL ? DT_INT_PRIVATE : DT_INT_SHARED;
93 int intoff = dt_inttab_insert(yypcb->pcb_inttab, x, flag);
94 dif_instr_t instr = DIF_INSTR_SETX((uint_t)intoff, reg);
97 longjmp(yypcb->pcb_jmpbuf, EDT_NOMEM);
99 if (intoff > DIF_INTOFF_MAX)
100 longjmp(yypcb->pcb_jmpbuf, EDT_INT2BIG);
102 dt_irlist_append(dlp, dt_cg_node_alloc(lbl, instr));
105 dlp->dl_last->di_extern = idp;
109 dt_cg_setx(dt_irlist_t *dlp, int reg, uint64_t x)
111 dt_cg_xsetx(dlp, NULL, DT_LBL_NONE, reg, x);
115 * When loading bit-fields, we want to convert a byte count in the range
116 * 1-8 to the closest power of 2 (e.g. 3->4, 5->8, etc). The clp2() function
117 * is a clever implementation from "Hacker's Delight" by Henry Warren, Jr.
134 * Lookup the correct load opcode to use for the specified node and CTF type.
135 * We determine the size and convert it to a 3-bit index. Our lookup table
136 * is constructed to use a 5-bit index, consisting of the 3-bit size 0-7, a
137 * bit for the sign, and a bit for userland address. For example, a 4-byte
138 * signed load from userland would be at the following table index:
139 * user=1 sign=1 size=4 => binary index 11011 = decimal index 27
142 dt_cg_load(dt_node_t *dnp, ctf_file_t *ctfp, ctf_id_t type)
144 static const uint_t ops[] = {
145 DIF_OP_LDUB, DIF_OP_LDUH, 0, DIF_OP_LDUW,
147 DIF_OP_LDSB, DIF_OP_LDSH, 0, DIF_OP_LDSW,
149 DIF_OP_ULDUB, DIF_OP_ULDUH, 0, DIF_OP_ULDUW,
150 0, 0, 0, DIF_OP_ULDX,
151 DIF_OP_ULDSB, DIF_OP_ULDSH, 0, DIF_OP_ULDSW,
152 0, 0, 0, DIF_OP_ULDX,
159 * If we're loading a bit-field, the size of our load is found by
160 * rounding cte_bits up to a byte boundary and then finding the
161 * nearest power of two to this value (see clp2(), above).
163 if ((dnp->dn_flags & DT_NF_BITFIELD) &&
164 ctf_type_encoding(ctfp, type, &e) != CTF_ERR)
165 size = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY);
167 size = ctf_type_size(ctfp, type);
169 if (size < 1 || size > 8 || (size & (size - 1)) != 0) {
170 xyerror(D_UNKNOWN, "internal error -- cg cannot load "
171 "size %ld when passed by value\n", (long)size);
174 size--; /* convert size to 3-bit index */
176 if (dnp->dn_flags & DT_NF_SIGNED)
178 if (dnp->dn_flags & DT_NF_USERLAND)
185 dt_cg_ptrsize(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp,
188 ctf_file_t *ctfp = dnp->dn_ctfp;
196 if ((sreg = dt_regset_alloc(drp)) == -1)
197 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
199 type = ctf_type_resolve(ctfp, dnp->dn_type);
200 kind = ctf_type_kind(ctfp, type);
201 assert(kind == CTF_K_POINTER || kind == CTF_K_ARRAY);
203 if (kind == CTF_K_ARRAY) {
204 if (ctf_array_info(ctfp, type, &r) != 0) {
205 yypcb->pcb_hdl->dt_ctferr = ctf_errno(ctfp);
206 longjmp(yypcb->pcb_jmpbuf, EDT_CTF);
208 type = r.ctr_contents;
210 type = ctf_type_reference(ctfp, type);
212 if ((size = ctf_type_size(ctfp, type)) == 1)
213 return; /* multiply or divide by one can be omitted */
215 dt_cg_setx(dlp, sreg, size);
216 instr = DIF_INSTR_FMT(op, dreg, sreg, dreg);
217 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
218 dt_regset_free(drp, sreg);
222 * If the result of a "." or "->" operation is a bit-field, we use this routine
223 * to generate an epilogue to the load instruction that extracts the value. In
224 * the diagrams below the "ld??" is the load instruction that is generated to
225 * load the containing word that is generating prior to calling this function.
227 * Epilogue for unsigned fields: Epilogue for signed fields:
229 * ldu? [r1], r1 lds? [r1], r1
230 * setx USHIFT, r2 setx 64 - SSHIFT, r2
231 * srl r1, r2, r1 sll r1, r2, r1
232 * setx (1 << bits) - 1, r2 setx 64 - bits, r2
233 * and r1, r2, r1 sra r1, r2, r1
235 * The *SHIFT constants above changes value depending on the endian-ness of our
236 * target architecture. Refer to the comments below for more details.
239 dt_cg_field_get(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp,
240 ctf_file_t *fp, const ctf_membinfo_t *mp)
247 if (ctf_type_encoding(fp, mp->ctm_type, &e) != 0 || e.cte_bits > 64) {
248 xyerror(D_UNKNOWN, "cg: bad field: off %lu type <%ld> "
249 "bits %u\n", mp->ctm_offset, mp->ctm_type, e.cte_bits);
252 assert(dnp->dn_op == DT_TOK_PTR || dnp->dn_op == DT_TOK_DOT);
253 r1 = dnp->dn_left->dn_reg;
255 if ((r2 = dt_regset_alloc(drp)) == -1)
256 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
259 * On little-endian architectures, ctm_offset counts from the right so
260 * ctm_offset % NBBY itself is the amount we want to shift right to
261 * move the value bits to the little end of the register to mask them.
262 * On big-endian architectures, ctm_offset counts from the left so we
263 * must subtract (ctm_offset % NBBY + cte_bits) from the size in bits
264 * we used for the load. The size of our load in turn is found by
265 * rounding cte_bits up to a byte boundary and then finding the
266 * nearest power of two to this value (see clp2(), above). These
267 * properties are used to compute shift as USHIFT or SSHIFT, below.
269 if (dnp->dn_flags & DT_NF_SIGNED) {
270 #if BYTE_ORDER == _BIG_ENDIAN
271 shift = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY) * NBBY -
272 mp->ctm_offset % NBBY;
274 shift = mp->ctm_offset % NBBY + e.cte_bits;
276 dt_cg_setx(dlp, r2, 64 - shift);
277 instr = DIF_INSTR_FMT(DIF_OP_SLL, r1, r2, r1);
278 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
280 dt_cg_setx(dlp, r2, 64 - e.cte_bits);
281 instr = DIF_INSTR_FMT(DIF_OP_SRA, r1, r2, r1);
282 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
284 #if BYTE_ORDER == _BIG_ENDIAN
285 shift = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY) * NBBY -
286 (mp->ctm_offset % NBBY + e.cte_bits);
288 shift = mp->ctm_offset % NBBY;
290 dt_cg_setx(dlp, r2, shift);
291 instr = DIF_INSTR_FMT(DIF_OP_SRL, r1, r2, r1);
292 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
294 dt_cg_setx(dlp, r2, (1ULL << e.cte_bits) - 1);
295 instr = DIF_INSTR_FMT(DIF_OP_AND, r1, r2, r1);
296 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
299 dt_regset_free(drp, r2);
303 * If the destination of a store operation is a bit-field, we use this routine
304 * to generate a prologue to the store instruction that loads the surrounding
305 * bits, clears the destination field, and ORs in the new value of the field.
306 * In the diagram below the "st?" is the store instruction that is generated to
307 * store the containing word that is generating after calling this function.
309 * ld [dst->dn_reg], r1
310 * setx ~(((1 << cte_bits) - 1) << (ctm_offset % NBBY)), r2
313 * setx (1 << cte_bits) - 1, r2
314 * and src->dn_reg, r2, r2
315 * setx ctm_offset % NBBY, r3
319 * st? r1, [dst->dn_reg]
321 * This routine allocates a new register to hold the value to be stored and
322 * returns it. The caller is responsible for freeing this register later.
325 dt_cg_field_set(dt_node_t *src, dt_irlist_t *dlp,
326 dt_regset_t *drp, dt_node_t *dst)
328 uint64_t cmask, fmask, shift;
334 ctf_file_t *fp, *ofp;
337 assert(dst->dn_op == DT_TOK_PTR || dst->dn_op == DT_TOK_DOT);
338 assert(dst->dn_right->dn_kind == DT_NODE_IDENT);
340 fp = dst->dn_left->dn_ctfp;
341 type = ctf_type_resolve(fp, dst->dn_left->dn_type);
343 if (dst->dn_op == DT_TOK_PTR) {
344 type = ctf_type_reference(fp, type);
345 type = ctf_type_resolve(fp, type);
348 if ((fp = dt_cg_membinfo(ofp = fp, type,
349 dst->dn_right->dn_string, &m)) == NULL) {
350 yypcb->pcb_hdl->dt_ctferr = ctf_errno(ofp);
351 longjmp(yypcb->pcb_jmpbuf, EDT_CTF);
354 if (ctf_type_encoding(fp, m.ctm_type, &e) != 0 || e.cte_bits > 64) {
355 xyerror(D_UNKNOWN, "cg: bad field: off %lu type <%ld> "
356 "bits %u\n", m.ctm_offset, m.ctm_type, e.cte_bits);
359 if ((r1 = dt_regset_alloc(drp)) == -1 ||
360 (r2 = dt_regset_alloc(drp)) == -1 ||
361 (r3 = dt_regset_alloc(drp)) == -1)
362 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
365 * Compute shifts and masks. We need to compute "shift" as the amount
366 * we need to shift left to position our field in the containing word.
367 * Refer to the comments in dt_cg_field_get(), above, for more info.
368 * We then compute fmask as the mask that truncates the value in the
369 * input register to width cte_bits, and cmask as the mask used to
370 * pass through the containing bits and zero the field bits.
372 #if BYTE_ORDER == _BIG_ENDIAN
373 shift = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY) * NBBY -
374 (m.ctm_offset % NBBY + e.cte_bits);
376 shift = m.ctm_offset % NBBY;
378 fmask = (1ULL << e.cte_bits) - 1;
379 cmask = ~(fmask << shift);
381 instr = DIF_INSTR_LOAD(
382 dt_cg_load(dst, fp, m.ctm_type), dst->dn_reg, r1);
383 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
385 dt_cg_setx(dlp, r2, cmask);
386 instr = DIF_INSTR_FMT(DIF_OP_AND, r1, r2, r1);
387 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
389 dt_cg_setx(dlp, r2, fmask);
390 instr = DIF_INSTR_FMT(DIF_OP_AND, src->dn_reg, r2, r2);
391 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
393 dt_cg_setx(dlp, r3, shift);
394 instr = DIF_INSTR_FMT(DIF_OP_SLL, r2, r3, r2);
395 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
397 instr = DIF_INSTR_FMT(DIF_OP_OR, r1, r2, r1);
398 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
400 dt_regset_free(drp, r3);
401 dt_regset_free(drp, r2);
407 dt_cg_store(dt_node_t *src, dt_irlist_t *dlp, dt_regset_t *drp, dt_node_t *dst)
415 * If we're loading a bit-field, the size of our store is found by
416 * rounding dst's cte_bits up to a byte boundary and then finding the
417 * nearest power of two to this value (see clp2(), above).
419 if ((dst->dn_flags & DT_NF_BITFIELD) &&
420 ctf_type_encoding(dst->dn_ctfp, dst->dn_type, &e) != CTF_ERR)
421 size = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY);
423 size = dt_node_type_size(src);
425 if (src->dn_flags & DT_NF_REF) {
426 if ((reg = dt_regset_alloc(drp)) == -1)
427 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
428 dt_cg_setx(dlp, reg, size);
429 instr = DIF_INSTR_COPYS(src->dn_reg, reg, dst->dn_reg);
430 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
431 dt_regset_free(drp, reg);
433 if (dst->dn_flags & DT_NF_BITFIELD)
434 reg = dt_cg_field_set(src, dlp, drp, dst);
440 instr = DIF_INSTR_STORE(DIF_OP_STB, reg, dst->dn_reg);
443 instr = DIF_INSTR_STORE(DIF_OP_STH, reg, dst->dn_reg);
446 instr = DIF_INSTR_STORE(DIF_OP_STW, reg, dst->dn_reg);
449 instr = DIF_INSTR_STORE(DIF_OP_STX, reg, dst->dn_reg);
452 xyerror(D_UNKNOWN, "internal error -- cg cannot store "
453 "size %lu when passed by value\n", (ulong_t)size);
455 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
457 if (dst->dn_flags & DT_NF_BITFIELD)
458 dt_regset_free(drp, reg);
463 * Generate code for a typecast or for argument promotion from the type of the
464 * actual to the type of the formal. We need to generate code for casts when
465 * a scalar type is being narrowed or changing signed-ness. We first shift the
466 * desired bits high (losing excess bits if narrowing) and then shift them down
467 * using logical shift (unsigned result) or arithmetic shift (signed result).
470 dt_cg_typecast(const dt_node_t *src, const dt_node_t *dst,
471 dt_irlist_t *dlp, dt_regset_t *drp)
473 size_t srcsize = dt_node_type_size(src);
474 size_t dstsize = dt_node_type_size(dst);
479 if (dt_node_is_scalar(dst) && (dstsize < srcsize ||
480 (src->dn_flags & DT_NF_SIGNED) ^ (dst->dn_flags & DT_NF_SIGNED))) {
481 if ((reg = dt_regset_alloc(drp)) == -1)
482 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
484 if (dstsize < srcsize)
485 n = sizeof (uint64_t) * NBBY - dstsize * NBBY;
487 n = sizeof (uint64_t) * NBBY - srcsize * NBBY;
489 dt_cg_setx(dlp, reg, n);
491 instr = DIF_INSTR_FMT(DIF_OP_SLL,
492 src->dn_reg, reg, dst->dn_reg);
493 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
495 instr = DIF_INSTR_FMT((dst->dn_flags & DT_NF_SIGNED) ?
496 DIF_OP_SRA : DIF_OP_SRL, dst->dn_reg, reg, dst->dn_reg);
498 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
499 dt_regset_free(drp, reg);
504 * Generate code to push the specified argument list on to the tuple stack.
505 * We use this routine for handling subroutine calls and associative arrays.
506 * We must first generate code for all subexpressions before loading the stack
507 * because any subexpression could itself require the use of the tuple stack.
508 * This holds a number of registers equal to the number of arguments, but this
509 * is not a huge problem because the number of arguments can't exceed the
510 * number of tuple register stack elements anyway. At most one extra register
511 * is required (either by dt_cg_typecast() or for dtdt_size, below). This
512 * implies that a DIF implementation should offer a number of general purpose
513 * registers at least one greater than the number of tuple registers.
516 dt_cg_arglist(dt_ident_t *idp, dt_node_t *args,
517 dt_irlist_t *dlp, dt_regset_t *drp)
519 const dt_idsig_t *isp = idp->di_data;
523 for (dnp = args; dnp != NULL; dnp = dnp->dn_list)
524 dt_cg_node(dnp, dlp, drp);
526 dt_irlist_append(dlp,
527 dt_cg_node_alloc(DT_LBL_NONE, DIF_INSTR_FLUSHTS));
529 for (dnp = args; dnp != NULL; dnp = dnp->dn_list, i++) {
535 dt_node_diftype(yypcb->pcb_hdl, dnp, &t);
537 isp->dis_args[i].dn_reg = dnp->dn_reg; /* re-use register */
538 dt_cg_typecast(dnp, &isp->dis_args[i], dlp, drp);
539 isp->dis_args[i].dn_reg = -1;
541 if (t.dtdt_flags & DIF_TF_BYREF)
546 if (t.dtdt_size != 0) {
547 if ((reg = dt_regset_alloc(drp)) == -1)
548 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
549 dt_cg_setx(dlp, reg, t.dtdt_size);
553 instr = DIF_INSTR_PUSHTS(op, t.dtdt_kind, reg, dnp->dn_reg);
554 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
555 dt_regset_free(drp, dnp->dn_reg);
557 if (reg != DIF_REG_R0)
558 dt_regset_free(drp, reg);
561 if (i > yypcb->pcb_hdl->dt_conf.dtc_diftupregs)
562 longjmp(yypcb->pcb_jmpbuf, EDT_NOTUPREG);
566 dt_cg_arithmetic_op(dt_node_t *dnp, dt_irlist_t *dlp,
567 dt_regset_t *drp, uint_t op)
569 int is_ptr_op = (dnp->dn_op == DT_TOK_ADD || dnp->dn_op == DT_TOK_SUB ||
570 dnp->dn_op == DT_TOK_ADD_EQ || dnp->dn_op == DT_TOK_SUB_EQ);
572 int lp_is_ptr = dt_node_is_pointer(dnp->dn_left);
573 int rp_is_ptr = dt_node_is_pointer(dnp->dn_right);
577 if (lp_is_ptr && rp_is_ptr) {
578 assert(dnp->dn_op == DT_TOK_SUB);
582 dt_cg_node(dnp->dn_left, dlp, drp);
583 if (is_ptr_op && rp_is_ptr)
584 dt_cg_ptrsize(dnp, dlp, drp, DIF_OP_MUL, dnp->dn_left->dn_reg);
586 dt_cg_node(dnp->dn_right, dlp, drp);
587 if (is_ptr_op && lp_is_ptr)
588 dt_cg_ptrsize(dnp, dlp, drp, DIF_OP_MUL, dnp->dn_right->dn_reg);
590 instr = DIF_INSTR_FMT(op, dnp->dn_left->dn_reg,
591 dnp->dn_right->dn_reg, dnp->dn_left->dn_reg);
593 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
594 dt_regset_free(drp, dnp->dn_right->dn_reg);
595 dnp->dn_reg = dnp->dn_left->dn_reg;
597 if (lp_is_ptr && rp_is_ptr)
598 dt_cg_ptrsize(dnp->dn_right,
599 dlp, drp, DIF_OP_UDIV, dnp->dn_reg);
603 dt_cg_stvar(const dt_ident_t *idp)
605 static const uint_t aops[] = { DIF_OP_STGAA, DIF_OP_STTAA, DIF_OP_NOP };
606 static const uint_t sops[] = { DIF_OP_STGS, DIF_OP_STTS, DIF_OP_STLS };
608 uint_t i = (((idp->di_flags & DT_IDFLG_LOCAL) != 0) << 1) |
609 ((idp->di_flags & DT_IDFLG_TLS) != 0);
611 return (idp->di_kind == DT_IDENT_ARRAY ? aops[i] : sops[i]);
615 dt_cg_prearith_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp, uint_t op)
617 ctf_file_t *ctfp = dnp->dn_ctfp;
623 if (dt_node_is_pointer(dnp)) {
624 type = ctf_type_resolve(ctfp, dnp->dn_type);
625 assert(ctf_type_kind(ctfp, type) == CTF_K_POINTER);
626 size = ctf_type_size(ctfp, ctf_type_reference(ctfp, type));
629 dt_cg_node(dnp->dn_child, dlp, drp);
630 dnp->dn_reg = dnp->dn_child->dn_reg;
632 if ((reg = dt_regset_alloc(drp)) == -1)
633 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
635 dt_cg_setx(dlp, reg, size);
637 instr = DIF_INSTR_FMT(op, dnp->dn_reg, reg, dnp->dn_reg);
638 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
639 dt_regset_free(drp, reg);
642 * If we are modifying a variable, generate an stv instruction from
643 * the variable specified by the identifier. If we are storing to a
644 * memory address, generate code again for the left-hand side using
645 * DT_NF_REF to get the address, and then generate a store to it.
646 * In both paths, we store the value in dnp->dn_reg (the new value).
648 if (dnp->dn_child->dn_kind == DT_NODE_VAR) {
649 dt_ident_t *idp = dt_ident_resolve(dnp->dn_child->dn_ident);
651 idp->di_flags |= DT_IDFLG_DIFW;
652 instr = DIF_INSTR_STV(dt_cg_stvar(idp),
653 idp->di_id, dnp->dn_reg);
654 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
656 uint_t rbit = dnp->dn_child->dn_flags & DT_NF_REF;
658 assert(dnp->dn_child->dn_flags & DT_NF_WRITABLE);
659 assert(dnp->dn_child->dn_flags & DT_NF_LVALUE);
661 dnp->dn_child->dn_flags |= DT_NF_REF; /* force pass-by-ref */
662 dt_cg_node(dnp->dn_child, dlp, drp);
664 dt_cg_store(dnp, dlp, drp, dnp->dn_child);
665 dt_regset_free(drp, dnp->dn_child->dn_reg);
667 dnp->dn_left->dn_flags &= ~DT_NF_REF;
668 dnp->dn_left->dn_flags |= rbit;
673 dt_cg_postarith_op(dt_node_t *dnp, dt_irlist_t *dlp,
674 dt_regset_t *drp, uint_t op)
676 ctf_file_t *ctfp = dnp->dn_ctfp;
682 if (dt_node_is_pointer(dnp)) {
683 type = ctf_type_resolve(ctfp, dnp->dn_type);
684 assert(ctf_type_kind(ctfp, type) == CTF_K_POINTER);
685 size = ctf_type_size(ctfp, ctf_type_reference(ctfp, type));
688 dt_cg_node(dnp->dn_child, dlp, drp);
689 dnp->dn_reg = dnp->dn_child->dn_reg;
691 if ((nreg = dt_regset_alloc(drp)) == -1)
692 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
694 dt_cg_setx(dlp, nreg, size);
695 instr = DIF_INSTR_FMT(op, dnp->dn_reg, nreg, nreg);
696 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
699 * If we are modifying a variable, generate an stv instruction from
700 * the variable specified by the identifier. If we are storing to a
701 * memory address, generate code again for the left-hand side using
702 * DT_NF_REF to get the address, and then generate a store to it.
703 * In both paths, we store the value from 'nreg' (the new value).
705 if (dnp->dn_child->dn_kind == DT_NODE_VAR) {
706 dt_ident_t *idp = dt_ident_resolve(dnp->dn_child->dn_ident);
708 idp->di_flags |= DT_IDFLG_DIFW;
709 instr = DIF_INSTR_STV(dt_cg_stvar(idp), idp->di_id, nreg);
710 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
712 uint_t rbit = dnp->dn_child->dn_flags & DT_NF_REF;
713 int oreg = dnp->dn_reg;
715 assert(dnp->dn_child->dn_flags & DT_NF_WRITABLE);
716 assert(dnp->dn_child->dn_flags & DT_NF_LVALUE);
718 dnp->dn_child->dn_flags |= DT_NF_REF; /* force pass-by-ref */
719 dt_cg_node(dnp->dn_child, dlp, drp);
722 dt_cg_store(dnp, dlp, drp, dnp->dn_child);
725 dt_regset_free(drp, dnp->dn_child->dn_reg);
726 dnp->dn_left->dn_flags &= ~DT_NF_REF;
727 dnp->dn_left->dn_flags |= rbit;
730 dt_regset_free(drp, nreg);
734 * Determine if we should perform signed or unsigned comparison for an OP2.
735 * If both operands are of arithmetic type, perform the usual arithmetic
736 * conversions to determine the common real type for comparison [ISOC 6.5.8.3].
739 dt_cg_compare_signed(dt_node_t *dnp)
743 if (dt_node_is_string(dnp->dn_left) ||
744 dt_node_is_string(dnp->dn_right))
745 return (1); /* strings always compare signed */
746 else if (!dt_node_is_arith(dnp->dn_left) ||
747 !dt_node_is_arith(dnp->dn_right))
748 return (0); /* non-arithmetic types always compare unsigned */
750 bzero(&dn, sizeof (dn));
751 dt_node_promote(dnp->dn_left, dnp->dn_right, &dn);
752 return (dn.dn_flags & DT_NF_SIGNED);
756 dt_cg_compare_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp, uint_t op)
758 uint_t lbl_true = dt_irlist_label(dlp);
759 uint_t lbl_post = dt_irlist_label(dlp);
764 dt_cg_node(dnp->dn_left, dlp, drp);
765 dt_cg_node(dnp->dn_right, dlp, drp);
767 if (dt_node_is_string(dnp->dn_left) || dt_node_is_string(dnp->dn_right))
772 instr = DIF_INSTR_CMP(opc, dnp->dn_left->dn_reg, dnp->dn_right->dn_reg);
773 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
774 dt_regset_free(drp, dnp->dn_right->dn_reg);
775 dnp->dn_reg = dnp->dn_left->dn_reg;
777 instr = DIF_INSTR_BRANCH(op, lbl_true);
778 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
780 instr = DIF_INSTR_MOV(DIF_REG_R0, dnp->dn_reg);
781 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
783 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
784 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
786 dt_cg_xsetx(dlp, NULL, lbl_true, dnp->dn_reg, 1);
787 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
791 * Code generation for the ternary op requires some trickery with the assembler
792 * in order to conserve registers. We generate code for dn_expr and dn_left
793 * and free their registers so they do not have be consumed across codegen for
794 * dn_right. We insert a dummy MOV at the end of dn_left into the destination
795 * register, which is not yet known because we haven't done dn_right yet, and
796 * save the pointer to this instruction node. We then generate code for
797 * dn_right and use its register as our output. Finally, we reach back and
798 * patch the instruction for dn_left to move its output into this register.
801 dt_cg_ternary_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
803 uint_t lbl_false = dt_irlist_label(dlp);
804 uint_t lbl_post = dt_irlist_label(dlp);
809 dt_cg_node(dnp->dn_expr, dlp, drp);
810 instr = DIF_INSTR_TST(dnp->dn_expr->dn_reg);
811 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
812 dt_regset_free(drp, dnp->dn_expr->dn_reg);
814 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_false);
815 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
817 dt_cg_node(dnp->dn_left, dlp, drp);
818 instr = DIF_INSTR_MOV(dnp->dn_left->dn_reg, DIF_REG_R0);
819 dip = dt_cg_node_alloc(DT_LBL_NONE, instr); /* save dip for below */
820 dt_irlist_append(dlp, dip);
821 dt_regset_free(drp, dnp->dn_left->dn_reg);
823 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
824 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
826 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_false, DIF_INSTR_NOP));
827 dt_cg_node(dnp->dn_right, dlp, drp);
828 dnp->dn_reg = dnp->dn_right->dn_reg;
831 * Now that dn_reg is assigned, reach back and patch the correct MOV
832 * instruction into the tail of dn_left. We know dn_reg was unused
833 * at that point because otherwise dn_right couldn't have allocated it.
835 dip->di_instr = DIF_INSTR_MOV(dnp->dn_left->dn_reg, dnp->dn_reg);
836 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
840 dt_cg_logical_and(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
842 uint_t lbl_false = dt_irlist_label(dlp);
843 uint_t lbl_post = dt_irlist_label(dlp);
847 dt_cg_node(dnp->dn_left, dlp, drp);
848 instr = DIF_INSTR_TST(dnp->dn_left->dn_reg);
849 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
850 dt_regset_free(drp, dnp->dn_left->dn_reg);
852 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_false);
853 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
855 dt_cg_node(dnp->dn_right, dlp, drp);
856 instr = DIF_INSTR_TST(dnp->dn_right->dn_reg);
857 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
858 dnp->dn_reg = dnp->dn_right->dn_reg;
860 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_false);
861 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
863 dt_cg_setx(dlp, dnp->dn_reg, 1);
865 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
866 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
868 instr = DIF_INSTR_MOV(DIF_REG_R0, dnp->dn_reg);
869 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_false, instr));
871 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
875 dt_cg_logical_xor(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
877 uint_t lbl_next = dt_irlist_label(dlp);
878 uint_t lbl_tail = dt_irlist_label(dlp);
882 dt_cg_node(dnp->dn_left, dlp, drp);
883 instr = DIF_INSTR_TST(dnp->dn_left->dn_reg);
884 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
886 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_next);
887 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
888 dt_cg_setx(dlp, dnp->dn_left->dn_reg, 1);
890 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_next, DIF_INSTR_NOP));
891 dt_cg_node(dnp->dn_right, dlp, drp);
893 instr = DIF_INSTR_TST(dnp->dn_right->dn_reg);
894 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
896 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_tail);
897 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
898 dt_cg_setx(dlp, dnp->dn_right->dn_reg, 1);
900 instr = DIF_INSTR_FMT(DIF_OP_XOR, dnp->dn_left->dn_reg,
901 dnp->dn_right->dn_reg, dnp->dn_left->dn_reg);
903 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_tail, instr));
905 dt_regset_free(drp, dnp->dn_right->dn_reg);
906 dnp->dn_reg = dnp->dn_left->dn_reg;
910 dt_cg_logical_or(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
912 uint_t lbl_true = dt_irlist_label(dlp);
913 uint_t lbl_false = dt_irlist_label(dlp);
914 uint_t lbl_post = dt_irlist_label(dlp);
918 dt_cg_node(dnp->dn_left, dlp, drp);
919 instr = DIF_INSTR_TST(dnp->dn_left->dn_reg);
920 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
921 dt_regset_free(drp, dnp->dn_left->dn_reg);
923 instr = DIF_INSTR_BRANCH(DIF_OP_BNE, lbl_true);
924 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
926 dt_cg_node(dnp->dn_right, dlp, drp);
927 instr = DIF_INSTR_TST(dnp->dn_right->dn_reg);
928 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
929 dnp->dn_reg = dnp->dn_right->dn_reg;
931 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_false);
932 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
934 dt_cg_xsetx(dlp, NULL, lbl_true, dnp->dn_reg, 1);
936 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
937 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
939 instr = DIF_INSTR_MOV(DIF_REG_R0, dnp->dn_reg);
940 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_false, instr));
942 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
946 dt_cg_logical_neg(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
948 uint_t lbl_zero = dt_irlist_label(dlp);
949 uint_t lbl_post = dt_irlist_label(dlp);
953 dt_cg_node(dnp->dn_child, dlp, drp);
954 dnp->dn_reg = dnp->dn_child->dn_reg;
956 instr = DIF_INSTR_TST(dnp->dn_reg);
957 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
959 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_zero);
960 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
962 instr = DIF_INSTR_MOV(DIF_REG_R0, dnp->dn_reg);
963 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
965 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
966 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
968 dt_cg_xsetx(dlp, NULL, lbl_zero, dnp->dn_reg, 1);
969 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
973 dt_cg_asgn_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
979 * If we are performing a structure assignment of a translated type,
980 * we must instantiate all members and create a snapshot of the object
981 * in scratch space. We allocs a chunk of memory, generate code for
982 * each member, and then set dnp->dn_reg to the scratch object address.
984 if ((idp = dt_node_resolve(dnp->dn_right, DT_IDENT_XLSOU)) != NULL) {
986 dt_xlator_t *dxp = idp->di_data;
987 dt_node_t *mnp, dn, mn;
991 * Create two fake dt_node_t's representing operator "." and a
992 * right-hand identifier child node. These will be repeatedly
993 * modified according to each instantiated member so that we
994 * can pass them to dt_cg_store() and effect a member store.
996 bzero(&dn, sizeof (dt_node_t));
997 dn.dn_kind = DT_NODE_OP2;
998 dn.dn_op = DT_TOK_DOT;
1002 bzero(&mn, sizeof (dt_node_t));
1003 mn.dn_kind = DT_NODE_IDENT;
1004 mn.dn_op = DT_TOK_IDENT;
1007 * Allocate a register for our scratch data pointer. First we
1008 * set it to the size of our data structure, and then replace
1009 * it with the result of an allocs of the specified size.
1011 if ((r1 = dt_regset_alloc(drp)) == -1)
1012 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1015 ctf_type_size(dxp->dx_dst_ctfp, dxp->dx_dst_base));
1017 instr = DIF_INSTR_ALLOCS(r1, r1);
1018 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1021 * When dt_cg_asgn_op() is called, we have already generated
1022 * code for dnp->dn_right, which is the translator input. We
1023 * now associate this register with the translator's input
1024 * identifier so it can be referenced during our member loop.
1026 dxp->dx_ident->di_flags |= DT_IDFLG_CGREG;
1027 dxp->dx_ident->di_id = dnp->dn_right->dn_reg;
1029 for (mnp = dxp->dx_members; mnp != NULL; mnp = mnp->dn_list) {
1031 * Generate code for the translator member expression,
1032 * and then cast the result to the member type.
1034 dt_cg_node(mnp->dn_membexpr, dlp, drp);
1035 mnp->dn_reg = mnp->dn_membexpr->dn_reg;
1036 dt_cg_typecast(mnp->dn_membexpr, mnp, dlp, drp);
1039 * Ask CTF for the offset of the member so we can store
1040 * to the appropriate offset. This call has already
1041 * been done once by the parser, so it should succeed.
1043 if (ctf_member_info(dxp->dx_dst_ctfp, dxp->dx_dst_base,
1044 mnp->dn_membname, &ctm) == CTF_ERR) {
1045 yypcb->pcb_hdl->dt_ctferr =
1046 ctf_errno(dxp->dx_dst_ctfp);
1047 longjmp(yypcb->pcb_jmpbuf, EDT_CTF);
1051 * If the destination member is at offset 0, store the
1052 * result directly to r1 (the scratch buffer address).
1053 * Otherwise allocate another temporary for the offset
1054 * and add r1 to it before storing the result.
1056 if (ctm.ctm_offset != 0) {
1057 if ((r2 = dt_regset_alloc(drp)) == -1)
1058 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1061 * Add the member offset rounded down to the
1062 * nearest byte. If the offset was not aligned
1063 * on a byte boundary, this member is a bit-
1064 * field and dt_cg_store() will handle masking.
1066 dt_cg_setx(dlp, r2, ctm.ctm_offset / NBBY);
1067 instr = DIF_INSTR_FMT(DIF_OP_ADD, r1, r2, r2);
1068 dt_irlist_append(dlp,
1069 dt_cg_node_alloc(DT_LBL_NONE, instr));
1071 dt_node_type_propagate(mnp, &dn);
1072 dn.dn_right->dn_string = mnp->dn_membname;
1075 dt_cg_store(mnp, dlp, drp, &dn);
1076 dt_regset_free(drp, r2);
1079 dt_node_type_propagate(mnp, &dn);
1080 dn.dn_right->dn_string = mnp->dn_membname;
1083 dt_cg_store(mnp, dlp, drp, &dn);
1086 dt_regset_free(drp, mnp->dn_reg);
1089 dxp->dx_ident->di_flags &= ~DT_IDFLG_CGREG;
1090 dxp->dx_ident->di_id = 0;
1092 if (dnp->dn_right->dn_reg != -1)
1093 dt_regset_free(drp, dnp->dn_right->dn_reg);
1095 assert(dnp->dn_reg == dnp->dn_right->dn_reg);
1100 * If we are storing to a variable, generate an stv instruction from
1101 * the variable specified by the identifier. If we are storing to a
1102 * memory address, generate code again for the left-hand side using
1103 * DT_NF_REF to get the address, and then generate a store to it.
1104 * In both paths, we assume dnp->dn_reg already has the new value.
1106 if (dnp->dn_left->dn_kind == DT_NODE_VAR) {
1107 idp = dt_ident_resolve(dnp->dn_left->dn_ident);
1109 if (idp->di_kind == DT_IDENT_ARRAY)
1110 dt_cg_arglist(idp, dnp->dn_left->dn_args, dlp, drp);
1112 idp->di_flags |= DT_IDFLG_DIFW;
1113 instr = DIF_INSTR_STV(dt_cg_stvar(idp),
1114 idp->di_id, dnp->dn_reg);
1115 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1117 uint_t rbit = dnp->dn_left->dn_flags & DT_NF_REF;
1119 assert(dnp->dn_left->dn_flags & DT_NF_WRITABLE);
1120 assert(dnp->dn_left->dn_flags & DT_NF_LVALUE);
1122 dnp->dn_left->dn_flags |= DT_NF_REF; /* force pass-by-ref */
1124 dt_cg_node(dnp->dn_left, dlp, drp);
1125 dt_cg_store(dnp, dlp, drp, dnp->dn_left);
1126 dt_regset_free(drp, dnp->dn_left->dn_reg);
1128 dnp->dn_left->dn_flags &= ~DT_NF_REF;
1129 dnp->dn_left->dn_flags |= rbit;
1134 dt_cg_assoc_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
1139 assert(dnp->dn_kind == DT_NODE_VAR);
1140 assert(!(dnp->dn_ident->di_flags & DT_IDFLG_LOCAL));
1141 assert(dnp->dn_args != NULL);
1143 dt_cg_arglist(dnp->dn_ident, dnp->dn_args, dlp, drp);
1145 if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
1146 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1148 if (dnp->dn_ident->di_flags & DT_IDFLG_TLS)
1153 dnp->dn_ident->di_flags |= DT_IDFLG_DIFR;
1154 instr = DIF_INSTR_LDV(op, dnp->dn_ident->di_id, dnp->dn_reg);
1155 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1158 * If the associative array is a pass-by-reference type, then we are
1159 * loading its value as a pointer to either load or store through it.
1160 * The array element in question may not have been faulted in yet, in
1161 * which case DIF_OP_LD*AA will return zero. We append an epilogue
1162 * of instructions similar to the following:
1164 * ld?aa id, %r1 ! base ld?aa instruction above
1165 * tst %r1 ! start of epilogue
1172 * label: < rest of code >
1174 * The idea is that we allocs a zero-filled chunk of scratch space and
1175 * do a DIF_OP_ST*AA to fault in and initialize the array element, and
1176 * then reload it to get the faulted-in address of the new variable
1177 * storage. This isn't cheap, but pass-by-ref associative array values
1178 * are (thus far) uncommon and the allocs cost only occurs once. If
1179 * this path becomes important to DTrace users, we can improve things
1180 * by adding a new DIF opcode to fault in associative array elements.
1182 if (dnp->dn_flags & DT_NF_REF) {
1183 uint_t stvop = op == DIF_OP_LDTAA ? DIF_OP_STTAA : DIF_OP_STGAA;
1184 uint_t label = dt_irlist_label(dlp);
1186 instr = DIF_INSTR_TST(dnp->dn_reg);
1187 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1189 instr = DIF_INSTR_BRANCH(DIF_OP_BNE, label);
1190 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1192 dt_cg_setx(dlp, dnp->dn_reg, dt_node_type_size(dnp));
1193 instr = DIF_INSTR_ALLOCS(dnp->dn_reg, dnp->dn_reg);
1194 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1196 dnp->dn_ident->di_flags |= DT_IDFLG_DIFW;
1197 instr = DIF_INSTR_STV(stvop, dnp->dn_ident->di_id, dnp->dn_reg);
1198 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1200 instr = DIF_INSTR_LDV(op, dnp->dn_ident->di_id, dnp->dn_reg);
1201 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1203 dt_irlist_append(dlp, dt_cg_node_alloc(label, DIF_INSTR_NOP));
1208 dt_cg_array_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
1210 dt_probe_t *prp = yypcb->pcb_probe;
1211 uintmax_t saved = dnp->dn_args->dn_value;
1212 dt_ident_t *idp = dnp->dn_ident;
1219 assert(dnp->dn_kind == DT_NODE_VAR);
1220 assert(!(idp->di_flags & DT_IDFLG_LOCAL));
1222 assert(dnp->dn_args->dn_kind == DT_NODE_INT);
1223 assert(dnp->dn_args->dn_list == NULL);
1226 * If this is a reference in the args[] array, temporarily modify the
1227 * array index according to the static argument mapping (if any),
1228 * unless the argument reference is provided by a dynamic translator.
1229 * If we're using a dynamic translator for args[], then just set dn_reg
1230 * to an invalid reg and return: DIF_OP_XLARG will fetch the arg later.
1232 if (idp->di_id == DIF_VAR_ARGS) {
1233 if ((idp->di_kind == DT_IDENT_XLPTR ||
1234 idp->di_kind == DT_IDENT_XLSOU) &&
1235 dt_xlator_dynamic(idp->di_data)) {
1239 dnp->dn_args->dn_value = prp->pr_mapping[saved];
1242 dt_cg_node(dnp->dn_args, dlp, drp);
1243 dnp->dn_args->dn_value = saved;
1245 dnp->dn_reg = dnp->dn_args->dn_reg;
1247 if (idp->di_flags & DT_IDFLG_TLS)
1252 idp->di_flags |= DT_IDFLG_DIFR;
1254 instr = DIF_INSTR_LDA(op, idp->di_id,
1255 dnp->dn_args->dn_reg, dnp->dn_reg);
1257 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1260 * If this is a reference to the args[] array, we need to take the
1261 * additional step of explicitly eliminating any bits larger than the
1262 * type size: the DIF interpreter in the kernel will always give us
1263 * the raw (64-bit) argument value, and any bits larger than the type
1264 * size may be junk. As a practical matter, this arises only on 64-bit
1265 * architectures and only when the argument index is larger than the
1266 * number of arguments passed directly to DTrace: if a 8-, 16- or
1267 * 32-bit argument must be retrieved from the stack, it is possible
1268 * (and it some cases, likely) that the upper bits will be garbage.
1270 if (idp->di_id != DIF_VAR_ARGS || !dt_node_is_scalar(dnp))
1273 if ((size = dt_node_type_size(dnp)) == sizeof (uint64_t))
1276 if ((reg = dt_regset_alloc(drp)) == -1)
1277 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1279 assert(size < sizeof (uint64_t));
1280 n = sizeof (uint64_t) * NBBY - size * NBBY;
1282 dt_cg_setx(dlp, reg, n);
1284 instr = DIF_INSTR_FMT(DIF_OP_SLL, dnp->dn_reg, reg, dnp->dn_reg);
1285 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1287 instr = DIF_INSTR_FMT((dnp->dn_flags & DT_NF_SIGNED) ?
1288 DIF_OP_SRA : DIF_OP_SRL, dnp->dn_reg, reg, dnp->dn_reg);
1290 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1291 dt_regset_free(drp, reg);
1295 * Generate code for an inlined variable reference. Inlines can be used to
1296 * define either scalar or associative array substitutions. For scalars, we
1297 * simply generate code for the parse tree saved in the identifier's din_root,
1298 * and then cast the resulting expression to the inline's declaration type.
1299 * For arrays, we take the input parameter subtrees from dnp->dn_args and
1300 * temporarily store them in the din_root of each din_argv[i] identifier,
1301 * which are themselves inlines and were set up for us by the parser. The
1302 * result is that any reference to the inlined parameter inside the top-level
1303 * din_root will turn into a recursive call to dt_cg_inline() for a scalar
1304 * inline whose din_root will refer to the subtree pointed to by the argument.
1307 dt_cg_inline(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
1309 dt_ident_t *idp = dnp->dn_ident;
1310 dt_idnode_t *inp = idp->di_iarg;
1316 assert(idp->di_flags & DT_IDFLG_INLINE);
1317 assert(idp->di_ops == &dt_idops_inline);
1319 if (idp->di_kind == DT_IDENT_ARRAY) {
1320 for (i = 0, pnp = dnp->dn_args;
1321 pnp != NULL; pnp = pnp->dn_list, i++) {
1322 if (inp->din_argv[i] != NULL) {
1323 pinp = inp->din_argv[i]->di_iarg;
1324 pinp->din_root = pnp;
1329 dt_cg_node(inp->din_root, dlp, drp);
1330 dnp->dn_reg = inp->din_root->dn_reg;
1331 dt_cg_typecast(inp->din_root, dnp, dlp, drp);
1333 if (idp->di_kind == DT_IDENT_ARRAY) {
1334 for (i = 0; i < inp->din_argc; i++) {
1335 pinp = inp->din_argv[i]->di_iarg;
1336 pinp->din_root = NULL;
1342 dt_cg_func_typeref(dtrace_hdl_t *dtp, dt_node_t *dnp)
1344 dtrace_typeinfo_t dtt;
1345 dt_node_t *addr = dnp->dn_args;
1346 dt_node_t *nelm = addr->dn_list;
1347 dt_node_t *strp = nelm->dn_list;
1348 dt_node_t *typs = strp->dn_list;
1349 char buf[DT_TYPE_NAMELEN];
1352 ctf_type_name(addr->dn_ctfp, addr->dn_type, buf, sizeof (buf));
1355 * XXX Hack alert! XXX
1356 * The prototype has two dummy args that we munge to represent
1357 * the type string and the type size.
1359 * Yes, I hear your grumble, but it works for now. We'll come
1360 * up with a more elegant implementation later. :-)
1362 free(strp->dn_string);
1364 if ((p = strchr(buf, '*')) != NULL)
1367 strp->dn_string = strdup(buf);
1369 if (dtrace_lookup_by_type(dtp, DTRACE_OBJ_EVERY, buf, &dtt) < 0)
1372 typs->dn_value = ctf_type_size(dtt.dtt_ctfp, dtt.dtt_type);
1376 dt_cg_node(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
1378 ctf_file_t *ctfp = dnp->dn_ctfp;
1389 switch (dnp->dn_op) {
1391 dt_cg_node(dnp->dn_left, dlp, drp);
1392 dt_regset_free(drp, dnp->dn_left->dn_reg);
1393 dt_cg_node(dnp->dn_right, dlp, drp);
1394 dnp->dn_reg = dnp->dn_right->dn_reg;
1398 dt_cg_node(dnp->dn_right, dlp, drp);
1399 dnp->dn_reg = dnp->dn_right->dn_reg;
1400 dt_cg_asgn_op(dnp, dlp, drp);
1404 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_ADD);
1405 dt_cg_asgn_op(dnp, dlp, drp);
1409 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_SUB);
1410 dt_cg_asgn_op(dnp, dlp, drp);
1414 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_MUL);
1415 dt_cg_asgn_op(dnp, dlp, drp);
1419 dt_cg_arithmetic_op(dnp, dlp, drp,
1420 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SDIV : DIF_OP_UDIV);
1421 dt_cg_asgn_op(dnp, dlp, drp);
1425 dt_cg_arithmetic_op(dnp, dlp, drp,
1426 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SREM : DIF_OP_UREM);
1427 dt_cg_asgn_op(dnp, dlp, drp);
1431 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_AND);
1432 dt_cg_asgn_op(dnp, dlp, drp);
1436 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_XOR);
1437 dt_cg_asgn_op(dnp, dlp, drp);
1441 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_OR);
1442 dt_cg_asgn_op(dnp, dlp, drp);
1446 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_SLL);
1447 dt_cg_asgn_op(dnp, dlp, drp);
1451 dt_cg_arithmetic_op(dnp, dlp, drp,
1452 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SRA : DIF_OP_SRL);
1453 dt_cg_asgn_op(dnp, dlp, drp);
1456 case DT_TOK_QUESTION:
1457 dt_cg_ternary_op(dnp, dlp, drp);
1461 dt_cg_logical_or(dnp, dlp, drp);
1465 dt_cg_logical_xor(dnp, dlp, drp);
1469 dt_cg_logical_and(dnp, dlp, drp);
1473 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_OR);
1477 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_XOR);
1481 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_AND);
1485 dt_cg_compare_op(dnp, dlp, drp, DIF_OP_BE);
1489 dt_cg_compare_op(dnp, dlp, drp, DIF_OP_BNE);
1493 dt_cg_compare_op(dnp, dlp, drp,
1494 dt_cg_compare_signed(dnp) ? DIF_OP_BL : DIF_OP_BLU);
1498 dt_cg_compare_op(dnp, dlp, drp,
1499 dt_cg_compare_signed(dnp) ? DIF_OP_BLE : DIF_OP_BLEU);
1503 dt_cg_compare_op(dnp, dlp, drp,
1504 dt_cg_compare_signed(dnp) ? DIF_OP_BG : DIF_OP_BGU);
1508 dt_cg_compare_op(dnp, dlp, drp,
1509 dt_cg_compare_signed(dnp) ? DIF_OP_BGE : DIF_OP_BGEU);
1513 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_SLL);
1517 dt_cg_arithmetic_op(dnp, dlp, drp,
1518 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SRA : DIF_OP_SRL);
1522 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_ADD);
1526 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_SUB);
1530 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_MUL);
1534 dt_cg_arithmetic_op(dnp, dlp, drp,
1535 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SDIV : DIF_OP_UDIV);
1539 dt_cg_arithmetic_op(dnp, dlp, drp,
1540 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SREM : DIF_OP_UREM);
1544 dt_cg_logical_neg(dnp, dlp, drp);
1548 dt_cg_node(dnp->dn_child, dlp, drp);
1549 dnp->dn_reg = dnp->dn_child->dn_reg;
1550 instr = DIF_INSTR_NOT(dnp->dn_reg, dnp->dn_reg);
1551 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1555 dt_cg_prearith_op(dnp, dlp, drp, DIF_OP_ADD);
1558 case DT_TOK_POSTINC:
1559 dt_cg_postarith_op(dnp, dlp, drp, DIF_OP_ADD);
1563 dt_cg_prearith_op(dnp, dlp, drp, DIF_OP_SUB);
1566 case DT_TOK_POSTDEC:
1567 dt_cg_postarith_op(dnp, dlp, drp, DIF_OP_SUB);
1571 dt_cg_node(dnp->dn_child, dlp, drp);
1572 dnp->dn_reg = dnp->dn_child->dn_reg;
1576 dt_cg_node(dnp->dn_child, dlp, drp);
1577 dnp->dn_reg = dnp->dn_child->dn_reg;
1579 instr = DIF_INSTR_FMT(DIF_OP_SUB, DIF_REG_R0,
1580 dnp->dn_reg, dnp->dn_reg);
1582 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1586 dt_cg_node(dnp->dn_child, dlp, drp);
1587 dnp->dn_reg = dnp->dn_child->dn_reg;
1589 if (!(dnp->dn_flags & DT_NF_REF)) {
1590 uint_t ubit = dnp->dn_flags & DT_NF_USERLAND;
1593 * Save and restore DT_NF_USERLAND across dt_cg_load():
1594 * we need the sign bit from dnp and the user bit from
1595 * dnp->dn_child in order to get the proper opcode.
1598 (dnp->dn_child->dn_flags & DT_NF_USERLAND);
1600 instr = DIF_INSTR_LOAD(dt_cg_load(dnp, ctfp,
1601 dnp->dn_type), dnp->dn_reg, dnp->dn_reg);
1603 dnp->dn_flags &= ~DT_NF_USERLAND;
1604 dnp->dn_flags |= ubit;
1606 dt_irlist_append(dlp,
1607 dt_cg_node_alloc(DT_LBL_NONE, instr));
1611 case DT_TOK_ADDROF: {
1612 uint_t rbit = dnp->dn_child->dn_flags & DT_NF_REF;
1614 dnp->dn_child->dn_flags |= DT_NF_REF; /* force pass-by-ref */
1615 dt_cg_node(dnp->dn_child, dlp, drp);
1616 dnp->dn_reg = dnp->dn_child->dn_reg;
1618 dnp->dn_child->dn_flags &= ~DT_NF_REF;
1619 dnp->dn_child->dn_flags |= rbit;
1623 case DT_TOK_SIZEOF: {
1624 size_t size = dt_node_sizeof(dnp->dn_child);
1626 if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
1627 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1630 dt_cg_setx(dlp, dnp->dn_reg, size);
1634 case DT_TOK_STRINGOF:
1635 dt_cg_node(dnp->dn_child, dlp, drp);
1636 dnp->dn_reg = dnp->dn_child->dn_reg;
1641 * An xlate operator appears in either an XLATOR, indicating a
1642 * reference to a dynamic translator, or an OP2, indicating
1643 * use of the xlate operator in the user's program. For the
1644 * dynamic case, generate an xlate opcode with a reference to
1645 * the corresponding member, pre-computed for us in dn_members.
1647 if (dnp->dn_kind == DT_NODE_XLATOR) {
1648 dt_xlator_t *dxp = dnp->dn_xlator;
1650 assert(dxp->dx_ident->di_flags & DT_IDFLG_CGREG);
1651 assert(dxp->dx_ident->di_id != 0);
1653 if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
1654 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1656 if (dxp->dx_arg == -1) {
1657 instr = DIF_INSTR_MOV(
1658 dxp->dx_ident->di_id, dnp->dn_reg);
1659 dt_irlist_append(dlp,
1660 dt_cg_node_alloc(DT_LBL_NONE, instr));
1665 instr = DIF_INSTR_XLATE(op, 0, dnp->dn_reg);
1666 dt_irlist_append(dlp,
1667 dt_cg_node_alloc(DT_LBL_NONE, instr));
1669 dlp->dl_last->di_extern = dnp->dn_xmember;
1673 assert(dnp->dn_kind == DT_NODE_OP2);
1674 dt_cg_node(dnp->dn_right, dlp, drp);
1675 dnp->dn_reg = dnp->dn_right->dn_reg;
1679 dt_cg_node(dnp->dn_right, dlp, drp);
1680 dnp->dn_reg = dnp->dn_right->dn_reg;
1681 dt_cg_typecast(dnp->dn_right, dnp, dlp, drp);
1686 assert(dnp->dn_right->dn_kind == DT_NODE_IDENT);
1687 dt_cg_node(dnp->dn_left, dlp, drp);
1690 * If the left-hand side of PTR or DOT is a dynamic variable,
1691 * we expect it to be the output of a D translator. In this
1692 * case, we look up the parse tree corresponding to the member
1693 * that is being accessed and run the code generator over it.
1694 * We then cast the result as if by the assignment operator.
1696 if ((idp = dt_node_resolve(
1697 dnp->dn_left, DT_IDENT_XLSOU)) != NULL ||
1698 (idp = dt_node_resolve(
1699 dnp->dn_left, DT_IDENT_XLPTR)) != NULL) {
1705 mnp = dt_xlator_member(dxp, dnp->dn_right->dn_string);
1706 assert(mnp != NULL);
1708 dxp->dx_ident->di_flags |= DT_IDFLG_CGREG;
1709 dxp->dx_ident->di_id = dnp->dn_left->dn_reg;
1711 dt_cg_node(mnp->dn_membexpr, dlp, drp);
1712 dnp->dn_reg = mnp->dn_membexpr->dn_reg;
1713 dt_cg_typecast(mnp->dn_membexpr, dnp, dlp, drp);
1715 dxp->dx_ident->di_flags &= ~DT_IDFLG_CGREG;
1716 dxp->dx_ident->di_id = 0;
1718 if (dnp->dn_left->dn_reg != -1)
1719 dt_regset_free(drp, dnp->dn_left->dn_reg);
1723 ctfp = dnp->dn_left->dn_ctfp;
1724 type = ctf_type_resolve(ctfp, dnp->dn_left->dn_type);
1726 if (dnp->dn_op == DT_TOK_PTR) {
1727 type = ctf_type_reference(ctfp, type);
1728 type = ctf_type_resolve(ctfp, type);
1731 if ((ctfp = dt_cg_membinfo(octfp = ctfp, type,
1732 dnp->dn_right->dn_string, &m)) == NULL) {
1733 yypcb->pcb_hdl->dt_ctferr = ctf_errno(octfp);
1734 longjmp(yypcb->pcb_jmpbuf, EDT_CTF);
1737 if (m.ctm_offset != 0) {
1738 if ((reg = dt_regset_alloc(drp)) == -1)
1739 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1742 * If the offset is not aligned on a byte boundary, it
1743 * is a bit-field member and we will extract the value
1744 * bits below after we generate the appropriate load.
1746 dt_cg_setx(dlp, reg, m.ctm_offset / NBBY);
1748 instr = DIF_INSTR_FMT(DIF_OP_ADD,
1749 dnp->dn_left->dn_reg, reg, dnp->dn_left->dn_reg);
1751 dt_irlist_append(dlp,
1752 dt_cg_node_alloc(DT_LBL_NONE, instr));
1753 dt_regset_free(drp, reg);
1756 if (!(dnp->dn_flags & DT_NF_REF)) {
1757 uint_t ubit = dnp->dn_flags & DT_NF_USERLAND;
1760 * Save and restore DT_NF_USERLAND across dt_cg_load():
1761 * we need the sign bit from dnp and the user bit from
1762 * dnp->dn_left in order to get the proper opcode.
1765 (dnp->dn_left->dn_flags & DT_NF_USERLAND);
1767 instr = DIF_INSTR_LOAD(dt_cg_load(dnp,
1768 ctfp, m.ctm_type), dnp->dn_left->dn_reg,
1769 dnp->dn_left->dn_reg);
1771 dnp->dn_flags &= ~DT_NF_USERLAND;
1772 dnp->dn_flags |= ubit;
1774 dt_irlist_append(dlp,
1775 dt_cg_node_alloc(DT_LBL_NONE, instr));
1777 if (dnp->dn_flags & DT_NF_BITFIELD)
1778 dt_cg_field_get(dnp, dlp, drp, ctfp, &m);
1781 dnp->dn_reg = dnp->dn_left->dn_reg;
1785 if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
1786 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1788 assert(dnp->dn_kind == DT_NODE_STRING);
1789 stroff = dt_strtab_insert(yypcb->pcb_strtab, dnp->dn_string);
1792 longjmp(yypcb->pcb_jmpbuf, EDT_NOMEM);
1793 if (stroff > DIF_STROFF_MAX)
1794 longjmp(yypcb->pcb_jmpbuf, EDT_STR2BIG);
1796 instr = DIF_INSTR_SETS((ulong_t)stroff, dnp->dn_reg);
1797 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1802 * If the specified identifier is a variable on which we have
1803 * set the code generator register flag, then this variable
1804 * has already had code generated for it and saved in di_id.
1805 * Allocate a new register and copy the existing value to it.
1807 if (dnp->dn_kind == DT_NODE_VAR &&
1808 (dnp->dn_ident->di_flags & DT_IDFLG_CGREG)) {
1809 if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
1810 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1811 instr = DIF_INSTR_MOV(dnp->dn_ident->di_id,
1813 dt_irlist_append(dlp,
1814 dt_cg_node_alloc(DT_LBL_NONE, instr));
1819 * Identifiers can represent function calls, variable refs, or
1820 * symbols. First we check for inlined variables, and handle
1821 * them by generating code for the inline parse tree.
1823 if (dnp->dn_kind == DT_NODE_VAR &&
1824 (dnp->dn_ident->di_flags & DT_IDFLG_INLINE)) {
1825 dt_cg_inline(dnp, dlp, drp);
1829 switch (dnp->dn_kind) {
1830 case DT_NODE_FUNC: {
1831 dtrace_hdl_t *dtp = yypcb->pcb_hdl;
1833 if ((idp = dnp->dn_ident)->di_kind != DT_IDENT_FUNC) {
1834 dnerror(dnp, D_CG_EXPR, "%s %s( ) may not be "
1835 "called from a D expression (D program "
1836 "context required)\n",
1837 dt_idkind_name(idp->di_kind), idp->di_name);
1840 switch (idp->di_id) {
1841 case DIF_SUBR_TYPEREF:
1842 dt_cg_func_typeref(dtp, dnp);
1849 dt_cg_arglist(dnp->dn_ident, dnp->dn_args, dlp, drp);
1851 if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
1852 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1854 instr = DIF_INSTR_CALL(
1855 dnp->dn_ident->di_id, dnp->dn_reg);
1857 dt_irlist_append(dlp,
1858 dt_cg_node_alloc(DT_LBL_NONE, instr));
1864 if (dnp->dn_ident->di_kind == DT_IDENT_XLSOU ||
1865 dnp->dn_ident->di_kind == DT_IDENT_XLPTR) {
1867 * This can only happen if we have translated
1868 * args[]. See dt_idcook_args() for details.
1870 assert(dnp->dn_ident->di_id == DIF_VAR_ARGS);
1871 dt_cg_array_op(dnp, dlp, drp);
1875 if (dnp->dn_ident->di_kind == DT_IDENT_ARRAY) {
1876 if (dnp->dn_ident->di_id > DIF_VAR_ARRAY_MAX)
1877 dt_cg_assoc_op(dnp, dlp, drp);
1879 dt_cg_array_op(dnp, dlp, drp);
1883 if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
1884 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1886 if (dnp->dn_ident->di_flags & DT_IDFLG_LOCAL)
1888 else if (dnp->dn_ident->di_flags & DT_IDFLG_TLS)
1893 dnp->dn_ident->di_flags |= DT_IDFLG_DIFR;
1895 instr = DIF_INSTR_LDV(op,
1896 dnp->dn_ident->di_id, dnp->dn_reg);
1898 dt_irlist_append(dlp,
1899 dt_cg_node_alloc(DT_LBL_NONE, instr));
1903 dtrace_hdl_t *dtp = yypcb->pcb_hdl;
1904 dtrace_syminfo_t *sip = dnp->dn_ident->di_data;
1907 if (dtrace_lookup_by_name(dtp,
1908 sip->dts_object, sip->dts_name, &sym, NULL) == -1) {
1909 xyerror(D_UNKNOWN, "cg failed for symbol %s`%s:"
1910 " %s\n", sip->dts_object, sip->dts_name,
1911 dtrace_errmsg(dtp, dtrace_errno(dtp)));
1914 if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
1915 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1917 dt_cg_xsetx(dlp, dnp->dn_ident,
1918 DT_LBL_NONE, dnp->dn_reg, sym.st_value);
1920 if (!(dnp->dn_flags & DT_NF_REF)) {
1921 instr = DIF_INSTR_LOAD(dt_cg_load(dnp, ctfp,
1922 dnp->dn_type), dnp->dn_reg, dnp->dn_reg);
1923 dt_irlist_append(dlp,
1924 dt_cg_node_alloc(DT_LBL_NONE, instr));
1930 xyerror(D_UNKNOWN, "internal error -- node type %u is "
1931 "not valid for an identifier\n", dnp->dn_kind);
1936 if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
1937 longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
1939 dt_cg_setx(dlp, dnp->dn_reg, dnp->dn_value);
1943 xyerror(D_UNKNOWN, "internal error -- token type %u is not a "
1944 "valid D compilation token\n", dnp->dn_op);
1949 dt_cg(dt_pcb_t *pcb, dt_node_t *dnp)
1954 if (pcb->pcb_regs == NULL && (pcb->pcb_regs =
1955 dt_regset_create(pcb->pcb_hdl->dt_conf.dtc_difintregs)) == NULL)
1956 longjmp(pcb->pcb_jmpbuf, EDT_NOMEM);
1958 dt_regset_reset(pcb->pcb_regs);
1959 (void) dt_regset_alloc(pcb->pcb_regs); /* allocate %r0 */
1961 if (pcb->pcb_inttab != NULL)
1962 dt_inttab_destroy(pcb->pcb_inttab);
1964 if ((pcb->pcb_inttab = dt_inttab_create(yypcb->pcb_hdl)) == NULL)
1965 longjmp(pcb->pcb_jmpbuf, EDT_NOMEM);
1967 if (pcb->pcb_strtab != NULL)
1968 dt_strtab_destroy(pcb->pcb_strtab);
1970 if ((pcb->pcb_strtab = dt_strtab_create(BUFSIZ)) == NULL)
1971 longjmp(pcb->pcb_jmpbuf, EDT_NOMEM);
1973 dt_irlist_destroy(&pcb->pcb_ir);
1974 dt_irlist_create(&pcb->pcb_ir);
1976 assert(pcb->pcb_dret == NULL);
1977 pcb->pcb_dret = dnp;
1979 if (dt_node_is_dynamic(dnp)) {
1980 dnerror(dnp, D_CG_DYN, "expression cannot evaluate to result "
1981 "of dynamic type\n");
1985 * If we're generating code for a translator body, assign the input
1986 * parameter to the first available register (i.e. caller passes %r1).
1988 if (dnp->dn_kind == DT_NODE_MEMBER) {
1989 dxp = dnp->dn_membxlator;
1990 dnp = dnp->dn_membexpr;
1992 dxp->dx_ident->di_flags |= DT_IDFLG_CGREG;
1993 dxp->dx_ident->di_id = dt_regset_alloc(pcb->pcb_regs);
1996 dt_cg_node(dnp, &pcb->pcb_ir, pcb->pcb_regs);
1997 instr = DIF_INSTR_RET(dnp->dn_reg);
1998 dt_regset_free(pcb->pcb_regs, dnp->dn_reg);
1999 dt_irlist_append(&pcb->pcb_ir, dt_cg_node_alloc(DT_LBL_NONE, instr));
2001 if (dnp->dn_kind == DT_NODE_MEMBER) {
2002 dt_regset_free(pcb->pcb_regs, dxp->dx_ident->di_id);
2003 dxp->dx_ident->di_id = 0;
2004 dxp->dx_ident->di_flags &= ~DT_IDFLG_CGREG;