1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget.is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget.isV9()">;
34 // HasNoV9 - This predicate is true when the target doesn't have V9
35 // instructions. Use of this is just a hack for the isel not having proper
36 // costs for V8 instructions that are more expensive than their V9 ones.
37 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
39 // HasVIS - This is true when the target processor has VIS extensions.
40 def HasVIS : Predicate<"Subtarget.isVIS()">;
42 // HasHardQuad - This is true when the target processor supports quad floating
43 // point instructions.
44 def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">;
46 // UseDeprecatedInsts - This predicate is true when the target processor is a
47 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
48 // to use when appropriate. In either of these cases, the instruction selector
49 // will pick deprecated instructions.
50 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
52 //===----------------------------------------------------------------------===//
53 // Instruction Pattern Stuff
54 //===----------------------------------------------------------------------===//
56 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
58 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
60 def LO10 : SDNodeXForm<imm, [{
61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
65 def HI22 : SDNodeXForm<imm, [{
66 // Transformation function: shift the immediate value down into the low bits.
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
70 def SETHIimm : PatLeaf<(imm), [{
71 return isShiftedUInt<22, 10>(N->getZExtValue());
75 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
76 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
79 def SparcMEMrrAsmOperand : AsmOperandClass {
81 let ParserMethod = "parseMEMOperand";
84 def SparcMEMriAsmOperand : AsmOperandClass {
86 let ParserMethod = "parseMEMOperand";
89 def MEMrr : Operand<iPTR> {
90 let PrintMethod = "printMemOperand";
91 let MIOperandInfo = (ops ptr_rc, ptr_rc);
92 let ParserMatchClass = SparcMEMrrAsmOperand;
94 def MEMri : Operand<iPTR> {
95 let PrintMethod = "printMemOperand";
96 let MIOperandInfo = (ops ptr_rc, i32imm);
97 let ParserMatchClass = SparcMEMriAsmOperand;
100 def TLSSym : Operand<iPTR>;
102 // Branch targets have OtherVT type.
103 def brtarget : Operand<OtherVT> {
104 let EncoderMethod = "getBranchTargetOpValue";
107 def calltarget : Operand<i32> {
108 let EncoderMethod = "getCallTargetOpValue";
111 // Operand for printing out a condition code.
112 let PrintMethod = "printCCOperand" in
113 def CCOp : Operand<i32>;
116 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
118 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
120 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
122 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
124 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
126 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
128 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
130 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
133 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
135 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
137 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
138 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
139 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
140 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
141 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
143 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
144 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
146 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
147 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
148 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
149 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
151 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
152 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
153 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
155 // These are target-independent nodes, but have target-specific formats.
156 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
157 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
160 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
161 [SDNPHasChain, SDNPOutGlue]>;
162 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
165 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
166 def call : SDNode<"SPISD::CALL", SDT_SPCall,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
170 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
171 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
172 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
174 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
175 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
177 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
178 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
179 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
183 def getPCX : Operand<iPTR> {
184 let PrintMethod = "printGetPCX";
187 //===----------------------------------------------------------------------===//
188 // SPARC Flag Conditions
189 //===----------------------------------------------------------------------===//
191 // Note that these values must be kept in sync with the CCOp::CondCode enum
193 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
194 def ICC_NE : ICC_VAL< 9>; // Not Equal
195 def ICC_E : ICC_VAL< 1>; // Equal
196 def ICC_G : ICC_VAL<10>; // Greater
197 def ICC_LE : ICC_VAL< 2>; // Less or Equal
198 def ICC_GE : ICC_VAL<11>; // Greater or Equal
199 def ICC_L : ICC_VAL< 3>; // Less
200 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
201 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
202 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
203 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
204 def ICC_POS : ICC_VAL<14>; // Positive
205 def ICC_NEG : ICC_VAL< 6>; // Negative
206 def ICC_VC : ICC_VAL<15>; // Overflow Clear
207 def ICC_VS : ICC_VAL< 7>; // Overflow Set
209 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
210 def FCC_U : FCC_VAL<23>; // Unordered
211 def FCC_G : FCC_VAL<22>; // Greater
212 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
213 def FCC_L : FCC_VAL<20>; // Less
214 def FCC_UL : FCC_VAL<19>; // Unordered or Less
215 def FCC_LG : FCC_VAL<18>; // Less or Greater
216 def FCC_NE : FCC_VAL<17>; // Not Equal
217 def FCC_E : FCC_VAL<25>; // Equal
218 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
219 def FCC_GE : FCC_VAL<25>; // Greater or Equal
220 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
221 def FCC_LE : FCC_VAL<27>; // Less or Equal
222 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
223 def FCC_O : FCC_VAL<29>; // Ordered
225 //===----------------------------------------------------------------------===//
226 // Instruction Class Templates
227 //===----------------------------------------------------------------------===//
229 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
230 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
231 RegisterClass RC, ValueType Ty, Operand immOp> {
232 def rr : F3_1<2, Op3Val,
233 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
234 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
235 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
236 def ri : F3_2<2, Op3Val,
237 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
238 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
239 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
242 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
244 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
245 def rr : F3_1<2, Op3Val,
246 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
247 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
248 def ri : F3_2<2, Op3Val,
249 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
250 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
253 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
254 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
255 RegisterClass RC, ValueType Ty> {
256 def rr : F3_1<3, Op3Val,
257 (outs RC:$dst), (ins MEMrr:$addr),
258 !strconcat(OpcStr, " [$addr], $dst"),
259 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
260 def ri : F3_2<3, Op3Val,
261 (outs RC:$dst), (ins MEMri:$addr),
262 !strconcat(OpcStr, " [$addr], $dst"),
263 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
266 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
267 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
268 RegisterClass RC, ValueType Ty> {
269 def rr : F3_1<3, Op3Val,
270 (outs), (ins MEMrr:$addr, RC:$rd),
271 !strconcat(OpcStr, " $rd, [$addr]"),
272 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
273 def ri : F3_2<3, Op3Val,
274 (outs), (ins MEMri:$addr, RC:$rd),
275 !strconcat(OpcStr, " $rd, [$addr]"),
276 [(OpNode Ty:$rd, ADDRri:$addr)]>;
279 //===----------------------------------------------------------------------===//
281 //===----------------------------------------------------------------------===//
283 // Pseudo instructions.
284 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
285 : InstSP<outs, ins, asmstr, pattern> {
286 let isCodeGenOnly = 1;
292 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
295 let Defs = [O6], Uses = [O6] in {
296 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
297 "!ADJCALLSTACKDOWN $amt",
298 [(callseq_start timm:$amt)]>;
299 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
300 "!ADJCALLSTACKUP $amt1",
301 [(callseq_end timm:$amt1, timm:$amt2)]>;
304 let hasSideEffects = 1, mayStore = 1 in {
305 let rd = 0, rs1 = 0, rs2 = 0 in
306 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
308 [(flushw)]>, Requires<[HasV9]>;
309 let rd = 0, rs1 = 1, simm13 = 3 in
310 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
315 let isBarrier = 1, isTerminator = 1, rd = 0b1000, rs1 = 0, simm13 = 5 in
316 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
319 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
322 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
323 // instruction selection into a branch sequence. This has to handle all
324 // permutations of selection between i32/f32/f64 on ICC and FCC.
325 // Expanded after instruction selection.
326 let Uses = [ICC], usesCustomInserter = 1 in {
327 def SELECT_CC_Int_ICC
328 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
329 "; SELECT_CC_Int_ICC PSEUDO!",
330 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
332 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
333 "; SELECT_CC_FP_ICC PSEUDO!",
334 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
336 def SELECT_CC_DFP_ICC
337 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
338 "; SELECT_CC_DFP_ICC PSEUDO!",
339 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
341 def SELECT_CC_QFP_ICC
342 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
343 "; SELECT_CC_QFP_ICC PSEUDO!",
344 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
347 let usesCustomInserter = 1, Uses = [FCC] in {
349 def SELECT_CC_Int_FCC
350 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
351 "; SELECT_CC_Int_FCC PSEUDO!",
352 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
355 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
356 "; SELECT_CC_FP_FCC PSEUDO!",
357 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
358 def SELECT_CC_DFP_FCC
359 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
360 "; SELECT_CC_DFP_FCC PSEUDO!",
361 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
362 def SELECT_CC_QFP_FCC
363 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
364 "; SELECT_CC_QFP_FCC PSEUDO!",
365 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
369 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
370 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
371 "jmpl $addr, $dst", []>;
372 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
373 "jmpl $addr, $dst", []>;
376 // Section A.3 - Synthetic Instructions, p. 85
377 // special cases of JMPL:
378 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
379 isCodeGenOnly = 1 in {
380 let rd = 0, rs1 = 15 in
381 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
382 "jmp %o7+$val", [(retflag simm13:$val)]>;
384 let rd = 0, rs1 = 31 in
385 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
389 // Section B.1 - Load Integer Instructions, p. 90
390 defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>;
391 defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
392 defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>;
393 defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
394 defm LD : Load<"ld", 0b000000, load, IntRegs, i32>;
396 // Section B.2 - Load Floating-point Instructions, p. 92
397 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
398 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;
399 defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,
400 Requires<[HasV9, HasHardQuad]>;
402 // Section B.4 - Store Integer Instructions, p. 95
403 defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>;
404 defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
405 defm ST : Store<"st", 0b000100, store, IntRegs, i32>;
407 // Section B.5 - Store Floating-point Instructions, p. 97
408 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
409 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;
410 defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
411 Requires<[HasV9, HasHardQuad]>;
413 // Section B.9 - SETHI Instruction, p. 104
414 def SETHIi: F2_1<0b100,
415 (outs IntRegs:$rd), (ins i32imm:$imm22),
417 [(set i32:$rd, SETHIimm:$imm22)]>;
419 // Section B.10 - NOP Instruction, p. 105
420 // (It's a special case of SETHI)
421 let rd = 0, imm22 = 0 in
422 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
424 // Section B.11 - Logical Instructions, p. 106
425 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
427 def ANDNrr : F3_1<2, 0b000101,
428 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
429 "andn $rs1, $rs2, $rd",
430 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
431 def ANDNri : F3_2<2, 0b000101,
432 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
433 "andn $rs1, $simm13, $rd", []>;
435 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
437 def ORNrr : F3_1<2, 0b000110,
438 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
439 "orn $rs1, $rs2, $rd",
440 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
441 def ORNri : F3_2<2, 0b000110,
442 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
443 "orn $rs1, $simm13, $rd", []>;
444 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
446 def XNORrr : F3_1<2, 0b000111,
447 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
448 "xnor $rs1, $rs2, $rd",
449 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
450 def XNORri : F3_2<2, 0b000111,
451 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
452 "xnor $rs1, $simm13, $rd", []>;
454 // Section B.12 - Shift Instructions, p. 107
455 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
456 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
457 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
459 // Section B.13 - Add Instructions, p. 108
460 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
462 // "LEA" forms of add (patterns to make tblgen happy)
463 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
464 def LEA_ADDri : F3_2<2, 0b000000,
465 (outs IntRegs:$dst), (ins MEMri:$addr),
466 "add ${addr:arith}, $dst",
467 [(set iPTR:$dst, ADDRri:$addr)]>;
470 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
472 let Uses = [ICC], Defs = [ICC] in
473 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
475 // Section B.15 - Subtract Instructions, p. 110
476 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, i32imm>;
477 let Uses = [ICC], Defs = [ICC] in
478 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
481 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
483 let Defs = [ICC], rd = 0 in {
484 def CMPrr : F3_1<2, 0b010100,
485 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
487 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
488 def CMPri : F3_2<2, 0b010100,
489 (outs), (ins IntRegs:$rs1, i32imm:$simm13),
491 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
494 // Section B.18 - Multiply Instructions, p. 113
496 defm UMUL : F3_12np<"umul", 0b001010>;
497 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
500 // Section B.19 - Divide Instructions, p. 115
502 defm UDIV : F3_12np<"udiv", 0b001110>;
503 defm SDIV : F3_12np<"sdiv", 0b001111>;
506 // Section B.20 - SAVE and RESTORE, p. 117
507 defm SAVE : F3_12np<"save" , 0b111100>;
508 defm RESTORE : F3_12np<"restore", 0b111101>;
510 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
512 // unconditional branch class.
513 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
514 : F2_2<0b010, (outs), ins, asmstr, pattern> {
516 let isTerminator = 1;
517 let hasDelaySlot = 1;
522 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
524 // conditional branch class:
525 class BranchSP<dag ins, string asmstr, list<dag> pattern>
526 : F2_2<0b010, (outs), ins, asmstr, pattern> {
528 let isTerminator = 1;
529 let hasDelaySlot = 1;
532 // Indirect branch instructions.
533 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
534 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
535 def BINDrr : F3_1<2, 0b111000,
536 (outs), (ins MEMrr:$ptr),
538 [(brind ADDRrr:$ptr)]>;
539 def BINDri : F3_2<2, 0b111000,
540 (outs), (ins MEMri:$ptr),
542 [(brind ADDRri:$ptr)]>;
546 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
548 [(SPbricc bb:$imm22, imm:$cond)]>;
550 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
552 // floating-point conditional branch class:
553 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
554 : F2_2<0b110, (outs), ins, asmstr, pattern> {
556 let isTerminator = 1;
557 let hasDelaySlot = 1;
561 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
563 [(SPbrfcc bb:$imm22, imm:$cond)]>;
566 // Section B.24 - Call and Link Instruction, p. 125
567 // This is the only Format 1 instruction
569 hasDelaySlot = 1, isCall = 1 in {
570 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
574 let Inst{29-0} = disp;
577 // indirect calls: special cases of JMPL.
578 let isCodeGenOnly = 1, rd = 15 in {
579 def CALLrr : F3_1<2, 0b111000,
580 (outs), (ins MEMrr:$ptr, variable_ops),
582 [(call ADDRrr:$ptr)]>;
583 def CALLri : F3_2<2, 0b111000,
584 (outs), (ins MEMri:$ptr, variable_ops),
586 [(call ADDRri:$ptr)]>;
590 // Section B.28 - Read State Register Instructions
591 let Uses = [Y], rs1 = 0, rs2 = 0 in
592 def RDY : F3_1<2, 0b101000,
593 (outs IntRegs:$dst), (ins),
596 // Section B.29 - Write State Register Instructions
597 let Defs = [Y], rd = 0 in {
598 def WRYrr : F3_1<2, 0b110000,
599 (outs), (ins IntRegs:$b, IntRegs:$c),
600 "wr $b, $c, %y", []>;
601 def WRYri : F3_2<2, 0b110000,
602 (outs), (ins IntRegs:$b, i32imm:$c),
603 "wr $b, $c, %y", []>;
605 // Convert Integer to Floating-point Instructions, p. 141
606 def FITOS : F3_3u<2, 0b110100, 0b011000100,
607 (outs FPRegs:$rd), (ins FPRegs:$rs2),
609 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
610 def FITOD : F3_3u<2, 0b110100, 0b011001000,
611 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
613 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
614 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
615 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
617 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
618 Requires<[HasHardQuad]>;
620 // Convert Floating-point to Integer Instructions, p. 142
621 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
622 (outs FPRegs:$rd), (ins FPRegs:$rs2),
624 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
625 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
626 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
628 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
629 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
630 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
632 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
633 Requires<[HasHardQuad]>;
635 // Convert between Floating-point Formats Instructions, p. 143
636 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
637 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
639 [(set f64:$rd, (fextend f32:$rs2))]>;
640 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
641 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
643 [(set f128:$rd, (fextend f32:$rs2))]>,
644 Requires<[HasHardQuad]>;
645 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
646 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
648 [(set f32:$rd, (fround f64:$rs2))]>;
649 def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
650 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
652 [(set f128:$rd, (fextend f64:$rs2))]>,
653 Requires<[HasHardQuad]>;
654 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
655 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
657 [(set f32:$rd, (fround f128:$rs2))]>,
658 Requires<[HasHardQuad]>;
659 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
660 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
662 [(set f64:$rd, (fround f128:$rs2))]>,
663 Requires<[HasHardQuad]>;
665 // Floating-point Move Instructions, p. 144
666 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
667 (outs FPRegs:$rd), (ins FPRegs:$rs2),
668 "fmovs $rs2, $rd", []>;
669 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
670 (outs FPRegs:$rd), (ins FPRegs:$rs2),
672 [(set f32:$rd, (fneg f32:$rs2))]>;
673 def FABSS : F3_3u<2, 0b110100, 0b000001001,
674 (outs FPRegs:$rd), (ins FPRegs:$rs2),
676 [(set f32:$rd, (fabs f32:$rs2))]>;
679 // Floating-point Square Root Instructions, p.145
680 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
681 (outs FPRegs:$rd), (ins FPRegs:$rs2),
683 [(set f32:$rd, (fsqrt f32:$rs2))]>;
684 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
685 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
687 [(set f64:$rd, (fsqrt f64:$rs2))]>;
688 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
689 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
691 [(set f128:$rd, (fsqrt f128:$rs2))]>,
692 Requires<[HasHardQuad]>;
696 // Floating-point Add and Subtract Instructions, p. 146
697 def FADDS : F3_3<2, 0b110100, 0b001000001,
698 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
699 "fadds $rs1, $rs2, $rd",
700 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
701 def FADDD : F3_3<2, 0b110100, 0b001000010,
702 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
703 "faddd $rs1, $rs2, $rd",
704 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
705 def FADDQ : F3_3<2, 0b110100, 0b001000011,
706 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
707 "faddq $rs1, $rs2, $rd",
708 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
709 Requires<[HasHardQuad]>;
711 def FSUBS : F3_3<2, 0b110100, 0b001000101,
712 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
713 "fsubs $rs1, $rs2, $rd",
714 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
715 def FSUBD : F3_3<2, 0b110100, 0b001000110,
716 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
717 "fsubd $rs1, $rs2, $rd",
718 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
719 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
720 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
721 "fsubq $rs1, $rs2, $rd",
722 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
723 Requires<[HasHardQuad]>;
726 // Floating-point Multiply and Divide Instructions, p. 147
727 def FMULS : F3_3<2, 0b110100, 0b001001001,
728 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
729 "fmuls $rs1, $rs2, $rd",
730 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
731 def FMULD : F3_3<2, 0b110100, 0b001001010,
732 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
733 "fmuld $rs1, $rs2, $rd",
734 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
735 def FMULQ : F3_3<2, 0b110100, 0b001001011,
736 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
737 "fmulq $rs1, $rs2, $rd",
738 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
739 Requires<[HasHardQuad]>;
741 def FSMULD : F3_3<2, 0b110100, 0b001101001,
742 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
743 "fsmuld $rs1, $rs2, $rd",
744 [(set f64:$rd, (fmul (fextend f32:$rs1),
745 (fextend f32:$rs2)))]>;
746 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
747 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
748 "fdmulq $rs1, $rs2, $rd",
749 [(set f128:$rd, (fmul (fextend f64:$rs1),
750 (fextend f64:$rs2)))]>,
751 Requires<[HasHardQuad]>;
753 def FDIVS : F3_3<2, 0b110100, 0b001001101,
754 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
755 "fdivs $rs1, $rs2, $rd",
756 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
757 def FDIVD : F3_3<2, 0b110100, 0b001001110,
758 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
759 "fdivd $rs1, $rs2, $rd",
760 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
761 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
762 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
763 "fdivq $rs1, $rs2, $rd",
764 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
765 Requires<[HasHardQuad]>;
767 // Floating-point Compare Instructions, p. 148
768 // Note: the 2nd template arg is different for these guys.
769 // Note 2: the result of a FCMP is not available until the 2nd cycle
770 // after the instr is retired, but there is no interlock in Sparc V8.
771 // This behavior is modeled with a forced noop after the instruction in
774 let Defs = [FCC] in {
775 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
776 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
778 [(SPcmpfcc f32:$rs1, f32:$rs2)]>;
779 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
780 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
782 [(SPcmpfcc f64:$rs1, f64:$rs2)]>;
783 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
784 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
786 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
787 Requires<[HasHardQuad]>;
790 //===----------------------------------------------------------------------===//
791 // Instructions for Thread Local Storage(TLS).
792 //===----------------------------------------------------------------------===//
793 let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
794 def TLS_ADDrr : F3_1<2, 0b000000,
796 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
797 "add $rs1, $rs2, $rd, $sym",
799 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
802 def TLS_LDrr : F3_1<3, 0b000000,
803 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
804 "ld [$addr], $dst, $sym",
806 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
808 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
809 def TLS_CALL : InstSP<(outs),
810 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
812 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
815 let Inst{29-0} = disp;
819 //===----------------------------------------------------------------------===//
821 //===----------------------------------------------------------------------===//
823 // V9 Conditional Moves.
824 let Predicates = [HasV9], Constraints = "$f = $rd" in {
825 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
826 let Uses = [ICC], cc = 0b100 in {
828 : F4_1<0b101100, (outs IntRegs:$rd),
829 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
830 "mov$cond %icc, $rs2, $rd",
831 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
834 : F4_2<0b101100, (outs IntRegs:$rd),
835 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
836 "mov$cond %icc, $simm11, $rd",
838 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
841 let Uses = [FCC], cc = 0b000 in {
843 : F4_1<0b101100, (outs IntRegs:$rd),
844 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
845 "mov$cond %fcc0, $rs2, $rd",
846 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
848 : F4_2<0b101100, (outs IntRegs:$rd),
849 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
850 "mov$cond %fcc0, $simm11, $rd",
852 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
855 let Uses = [ICC], opf_cc = 0b100 in {
857 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
858 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
859 "fmovs$cond %icc, $rs2, $rd",
860 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
862 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
863 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
864 "fmovd$cond %icc, $rs2, $rd",
865 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
867 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
868 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
869 "fmovq$cond %icc, $rs2, $rd",
870 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
871 Requires<[HasHardQuad]>;
874 let Uses = [FCC], opf_cc = 0b000 in {
876 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
877 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
878 "fmovs$cond %fcc0, $rs2, $rd",
879 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
881 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
882 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
883 "fmovd$cond %fcc0, $rs2, $rd",
884 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
886 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
887 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
888 "fmovq$cond %fcc0, $rs2, $rd",
889 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
890 Requires<[HasHardQuad]>;
895 // Floating-Point Move Instructions, p. 164 of the V9 manual.
896 let Predicates = [HasV9] in {
897 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
898 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
899 "fmovd $rs2, $rd", []>;
900 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
901 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
902 "fmovq $rs2, $rd", []>,
903 Requires<[HasHardQuad]>;
904 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
905 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
907 [(set f64:$rd, (fneg f64:$rs2))]>;
908 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
909 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
911 [(set f128:$rd, (fneg f128:$rs2))]>,
912 Requires<[HasHardQuad]>;
913 def FABSD : F3_3u<2, 0b110100, 0b000001010,
914 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
916 [(set f64:$rd, (fabs f64:$rs2))]>;
917 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
918 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
920 [(set f128:$rd, (fabs f128:$rs2))]>,
921 Requires<[HasHardQuad]>;
924 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
925 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
927 def POPCrr : F3_1<2, 0b101110,
928 (outs IntRegs:$dst), (ins IntRegs:$src),
929 "popc $src, $dst", []>, Requires<[HasV9]>;
930 def : Pat<(ctpop i32:$src),
931 (POPCrr (SRLri $src, 0))>;
934 let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
935 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
937 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
938 def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
939 "membar $simm13", []>;
941 let Constraints = "$val = $dst" in {
942 def SWAPrr : F3_1<3, 0b001111,
943 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
944 "swap [$addr], $dst",
945 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
946 def SWAPri : F3_2<3, 0b001111,
947 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
948 "swap [$addr], $dst",
949 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
952 let Predicates = [HasV9], Constraints = "$swap = $rd" in
953 def CASrr: F3_1_asi<3, 0b111100, 0b10000000,
954 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
956 "cas [$rs1], $rs2, $rd",
958 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
960 //===----------------------------------------------------------------------===//
961 // Non-Instruction Patterns
962 //===----------------------------------------------------------------------===//
965 def : Pat<(i32 simm13:$val),
966 (ORri (i32 G0), imm:$val)>;
967 // Arbitrary immediates.
968 def : Pat<(i32 imm:$val),
969 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
972 // Global addresses, constant pool entries
973 let Predicates = [Is32Bit] in {
975 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
976 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
977 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
978 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
980 // GlobalTLS addresses
981 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
982 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
983 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
984 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
985 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
986 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
989 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
990 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
992 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
993 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
994 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
995 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
996 (ADDri $r, tblockaddress:$in)>;
1000 def : Pat<(call tglobaladdr:$dst),
1001 (CALL tglobaladdr:$dst)>;
1002 def : Pat<(call texternalsym:$dst),
1003 (CALL texternalsym:$dst)>;
1005 // Map integer extload's to zextloads.
1006 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1007 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1008 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1009 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1010 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1011 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1013 // zextload bool -> zextload byte
1014 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1015 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1017 // store 0, addr -> store %g0, addr
1018 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1019 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1021 // store bar for all atomic_fence in V8.
1022 let Predicates = [HasNoV9] in
1023 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1025 // atomic_load_32 addr -> load addr
1026 def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1027 def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1029 // atomic_store_32 val, addr -> store val, addr
1030 def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1031 def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1034 include "SparcInstr64Bit.td"
1035 include "SparcInstrAliases.td"