1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "llvm/ADT/APFloat.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/ADT/Twine.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCTargetAsmParser.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
37 static const char OpPrecedence[] = {
48 class X86AsmParser : public MCTargetAsmParser {
51 ParseInstructionInfo *InstInfo;
53 enum InfixCalculatorTok {
64 class InfixCalculator {
65 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
66 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
67 SmallVector<ICToken, 4> PostfixStack;
70 int64_t popOperand() {
71 assert (!PostfixStack.empty() && "Poped an empty stack!");
72 ICToken Op = PostfixStack.pop_back_val();
73 assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
74 && "Expected and immediate or register!");
77 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
78 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
79 "Unexpected operand!");
80 PostfixStack.push_back(std::make_pair(Op, Val));
83 void popOperator() { InfixOperatorStack.pop_back(); }
84 void pushOperator(InfixCalculatorTok Op) {
85 // Push the new operator if the stack is empty.
86 if (InfixOperatorStack.empty()) {
87 InfixOperatorStack.push_back(Op);
91 // Push the new operator if it has a higher precedence than the operator
92 // on the top of the stack or the operator on the top of the stack is a
94 unsigned Idx = InfixOperatorStack.size() - 1;
95 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
96 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
97 InfixOperatorStack.push_back(Op);
101 // The operator on the top of the stack has higher precedence than the
103 unsigned ParenCount = 0;
105 // Nothing to process.
106 if (InfixOperatorStack.empty())
109 Idx = InfixOperatorStack.size() - 1;
110 StackOp = InfixOperatorStack[Idx];
111 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
114 // If we have an even parentheses count and we see a left parentheses,
115 // then stop processing.
116 if (!ParenCount && StackOp == IC_LPAREN)
119 if (StackOp == IC_RPAREN) {
121 InfixOperatorStack.pop_back();
122 } else if (StackOp == IC_LPAREN) {
124 InfixOperatorStack.pop_back();
126 InfixOperatorStack.pop_back();
127 PostfixStack.push_back(std::make_pair(StackOp, 0));
130 // Push the new operator.
131 InfixOperatorStack.push_back(Op);
134 // Push any remaining operators onto the postfix stack.
135 while (!InfixOperatorStack.empty()) {
136 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
137 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
138 PostfixStack.push_back(std::make_pair(StackOp, 0));
141 if (PostfixStack.empty())
144 SmallVector<ICToken, 16> OperandStack;
145 for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
146 ICToken Op = PostfixStack[i];
147 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
148 OperandStack.push_back(Op);
150 assert (OperandStack.size() > 1 && "Too few operands.");
152 ICToken Op2 = OperandStack.pop_back_val();
153 ICToken Op1 = OperandStack.pop_back_val();
156 report_fatal_error("Unexpected operator!");
159 Val = Op1.second + Op2.second;
160 OperandStack.push_back(std::make_pair(IC_IMM, Val));
163 Val = Op1.second - Op2.second;
164 OperandStack.push_back(std::make_pair(IC_IMM, Val));
167 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
168 "Multiply operation with an immediate and a register!");
169 Val = Op1.second * Op2.second;
170 OperandStack.push_back(std::make_pair(IC_IMM, Val));
173 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
174 "Divide operation with an immediate and a register!");
175 assert (Op2.second != 0 && "Division by zero!");
176 Val = Op1.second / Op2.second;
177 OperandStack.push_back(std::make_pair(IC_IMM, Val));
182 assert (OperandStack.size() == 1 && "Expected a single result.");
183 return OperandStack.pop_back_val().second;
187 enum IntelExprState {
202 class IntelExprStateMachine {
203 IntelExprState State, PrevState;
204 unsigned BaseReg, IndexReg, TmpReg, Scale;
208 bool StopOnLBrac, AddImmPrefix;
210 InlineAsmIdentifierInfo Info;
212 IntelExprStateMachine(int64_t imm, bool stoponlbrac, bool addimmprefix) :
213 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
214 Scale(1), Imm(imm), Sym(0), StopOnLBrac(stoponlbrac),
215 AddImmPrefix(addimmprefix) { Info.clear(); }
217 unsigned getBaseReg() { return BaseReg; }
218 unsigned getIndexReg() { return IndexReg; }
219 unsigned getScale() { return Scale; }
220 const MCExpr *getSym() { return Sym; }
221 StringRef getSymName() { return SymName; }
222 int64_t getImm() { return Imm + IC.execute(); }
223 bool isValidEndState() {
224 return State == IES_RBRAC || State == IES_INTEGER;
226 bool getStopOnLBrac() { return StopOnLBrac; }
227 bool getAddImmPrefix() { return AddImmPrefix; }
228 bool hadError() { return State == IES_ERROR; }
230 InlineAsmIdentifierInfo &getIdentifierInfo() {
235 IntelExprState CurrState = State;
244 IC.pushOperator(IC_PLUS);
245 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
246 // If we already have a BaseReg, then assume this is the IndexReg with
251 assert (!IndexReg && "BaseReg/IndexReg already set!");
258 PrevState = CurrState;
261 IntelExprState CurrState = State;
276 // Only push the minus operator if it is not a unary operator.
277 if (!(CurrState == IES_PLUS || CurrState == IES_MINUS ||
278 CurrState == IES_MULTIPLY || CurrState == IES_DIVIDE ||
279 CurrState == IES_LPAREN || CurrState == IES_LBRAC))
280 IC.pushOperator(IC_MINUS);
281 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
282 // If we already have a BaseReg, then assume this is the IndexReg with
287 assert (!IndexReg && "BaseReg/IndexReg already set!");
294 PrevState = CurrState;
296 void onRegister(unsigned Reg) {
297 IntelExprState CurrState = State;
304 State = IES_REGISTER;
306 IC.pushOperand(IC_REGISTER);
309 // Index Register - Scale * Register
310 if (PrevState == IES_INTEGER) {
311 assert (!IndexReg && "IndexReg already set!");
312 State = IES_REGISTER;
314 // Get the scale and replace the 'Scale * Register' with '0'.
315 Scale = IC.popOperand();
316 IC.pushOperand(IC_IMM);
323 PrevState = CurrState;
325 void onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName) {
335 SymName = SymRefName;
336 IC.pushOperand(IC_IMM);
340 void onInteger(int64_t TmpInt) {
341 IntelExprState CurrState = State;
352 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
353 // Index Register - Register * Scale
354 assert (!IndexReg && "IndexReg already set!");
357 // Get the scale and replace the 'Register * Scale' with '0'.
359 } else if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
360 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
361 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
362 CurrState == IES_MINUS) {
363 // Unary minus. No need to pop the minus operand because it was never
365 IC.pushOperand(IC_IMM, -TmpInt); // Push -Imm.
367 IC.pushOperand(IC_IMM, TmpInt);
371 PrevState = CurrState;
382 State = IES_MULTIPLY;
383 IC.pushOperator(IC_MULTIPLY);
396 IC.pushOperator(IC_DIVIDE);
408 IC.pushOperator(IC_PLUS);
413 IntelExprState CurrState = State;
422 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
423 // If we already have a BaseReg, then assume this is the IndexReg with
428 assert (!IndexReg && "BaseReg/IndexReg already set!");
435 PrevState = CurrState;
438 IntelExprState CurrState = State;
448 // FIXME: We don't handle this type of unary minus, yet.
449 if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
450 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
451 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
452 CurrState == IES_MINUS) {
457 IC.pushOperator(IC_LPAREN);
460 PrevState = CurrState;
472 IC.pushOperator(IC_RPAREN);
478 MCAsmParser &getParser() const { return Parser; }
480 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
482 bool Error(SMLoc L, const Twine &Msg,
483 ArrayRef<SMRange> Ranges = None,
484 bool MatchingInlineAsm = false) {
485 if (MatchingInlineAsm) return true;
486 return Parser.Error(L, Msg, Ranges);
489 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
494 X86Operand *ParseOperand();
495 X86Operand *ParseATTOperand();
496 X86Operand *ParseIntelOperand();
497 X86Operand *ParseIntelOffsetOfOperator();
498 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
499 X86Operand *ParseIntelOperator(unsigned OpKind);
500 X86Operand *ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
501 X86Operand *ParseIntelMemOperand(int64_t ImmDisp, SMLoc StartLoc,
503 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
504 X86Operand *ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
505 int64_t ImmDisp, unsigned Size);
506 bool ParseIntelIdentifier(const MCExpr *&Val, StringRef &Identifier,
507 InlineAsmIdentifierInfo &Info,
508 bool IsUnevaluatedOperand, SMLoc &End);
510 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
512 X86Operand *CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
513 unsigned BaseReg, unsigned IndexReg,
514 unsigned Scale, SMLoc Start, SMLoc End,
515 unsigned Size, StringRef Identifier,
516 InlineAsmIdentifierInfo &Info);
518 bool ParseDirectiveWord(unsigned Size, SMLoc L);
519 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
521 bool processInstruction(MCInst &Inst,
522 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
524 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
525 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
526 MCStreamer &Out, unsigned &ErrorInfo,
527 bool MatchingInlineAsm);
529 /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
530 /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
531 bool isSrcOp(X86Operand &Op);
533 /// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
534 /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
535 bool isDstOp(X86Operand &Op);
537 bool is64BitMode() const {
538 // FIXME: Can tablegen auto-generate this?
539 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
542 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
543 setAvailableFeatures(FB);
546 bool isParsingIntelSyntax() {
547 return getParser().getAssemblerDialect();
550 /// @name Auto-generated Matcher Functions
553 #define GET_ASSEMBLER_HEADER
554 #include "X86GenAsmMatcher.inc"
559 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
560 const MCInstrInfo &MII)
561 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
563 // Initialize the set of available features.
564 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
566 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
568 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
570 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
572 virtual bool ParseDirective(AsmToken DirectiveID);
574 } // end anonymous namespace
576 /// @name Auto-generated Match Functions
579 static unsigned MatchRegisterName(StringRef Name);
583 static bool isImmSExti16i8Value(uint64_t Value) {
584 return (( Value <= 0x000000000000007FULL)||
585 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
586 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
589 static bool isImmSExti32i8Value(uint64_t Value) {
590 return (( Value <= 0x000000000000007FULL)||
591 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
592 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
595 static bool isImmZExtu32u8Value(uint64_t Value) {
596 return (Value <= 0x00000000000000FFULL);
599 static bool isImmSExti64i8Value(uint64_t Value) {
600 return (( Value <= 0x000000000000007FULL)||
601 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
604 static bool isImmSExti64i32Value(uint64_t Value) {
605 return (( Value <= 0x000000007FFFFFFFULL)||
606 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
610 /// X86Operand - Instances of this class represent a parsed X86 machine
612 struct X86Operand : public MCParsedAsmOperand {
620 SMLoc StartLoc, EndLoc;
655 X86Operand(KindTy K, SMLoc Start, SMLoc End)
656 : Kind(K), StartLoc(Start), EndLoc(End) {}
658 StringRef getSymName() { return SymName; }
659 void *getOpDecl() { return OpDecl; }
661 /// getStartLoc - Get the location of the first token of this operand.
662 SMLoc getStartLoc() const { return StartLoc; }
663 /// getEndLoc - Get the location of the last token of this operand.
664 SMLoc getEndLoc() const { return EndLoc; }
665 /// getLocRange - Get the range between the first and last token of this
667 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
668 /// getOffsetOfLoc - Get the location of the offset operator.
669 SMLoc getOffsetOfLoc() const { return OffsetOfLoc; }
671 virtual void print(raw_ostream &OS) const {}
673 StringRef getToken() const {
674 assert(Kind == Token && "Invalid access!");
675 return StringRef(Tok.Data, Tok.Length);
677 void setTokenValue(StringRef Value) {
678 assert(Kind == Token && "Invalid access!");
679 Tok.Data = Value.data();
680 Tok.Length = Value.size();
683 unsigned getReg() const {
684 assert(Kind == Register && "Invalid access!");
688 const MCExpr *getImm() const {
689 assert(Kind == Immediate && "Invalid access!");
693 const MCExpr *getMemDisp() const {
694 assert(Kind == Memory && "Invalid access!");
697 unsigned getMemSegReg() const {
698 assert(Kind == Memory && "Invalid access!");
701 unsigned getMemBaseReg() const {
702 assert(Kind == Memory && "Invalid access!");
705 unsigned getMemIndexReg() const {
706 assert(Kind == Memory && "Invalid access!");
709 unsigned getMemScale() const {
710 assert(Kind == Memory && "Invalid access!");
714 bool isToken() const {return Kind == Token; }
716 bool isImm() const { return Kind == Immediate; }
718 bool isImmSExti16i8() const {
722 // If this isn't a constant expr, just assume it fits and let relaxation
724 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
728 // Otherwise, check the value is in a range that makes sense for this
730 return isImmSExti16i8Value(CE->getValue());
732 bool isImmSExti32i8() const {
736 // If this isn't a constant expr, just assume it fits and let relaxation
738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
742 // Otherwise, check the value is in a range that makes sense for this
744 return isImmSExti32i8Value(CE->getValue());
746 bool isImmZExtu32u8() const {
750 // If this isn't a constant expr, just assume it fits and let relaxation
752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
756 // Otherwise, check the value is in a range that makes sense for this
758 return isImmZExtu32u8Value(CE->getValue());
760 bool isImmSExti64i8() const {
764 // If this isn't a constant expr, just assume it fits and let relaxation
766 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
770 // Otherwise, check the value is in a range that makes sense for this
772 return isImmSExti64i8Value(CE->getValue());
774 bool isImmSExti64i32() const {
778 // If this isn't a constant expr, just assume it fits and let relaxation
780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
784 // Otherwise, check the value is in a range that makes sense for this
786 return isImmSExti64i32Value(CE->getValue());
789 bool isOffsetOf() const {
790 return OffsetOfLoc.getPointer();
793 bool needAddressOf() const {
797 bool isMem() const { return Kind == Memory; }
798 bool isMem8() const {
799 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
801 bool isMem16() const {
802 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
804 bool isMem32() const {
805 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
807 bool isMem64() const {
808 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
810 bool isMem80() const {
811 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
813 bool isMem128() const {
814 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
816 bool isMem256() const {
817 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
819 bool isMem512() const {
820 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
823 bool isMemVX32() const {
824 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
825 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
827 bool isMemVY32() const {
828 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
829 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
831 bool isMemVX64() const {
832 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
833 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
835 bool isMemVY64() const {
836 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
837 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
839 bool isMemVZ32() const {
840 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
841 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
843 bool isMemVZ64() const {
844 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
845 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
848 bool isAbsMem() const {
849 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
850 !getMemIndexReg() && getMemScale() == 1;
853 bool isMemOffs8() const {
854 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
855 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 8);
857 bool isMemOffs16() const {
858 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
859 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 16);
861 bool isMemOffs32() const {
862 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
863 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 32);
865 bool isMemOffs64() const {
866 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
867 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 64);
870 bool isReg() const { return Kind == Register; }
872 bool isGR32orGR64() const {
873 return Kind == Register &&
874 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
875 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
878 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
879 // Add as immediates when possible.
880 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
881 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
883 Inst.addOperand(MCOperand::CreateExpr(Expr));
886 void addRegOperands(MCInst &Inst, unsigned N) const {
887 assert(N == 1 && "Invalid number of operands!");
888 Inst.addOperand(MCOperand::CreateReg(getReg()));
891 static unsigned getGR32FromGR64(unsigned RegNo) {
893 default: llvm_unreachable("Unexpected register");
894 case X86::RAX: return X86::EAX;
895 case X86::RCX: return X86::ECX;
896 case X86::RDX: return X86::EDX;
897 case X86::RBX: return X86::EBX;
898 case X86::RBP: return X86::EBP;
899 case X86::RSP: return X86::ESP;
900 case X86::RSI: return X86::ESI;
901 case X86::RDI: return X86::EDI;
902 case X86::R8: return X86::R8D;
903 case X86::R9: return X86::R9D;
904 case X86::R10: return X86::R10D;
905 case X86::R11: return X86::R11D;
906 case X86::R12: return X86::R12D;
907 case X86::R13: return X86::R13D;
908 case X86::R14: return X86::R14D;
909 case X86::R15: return X86::R15D;
910 case X86::RIP: return X86::EIP;
914 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
915 assert(N == 1 && "Invalid number of operands!");
916 unsigned RegNo = getReg();
917 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
918 RegNo = getGR32FromGR64(RegNo);
919 Inst.addOperand(MCOperand::CreateReg(RegNo));
922 void addImmOperands(MCInst &Inst, unsigned N) const {
923 assert(N == 1 && "Invalid number of operands!");
924 addExpr(Inst, getImm());
927 void addMemOperands(MCInst &Inst, unsigned N) const {
928 assert((N == 5) && "Invalid number of operands!");
929 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
930 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
931 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
932 addExpr(Inst, getMemDisp());
933 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
936 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
937 assert((N == 1) && "Invalid number of operands!");
938 // Add as immediates when possible.
939 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
940 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
942 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
945 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
946 assert((N == 1) && "Invalid number of operands!");
947 // Add as immediates when possible.
948 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
949 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
951 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
954 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
955 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
956 X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
957 Res->Tok.Data = Str.data();
958 Res->Tok.Length = Str.size();
962 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
963 bool AddressOf = false,
964 SMLoc OffsetOfLoc = SMLoc(),
965 StringRef SymName = StringRef(),
967 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
968 Res->Reg.RegNo = RegNo;
969 Res->AddressOf = AddressOf;
970 Res->OffsetOfLoc = OffsetOfLoc;
971 Res->SymName = SymName;
972 Res->OpDecl = OpDecl;
976 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
977 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
982 /// Create an absolute memory operand.
983 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
984 unsigned Size = 0, StringRef SymName = StringRef(),
986 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
988 Res->Mem.Disp = Disp;
989 Res->Mem.BaseReg = 0;
990 Res->Mem.IndexReg = 0;
992 Res->Mem.Size = Size;
993 Res->SymName = SymName;
994 Res->OpDecl = OpDecl;
995 Res->AddressOf = false;
999 /// Create a generalized memory operand.
1000 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
1001 unsigned BaseReg, unsigned IndexReg,
1002 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
1004 StringRef SymName = StringRef(),
1006 // We should never just have a displacement, that should be parsed as an
1007 // absolute memory operand.
1008 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
1010 // The scale should always be one of {1,2,4,8}.
1011 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
1013 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
1014 Res->Mem.SegReg = SegReg;
1015 Res->Mem.Disp = Disp;
1016 Res->Mem.BaseReg = BaseReg;
1017 Res->Mem.IndexReg = IndexReg;
1018 Res->Mem.Scale = Scale;
1019 Res->Mem.Size = Size;
1020 Res->SymName = SymName;
1021 Res->OpDecl = OpDecl;
1022 Res->AddressOf = false;
1027 } // end anonymous namespace.
1029 bool X86AsmParser::isSrcOp(X86Operand &Op) {
1030 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
1032 return (Op.isMem() &&
1033 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
1034 isa<MCConstantExpr>(Op.Mem.Disp) &&
1035 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1036 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
1039 bool X86AsmParser::isDstOp(X86Operand &Op) {
1040 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
1042 return Op.isMem() &&
1043 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
1044 isa<MCConstantExpr>(Op.Mem.Disp) &&
1045 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1046 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
1049 bool X86AsmParser::ParseRegister(unsigned &RegNo,
1050 SMLoc &StartLoc, SMLoc &EndLoc) {
1052 const AsmToken &PercentTok = Parser.getTok();
1053 StartLoc = PercentTok.getLoc();
1055 // If we encounter a %, ignore it. This code handles registers with and
1056 // without the prefix, unprefixed registers can occur in cfi directives.
1057 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
1058 Parser.Lex(); // Eat percent token.
1060 const AsmToken &Tok = Parser.getTok();
1061 EndLoc = Tok.getEndLoc();
1063 if (Tok.isNot(AsmToken::Identifier)) {
1064 if (isParsingIntelSyntax()) return true;
1065 return Error(StartLoc, "invalid register name",
1066 SMRange(StartLoc, EndLoc));
1069 RegNo = MatchRegisterName(Tok.getString());
1071 // If the match failed, try the register name as lowercase.
1073 RegNo = MatchRegisterName(Tok.getString().lower());
1075 if (!is64BitMode()) {
1076 // FIXME: This should be done using Requires<In32BitMode> and
1077 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1079 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1081 if (RegNo == X86::RIZ ||
1082 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1083 X86II::isX86_64NonExtLowByteReg(RegNo) ||
1084 X86II::isX86_64ExtendedReg(RegNo))
1085 return Error(StartLoc, "register %"
1086 + Tok.getString() + " is only available in 64-bit mode",
1087 SMRange(StartLoc, EndLoc));
1090 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1091 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
1093 Parser.Lex(); // Eat 'st'
1095 // Check to see if we have '(4)' after %st.
1096 if (getLexer().isNot(AsmToken::LParen))
1101 const AsmToken &IntTok = Parser.getTok();
1102 if (IntTok.isNot(AsmToken::Integer))
1103 return Error(IntTok.getLoc(), "expected stack index");
1104 switch (IntTok.getIntVal()) {
1105 case 0: RegNo = X86::ST0; break;
1106 case 1: RegNo = X86::ST1; break;
1107 case 2: RegNo = X86::ST2; break;
1108 case 3: RegNo = X86::ST3; break;
1109 case 4: RegNo = X86::ST4; break;
1110 case 5: RegNo = X86::ST5; break;
1111 case 6: RegNo = X86::ST6; break;
1112 case 7: RegNo = X86::ST7; break;
1113 default: return Error(IntTok.getLoc(), "invalid stack index");
1116 if (getParser().Lex().isNot(AsmToken::RParen))
1117 return Error(Parser.getTok().getLoc(), "expected ')'");
1119 EndLoc = Parser.getTok().getEndLoc();
1120 Parser.Lex(); // Eat ')'
1124 EndLoc = Parser.getTok().getEndLoc();
1126 // If this is "db[0-7]", match it as an alias
1128 if (RegNo == 0 && Tok.getString().size() == 3 &&
1129 Tok.getString().startswith("db")) {
1130 switch (Tok.getString()[2]) {
1131 case '0': RegNo = X86::DR0; break;
1132 case '1': RegNo = X86::DR1; break;
1133 case '2': RegNo = X86::DR2; break;
1134 case '3': RegNo = X86::DR3; break;
1135 case '4': RegNo = X86::DR4; break;
1136 case '5': RegNo = X86::DR5; break;
1137 case '6': RegNo = X86::DR6; break;
1138 case '7': RegNo = X86::DR7; break;
1142 EndLoc = Parser.getTok().getEndLoc();
1143 Parser.Lex(); // Eat it.
1149 if (isParsingIntelSyntax()) return true;
1150 return Error(StartLoc, "invalid register name",
1151 SMRange(StartLoc, EndLoc));
1154 Parser.Lex(); // Eat identifier token.
1158 X86Operand *X86AsmParser::ParseOperand() {
1159 if (isParsingIntelSyntax())
1160 return ParseIntelOperand();
1161 return ParseATTOperand();
1164 /// getIntelMemOperandSize - Return intel memory operand size.
1165 static unsigned getIntelMemOperandSize(StringRef OpStr) {
1166 unsigned Size = StringSwitch<unsigned>(OpStr)
1167 .Cases("BYTE", "byte", 8)
1168 .Cases("WORD", "word", 16)
1169 .Cases("DWORD", "dword", 32)
1170 .Cases("QWORD", "qword", 64)
1171 .Cases("XWORD", "xword", 80)
1172 .Cases("XMMWORD", "xmmword", 128)
1173 .Cases("YMMWORD", "ymmword", 256)
1179 X86AsmParser::CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
1180 unsigned BaseReg, unsigned IndexReg,
1181 unsigned Scale, SMLoc Start, SMLoc End,
1182 unsigned Size, StringRef Identifier,
1183 InlineAsmIdentifierInfo &Info){
1184 if (isa<MCSymbolRefExpr>(Disp)) {
1185 // If this is not a VarDecl then assume it is a FuncDecl or some other label
1186 // reference. We need an 'r' constraint here, so we need to create register
1187 // operand to ensure proper matching. Just pick a GPR based on the size of
1189 if (!Info.IsVarDecl) {
1190 unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1191 return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,
1192 SMLoc(), Identifier, Info.OpDecl);
1195 Size = Info.Type * 8; // Size is in terms of bits in this context.
1197 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_SizeDirective, Start,
1202 // When parsing inline assembly we set the base register to a non-zero value
1203 // if we don't know the actual value at this time. This is necessary to
1204 // get the matching correct in some cases.
1205 BaseReg = BaseReg ? BaseReg : 1;
1206 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1207 End, Size, Identifier, Info.OpDecl);
1211 RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> *AsmRewrites,
1212 StringRef SymName, int64_t ImmDisp,
1213 int64_t FinalImmDisp, SMLoc &BracLoc,
1214 SMLoc &StartInBrac, SMLoc &End) {
1215 // Remove the '[' and ']' from the IR string.
1216 AsmRewrites->push_back(AsmRewrite(AOK_Skip, BracLoc, 1));
1217 AsmRewrites->push_back(AsmRewrite(AOK_Skip, End, 1));
1219 // If ImmDisp is non-zero, then we parsed a displacement before the
1220 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1221 // If ImmDisp doesn't match the displacement computed by the state machine
1222 // then we have an additional displacement in the bracketed expression.
1223 if (ImmDisp != FinalImmDisp) {
1225 // We have an immediate displacement before the bracketed expression.
1226 // Adjust this to match the final immediate displacement.
1228 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1229 E = AsmRewrites->end(); I != E; ++I) {
1230 if ((*I).Loc.getPointer() > BracLoc.getPointer())
1232 if ((*I).Kind == AOK_ImmPrefix || (*I).Kind == AOK_Imm) {
1233 assert (!Found && "ImmDisp already rewritten.");
1234 (*I).Kind = AOK_Imm;
1235 (*I).Len = BracLoc.getPointer() - (*I).Loc.getPointer();
1236 (*I).Val = FinalImmDisp;
1241 assert (Found && "Unable to rewrite ImmDisp.");
1244 // We have a symbolic and an immediate displacement, but no displacement
1245 // before the bracketed expression. Put the immediate displacement
1246 // before the bracketed expression.
1247 AsmRewrites->push_back(AsmRewrite(AOK_Imm, BracLoc, 0, FinalImmDisp));
1250 // Remove all the ImmPrefix rewrites within the brackets.
1251 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1252 E = AsmRewrites->end(); I != E; ++I) {
1253 if ((*I).Loc.getPointer() < StartInBrac.getPointer())
1255 if ((*I).Kind == AOK_ImmPrefix)
1256 (*I).Kind = AOK_Delete;
1258 const char *SymLocPtr = SymName.data();
1259 // Skip everything before the symbol.
1260 if (unsigned Len = SymLocPtr - StartInBrac.getPointer()) {
1261 assert(Len > 0 && "Expected a non-negative length.");
1262 AsmRewrites->push_back(AsmRewrite(AOK_Skip, StartInBrac, Len));
1264 // Skip everything after the symbol.
1265 if (unsigned Len = End.getPointer() - (SymLocPtr + SymName.size())) {
1266 SMLoc Loc = SMLoc::getFromPointer(SymLocPtr + SymName.size());
1267 assert(Len > 0 && "Expected a non-negative length.");
1268 AsmRewrites->push_back(AsmRewrite(AOK_Skip, Loc, Len));
1272 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1273 const AsmToken &Tok = Parser.getTok();
1277 bool UpdateLocLex = true;
1279 // The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
1280 // identifier. Don't try an parse it as a register.
1281 if (Tok.getString().startswith("."))
1284 // If we're parsing an immediate expression, we don't expect a '['.
1285 if (SM.getStopOnLBrac() && getLexer().getKind() == AsmToken::LBrac)
1288 switch (getLexer().getKind()) {
1290 if (SM.isValidEndState()) {
1294 return Error(Tok.getLoc(), "unknown token in expression");
1296 case AsmToken::EndOfStatement: {
1300 case AsmToken::Identifier: {
1301 // This could be a register or a symbolic displacement.
1304 SMLoc IdentLoc = Tok.getLoc();
1305 StringRef Identifier = Tok.getString();
1306 if(!ParseRegister(TmpReg, IdentLoc, End)) {
1307 SM.onRegister(TmpReg);
1308 UpdateLocLex = false;
1311 if (!isParsingInlineAsm()) {
1312 if (getParser().parsePrimaryExpr(Val, End))
1313 return Error(Tok.getLoc(), "Unexpected identifier!");
1315 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1316 if (ParseIntelIdentifier(Val, Identifier, Info,
1317 /*Unevaluated=*/false, End))
1320 SM.onIdentifierExpr(Val, Identifier);
1321 UpdateLocLex = false;
1324 return Error(Tok.getLoc(), "Unexpected identifier!");
1326 case AsmToken::Integer:
1327 if (isParsingInlineAsm() && SM.getAddImmPrefix())
1328 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1330 SM.onInteger(Tok.getIntVal());
1332 case AsmToken::Plus: SM.onPlus(); break;
1333 case AsmToken::Minus: SM.onMinus(); break;
1334 case AsmToken::Star: SM.onStar(); break;
1335 case AsmToken::Slash: SM.onDivide(); break;
1336 case AsmToken::LBrac: SM.onLBrac(); break;
1337 case AsmToken::RBrac: SM.onRBrac(); break;
1338 case AsmToken::LParen: SM.onLParen(); break;
1339 case AsmToken::RParen: SM.onRParen(); break;
1342 return Error(Tok.getLoc(), "unknown token in expression");
1344 if (!Done && UpdateLocLex) {
1346 Parser.Lex(); // Consume the token.
1352 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
1355 const AsmToken &Tok = Parser.getTok();
1356 SMLoc BracLoc = Tok.getLoc(), End = Tok.getEndLoc();
1357 if (getLexer().isNot(AsmToken::LBrac))
1358 return ErrorOperand(BracLoc, "Expected '[' token!");
1359 Parser.Lex(); // Eat '['
1361 SMLoc StartInBrac = Tok.getLoc();
1362 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1363 // may have already parsed an immediate displacement before the bracketed
1365 IntelExprStateMachine SM(ImmDisp, /*StopOnLBrac=*/false, /*AddImmPrefix=*/true);
1366 if (ParseIntelExpression(SM, End))
1370 if (const MCExpr *Sym = SM.getSym()) {
1371 // A symbolic displacement.
1373 if (isParsingInlineAsm())
1374 RewriteIntelBracExpression(InstInfo->AsmRewrites, SM.getSymName(),
1375 ImmDisp, SM.getImm(), BracLoc, StartInBrac,
1378 // An immediate displacement only.
1379 Disp = MCConstantExpr::Create(SM.getImm(), getContext());
1382 // Parse the dot operator (e.g., [ebx].foo.bar).
1383 if (Tok.getString().startswith(".")) {
1384 const MCExpr *NewDisp;
1385 if (ParseIntelDotOperator(Disp, NewDisp))
1388 End = Tok.getEndLoc();
1389 Parser.Lex(); // Eat the field.
1393 int BaseReg = SM.getBaseReg();
1394 int IndexReg = SM.getIndexReg();
1395 int Scale = SM.getScale();
1396 if (!isParsingInlineAsm()) {
1398 if (!BaseReg && !IndexReg) {
1400 return X86Operand::CreateMem(Disp, Start, End, Size);
1402 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
1404 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1408 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1409 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1410 End, Size, SM.getSymName(), Info);
1413 // Inline assembly may use variable names with namespace alias qualifiers.
1414 bool X86AsmParser::ParseIntelIdentifier(const MCExpr *&Val,
1415 StringRef &Identifier,
1416 InlineAsmIdentifierInfo &Info,
1417 bool IsUnevaluatedOperand, SMLoc &End) {
1418 assert (isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1421 StringRef LineBuf(Identifier.data());
1422 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1424 const AsmToken &Tok = Parser.getTok();
1426 // Advance the token stream until the end of the current token is
1427 // after the end of what the frontend claimed.
1428 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1430 End = Tok.getEndLoc();
1433 assert(End.getPointer() <= EndPtr && "frontend claimed part of a token?");
1434 if (End.getPointer() == EndPtr) break;
1437 // Create the symbol reference.
1438 Identifier = LineBuf;
1439 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
1440 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1441 Val = MCSymbolRefExpr::Create(Sym, Variant, getParser().getContext());
1445 /// \brief Parse intel style segment override.
1446 X86Operand *X86AsmParser::ParseIntelSegmentOverride(unsigned SegReg,
1449 assert(SegReg != 0 && "Tried to parse a segment override without a segment!");
1450 const AsmToken &Tok = Parser.getTok(); // Eat colon.
1451 if (Tok.isNot(AsmToken::Colon))
1452 return ErrorOperand(Tok.getLoc(), "Expected ':' token!");
1453 Parser.Lex(); // Eat ':'
1455 int64_t ImmDisp = 0;
1456 if (getLexer().is(AsmToken::Integer)) {
1457 ImmDisp = Tok.getIntVal();
1458 AsmToken ImmDispToken = Parser.Lex(); // Eat the integer.
1460 if (isParsingInlineAsm())
1461 InstInfo->AsmRewrites->push_back(
1462 AsmRewrite(AOK_ImmPrefix, ImmDispToken.getLoc()));
1464 if (getLexer().isNot(AsmToken::LBrac)) {
1465 // An immediate following a 'segment register', 'colon' token sequence can
1466 // be followed by a bracketed expression. If it isn't we know we have our
1467 // final segment override.
1468 const MCExpr *Disp = MCConstantExpr::Create(ImmDisp, getContext());
1469 return X86Operand::CreateMem(SegReg, Disp, /*BaseReg=*/0, /*IndexReg=*/0,
1470 /*Scale=*/1, Start, ImmDispToken.getEndLoc(),
1475 if (getLexer().is(AsmToken::LBrac))
1476 return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1480 if (!isParsingInlineAsm()) {
1481 if (getParser().parsePrimaryExpr(Val, End))
1482 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1484 return X86Operand::CreateMem(Val, Start, End, Size);
1487 InlineAsmIdentifierInfo Info;
1488 StringRef Identifier = Tok.getString();
1489 if (ParseIntelIdentifier(Val, Identifier, Info,
1490 /*Unevaluated=*/false, End))
1492 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1493 /*Scale=*/1, Start, End, Size, Identifier, Info);
1496 /// ParseIntelMemOperand - Parse intel style memory operand.
1497 X86Operand *X86AsmParser::ParseIntelMemOperand(int64_t ImmDisp, SMLoc Start,
1499 const AsmToken &Tok = Parser.getTok();
1502 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1503 if (getLexer().is(AsmToken::LBrac))
1504 return ParseIntelBracExpression(/*SegReg=*/0, Start, ImmDisp, Size);
1507 if (!isParsingInlineAsm()) {
1508 if (getParser().parsePrimaryExpr(Val, End))
1509 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1511 return X86Operand::CreateMem(Val, Start, End, Size);
1514 InlineAsmIdentifierInfo Info;
1515 StringRef Identifier = Tok.getString();
1516 if (ParseIntelIdentifier(Val, Identifier, Info,
1517 /*Unevaluated=*/false, End))
1519 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1520 /*Scale=*/1, Start, End, Size, Identifier, Info);
1523 /// Parse the '.' operator.
1524 bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
1525 const MCExpr *&NewDisp) {
1526 const AsmToken &Tok = Parser.getTok();
1527 int64_t OrigDispVal, DotDispVal;
1529 // FIXME: Handle non-constant expressions.
1530 if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp))
1531 OrigDispVal = OrigDisp->getValue();
1533 return Error(Tok.getLoc(), "Non-constant offsets are not supported!");
1536 StringRef DotDispStr = Tok.getString().drop_front(1);
1538 // .Imm gets lexed as a real.
1539 if (Tok.is(AsmToken::Real)) {
1541 DotDispStr.getAsInteger(10, DotDisp);
1542 DotDispVal = DotDisp.getZExtValue();
1543 } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1545 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1546 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1548 return Error(Tok.getLoc(), "Unable to lookup field reference!");
1549 DotDispVal = DotDisp;
1551 return Error(Tok.getLoc(), "Unexpected token type!");
1553 if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1554 SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
1555 unsigned Len = DotDispStr.size();
1556 unsigned Val = OrigDispVal + DotDispVal;
1557 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_DotOperator, Loc, Len,
1561 NewDisp = MCConstantExpr::Create(OrigDispVal + DotDispVal, getContext());
1565 /// Parse the 'offset' operator. This operator is used to specify the
1566 /// location rather then the content of a variable.
1567 X86Operand *X86AsmParser::ParseIntelOffsetOfOperator() {
1568 const AsmToken &Tok = Parser.getTok();
1569 SMLoc OffsetOfLoc = Tok.getLoc();
1570 Parser.Lex(); // Eat offset.
1573 InlineAsmIdentifierInfo Info;
1574 SMLoc Start = Tok.getLoc(), End;
1575 StringRef Identifier = Tok.getString();
1576 if (ParseIntelIdentifier(Val, Identifier, Info,
1577 /*Unevaluated=*/false, End))
1580 // Don't emit the offset operator.
1581 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
1583 // The offset operator will have an 'r' constraint, thus we need to create
1584 // register operand to ensure proper matching. Just pick a GPR based on
1585 // the size of a pointer.
1586 unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1587 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1588 OffsetOfLoc, Identifier, Info.OpDecl);
1591 enum IntelOperatorKind {
1597 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1598 /// returns the number of elements in an array. It returns the value 1 for
1599 /// non-array variables. The SIZE operator returns the size of a C or C++
1600 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1601 /// TYPE operator returns the size of a C or C++ type or variable. If the
1602 /// variable is an array, TYPE returns the size of a single element.
1603 X86Operand *X86AsmParser::ParseIntelOperator(unsigned OpKind) {
1604 const AsmToken &Tok = Parser.getTok();
1605 SMLoc TypeLoc = Tok.getLoc();
1606 Parser.Lex(); // Eat operator.
1608 const MCExpr *Val = 0;
1609 InlineAsmIdentifierInfo Info;
1610 SMLoc Start = Tok.getLoc(), End;
1611 StringRef Identifier = Tok.getString();
1612 if (ParseIntelIdentifier(Val, Identifier, Info,
1613 /*Unevaluated=*/true, End))
1617 return ErrorOperand(Start, "unable to lookup expression");
1621 default: llvm_unreachable("Unexpected operand kind!");
1622 case IOK_LENGTH: CVal = Info.Length; break;
1623 case IOK_SIZE: CVal = Info.Size; break;
1624 case IOK_TYPE: CVal = Info.Type; break;
1627 // Rewrite the type operator and the C or C++ type or variable in terms of an
1628 // immediate. E.g. TYPE foo -> $$4
1629 unsigned Len = End.getPointer() - TypeLoc.getPointer();
1630 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, TypeLoc, Len, CVal));
1632 const MCExpr *Imm = MCConstantExpr::Create(CVal, getContext());
1633 return X86Operand::CreateImm(Imm, Start, End);
1636 X86Operand *X86AsmParser::ParseIntelOperand() {
1637 const AsmToken &Tok = Parser.getTok();
1640 // Offset, length, type and size operators.
1641 if (isParsingInlineAsm()) {
1642 StringRef AsmTokStr = Tok.getString();
1643 if (AsmTokStr == "offset" || AsmTokStr == "OFFSET")
1644 return ParseIntelOffsetOfOperator();
1645 if (AsmTokStr == "length" || AsmTokStr == "LENGTH")
1646 return ParseIntelOperator(IOK_LENGTH);
1647 if (AsmTokStr == "size" || AsmTokStr == "SIZE")
1648 return ParseIntelOperator(IOK_SIZE);
1649 if (AsmTokStr == "type" || AsmTokStr == "TYPE")
1650 return ParseIntelOperator(IOK_TYPE);
1653 unsigned Size = getIntelMemOperandSize(Tok.getString());
1655 Parser.Lex(); // Eat operand size (e.g., byte, word).
1656 if (Tok.getString() != "PTR" && Tok.getString() != "ptr")
1657 return ErrorOperand(Start, "Expected 'PTR' or 'ptr' token!");
1658 Parser.Lex(); // Eat ptr.
1660 Start = Tok.getLoc();
1663 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Minus) ||
1664 getLexer().is(AsmToken::LParen)) {
1665 AsmToken StartTok = Tok;
1666 IntelExprStateMachine SM(/*Imm=*/0, /*StopOnLBrac=*/true,
1667 /*AddImmPrefix=*/false);
1668 if (ParseIntelExpression(SM, End))
1671 int64_t Imm = SM.getImm();
1672 if (isParsingInlineAsm()) {
1673 unsigned Len = Tok.getLoc().getPointer() - Start.getPointer();
1674 if (StartTok.getString().size() == Len)
1675 // Just add a prefix if this wasn't a complex immediate expression.
1676 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix, Start));
1678 // Otherwise, rewrite the complex expression as a single immediate.
1679 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, Start, Len, Imm));
1682 if (getLexer().isNot(AsmToken::LBrac)) {
1683 const MCExpr *ImmExpr = MCConstantExpr::Create(Imm, getContext());
1684 return X86Operand::CreateImm(ImmExpr, Start, End);
1687 // Only positive immediates are valid.
1689 return ErrorOperand(Start, "expected a positive immediate displacement "
1690 "before bracketed expr.");
1692 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1693 return ParseIntelMemOperand(Imm, Start, Size);
1698 if (!ParseRegister(RegNo, Start, End)) {
1699 // If this is a segment register followed by a ':', then this is the start
1700 // of a segment override, otherwise this is a normal register reference.
1701 if (getLexer().isNot(AsmToken::Colon))
1702 return X86Operand::CreateReg(RegNo, Start, End);
1704 return ParseIntelSegmentOverride(/*SegReg=*/RegNo, Start, Size);
1708 return ParseIntelMemOperand(/*Disp=*/0, Start, Size);
1711 X86Operand *X86AsmParser::ParseATTOperand() {
1712 switch (getLexer().getKind()) {
1714 // Parse a memory operand with no segment register.
1715 return ParseMemOperand(0, Parser.getTok().getLoc());
1716 case AsmToken::Percent: {
1717 // Read the register.
1720 if (ParseRegister(RegNo, Start, End)) return 0;
1721 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1722 Error(Start, "%eiz and %riz can only be used as index registers",
1723 SMRange(Start, End));
1727 // If this is a segment register followed by a ':', then this is the start
1728 // of a memory reference, otherwise this is a normal register reference.
1729 if (getLexer().isNot(AsmToken::Colon))
1730 return X86Operand::CreateReg(RegNo, Start, End);
1732 getParser().Lex(); // Eat the colon.
1733 return ParseMemOperand(RegNo, Start);
1735 case AsmToken::Dollar: {
1736 // $42 -> immediate.
1737 SMLoc Start = Parser.getTok().getLoc(), End;
1740 if (getParser().parseExpression(Val, End))
1742 return X86Operand::CreateImm(Val, Start, End);
1747 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1748 /// has already been parsed if present.
1749 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
1751 // We have to disambiguate a parenthesized expression "(4+5)" from the start
1752 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
1753 // only way to do this without lookahead is to eat the '(' and see what is
1755 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
1756 if (getLexer().isNot(AsmToken::LParen)) {
1758 if (getParser().parseExpression(Disp, ExprEnd)) return 0;
1760 // After parsing the base expression we could either have a parenthesized
1761 // memory address or not. If not, return now. If so, eat the (.
1762 if (getLexer().isNot(AsmToken::LParen)) {
1763 // Unless we have a segment register, treat this as an immediate.
1765 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
1766 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1772 // Okay, we have a '('. We don't know if this is an expression or not, but
1773 // so we have to eat the ( to see beyond it.
1774 SMLoc LParenLoc = Parser.getTok().getLoc();
1775 Parser.Lex(); // Eat the '('.
1777 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
1778 // Nothing to do here, fall into the code below with the '(' part of the
1779 // memory operand consumed.
1783 // It must be an parenthesized expression, parse it now.
1784 if (getParser().parseParenExpression(Disp, ExprEnd))
1787 // After parsing the base expression we could either have a parenthesized
1788 // memory address or not. If not, return now. If so, eat the (.
1789 if (getLexer().isNot(AsmToken::LParen)) {
1790 // Unless we have a segment register, treat this as an immediate.
1792 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
1793 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1801 // If we reached here, then we just ate the ( of the memory operand. Process
1802 // the rest of the memory operand.
1803 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1806 if (getLexer().is(AsmToken::Percent)) {
1807 SMLoc StartLoc, EndLoc;
1808 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
1809 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
1810 Error(StartLoc, "eiz and riz can only be used as index registers",
1811 SMRange(StartLoc, EndLoc));
1816 if (getLexer().is(AsmToken::Comma)) {
1817 Parser.Lex(); // Eat the comma.
1818 IndexLoc = Parser.getTok().getLoc();
1820 // Following the comma we should have either an index register, or a scale
1821 // value. We don't support the later form, but we want to parse it
1824 // Not that even though it would be completely consistent to support syntax
1825 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
1826 if (getLexer().is(AsmToken::Percent)) {
1828 if (ParseRegister(IndexReg, L, L)) return 0;
1830 if (getLexer().isNot(AsmToken::RParen)) {
1831 // Parse the scale amount:
1832 // ::= ',' [scale-expression]
1833 if (getLexer().isNot(AsmToken::Comma)) {
1834 Error(Parser.getTok().getLoc(),
1835 "expected comma in scale expression");
1838 Parser.Lex(); // Eat the comma.
1840 if (getLexer().isNot(AsmToken::RParen)) {
1841 SMLoc Loc = Parser.getTok().getLoc();
1844 if (getParser().parseAbsoluteExpression(ScaleVal)){
1845 Error(Loc, "expected scale expression");
1849 // Validate the scale amount.
1850 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
1851 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
1854 Scale = (unsigned)ScaleVal;
1857 } else if (getLexer().isNot(AsmToken::RParen)) {
1858 // A scale amount without an index is ignored.
1860 SMLoc Loc = Parser.getTok().getLoc();
1863 if (getParser().parseAbsoluteExpression(Value))
1867 Warning(Loc, "scale factor without index register is ignored");
1872 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
1873 if (getLexer().isNot(AsmToken::RParen)) {
1874 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
1877 SMLoc MemEnd = Parser.getTok().getEndLoc();
1878 Parser.Lex(); // Eat the ')'.
1880 // If we have both a base register and an index register make sure they are
1881 // both 64-bit or 32-bit registers.
1882 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1883 if (BaseReg != 0 && IndexReg != 0) {
1884 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1885 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1886 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
1887 IndexReg != X86::RIZ) {
1888 Error(IndexLoc, "index register is 32-bit, but base register is 64-bit");
1891 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1892 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1893 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
1894 IndexReg != X86::EIZ){
1895 Error(IndexLoc, "index register is 64-bit, but base register is 32-bit");
1900 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
1905 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1906 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1908 StringRef PatchedName = Name;
1910 // FIXME: Hack to recognize setneb as setne.
1911 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
1912 PatchedName != "setb" && PatchedName != "setnb")
1913 PatchedName = PatchedName.substr(0, Name.size()-1);
1915 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
1916 const MCExpr *ExtraImmOp = 0;
1917 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
1918 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
1919 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
1920 bool IsVCMP = PatchedName[0] == 'v';
1921 unsigned SSECCIdx = IsVCMP ? 4 : 3;
1922 unsigned SSEComparisonCode = StringSwitch<unsigned>(
1923 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
1927 .Case("unord", 0x03)
1932 /* AVX only from here */
1933 .Case("eq_uq", 0x08)
1936 .Case("false", 0x0B)
1937 .Case("neq_oq", 0x0C)
1941 .Case("eq_os", 0x10)
1942 .Case("lt_oq", 0x11)
1943 .Case("le_oq", 0x12)
1944 .Case("unord_s", 0x13)
1945 .Case("neq_us", 0x14)
1946 .Case("nlt_uq", 0x15)
1947 .Case("nle_uq", 0x16)
1948 .Case("ord_s", 0x17)
1949 .Case("eq_us", 0x18)
1950 .Case("nge_uq", 0x19)
1951 .Case("ngt_uq", 0x1A)
1952 .Case("false_os", 0x1B)
1953 .Case("neq_os", 0x1C)
1954 .Case("ge_oq", 0x1D)
1955 .Case("gt_oq", 0x1E)
1956 .Case("true_us", 0x1F)
1958 if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
1959 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
1960 getParser().getContext());
1961 if (PatchedName.endswith("ss")) {
1962 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
1963 } else if (PatchedName.endswith("sd")) {
1964 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
1965 } else if (PatchedName.endswith("ps")) {
1966 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
1968 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
1969 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
1974 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1976 if (ExtraImmOp && !isParsingIntelSyntax())
1977 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1979 // Determine whether this is an instruction prefix.
1981 Name == "lock" || Name == "rep" ||
1982 Name == "repe" || Name == "repz" ||
1983 Name == "repne" || Name == "repnz" ||
1984 Name == "rex64" || Name == "data16";
1987 // This does the actual operand parsing. Don't parse any more if we have a
1988 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
1989 // just want to parse the "lock" as the first instruction and the "incl" as
1991 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
1993 // Parse '*' modifier.
1994 if (getLexer().is(AsmToken::Star)) {
1995 SMLoc Loc = Parser.getTok().getLoc();
1996 Operands.push_back(X86Operand::CreateToken("*", Loc));
1997 Parser.Lex(); // Eat the star.
2000 // Read the first operand.
2001 if (X86Operand *Op = ParseOperand())
2002 Operands.push_back(Op);
2004 Parser.eatToEndOfStatement();
2008 while (getLexer().is(AsmToken::Comma)) {
2009 Parser.Lex(); // Eat the comma.
2011 // Parse and remember the operand.
2012 if (X86Operand *Op = ParseOperand())
2013 Operands.push_back(Op);
2015 Parser.eatToEndOfStatement();
2020 if (STI.getFeatureBits() & X86::FeatureAVX512) {
2021 // Parse mask register {%k1}
2022 if (getLexer().is(AsmToken::LCurly)) {
2023 SMLoc Loc = Parser.getTok().getLoc();
2024 Operands.push_back(X86Operand::CreateToken("{", Loc));
2025 Parser.Lex(); // Eat the {
2026 if (X86Operand *Op = ParseOperand()) {
2027 Operands.push_back(Op);
2028 if (!getLexer().is(AsmToken::RCurly)) {
2029 SMLoc Loc = getLexer().getLoc();
2030 Parser.eatToEndOfStatement();
2031 return Error(Loc, "Expected } at this point");
2033 Loc = Parser.getTok().getLoc();
2034 Operands.push_back(X86Operand::CreateToken("}", Loc));
2035 Parser.Lex(); // Eat the }
2037 Parser.eatToEndOfStatement();
2041 // Parse "zeroing non-masked" semantic {z}
2042 if (getLexer().is(AsmToken::LCurly)) {
2043 SMLoc Loc = Parser.getTok().getLoc();
2044 Operands.push_back(X86Operand::CreateToken("{z}", Loc));
2045 Parser.Lex(); // Eat the {
2046 if (!getLexer().is(AsmToken::Identifier) || getLexer().getTok().getIdentifier() != "z") {
2047 SMLoc Loc = getLexer().getLoc();
2048 Parser.eatToEndOfStatement();
2049 return Error(Loc, "Expected z at this point");
2051 Parser.Lex(); // Eat the z
2052 if (!getLexer().is(AsmToken::RCurly)) {
2053 SMLoc Loc = getLexer().getLoc();
2054 Parser.eatToEndOfStatement();
2055 return Error(Loc, "Expected } at this point");
2057 Parser.Lex(); // Eat the }
2061 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2062 SMLoc Loc = getLexer().getLoc();
2063 Parser.eatToEndOfStatement();
2064 return Error(Loc, "unexpected token in argument list");
2068 if (getLexer().is(AsmToken::EndOfStatement))
2069 Parser.Lex(); // Consume the EndOfStatement
2070 else if (isPrefix && getLexer().is(AsmToken::Slash))
2071 Parser.Lex(); // Consume the prefix separator Slash
2073 if (ExtraImmOp && isParsingIntelSyntax())
2074 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
2076 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
2077 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2078 // documented form in various unofficial manuals, so a lot of code uses it.
2079 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
2080 Operands.size() == 3) {
2081 X86Operand &Op = *(X86Operand*)Operands.back();
2082 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2083 isa<MCConstantExpr>(Op.Mem.Disp) &&
2084 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2085 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2086 SMLoc Loc = Op.getEndLoc();
2087 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2091 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
2092 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
2093 Operands.size() == 3) {
2094 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2095 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2096 isa<MCConstantExpr>(Op.Mem.Disp) &&
2097 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2098 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2099 SMLoc Loc = Op.getEndLoc();
2100 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2104 // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
2105 if (Name.startswith("ins") && Operands.size() == 3 &&
2106 (Name == "insb" || Name == "insw" || Name == "insl")) {
2107 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2108 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2109 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
2110 Operands.pop_back();
2111 Operands.pop_back();
2117 // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
2118 if (Name.startswith("outs") && Operands.size() == 3 &&
2119 (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
2120 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2121 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2122 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
2123 Operands.pop_back();
2124 Operands.pop_back();
2130 // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
2131 if (Name.startswith("movs") && Operands.size() == 3 &&
2132 (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
2133 (is64BitMode() && Name == "movsq"))) {
2134 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2135 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2136 if (isSrcOp(Op) && isDstOp(Op2)) {
2137 Operands.pop_back();
2138 Operands.pop_back();
2143 // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
2144 if (Name.startswith("lods") && Operands.size() == 3 &&
2145 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2146 Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
2147 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2148 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
2149 if (isSrcOp(*Op1) && Op2->isReg()) {
2151 unsigned reg = Op2->getReg();
2152 bool isLods = Name == "lods";
2153 if (reg == X86::AL && (isLods || Name == "lodsb"))
2155 else if (reg == X86::AX && (isLods || Name == "lodsw"))
2157 else if (reg == X86::EAX && (isLods || Name == "lodsl"))
2159 else if (reg == X86::RAX && (isLods || Name == "lodsq"))
2164 Operands.pop_back();
2165 Operands.pop_back();
2169 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
2173 // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
2174 if (Name.startswith("stos") && Operands.size() == 3 &&
2175 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2176 Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
2177 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2178 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
2179 if (isDstOp(*Op2) && Op1->isReg()) {
2181 unsigned reg = Op1->getReg();
2182 bool isStos = Name == "stos";
2183 if (reg == X86::AL && (isStos || Name == "stosb"))
2185 else if (reg == X86::AX && (isStos || Name == "stosw"))
2187 else if (reg == X86::EAX && (isStos || Name == "stosl"))
2189 else if (reg == X86::RAX && (isStos || Name == "stosq"))
2194 Operands.pop_back();
2195 Operands.pop_back();
2199 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
2204 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2206 if ((Name.startswith("shr") || Name.startswith("sar") ||
2207 Name.startswith("shl") || Name.startswith("sal") ||
2208 Name.startswith("rcl") || Name.startswith("rcr") ||
2209 Name.startswith("rol") || Name.startswith("ror")) &&
2210 Operands.size() == 3) {
2211 if (isParsingIntelSyntax()) {
2213 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
2214 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2215 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2217 Operands.pop_back();
2220 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2221 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2222 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2224 Operands.erase(Operands.begin() + 1);
2229 // Transforms "int $3" into "int3" as a size optimization. We can't write an
2230 // instalias with an immediate operand yet.
2231 if (Name == "int" && Operands.size() == 2) {
2232 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2233 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2234 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
2236 Operands.erase(Operands.begin() + 1);
2237 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
2244 static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
2247 TmpInst.setOpcode(Opcode);
2249 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2250 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2251 TmpInst.addOperand(Inst.getOperand(0));
2256 static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
2257 bool isCmp = false) {
2258 if (!Inst.getOperand(0).isImm() ||
2259 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
2262 return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
2265 static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
2266 bool isCmp = false) {
2267 if (!Inst.getOperand(0).isImm() ||
2268 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
2271 return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
2274 static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
2275 bool isCmp = false) {
2276 if (!Inst.getOperand(0).isImm() ||
2277 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
2280 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
2284 processInstruction(MCInst &Inst,
2285 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
2286 switch (Inst.getOpcode()) {
2287 default: return false;
2288 case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
2289 case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
2290 case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
2291 case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
2292 case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
2293 case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
2294 case X86::OR16i16: return convert16i16to16ri8(Inst, X86::OR16ri8);
2295 case X86::OR32i32: return convert32i32to32ri8(Inst, X86::OR32ri8);
2296 case X86::OR64i32: return convert64i32to64ri8(Inst, X86::OR64ri8);
2297 case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
2298 case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
2299 case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
2300 case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
2301 case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
2302 case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
2303 case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
2304 case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
2305 case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
2306 case X86::ADC16i16: return convert16i16to16ri8(Inst, X86::ADC16ri8);
2307 case X86::ADC32i32: return convert32i32to32ri8(Inst, X86::ADC32ri8);
2308 case X86::ADC64i32: return convert64i32to64ri8(Inst, X86::ADC64ri8);
2309 case X86::SBB16i16: return convert16i16to16ri8(Inst, X86::SBB16ri8);
2310 case X86::SBB32i32: return convert32i32to32ri8(Inst, X86::SBB32ri8);
2311 case X86::SBB64i32: return convert64i32to64ri8(Inst, X86::SBB64ri8);
2312 case X86::VMOVAPDrr:
2313 case X86::VMOVAPDYrr:
2314 case X86::VMOVAPSrr:
2315 case X86::VMOVAPSYrr:
2316 case X86::VMOVDQArr:
2317 case X86::VMOVDQAYrr:
2318 case X86::VMOVDQUrr:
2319 case X86::VMOVDQUYrr:
2320 case X86::VMOVUPDrr:
2321 case X86::VMOVUPDYrr:
2322 case X86::VMOVUPSrr:
2323 case X86::VMOVUPSYrr: {
2324 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2325 !X86II::isX86_64ExtendedReg(Inst.getOperand(1).getReg()))
2329 switch (Inst.getOpcode()) {
2330 default: llvm_unreachable("Invalid opcode");
2331 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2332 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2333 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2334 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2335 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2336 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2337 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2338 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2339 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
2340 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2341 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
2342 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
2344 Inst.setOpcode(NewOpc);
2348 case X86::VMOVSSrr: {
2349 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2350 !X86II::isX86_64ExtendedReg(Inst.getOperand(2).getReg()))
2353 switch (Inst.getOpcode()) {
2354 default: llvm_unreachable("Invalid opcode");
2355 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
2356 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
2358 Inst.setOpcode(NewOpc);
2364 static const char *getSubtargetFeatureName(unsigned Val);
2366 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2367 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2368 MCStreamer &Out, unsigned &ErrorInfo,
2369 bool MatchingInlineAsm) {
2370 assert(!Operands.empty() && "Unexpect empty operand list!");
2371 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
2372 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
2373 ArrayRef<SMRange> EmptyRanges = None;
2375 // First, handle aliases that expand to multiple instructions.
2376 // FIXME: This should be replaced with a real .td file alias mechanism.
2377 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2379 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
2380 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
2381 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
2382 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
2384 Inst.setOpcode(X86::WAIT);
2386 if (!MatchingInlineAsm)
2387 Out.EmitInstruction(Inst);
2390 StringSwitch<const char*>(Op->getToken())
2391 .Case("finit", "fninit")
2392 .Case("fsave", "fnsave")
2393 .Case("fstcw", "fnstcw")
2394 .Case("fstcww", "fnstcw")
2395 .Case("fstenv", "fnstenv")
2396 .Case("fstsw", "fnstsw")
2397 .Case("fstsww", "fnstsw")
2398 .Case("fclex", "fnclex")
2400 assert(Repl && "Unknown wait-prefixed instruction");
2402 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2405 bool WasOriginallyInvalidOperand = false;
2408 // First, try a direct match.
2409 switch (MatchInstructionImpl(Operands, Inst,
2410 ErrorInfo, MatchingInlineAsm,
2411 isParsingIntelSyntax())) {
2414 // Some instructions need post-processing to, for example, tweak which
2415 // encoding is selected. Loop on it while changes happen so the
2416 // individual transformations can chain off each other.
2417 if (!MatchingInlineAsm)
2418 while (processInstruction(Inst, Operands))
2422 if (!MatchingInlineAsm)
2423 Out.EmitInstruction(Inst);
2424 Opcode = Inst.getOpcode();
2426 case Match_MissingFeature: {
2427 assert(ErrorInfo && "Unknown missing feature!");
2428 // Special case the error message for the very common case where only
2429 // a single subtarget feature is missing.
2430 std::string Msg = "instruction requires:";
2432 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2433 if (ErrorInfo & Mask) {
2435 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
2439 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2441 case Match_InvalidOperand:
2442 WasOriginallyInvalidOperand = true;
2444 case Match_MnemonicFail:
2448 // FIXME: Ideally, we would only attempt suffix matches for things which are
2449 // valid prefixes, and we could just infer the right unambiguous
2450 // type. However, that requires substantially more matcher support than the
2453 // Change the operand to point to a temporary token.
2454 StringRef Base = Op->getToken();
2455 SmallString<16> Tmp;
2458 Op->setTokenValue(Tmp.str());
2460 // If this instruction starts with an 'f', then it is a floating point stack
2461 // instruction. These come in up to three forms for 32-bit, 64-bit, and
2462 // 80-bit floating point, which use the suffixes s,l,t respectively.
2464 // Otherwise, we assume that this may be an integer instruction, which comes
2465 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2466 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
2468 // Check for the various suffix matches.
2469 Tmp[Base.size()] = Suffixes[0];
2470 unsigned ErrorInfoIgnore;
2471 unsigned ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2472 unsigned Match1, Match2, Match3, Match4;
2474 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2475 MatchingInlineAsm, isParsingIntelSyntax());
2476 // If this returned as a missing feature failure, remember that.
2477 if (Match1 == Match_MissingFeature)
2478 ErrorInfoMissingFeature = ErrorInfoIgnore;
2479 Tmp[Base.size()] = Suffixes[1];
2480 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2481 MatchingInlineAsm, isParsingIntelSyntax());
2482 // If this returned as a missing feature failure, remember that.
2483 if (Match2 == Match_MissingFeature)
2484 ErrorInfoMissingFeature = ErrorInfoIgnore;
2485 Tmp[Base.size()] = Suffixes[2];
2486 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2487 MatchingInlineAsm, isParsingIntelSyntax());
2488 // If this returned as a missing feature failure, remember that.
2489 if (Match3 == Match_MissingFeature)
2490 ErrorInfoMissingFeature = ErrorInfoIgnore;
2491 Tmp[Base.size()] = Suffixes[3];
2492 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2493 MatchingInlineAsm, isParsingIntelSyntax());
2494 // If this returned as a missing feature failure, remember that.
2495 if (Match4 == Match_MissingFeature)
2496 ErrorInfoMissingFeature = ErrorInfoIgnore;
2498 // Restore the old token.
2499 Op->setTokenValue(Base);
2501 // If exactly one matched, then we treat that as a successful match (and the
2502 // instruction will already have been filled in correctly, since the failing
2503 // matches won't have modified it).
2504 unsigned NumSuccessfulMatches =
2505 (Match1 == Match_Success) + (Match2 == Match_Success) +
2506 (Match3 == Match_Success) + (Match4 == Match_Success);
2507 if (NumSuccessfulMatches == 1) {
2509 if (!MatchingInlineAsm)
2510 Out.EmitInstruction(Inst);
2511 Opcode = Inst.getOpcode();
2515 // Otherwise, the match failed, try to produce a decent error message.
2517 // If we had multiple suffix matches, then identify this as an ambiguous
2519 if (NumSuccessfulMatches > 1) {
2521 unsigned NumMatches = 0;
2522 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
2523 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
2524 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
2525 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
2527 SmallString<126> Msg;
2528 raw_svector_ostream OS(Msg);
2529 OS << "ambiguous instructions require an explicit suffix (could be ";
2530 for (unsigned i = 0; i != NumMatches; ++i) {
2533 if (i + 1 == NumMatches)
2535 OS << "'" << Base << MatchChars[i] << "'";
2538 Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
2542 // Okay, we know that none of the variants matched successfully.
2544 // If all of the instructions reported an invalid mnemonic, then the original
2545 // mnemonic was invalid.
2546 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
2547 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
2548 if (!WasOriginallyInvalidOperand) {
2549 ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges :
2551 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
2552 Ranges, MatchingInlineAsm);
2555 // Recover location info for the operand if we know which was the problem.
2556 if (ErrorInfo != ~0U) {
2557 if (ErrorInfo >= Operands.size())
2558 return Error(IDLoc, "too few operands for instruction",
2559 EmptyRanges, MatchingInlineAsm);
2561 X86Operand *Operand = (X86Operand*)Operands[ErrorInfo];
2562 if (Operand->getStartLoc().isValid()) {
2563 SMRange OperandRange = Operand->getLocRange();
2564 return Error(Operand->getStartLoc(), "invalid operand for instruction",
2565 OperandRange, MatchingInlineAsm);
2569 return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2573 // If one instruction matched with a missing feature, report this as a
2575 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
2576 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
2577 std::string Msg = "instruction requires:";
2579 for (unsigned i = 0; i < (sizeof(ErrorInfoMissingFeature)*8-1); ++i) {
2580 if (ErrorInfoMissingFeature & Mask) {
2582 Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask);
2586 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2589 // If one instruction matched with an invalid operand, report this as an
2591 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
2592 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
2593 Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2598 // If all of these were an outright failure, report it in a useless way.
2599 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
2600 EmptyRanges, MatchingInlineAsm);
2605 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
2606 StringRef IDVal = DirectiveID.getIdentifier();
2607 if (IDVal == ".word")
2608 return ParseDirectiveWord(2, DirectiveID.getLoc());
2609 else if (IDVal.startswith(".code"))
2610 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
2611 else if (IDVal.startswith(".att_syntax")) {
2612 getParser().setAssemblerDialect(0);
2614 } else if (IDVal.startswith(".intel_syntax")) {
2615 getParser().setAssemblerDialect(1);
2616 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2617 if(Parser.getTok().getString() == "noprefix") {
2618 // FIXME : Handle noprefix
2628 /// ParseDirectiveWord
2629 /// ::= .word [ expression (, expression)* ]
2630 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2631 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2633 const MCExpr *Value;
2634 if (getParser().parseExpression(Value))
2637 getParser().getStreamer().EmitValue(Value, Size);
2639 if (getLexer().is(AsmToken::EndOfStatement))
2642 // FIXME: Improve diagnostic.
2643 if (getLexer().isNot(AsmToken::Comma))
2644 return Error(L, "unexpected token in directive");
2653 /// ParseDirectiveCode
2654 /// ::= .code32 | .code64
2655 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
2656 if (IDVal == ".code32") {
2658 if (is64BitMode()) {
2660 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2662 } else if (IDVal == ".code64") {
2664 if (!is64BitMode()) {
2666 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
2669 return Error(L, "unexpected directive " + IDVal);
2675 // Force static initialization.
2676 extern "C" void LLVMInitializeX86AsmParser() {
2677 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
2678 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
2681 #define GET_REGISTER_MATCHER
2682 #define GET_MATCHER_IMPLEMENTATION
2683 #define GET_SUBTARGET_FEATURE_NAME
2684 #include "X86GenAsmMatcher.inc"