1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
32 using namespace clang;
34 //===----------------------------------------------------------------------===//
35 // Common code shared among targets.
36 //===----------------------------------------------------------------------===//
38 /// DefineStd - Define a macro name and standard variants. For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42 const LangOptions &Opts) {
43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46 // in the user's namespace.
48 Builder.defineMacro(MacroName);
51 Builder.defineMacro("__" + MacroName);
54 Builder.defineMacro("__" + MacroName + "__");
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59 Builder.defineMacro("__" + CPUName);
60 Builder.defineMacro("__" + CPUName + "__");
62 Builder.defineMacro("__tune_" + CPUName + "__");
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74 MacroBuilder &Builder) const=0;
76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77 virtual void getTargetDefines(const LangOptions &Opts,
78 MacroBuilder &Builder) const {
79 TgtInfo::getTargetDefines(Opts, Builder);
80 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
84 } // end anonymous namespace
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88 const llvm::Triple &Triple,
89 StringRef &PlatformName,
90 VersionTuple &PlatformMinVersion) {
91 Builder.defineMacro("__APPLE_CC__", "5621");
92 Builder.defineMacro("__APPLE__");
93 Builder.defineMacro("__MACH__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
99 if (!Opts.ObjCAutoRefCount) {
100 // __weak is always defined, for use in blocks and with objc pointers.
101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103 // Darwin defines __strong even in C mode (just to nothing).
104 if (Opts.getGC() != LangOptions::NonGC)
105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107 Builder.defineMacro("__strong", "");
109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110 // allow this in C, since one might have block pointers in structs that
111 // are used in pure C code and in Objective-C ARC.
112 Builder.defineMacro("__unsafe_unretained", "");
116 Builder.defineMacro("__STATIC__");
118 Builder.defineMacro("__DYNAMIC__");
120 if (Opts.POSIXThreads)
121 Builder.defineMacro("_REENTRANT");
123 // Get the platform type and version number from the triple.
124 unsigned Maj, Min, Rev;
125 if (Triple.isMacOSX()) {
126 Triple.getMacOSXVersion(Maj, Min, Rev);
127 PlatformName = "macosx";
129 Triple.getOSVersion(Maj, Min, Rev);
130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
133 // If -target arch-pc-win32-macho option specified, we're
134 // generating code for Win32 ABI. No need to emit
135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136 if (PlatformName == "win32") {
137 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
141 // Set the appropriate OS version define.
142 if (Triple.getOS() == llvm::Triple::IOS) {
143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
146 Str[1] = '0' + (Min / 10);
147 Str[2] = '0' + (Min % 10);
148 Str[3] = '0' + (Rev / 10);
149 Str[4] = '0' + (Rev % 10);
151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
153 // Note that the Driver allows versions which aren't representable in the
154 // define (because we only get a single digit for the minor and micro
155 // revision numbers). So, we limit them to the maximum representable
157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160 Str[0] = '0' + (Maj / 10);
161 Str[1] = '0' + (Maj % 10);
162 Str[2] = '0' + std::min(Min, 9U);
163 Str[3] = '0' + std::min(Rev, 9U);
165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
168 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
172 template<typename Target>
173 class DarwinTargetInfo : public OSTargetInfo<Target> {
175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176 MacroBuilder &Builder) const {
177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178 this->PlatformMinVersion);
182 DarwinTargetInfo(const std::string& triple) :
183 OSTargetInfo<Target>(triple) {
184 llvm::Triple T = llvm::Triple(triple);
185 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186 this->MCountName = "\01mcount";
189 virtual std::string isValidSectionSpecifier(StringRef SR) const {
190 // Let MCSectionMachO validate this.
191 StringRef Segment, Section;
192 unsigned TAA, StubSize;
194 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195 TAA, HasTAA, StubSize);
198 virtual const char *getStaticInitSectionSpecifier() const {
199 // FIXME: We should return 0 when building kexts.
200 return "__TEXT,__StaticInit,regular,pure_instructions";
203 /// Darwin does not support protected visibility. Darwin's "default"
204 /// is very similar to ELF's "protected"; Darwin requires a "weak"
205 /// attribute on declarations that can be dynamically replaced.
206 virtual bool hasProtectedVisibility() const {
212 // DragonFlyBSD Target
213 template<typename Target>
214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
216 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217 MacroBuilder &Builder) const {
218 // DragonFly defines; list based off of gcc output
219 Builder.defineMacro("__DragonFly__");
220 Builder.defineMacro("__DragonFly_cc_version", "100001");
221 Builder.defineMacro("__ELF__");
222 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223 Builder.defineMacro("__tune_i386__");
224 DefineStd(Builder, "unix", Opts);
227 DragonFlyBSDTargetInfo(const std::string &triple)
228 : OSTargetInfo<Target>(triple) {
229 this->UserLabelPrefix = "";
231 llvm::Triple Triple(triple);
232 switch (Triple.getArch()) {
234 case llvm::Triple::x86:
235 case llvm::Triple::x86_64:
236 this->MCountName = ".mcount";
243 template<typename Target>
244 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247 MacroBuilder &Builder) const {
248 // FreeBSD defines; list based off of gcc output
250 unsigned Release = Triple.getOSMajorVersion();
254 Builder.defineMacro("__FreeBSD__", llvm::Twine(Release));
255 Builder.defineMacro("__FreeBSD_cc_version",
256 llvm::Twine(Release * 100000U + 1U));
257 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
258 DefineStd(Builder, "unix", Opts);
259 Builder.defineMacro("__ELF__");
262 FreeBSDTargetInfo(const std::string &triple)
263 : OSTargetInfo<Target>(triple) {
264 this->UserLabelPrefix = "";
266 llvm::Triple Triple(triple);
267 switch (Triple.getArch()) {
269 case llvm::Triple::x86:
270 case llvm::Triple::x86_64:
271 this->MCountName = ".mcount";
273 case llvm::Triple::mips:
274 case llvm::Triple::mipsel:
275 case llvm::Triple::ppc:
276 case llvm::Triple::ppc64:
277 this->MCountName = "_mcount";
279 case llvm::Triple::arm:
280 this->MCountName = "__mcount";
288 template<typename Target>
289 class MinixTargetInfo : public OSTargetInfo<Target> {
291 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
292 MacroBuilder &Builder) const {
295 Builder.defineMacro("__minix", "3");
296 Builder.defineMacro("_EM_WSIZE", "4");
297 Builder.defineMacro("_EM_PSIZE", "4");
298 Builder.defineMacro("_EM_SSIZE", "2");
299 Builder.defineMacro("_EM_LSIZE", "4");
300 Builder.defineMacro("_EM_FSIZE", "4");
301 Builder.defineMacro("_EM_DSIZE", "8");
302 Builder.defineMacro("__ELF__");
303 DefineStd(Builder, "unix", Opts);
306 MinixTargetInfo(const std::string &triple)
307 : OSTargetInfo<Target>(triple) {
308 this->UserLabelPrefix = "";
313 template<typename Target>
314 class LinuxTargetInfo : public OSTargetInfo<Target> {
316 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
317 MacroBuilder &Builder) const {
318 // Linux defines; list based off of gcc output
319 DefineStd(Builder, "unix", Opts);
320 DefineStd(Builder, "linux", Opts);
321 Builder.defineMacro("__gnu_linux__");
322 Builder.defineMacro("__ELF__");
323 if (Triple.getEnvironment() == llvm::Triple::Android)
324 Builder.defineMacro("__ANDROID__", "1");
325 if (Opts.POSIXThreads)
326 Builder.defineMacro("_REENTRANT");
328 Builder.defineMacro("_GNU_SOURCE");
331 LinuxTargetInfo(const std::string& triple)
332 : OSTargetInfo<Target>(triple) {
333 this->UserLabelPrefix = "";
334 this->WIntType = TargetInfo::UnsignedInt;
337 virtual const char *getStaticInitSectionSpecifier() const {
338 return ".text.startup";
343 template<typename Target>
344 class NetBSDTargetInfo : public OSTargetInfo<Target> {
346 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
347 MacroBuilder &Builder) const {
348 // NetBSD defines; list based off of gcc output
349 Builder.defineMacro("__NetBSD__");
350 Builder.defineMacro("__unix__");
351 Builder.defineMacro("__ELF__");
352 if (Opts.POSIXThreads)
353 Builder.defineMacro("_POSIX_THREADS");
356 NetBSDTargetInfo(const std::string &triple)
357 : OSTargetInfo<Target>(triple) {
358 this->UserLabelPrefix = "";
363 template<typename Target>
364 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
366 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
367 MacroBuilder &Builder) const {
368 // OpenBSD defines; list based off of gcc output
370 Builder.defineMacro("__OpenBSD__");
371 DefineStd(Builder, "unix", Opts);
372 Builder.defineMacro("__ELF__");
373 if (Opts.POSIXThreads)
374 Builder.defineMacro("_REENTRANT");
377 OpenBSDTargetInfo(const std::string &triple)
378 : OSTargetInfo<Target>(triple) {
379 this->UserLabelPrefix = "";
380 this->TLSSupported = false;
382 llvm::Triple Triple(triple);
383 switch (Triple.getArch()) {
385 case llvm::Triple::x86:
386 case llvm::Triple::x86_64:
387 case llvm::Triple::arm:
388 case llvm::Triple::sparc:
389 this->MCountName = "__mcount";
391 case llvm::Triple::mips64:
392 case llvm::Triple::mips64el:
393 case llvm::Triple::ppc:
394 case llvm::Triple::sparcv9:
395 this->MCountName = "_mcount";
402 template<typename Target>
403 class BitrigTargetInfo : public OSTargetInfo<Target> {
405 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
406 MacroBuilder &Builder) const {
407 // Bitrig defines; list based off of gcc output
409 Builder.defineMacro("__Bitrig__");
410 DefineStd(Builder, "unix", Opts);
411 Builder.defineMacro("__ELF__");
412 if (Opts.POSIXThreads)
413 Builder.defineMacro("_REENTRANT");
416 BitrigTargetInfo(const std::string &triple)
417 : OSTargetInfo<Target>(triple) {
418 this->UserLabelPrefix = "";
419 this->TLSSupported = false;
420 this->MCountName = "__mcount";
425 template<typename Target>
426 class PSPTargetInfo : public OSTargetInfo<Target> {
428 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
429 MacroBuilder &Builder) const {
430 // PSP defines; list based on the output of the pspdev gcc toolchain.
431 Builder.defineMacro("PSP");
432 Builder.defineMacro("_PSP");
433 Builder.defineMacro("__psp__");
434 Builder.defineMacro("__ELF__");
437 PSPTargetInfo(const std::string& triple)
438 : OSTargetInfo<Target>(triple) {
439 this->UserLabelPrefix = "";
444 template<typename Target>
445 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
447 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
448 MacroBuilder &Builder) const {
450 Builder.defineMacro("__PPC__");
451 Builder.defineMacro("__PPU__");
452 Builder.defineMacro("__CELLOS_LV2__");
453 Builder.defineMacro("__ELF__");
454 Builder.defineMacro("__LP32__");
455 Builder.defineMacro("_ARCH_PPC64");
456 Builder.defineMacro("__powerpc64__");
459 PS3PPUTargetInfo(const std::string& triple)
460 : OSTargetInfo<Target>(triple) {
461 this->UserLabelPrefix = "";
462 this->LongWidth = this->LongAlign = 32;
463 this->PointerWidth = this->PointerAlign = 32;
464 this->IntMaxType = TargetInfo::SignedLongLong;
465 this->UIntMaxType = TargetInfo::UnsignedLongLong;
466 this->Int64Type = TargetInfo::SignedLongLong;
467 this->SizeType = TargetInfo::UnsignedInt;
468 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
469 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
473 // FIXME: Need a real SPU target.
475 template<typename Target>
476 class PS3SPUTargetInfo : public OSTargetInfo<Target> {
478 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
479 MacroBuilder &Builder) const {
481 Builder.defineMacro("__SPU__");
482 Builder.defineMacro("__ELF__");
485 PS3SPUTargetInfo(const std::string& triple)
486 : OSTargetInfo<Target>(triple) {
487 this->UserLabelPrefix = "";
492 template<typename Target>
493 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
495 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
496 MacroBuilder &Builder) const {
497 DefineStd(Builder, "sun", Opts);
498 DefineStd(Builder, "unix", Opts);
499 Builder.defineMacro("__ELF__");
500 Builder.defineMacro("__svr4__");
501 Builder.defineMacro("__SVR4");
504 AuroraUXTargetInfo(const std::string& triple)
505 : OSTargetInfo<Target>(triple) {
506 this->UserLabelPrefix = "";
507 this->WCharType = this->SignedLong;
508 // FIXME: WIntType should be SignedLong
513 template<typename Target>
514 class SolarisTargetInfo : public OSTargetInfo<Target> {
516 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
517 MacroBuilder &Builder) const {
518 DefineStd(Builder, "sun", Opts);
519 DefineStd(Builder, "unix", Opts);
520 Builder.defineMacro("__ELF__");
521 Builder.defineMacro("__svr4__");
522 Builder.defineMacro("__SVR4");
523 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
524 // newer, but to 500 for everything else. feature_test.h has a check to
525 // ensure that you are not using C99 with an old version of X/Open or C89
526 // with a new version.
527 if (Opts.C99 || Opts.C11)
528 Builder.defineMacro("_XOPEN_SOURCE", "600");
530 Builder.defineMacro("_XOPEN_SOURCE", "500");
532 Builder.defineMacro("__C99FEATURES__");
533 Builder.defineMacro("_LARGEFILE_SOURCE");
534 Builder.defineMacro("_LARGEFILE64_SOURCE");
535 Builder.defineMacro("__EXTENSIONS__");
536 Builder.defineMacro("_REENTRANT");
539 SolarisTargetInfo(const std::string& triple)
540 : OSTargetInfo<Target>(triple) {
541 this->UserLabelPrefix = "";
542 this->WCharType = this->SignedInt;
543 // FIXME: WIntType should be SignedLong
548 template<typename Target>
549 class WindowsTargetInfo : public OSTargetInfo<Target> {
551 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
552 MacroBuilder &Builder) const {
553 Builder.defineMacro("_WIN32");
555 void getVisualStudioDefines(const LangOptions &Opts,
556 MacroBuilder &Builder) const {
557 if (Opts.CPlusPlus) {
559 Builder.defineMacro("_CPPRTTI");
562 Builder.defineMacro("_CPPUNWIND");
565 if (!Opts.CharIsSigned)
566 Builder.defineMacro("_CHAR_UNSIGNED");
568 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
569 // but it works for now.
570 if (Opts.POSIXThreads)
571 Builder.defineMacro("_MT");
573 if (Opts.MSCVersion != 0)
574 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
576 if (Opts.MicrosoftExt) {
577 Builder.defineMacro("_MSC_EXTENSIONS");
579 if (Opts.CPlusPlus11) {
580 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
581 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
582 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
586 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
590 WindowsTargetInfo(const std::string &triple)
591 : OSTargetInfo<Target>(triple) {}
594 template <typename Target>
595 class NaClTargetInfo : public OSTargetInfo<Target> {
597 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
598 MacroBuilder &Builder) const {
599 if (Opts.POSIXThreads)
600 Builder.defineMacro("_REENTRANT");
602 Builder.defineMacro("_GNU_SOURCE");
604 DefineStd(Builder, "unix", Opts);
605 Builder.defineMacro("__ELF__");
606 Builder.defineMacro("__native_client__");
609 NaClTargetInfo(const std::string &triple)
610 : OSTargetInfo<Target>(triple) {
611 this->UserLabelPrefix = "";
612 this->LongAlign = 32;
613 this->LongWidth = 32;
614 this->PointerAlign = 32;
615 this->PointerWidth = 32;
616 this->IntMaxType = TargetInfo::SignedLongLong;
617 this->UIntMaxType = TargetInfo::UnsignedLongLong;
618 this->Int64Type = TargetInfo::SignedLongLong;
619 this->DoubleAlign = 64;
620 this->LongDoubleWidth = 64;
621 this->LongDoubleAlign = 64;
622 this->SizeType = TargetInfo::UnsignedInt;
623 this->PtrDiffType = TargetInfo::SignedInt;
624 this->IntPtrType = TargetInfo::SignedInt;
625 // RegParmMax is inherited from the underlying architecture
626 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
627 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
628 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
630 virtual typename Target::CallingConvCheckResult checkCallingConvention(
631 CallingConv CC) const {
632 return CC == CC_PnaclCall ? Target::CCCR_OK :
633 Target::checkCallingConvention(CC);
636 } // end anonymous namespace.
638 //===----------------------------------------------------------------------===//
639 // Specific target implementations.
640 //===----------------------------------------------------------------------===//
643 // PPC abstract base class
644 class PPCTargetInfo : public TargetInfo {
645 static const Builtin::Info BuiltinInfo[];
646 static const char * const GCCRegNames[];
647 static const TargetInfo::GCCRegAlias GCCRegAliases[];
650 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
651 LongDoubleWidth = LongDoubleAlign = 128;
652 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
655 /// \brief Flags for architecture specific defines.
658 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
659 ArchDefinePpcgr = 1 << 1,
660 ArchDefinePpcsq = 1 << 2,
661 ArchDefine440 = 1 << 3,
662 ArchDefine603 = 1 << 4,
663 ArchDefine604 = 1 << 5,
664 ArchDefinePwr4 = 1 << 6,
665 ArchDefinePwr5 = 1 << 7,
666 ArchDefinePwr5x = 1 << 8,
667 ArchDefinePwr6 = 1 << 9,
668 ArchDefinePwr6x = 1 << 10,
669 ArchDefinePwr7 = 1 << 11,
670 ArchDefineA2 = 1 << 12,
671 ArchDefineA2q = 1 << 13
674 // Note: GCC recognizes the following additional cpus:
675 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
676 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
678 virtual bool setCPU(const std::string &Name) {
679 bool CPUKnown = llvm::StringSwitch<bool>(Name)
680 .Case("generic", true)
702 .Case("e500mc", true)
704 .Case("power3", true)
706 .Case("power4", true)
708 .Case("power5", true)
710 .Case("power5x", true)
712 .Case("power6", true)
714 .Case("power6x", true)
716 .Case("power7", true)
718 .Case("powerpc", true)
720 .Case("powerpc64", true)
730 virtual void getTargetBuiltins(const Builtin::Info *&Records,
731 unsigned &NumRecords) const {
732 Records = BuiltinInfo;
733 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
736 virtual bool isCLZForZeroUndef() const { return false; }
738 virtual void getTargetDefines(const LangOptions &Opts,
739 MacroBuilder &Builder) const;
741 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
743 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
747 virtual bool hasFeature(StringRef Feature) const;
749 virtual void getGCCRegNames(const char * const *&Names,
750 unsigned &NumNames) const;
751 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
752 unsigned &NumAliases) const;
753 virtual bool validateAsmConstraint(const char *&Name,
754 TargetInfo::ConstraintInfo &Info) const {
756 default: return false;
759 case 'b': // Base register
760 case 'f': // Floating point register
761 Info.setAllowsRegister();
763 // FIXME: The following are added to allow parsing.
764 // I just took a guess at what the actions should be.
765 // Also, is more specific checking needed? I.e. specific registers?
766 case 'd': // Floating point register (containing 64-bit value)
767 case 'v': // Altivec vector register
768 Info.setAllowsRegister();
772 case 'd':// VSX vector register to hold vector double data
773 case 'f':// VSX vector register to hold vector float data
774 case 's':// VSX vector register to hold scalar float data
775 case 'a':// Any VSX register
780 Info.setAllowsRegister();
781 Name++; // Skip over 'w'.
783 case 'h': // `MQ', `CTR', or `LINK' register
784 case 'q': // `MQ' register
785 case 'c': // `CTR' register
786 case 'l': // `LINK' register
787 case 'x': // `CR' register (condition register) number 0
788 case 'y': // `CR' register (condition register)
789 case 'z': // `XER[CA]' carry bit (part of the XER register)
790 Info.setAllowsRegister();
792 case 'I': // Signed 16-bit constant
793 case 'J': // Unsigned 16-bit constant shifted left 16 bits
794 // (use `L' instead for SImode constants)
795 case 'K': // Unsigned 16-bit constant
796 case 'L': // Signed 16-bit constant shifted left 16 bits
797 case 'M': // Constant larger than 31
798 case 'N': // Exact power of 2
799 case 'P': // Constant whose negation is a signed 16-bit constant
800 case 'G': // Floating point constant that can be loaded into a
801 // register with one instruction per word
802 case 'H': // Integer/Floating point constant that can be loaded
803 // into a register using three instructions
805 case 'm': // Memory operand. Note that on PowerPC targets, m can
806 // include addresses that update the base register. It
807 // is therefore only safe to use `m' in an asm statement
808 // if that asm statement accesses the operand exactly once.
809 // The asm statement must also use `%U<opno>' as a
810 // placeholder for the "update" flag in the corresponding
811 // load or store instruction. For example:
812 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
814 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
815 // is not. Use es rather than m if you don't want the base
816 // register to be updated.
820 // es: A "stable" memory operand; that is, one which does not
821 // include any automodification of the base register. Unlike
822 // `m', this constraint can be used in asm statements that
823 // might access the operand several times, or that might not
825 Info.setAllowsMemory();
826 Name++; // Skip over 'e'.
828 case 'Q': // Memory operand that is an offset from a register (it is
829 // usually better to use `m' or `es' in asm statements)
830 case 'Z': // Memory operand that is an indexed or indirect from a
831 // register (it is usually better to use `m' or `es' in
833 Info.setAllowsMemory();
834 Info.setAllowsRegister();
836 case 'R': // AIX TOC entry
837 case 'a': // Address operand that is an indexed or indirect from a
838 // register (`p' is preferable for asm statements)
839 case 'S': // Constant suitable as a 64-bit mask operand
840 case 'T': // Constant suitable as a 32-bit mask operand
841 case 'U': // System V Release 4 small data area reference
842 case 't': // AND masks that can be performed by two rldic{l, r}
844 case 'W': // Vector constant that does not require memory
845 case 'j': // Vector constant that is all zeros.
851 virtual const char *getClobbers() const {
854 int getEHDataRegisterNumber(unsigned RegNo) const {
855 if (RegNo == 0) return 3;
856 if (RegNo == 1) return 4;
861 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
862 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
863 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
865 #include "clang/Basic/BuiltinsPPC.def"
869 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
870 /// #defines that are not tied to a specific subtarget.
871 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
872 MacroBuilder &Builder) const {
873 // Target identification.
874 Builder.defineMacro("__ppc__");
875 Builder.defineMacro("_ARCH_PPC");
876 Builder.defineMacro("__powerpc__");
877 Builder.defineMacro("__POWERPC__");
878 if (PointerWidth == 64) {
879 Builder.defineMacro("_ARCH_PPC64");
880 Builder.defineMacro("__powerpc64__");
881 Builder.defineMacro("__ppc64__");
883 Builder.defineMacro("__ppc__");
886 // Target properties.
887 if (getTriple().getOS() != llvm::Triple::NetBSD &&
888 getTriple().getOS() != llvm::Triple::OpenBSD)
889 Builder.defineMacro("_BIG_ENDIAN");
890 Builder.defineMacro("__BIG_ENDIAN__");
892 // Subtarget options.
893 Builder.defineMacro("__NATURAL_ALIGNMENT__");
894 Builder.defineMacro("__REGISTER_PREFIX__", "");
896 // FIXME: Should be controlled by command line option.
897 Builder.defineMacro("__LONG_DOUBLE_128__");
900 Builder.defineMacro("__VEC__", "10206");
901 Builder.defineMacro("__ALTIVEC__");
904 // CPU identification.
905 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
906 .Case("440", ArchDefineName)
907 .Case("450", ArchDefineName | ArchDefine440)
908 .Case("601", ArchDefineName)
909 .Case("602", ArchDefineName | ArchDefinePpcgr)
910 .Case("603", ArchDefineName | ArchDefinePpcgr)
911 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
913 .Case("604", ArchDefineName | ArchDefinePpcgr)
914 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
915 .Case("620", ArchDefineName | ArchDefinePpcgr)
916 .Case("630", ArchDefineName | ArchDefinePpcgr)
917 .Case("7400", ArchDefineName | ArchDefinePpcgr)
918 .Case("7450", ArchDefineName | ArchDefinePpcgr)
919 .Case("750", ArchDefineName | ArchDefinePpcgr)
920 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
922 .Case("a2", ArchDefineA2)
923 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
924 .Case("pwr3", ArchDefinePpcgr)
925 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
926 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
928 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
929 | ArchDefinePpcgr | ArchDefinePpcsq)
930 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
931 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
932 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
933 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
935 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
936 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
937 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
938 .Case("power3", ArchDefinePpcgr)
939 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
940 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
942 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
943 | ArchDefinePpcgr | ArchDefinePpcsq)
944 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
945 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
946 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
947 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
949 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
950 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
951 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
952 .Default(ArchDefineNone);
954 if (defs & ArchDefineName)
955 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
956 if (defs & ArchDefinePpcgr)
957 Builder.defineMacro("_ARCH_PPCGR");
958 if (defs & ArchDefinePpcsq)
959 Builder.defineMacro("_ARCH_PPCSQ");
960 if (defs & ArchDefine440)
961 Builder.defineMacro("_ARCH_440");
962 if (defs & ArchDefine603)
963 Builder.defineMacro("_ARCH_603");
964 if (defs & ArchDefine604)
965 Builder.defineMacro("_ARCH_604");
966 if (defs & ArchDefinePwr4)
967 Builder.defineMacro("_ARCH_PWR4");
968 if (defs & ArchDefinePwr5)
969 Builder.defineMacro("_ARCH_PWR5");
970 if (defs & ArchDefinePwr5x)
971 Builder.defineMacro("_ARCH_PWR5X");
972 if (defs & ArchDefinePwr6)
973 Builder.defineMacro("_ARCH_PWR6");
974 if (defs & ArchDefinePwr6x)
975 Builder.defineMacro("_ARCH_PWR6X");
976 if (defs & ArchDefinePwr7)
977 Builder.defineMacro("_ARCH_PWR7");
978 if (defs & ArchDefineA2)
979 Builder.defineMacro("_ARCH_A2");
980 if (defs & ArchDefineA2q) {
981 Builder.defineMacro("_ARCH_A2Q");
982 Builder.defineMacro("_ARCH_QP");
985 if (getTriple().getVendor() == llvm::Triple::BGQ) {
986 Builder.defineMacro("__bg__");
987 Builder.defineMacro("__THW_BLUEGENE__");
988 Builder.defineMacro("__bgq__");
989 Builder.defineMacro("__TOS_BGQ__");
992 // FIXME: The following are not yet generated here by Clang, but are
996 // __RECIP_PRECISION__
1007 // __CMODEL_MEDIUM__
1014 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1015 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1024 .Case("ppc64", true)
1027 Features["qpx"] = (CPU == "a2q");
1030 bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1032 bool Enabled) const {
1033 if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1034 Name == "popcntd" || Name == "qpx") {
1035 Features[Name] = Enabled;
1042 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1043 return Feature == "powerpc";
1047 const char * const PPCTargetInfo::GCCRegNames[] = {
1048 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1049 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1050 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1051 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1052 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1053 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1054 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1055 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1056 "mq", "lr", "ctr", "ap",
1057 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1059 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1060 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1061 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1062 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1064 "spe_acc", "spefscr",
1068 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1069 unsigned &NumNames) const {
1070 Names = GCCRegNames;
1071 NumNames = llvm::array_lengthof(GCCRegNames);
1074 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1075 // While some of these aliases do map to different registers
1076 // they still share the same register name.
1087 { { "10" }, "r10" },
1088 { { "11" }, "r11" },
1089 { { "12" }, "r12" },
1090 { { "13" }, "r13" },
1091 { { "14" }, "r14" },
1092 { { "15" }, "r15" },
1093 { { "16" }, "r16" },
1094 { { "17" }, "r17" },
1095 { { "18" }, "r18" },
1096 { { "19" }, "r19" },
1097 { { "20" }, "r20" },
1098 { { "21" }, "r21" },
1099 { { "22" }, "r22" },
1100 { { "23" }, "r23" },
1101 { { "24" }, "r24" },
1102 { { "25" }, "r25" },
1103 { { "26" }, "r26" },
1104 { { "27" }, "r27" },
1105 { { "28" }, "r28" },
1106 { { "29" }, "r29" },
1107 { { "30" }, "r30" },
1108 { { "31" }, "r31" },
1109 { { "fr0" }, "f0" },
1110 { { "fr1" }, "f1" },
1111 { { "fr2" }, "f2" },
1112 { { "fr3" }, "f3" },
1113 { { "fr4" }, "f4" },
1114 { { "fr5" }, "f5" },
1115 { { "fr6" }, "f6" },
1116 { { "fr7" }, "f7" },
1117 { { "fr8" }, "f8" },
1118 { { "fr9" }, "f9" },
1119 { { "fr10" }, "f10" },
1120 { { "fr11" }, "f11" },
1121 { { "fr12" }, "f12" },
1122 { { "fr13" }, "f13" },
1123 { { "fr14" }, "f14" },
1124 { { "fr15" }, "f15" },
1125 { { "fr16" }, "f16" },
1126 { { "fr17" }, "f17" },
1127 { { "fr18" }, "f18" },
1128 { { "fr19" }, "f19" },
1129 { { "fr20" }, "f20" },
1130 { { "fr21" }, "f21" },
1131 { { "fr22" }, "f22" },
1132 { { "fr23" }, "f23" },
1133 { { "fr24" }, "f24" },
1134 { { "fr25" }, "f25" },
1135 { { "fr26" }, "f26" },
1136 { { "fr27" }, "f27" },
1137 { { "fr28" }, "f28" },
1138 { { "fr29" }, "f29" },
1139 { { "fr30" }, "f30" },
1140 { { "fr31" }, "f31" },
1141 { { "cc" }, "cr0" },
1144 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1145 unsigned &NumAliases) const {
1146 Aliases = GCCRegAliases;
1147 NumAliases = llvm::array_lengthof(GCCRegAliases);
1149 } // end anonymous namespace.
1152 class PPC32TargetInfo : public PPCTargetInfo {
1154 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1155 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1156 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1158 switch (getTriple().getOS()) {
1159 case llvm::Triple::Linux:
1160 case llvm::Triple::FreeBSD:
1161 case llvm::Triple::NetBSD:
1162 SizeType = UnsignedInt;
1163 PtrDiffType = SignedInt;
1164 IntPtrType = SignedInt;
1170 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1171 LongDoubleWidth = LongDoubleAlign = 64;
1172 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1175 // PPC32 supports atomics up to 4 bytes.
1176 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1179 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1180 // This is the ELF definition, and is overridden by the Darwin sub-target
1181 return TargetInfo::PowerABIBuiltinVaList;
1184 } // end anonymous namespace.
1187 class PPC64TargetInfo : public PPCTargetInfo {
1189 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1190 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1191 IntMaxType = SignedLong;
1192 UIntMaxType = UnsignedLong;
1193 Int64Type = SignedLong;
1195 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1196 LongDoubleWidth = LongDoubleAlign = 64;
1197 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1198 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1199 "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1200 "v128:128:128-n32:64";
1202 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1203 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1204 "v128:128:128-n32:64";
1206 // PPC64 supports atomics up to 8 bytes.
1207 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1209 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1210 return TargetInfo::CharPtrBuiltinVaList;
1213 } // end anonymous namespace.
1217 class DarwinPPC32TargetInfo :
1218 public DarwinTargetInfo<PPC32TargetInfo> {
1220 DarwinPPC32TargetInfo(const std::string& triple)
1221 : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1222 HasAlignMac68kSupport = true;
1223 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1225 SuitableAlign = 128;
1226 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1227 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1229 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1230 return TargetInfo::CharPtrBuiltinVaList;
1234 class DarwinPPC64TargetInfo :
1235 public DarwinTargetInfo<PPC64TargetInfo> {
1237 DarwinPPC64TargetInfo(const std::string& triple)
1238 : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1239 HasAlignMac68kSupport = true;
1240 SuitableAlign = 128;
1241 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1242 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1245 } // end anonymous namespace.
1248 static const unsigned NVPTXAddrSpaceMap[] = {
1251 4, // opencl_constant
1256 class NVPTXTargetInfo : public TargetInfo {
1257 static const char * const GCCRegNames[];
1258 static const Builtin::Info BuiltinInfo[];
1259 std::vector<StringRef> AvailableFeatures;
1261 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1263 TLSSupported = false;
1264 LongWidth = LongAlign = 64;
1265 AddrSpaceMap = &NVPTXAddrSpaceMap;
1266 // Define available target features
1267 // These must be defined in sorted order!
1268 NoAsmVariants = true;
1270 virtual void getTargetDefines(const LangOptions &Opts,
1271 MacroBuilder &Builder) const {
1272 Builder.defineMacro("__PTX__");
1273 Builder.defineMacro("__NVPTX__");
1275 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1276 unsigned &NumRecords) const {
1277 Records = BuiltinInfo;
1278 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1280 virtual bool hasFeature(StringRef Feature) const {
1281 return Feature == "ptx" || Feature == "nvptx";
1284 virtual void getGCCRegNames(const char * const *&Names,
1285 unsigned &NumNames) const;
1286 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1287 unsigned &NumAliases) const {
1292 virtual bool validateAsmConstraint(const char *&Name,
1293 TargetInfo::ConstraintInfo &info) const {
1297 virtual const char *getClobbers() const {
1298 // FIXME: Is this really right?
1301 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1303 return TargetInfo::CharPtrBuiltinVaList;
1305 virtual bool setCPU(const std::string &Name) {
1306 bool Valid = llvm::StringSwitch<bool>(Name)
1307 .Case("sm_20", true)
1308 .Case("sm_21", true)
1309 .Case("sm_30", true)
1310 .Case("sm_35", true)
1315 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1317 bool Enabled) const;
1320 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1321 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1322 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1324 #include "clang/Basic/BuiltinsNVPTX.def"
1327 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1331 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1332 unsigned &NumNames) const {
1333 Names = GCCRegNames;
1334 NumNames = llvm::array_lengthof(GCCRegNames);
1337 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1339 bool Enabled) const {
1340 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1342 Features[Name] = Enabled;
1349 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1351 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1352 PointerWidth = PointerAlign = 32;
1353 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1355 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1356 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1361 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1363 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1364 PointerWidth = PointerAlign = 64;
1365 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1367 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1368 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1376 static const unsigned R600AddrSpaceMap[] = {
1379 2, // opencl_constant
1385 static const char *DescriptionStringR600 =
1388 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1389 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1390 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1393 static const char *DescriptionStringR600DoubleOps =
1396 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1397 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1398 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1401 static const char *DescriptionStringSI =
1404 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1405 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1406 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1409 class R600TargetInfo : public TargetInfo {
1410 /// \brief The GPU profiles supported by the R600 target.
1418 GK_EVERGREEN_DOUBLE_OPS,
1419 GK_NORTHERN_ISLANDS,
1425 R600TargetInfo(const std::string& triple)
1426 : TargetInfo(triple),
1428 DescriptionString = DescriptionStringR600;
1429 AddrSpaceMap = &R600AddrSpaceMap;
1432 virtual const char * getClobbers() const {
1436 virtual void getGCCRegNames(const char * const *&Names,
1437 unsigned &numNames) const {
1442 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1443 unsigned &NumAliases) const {
1448 virtual bool validateAsmConstraint(const char *&Name,
1449 TargetInfo::ConstraintInfo &info) const {
1453 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1454 unsigned &NumRecords) const {
1460 virtual void getTargetDefines(const LangOptions &Opts,
1461 MacroBuilder &Builder) const {
1462 Builder.defineMacro("__R600__");
1465 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1466 return TargetInfo::CharPtrBuiltinVaList;
1469 virtual bool setCPU(const std::string &Name) {
1470 GPU = llvm::StringSwitch<GPUKind>(Name)
1471 .Case("r600" , GK_R600)
1472 .Case("rv610", GK_R600)
1473 .Case("rv620", GK_R600)
1474 .Case("rv630", GK_R600)
1475 .Case("rv635", GK_R600)
1476 .Case("rs780", GK_R600)
1477 .Case("rs880", GK_R600)
1478 .Case("rv670", GK_R600_DOUBLE_OPS)
1479 .Case("rv710", GK_R700)
1480 .Case("rv730", GK_R700)
1481 .Case("rv740", GK_R700_DOUBLE_OPS)
1482 .Case("rv770", GK_R700_DOUBLE_OPS)
1483 .Case("palm", GK_EVERGREEN)
1484 .Case("cedar", GK_EVERGREEN)
1485 .Case("sumo", GK_EVERGREEN)
1486 .Case("sumo2", GK_EVERGREEN)
1487 .Case("redwood", GK_EVERGREEN)
1488 .Case("juniper", GK_EVERGREEN)
1489 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1490 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1491 .Case("barts", GK_NORTHERN_ISLANDS)
1492 .Case("turks", GK_NORTHERN_ISLANDS)
1493 .Case("caicos", GK_NORTHERN_ISLANDS)
1494 .Case("cayman", GK_CAYMAN)
1495 .Case("aruba", GK_CAYMAN)
1496 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1497 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1498 .Case("verde", GK_SOUTHERN_ISLANDS)
1499 .Case("oland", GK_SOUTHERN_ISLANDS)
1502 if (GPU == GK_NONE) {
1506 // Set the correct data layout
1512 case GK_NORTHERN_ISLANDS:
1513 DescriptionString = DescriptionStringR600;
1515 case GK_R600_DOUBLE_OPS:
1516 case GK_R700_DOUBLE_OPS:
1517 case GK_EVERGREEN_DOUBLE_OPS:
1519 DescriptionString = DescriptionStringR600DoubleOps;
1521 case GK_SOUTHERN_ISLANDS:
1522 DescriptionString = DescriptionStringSI;
1530 } // end anonymous namespace
1533 // MBlaze abstract base class
1534 class MBlazeTargetInfo : public TargetInfo {
1535 static const char * const GCCRegNames[];
1536 static const TargetInfo::GCCRegAlias GCCRegAliases[];
1539 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1540 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1543 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1544 unsigned &NumRecords) const {
1545 // FIXME: Implement.
1550 virtual void getTargetDefines(const LangOptions &Opts,
1551 MacroBuilder &Builder) const;
1553 virtual bool hasFeature(StringRef Feature) const {
1554 return Feature == "mblaze";
1557 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1558 return TargetInfo::CharPtrBuiltinVaList;
1560 virtual const char *getTargetPrefix() const {
1563 virtual void getGCCRegNames(const char * const *&Names,
1564 unsigned &NumNames) const;
1565 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1566 unsigned &NumAliases) const;
1567 virtual bool validateAsmConstraint(const char *&Name,
1568 TargetInfo::ConstraintInfo &Info) const {
1570 default: return false;
1573 case 'b': // Base register
1574 case 'f': // Floating point register
1575 Info.setAllowsRegister();
1579 virtual const char *getClobbers() const {
1584 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1585 /// #defines that are not tied to a specific subtarget.
1586 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1587 MacroBuilder &Builder) const {
1588 // Target identification.
1589 Builder.defineMacro("__microblaze__");
1590 Builder.defineMacro("_ARCH_MICROBLAZE");
1591 Builder.defineMacro("__MICROBLAZE__");
1593 // Target properties.
1594 Builder.defineMacro("_BIG_ENDIAN");
1595 Builder.defineMacro("__BIG_ENDIAN__");
1597 // Subtarget options.
1598 Builder.defineMacro("__REGISTER_PREFIX__", "");
1602 const char * const MBlazeTargetInfo::GCCRegNames[] = {
1603 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1604 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1605 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1606 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1607 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
1608 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1609 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1610 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1611 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1612 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp"
1615 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1616 unsigned &NumNames) const {
1617 Names = GCCRegNames;
1618 NumNames = llvm::array_lengthof(GCCRegNames);
1621 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1656 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1657 unsigned &NumAliases) const {
1658 Aliases = GCCRegAliases;
1659 NumAliases = llvm::array_lengthof(GCCRegAliases);
1661 } // end anonymous namespace.
1664 // Namespace for x86 abstract base class
1665 const Builtin::Info BuiltinInfo[] = {
1666 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1667 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1669 #include "clang/Basic/BuiltinsX86.def"
1672 static const char* const GCCRegNames[] = {
1673 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1674 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1675 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1676 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1677 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1678 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1679 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1680 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1681 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1684 const TargetInfo::AddlRegName AddlRegNames[] = {
1685 { { "al", "ah", "eax", "rax" }, 0 },
1686 { { "bl", "bh", "ebx", "rbx" }, 3 },
1687 { { "cl", "ch", "ecx", "rcx" }, 2 },
1688 { { "dl", "dh", "edx", "rdx" }, 1 },
1689 { { "esi", "rsi" }, 4 },
1690 { { "edi", "rdi" }, 5 },
1691 { { "esp", "rsp" }, 7 },
1692 { { "ebp", "rbp" }, 6 },
1695 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1696 // most of the implementation can be shared.
1697 class X86TargetInfo : public TargetInfo {
1699 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1702 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1721 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1723 /// Each enumeration represents a particular CPU supported by Clang. These
1724 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1729 /// i386-generation processors.
1735 /// i486-generation processors.
1744 /// i586-generation processors, P5 microarchitecture based.
1752 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1762 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1763 /// Clang however has some logic to suport this.
1764 // FIXME: Warn, deprecate, and potentially remove this.
1769 /// Netburst microarchitecture based processors.
1778 /// Core microarchitecture based processors.
1782 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1783 /// codename which GCC no longer accepts as an option to -march, but Clang
1784 /// has some logic for recognizing it.
1785 // FIXME: Warn, deprecate, and potentially remove this.
1796 /// Nehalem microarchitecture based processors.
1805 /// K6 architecture processors.
1813 /// K7 architecture processors.
1816 CK_AthlonThunderbird,
1823 /// K8 architecture processors.
1836 /// Bobcat architecture processors.
1843 /// Bulldozer architecture processors.
1849 /// This specification is deprecated and will be removed in the future.
1850 /// Users should prefer \see CK_K8.
1851 // FIXME: Warn on this when the CPU is set to it.
1856 /// Geode processors.
1863 X86TargetInfo(const std::string& triple)
1864 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1865 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1866 HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1867 HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1868 HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1870 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1872 virtual unsigned getFloatEvalMethod() const {
1873 // X87 evaluates with 80 bits "long double" precision.
1874 return SSELevel == NoSSE ? 2 : 0;
1876 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1877 unsigned &NumRecords) const {
1878 Records = BuiltinInfo;
1879 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1881 virtual void getGCCRegNames(const char * const *&Names,
1882 unsigned &NumNames) const {
1883 Names = GCCRegNames;
1884 NumNames = llvm::array_lengthof(GCCRegNames);
1886 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1887 unsigned &NumAliases) const {
1891 virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1892 unsigned &NumNames) const {
1893 Names = AddlRegNames;
1894 NumNames = llvm::array_lengthof(AddlRegNames);
1896 virtual bool validateAsmConstraint(const char *&Name,
1897 TargetInfo::ConstraintInfo &info) const;
1898 virtual std::string convertConstraint(const char *&Constraint) const;
1899 virtual const char *getClobbers() const {
1900 return "~{dirflag},~{fpsr},~{flags}";
1902 virtual void getTargetDefines(const LangOptions &Opts,
1903 MacroBuilder &Builder) const;
1904 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1906 bool Enabled) const;
1907 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1908 virtual bool hasFeature(StringRef Feature) const;
1909 virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1910 virtual const char* getABI() const {
1911 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1913 else if (getTriple().getArch() == llvm::Triple::x86 &&
1914 MMX3DNowLevel == NoMMX3DNow)
1918 virtual bool setCPU(const std::string &Name) {
1919 CPU = llvm::StringSwitch<CPUKind>(Name)
1920 .Case("i386", CK_i386)
1921 .Case("i486", CK_i486)
1922 .Case("winchip-c6", CK_WinChipC6)
1923 .Case("winchip2", CK_WinChip2)
1925 .Case("i586", CK_i586)
1926 .Case("pentium", CK_Pentium)
1927 .Case("pentium-mmx", CK_PentiumMMX)
1928 .Case("i686", CK_i686)
1929 .Case("pentiumpro", CK_PentiumPro)
1930 .Case("pentium2", CK_Pentium2)
1931 .Case("pentium3", CK_Pentium3)
1932 .Case("pentium3m", CK_Pentium3M)
1933 .Case("pentium-m", CK_PentiumM)
1934 .Case("c3-2", CK_C3_2)
1935 .Case("yonah", CK_Yonah)
1936 .Case("pentium4", CK_Pentium4)
1937 .Case("pentium4m", CK_Pentium4M)
1938 .Case("prescott", CK_Prescott)
1939 .Case("nocona", CK_Nocona)
1940 .Case("core2", CK_Core2)
1941 .Case("penryn", CK_Penryn)
1942 .Case("atom", CK_Atom)
1943 .Case("corei7", CK_Corei7)
1944 .Case("corei7-avx", CK_Corei7AVX)
1945 .Case("core-avx-i", CK_CoreAVXi)
1946 .Case("core-avx2", CK_CoreAVX2)
1948 .Case("k6-2", CK_K6_2)
1949 .Case("k6-3", CK_K6_3)
1950 .Case("athlon", CK_Athlon)
1951 .Case("athlon-tbird", CK_AthlonThunderbird)
1952 .Case("athlon-4", CK_Athlon4)
1953 .Case("athlon-xp", CK_AthlonXP)
1954 .Case("athlon-mp", CK_AthlonMP)
1955 .Case("athlon64", CK_Athlon64)
1956 .Case("athlon64-sse3", CK_Athlon64SSE3)
1957 .Case("athlon-fx", CK_AthlonFX)
1959 .Case("k8-sse3", CK_K8SSE3)
1960 .Case("opteron", CK_Opteron)
1961 .Case("opteron-sse3", CK_OpteronSSE3)
1962 .Case("amdfam10", CK_AMDFAM10)
1963 .Case("btver1", CK_BTVER1)
1964 .Case("btver2", CK_BTVER2)
1965 .Case("bdver1", CK_BDVER1)
1966 .Case("bdver2", CK_BDVER2)
1967 .Case("x86-64", CK_x86_64)
1968 .Case("geode", CK_Geode)
1969 .Default(CK_Generic);
1971 // Perform any per-CPU checks necessary to determine if this CPU is
1973 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1974 // invalid without explaining *why*.
1977 // No processor selected!
2003 case CK_AthlonThunderbird:
2008 // Only accept certain architectures when compiling in 32-bit mode.
2009 if (getTriple().getArch() != llvm::Triple::x86)
2022 case CK_Athlon64SSE3:
2027 case CK_OpteronSSE3:
2036 llvm_unreachable("Unhandled CPU kind");
2039 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2040 // We accept all non-ARM calling conventions
2041 return (CC == CC_X86ThisCall ||
2042 CC == CC_X86FastCall ||
2043 CC == CC_X86StdCall ||
2045 CC == CC_X86Pascal ||
2046 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2049 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2050 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2054 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2055 // FIXME: This should not be here.
2056 Features["3dnow"] = false;
2057 Features["3dnowa"] = false;
2058 Features["mmx"] = false;
2059 Features["sse"] = false;
2060 Features["sse2"] = false;
2061 Features["sse3"] = false;
2062 Features["ssse3"] = false;
2063 Features["sse41"] = false;
2064 Features["sse42"] = false;
2065 Features["sse4a"] = false;
2066 Features["aes"] = false;
2067 Features["pclmul"] = false;
2068 Features["avx"] = false;
2069 Features["avx2"] = false;
2070 Features["lzcnt"] = false;
2071 Features["rdrand"] = false;
2072 Features["bmi"] = false;
2073 Features["bmi2"] = false;
2074 Features["popcnt"] = false;
2075 Features["rtm"] = false;
2076 Features["prfchw"] = false;
2077 Features["rdseed"] = false;
2078 Features["fma4"] = false;
2079 Features["fma"] = false;
2080 Features["xop"] = false;
2081 Features["f16c"] = false;
2083 // FIXME: This *really* should not be here.
2085 // X86_64 always has SSE2.
2086 if (getTriple().getArch() == llvm::Triple::x86_64)
2087 setFeatureEnabled(Features, "sse2", true);
2100 setFeatureEnabled(Features, "mmx", true);
2104 setFeatureEnabled(Features, "sse", true);
2110 setFeatureEnabled(Features, "sse2", true);
2115 setFeatureEnabled(Features, "sse3", true);
2118 setFeatureEnabled(Features, "ssse3", true);
2121 setFeatureEnabled(Features, "sse4.1", true);
2124 setFeatureEnabled(Features, "ssse3", true);
2127 setFeatureEnabled(Features, "sse4", true);
2130 setFeatureEnabled(Features, "avx", true);
2131 setFeatureEnabled(Features, "aes", true);
2132 setFeatureEnabled(Features, "pclmul", true);
2135 setFeatureEnabled(Features, "avx", true);
2136 setFeatureEnabled(Features, "aes", true);
2137 setFeatureEnabled(Features, "pclmul", true);
2138 setFeatureEnabled(Features, "rdrnd", true);
2139 setFeatureEnabled(Features, "f16c", true);
2142 setFeatureEnabled(Features, "avx2", true);
2143 setFeatureEnabled(Features, "aes", true);
2144 setFeatureEnabled(Features, "pclmul", true);
2145 setFeatureEnabled(Features, "lzcnt", true);
2146 setFeatureEnabled(Features, "rdrnd", true);
2147 setFeatureEnabled(Features, "f16c", true);
2148 setFeatureEnabled(Features, "bmi", true);
2149 setFeatureEnabled(Features, "bmi2", true);
2150 setFeatureEnabled(Features, "rtm", true);
2151 setFeatureEnabled(Features, "fma", true);
2155 setFeatureEnabled(Features, "mmx", true);
2161 setFeatureEnabled(Features, "3dnow", true);
2164 case CK_AthlonThunderbird:
2166 setFeatureEnabled(Features, "3dnowa", true);
2171 setFeatureEnabled(Features, "sse", true);
2172 setFeatureEnabled(Features, "3dnowa", true);
2178 setFeatureEnabled(Features, "sse2", true);
2179 setFeatureEnabled(Features, "3dnowa", true);
2182 case CK_OpteronSSE3:
2183 case CK_Athlon64SSE3:
2184 setFeatureEnabled(Features, "sse3", true);
2185 setFeatureEnabled(Features, "3dnowa", true);
2188 setFeatureEnabled(Features, "sse3", true);
2189 setFeatureEnabled(Features, "sse4a", true);
2190 setFeatureEnabled(Features, "3dnowa", true);
2191 setFeatureEnabled(Features, "lzcnt", true);
2192 setFeatureEnabled(Features, "popcnt", true);
2195 setFeatureEnabled(Features, "ssse3", true);
2196 setFeatureEnabled(Features, "sse4a", true);
2197 setFeatureEnabled(Features, "lzcnt", true);
2198 setFeatureEnabled(Features, "popcnt", true);
2201 setFeatureEnabled(Features, "avx", true);
2202 setFeatureEnabled(Features, "sse4a", true);
2203 setFeatureEnabled(Features, "lzcnt", true);
2204 setFeatureEnabled(Features, "aes", true);
2205 setFeatureEnabled(Features, "pclmul", true);
2206 setFeatureEnabled(Features, "bmi", true);
2207 setFeatureEnabled(Features, "f16c", true);
2210 setFeatureEnabled(Features, "xop", true);
2211 setFeatureEnabled(Features, "lzcnt", true);
2212 setFeatureEnabled(Features, "aes", true);
2213 setFeatureEnabled(Features, "pclmul", true);
2216 setFeatureEnabled(Features, "xop", true);
2217 setFeatureEnabled(Features, "lzcnt", true);
2218 setFeatureEnabled(Features, "aes", true);
2219 setFeatureEnabled(Features, "pclmul", true);
2220 setFeatureEnabled(Features, "bmi", true);
2221 setFeatureEnabled(Features, "fma", true);
2222 setFeatureEnabled(Features, "f16c", true);
2225 setFeatureEnabled(Features, "sse", true);
2230 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2232 bool Enabled) const {
2233 // FIXME: This *really* should not be here. We need some way of translating
2234 // options into llvm subtarget features.
2235 if (!Features.count(Name) &&
2236 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2240 // FIXME: this should probably use a switch with fall through.
2244 Features["mmx"] = true;
2245 else if (Name == "sse")
2246 Features["mmx"] = Features["sse"] = true;
2247 else if (Name == "sse2")
2248 Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2249 else if (Name == "sse3")
2250 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2252 else if (Name == "ssse3")
2253 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2254 Features["ssse3"] = true;
2255 else if (Name == "sse4" || Name == "sse4.2")
2256 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2257 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2258 Features["popcnt"] = true;
2259 else if (Name == "sse4.1")
2260 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2261 Features["ssse3"] = Features["sse41"] = true;
2262 else if (Name == "3dnow")
2263 Features["mmx"] = Features["3dnow"] = true;
2264 else if (Name == "3dnowa")
2265 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2266 else if (Name == "aes")
2267 Features["sse"] = Features["sse2"] = Features["aes"] = true;
2268 else if (Name == "pclmul")
2269 Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2270 else if (Name == "avx")
2271 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2272 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2273 Features["popcnt"] = Features["avx"] = true;
2274 else if (Name == "avx2")
2275 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2276 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2277 Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2278 else if (Name == "fma")
2279 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2280 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2281 Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2282 else if (Name == "fma4")
2283 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2284 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2285 Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2286 Features["fma4"] = true;
2287 else if (Name == "xop")
2288 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2289 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2290 Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2291 Features["fma4"] = Features["xop"] = true;
2292 else if (Name == "sse4a")
2293 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2294 Features["sse4a"] = true;
2295 else if (Name == "lzcnt")
2296 Features["lzcnt"] = true;
2297 else if (Name == "rdrnd")
2298 Features["rdrand"] = true;
2299 else if (Name == "bmi")
2300 Features["bmi"] = true;
2301 else if (Name == "bmi2")
2302 Features["bmi2"] = true;
2303 else if (Name == "popcnt")
2304 Features["popcnt"] = true;
2305 else if (Name == "f16c")
2306 Features["f16c"] = true;
2307 else if (Name == "rtm")
2308 Features["rtm"] = true;
2309 else if (Name == "prfchw")
2310 Features["prfchw"] = true;
2311 else if (Name == "rdseed")
2312 Features["rdseed"] = true;
2315 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2316 else if (Name == "sse")
2317 Features["sse"] = Features["sse2"] = Features["sse3"] =
2318 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2319 Features["sse4a"] = Features["avx"] = Features["avx2"] =
2320 Features["fma"] = Features["fma4"] = Features["aes"] =
2321 Features["pclmul"] = Features["xop"] = false;
2322 else if (Name == "sse2")
2323 Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2324 Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2325 Features["avx"] = Features["avx2"] = Features["fma"] =
2326 Features["fma4"] = Features["aes"] = Features["pclmul"] =
2327 Features["xop"] = false;
2328 else if (Name == "sse3")
2329 Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2330 Features["sse42"] = Features["sse4a"] = Features["avx"] =
2331 Features["avx2"] = Features["fma"] = Features["fma4"] =
2332 Features["xop"] = false;
2333 else if (Name == "ssse3")
2334 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2335 Features["avx"] = Features["avx2"] = Features["fma"] = false;
2336 else if (Name == "sse4" || Name == "sse4.1")
2337 Features["sse41"] = Features["sse42"] = Features["avx"] =
2338 Features["avx2"] = Features["fma"] = false;
2339 else if (Name == "sse4.2")
2340 Features["sse42"] = Features["avx"] = Features["avx2"] =
2341 Features["fma"] = false;
2342 else if (Name == "3dnow")
2343 Features["3dnow"] = Features["3dnowa"] = false;
2344 else if (Name == "3dnowa")
2345 Features["3dnowa"] = false;
2346 else if (Name == "aes")
2347 Features["aes"] = false;
2348 else if (Name == "pclmul")
2349 Features["pclmul"] = false;
2350 else if (Name == "avx")
2351 Features["avx"] = Features["avx2"] = Features["fma"] =
2352 Features["fma4"] = Features["xop"] = false;
2353 else if (Name == "avx2")
2354 Features["avx2"] = false;
2355 else if (Name == "fma")
2356 Features["fma"] = false;
2357 else if (Name == "sse4a")
2358 Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2359 else if (Name == "lzcnt")
2360 Features["lzcnt"] = false;
2361 else if (Name == "rdrnd")
2362 Features["rdrand"] = false;
2363 else if (Name == "bmi")
2364 Features["bmi"] = false;
2365 else if (Name == "bmi2")
2366 Features["bmi2"] = false;
2367 else if (Name == "popcnt")
2368 Features["popcnt"] = false;
2369 else if (Name == "fma4")
2370 Features["fma4"] = Features["xop"] = false;
2371 else if (Name == "xop")
2372 Features["xop"] = false;
2373 else if (Name == "f16c")
2374 Features["f16c"] = false;
2375 else if (Name == "rtm")
2376 Features["rtm"] = false;
2377 else if (Name == "prfchw")
2378 Features["prfchw"] = false;
2379 else if (Name == "rdseed")
2380 Features["rdseed"] = false;
2386 /// HandleTargetOptions - Perform initialization based on the user
2387 /// configured set of features.
2388 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2389 // Remember the maximum enabled sselevel.
2390 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2391 // Ignore disabled features.
2392 if (Features[i][0] == '-')
2395 StringRef Feature = StringRef(Features[i]).substr(1);
2397 if (Feature == "aes") {
2402 if (Feature == "pclmul") {
2407 if (Feature == "lzcnt") {
2412 if (Feature == "rdrand") {
2417 if (Feature == "bmi") {
2422 if (Feature == "bmi2") {
2427 if (Feature == "popcnt") {
2432 if (Feature == "rtm") {
2437 if (Feature == "prfchw") {
2442 if (Feature == "rdseed") {
2447 if (Feature == "sse4a") {
2452 if (Feature == "fma4") {
2457 if (Feature == "fma") {
2462 if (Feature == "xop") {
2467 if (Feature == "f16c") {
2472 assert(Features[i][0] == '+' && "Invalid target feature!");
2473 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2476 .Case("sse42", SSE42)
2477 .Case("sse41", SSE41)
2478 .Case("ssse3", SSSE3)
2483 SSELevel = std::max(SSELevel, Level);
2485 MMX3DNowEnum ThreeDNowLevel =
2486 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2487 .Case("3dnowa", AMD3DNowAthlon)
2488 .Case("3dnow", AMD3DNow)
2490 .Default(NoMMX3DNow);
2492 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2495 // Don't tell the backend if we're turning off mmx; it will end up disabling
2496 // SSE, which we don't want.
2497 std::vector<std::string>::iterator it;
2498 it = std::find(Features.begin(), Features.end(), "-mmx");
2499 if (it != Features.end())
2503 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2504 /// definitions for this particular subtarget.
2505 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2506 MacroBuilder &Builder) const {
2507 // Target identification.
2508 if (getTriple().getArch() == llvm::Triple::x86_64) {
2509 Builder.defineMacro("__amd64__");
2510 Builder.defineMacro("__amd64");
2511 Builder.defineMacro("__x86_64");
2512 Builder.defineMacro("__x86_64__");
2514 DefineStd(Builder, "i386", Opts);
2517 // Subtarget options.
2518 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2519 // truly should be based on -mtune options.
2524 // The rest are coming from the i386 define above.
2525 Builder.defineMacro("__tune_i386__");
2531 defineCPUMacros(Builder, "i486");
2534 Builder.defineMacro("__pentium_mmx__");
2535 Builder.defineMacro("__tune_pentium_mmx__");
2539 defineCPUMacros(Builder, "i586");
2540 defineCPUMacros(Builder, "pentium");
2545 Builder.defineMacro("__tune_pentium3__");
2549 Builder.defineMacro("__tune_pentium2__");
2552 Builder.defineMacro("__tune_i686__");
2553 Builder.defineMacro("__tune_pentiumpro__");
2556 Builder.defineMacro("__i686");
2557 Builder.defineMacro("__i686__");
2558 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2559 Builder.defineMacro("__pentiumpro");
2560 Builder.defineMacro("__pentiumpro__");
2564 defineCPUMacros(Builder, "pentium4");
2569 defineCPUMacros(Builder, "nocona");
2573 defineCPUMacros(Builder, "core2");
2576 defineCPUMacros(Builder, "atom");
2582 defineCPUMacros(Builder, "corei7");
2585 Builder.defineMacro("__k6_2__");
2586 Builder.defineMacro("__tune_k6_2__");
2589 if (CPU != CK_K6_2) { // In case of fallthrough
2590 // FIXME: GCC may be enabling these in cases where some other k6
2591 // architecture is specified but -m3dnow is explicitly provided. The
2592 // exact semantics need to be determined and emulated here.
2593 Builder.defineMacro("__k6_3__");
2594 Builder.defineMacro("__tune_k6_3__");
2598 defineCPUMacros(Builder, "k6");
2601 case CK_AthlonThunderbird:
2605 defineCPUMacros(Builder, "athlon");
2606 if (SSELevel != NoSSE) {
2607 Builder.defineMacro("__athlon_sse__");
2608 Builder.defineMacro("__tune_athlon_sse__");
2615 case CK_OpteronSSE3:
2617 case CK_Athlon64SSE3:
2619 defineCPUMacros(Builder, "k8");
2622 defineCPUMacros(Builder, "amdfam10");
2625 defineCPUMacros(Builder, "btver1");
2628 defineCPUMacros(Builder, "btver2");
2631 defineCPUMacros(Builder, "bdver1");
2634 defineCPUMacros(Builder, "bdver2");
2637 defineCPUMacros(Builder, "geode");
2641 // Target properties.
2642 Builder.defineMacro("__LITTLE_ENDIAN__");
2643 Builder.defineMacro("__REGISTER_PREFIX__", "");
2645 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2646 // functions in glibc header files that use FP Stack inline asm which the
2647 // backend can't deal with (PR879).
2648 Builder.defineMacro("__NO_MATH_INLINES");
2651 Builder.defineMacro("__AES__");
2654 Builder.defineMacro("__PCLMUL__");
2657 Builder.defineMacro("__LZCNT__");
2660 Builder.defineMacro("__RDRND__");
2663 Builder.defineMacro("__BMI__");
2666 Builder.defineMacro("__BMI2__");
2669 Builder.defineMacro("__POPCNT__");
2672 Builder.defineMacro("__RTM__");
2675 Builder.defineMacro("__PRFCHW__");
2678 Builder.defineMacro("__RDSEED__");
2681 Builder.defineMacro("__SSE4A__");
2684 Builder.defineMacro("__FMA4__");
2687 Builder.defineMacro("__FMA__");
2690 Builder.defineMacro("__XOP__");
2693 Builder.defineMacro("__F16C__");
2695 // Each case falls through to the previous one here.
2698 Builder.defineMacro("__AVX2__");
2700 Builder.defineMacro("__AVX__");
2702 Builder.defineMacro("__SSE4_2__");
2704 Builder.defineMacro("__SSE4_1__");
2706 Builder.defineMacro("__SSSE3__");
2708 Builder.defineMacro("__SSE3__");
2710 Builder.defineMacro("__SSE2__");
2711 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
2713 Builder.defineMacro("__SSE__");
2714 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
2719 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2728 Builder.defineMacro("_M_IX86_FP", Twine(2));
2731 Builder.defineMacro("_M_IX86_FP", Twine(1));
2734 Builder.defineMacro("_M_IX86_FP", Twine(0));
2738 // Each case falls through to the previous one here.
2739 switch (MMX3DNowLevel) {
2740 case AMD3DNowAthlon:
2741 Builder.defineMacro("__3dNOW_A__");
2743 Builder.defineMacro("__3dNOW__");
2745 Builder.defineMacro("__MMX__");
2750 if (CPU >= CK_i486) {
2751 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2752 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2753 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2756 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2759 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2760 return llvm::StringSwitch<bool>(Feature)
2761 .Case("aes", HasAES)
2762 .Case("avx", SSELevel >= AVX)
2763 .Case("avx2", SSELevel >= AVX2)
2764 .Case("bmi", HasBMI)
2765 .Case("bmi2", HasBMI2)
2766 .Case("fma", HasFMA)
2767 .Case("fma4", HasFMA4)
2768 .Case("lzcnt", HasLZCNT)
2769 .Case("rdrnd", HasRDRND)
2770 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2771 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2772 .Case("mmx", MMX3DNowLevel >= MMX)
2773 .Case("pclmul", HasPCLMUL)
2774 .Case("popcnt", HasPOPCNT)
2775 .Case("rtm", HasRTM)
2776 .Case("prfchw", HasPRFCHW)
2777 .Case("rdseed", HasRDSEED)
2778 .Case("sse", SSELevel >= SSE1)
2779 .Case("sse2", SSELevel >= SSE2)
2780 .Case("sse3", SSELevel >= SSE3)
2781 .Case("ssse3", SSELevel >= SSSE3)
2782 .Case("sse41", SSELevel >= SSE41)
2783 .Case("sse42", SSELevel >= SSE42)
2784 .Case("sse4a", HasSSE4a)
2786 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2787 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2788 .Case("xop", HasXOP)
2789 .Case("f16c", HasF16C)
2794 X86TargetInfo::validateAsmConstraint(const char *&Name,
2795 TargetInfo::ConstraintInfo &Info) const {
2797 default: return false;
2798 case 'Y': // first letter of a pair:
2799 switch (*(Name+1)) {
2800 default: return false;
2801 case '0': // First SSE register.
2802 case 't': // Any SSE register, when SSE2 is enabled.
2803 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
2804 case 'm': // any MMX register, when inter-unit moves enabled.
2805 break; // falls through to setAllowsRegister.
2813 case 'A': // edx:eax.
2814 case 'f': // any x87 floating point stack register.
2815 case 't': // top of floating point stack.
2816 case 'u': // second from top of floating point stack.
2817 case 'q': // Any register accessible as [r]l: a, b, c, and d.
2818 case 'y': // Any MMX register.
2819 case 'x': // Any SSE register.
2820 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2821 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2822 case 'l': // "Index" registers: any general register that can be used as an
2823 // index in a base+index memory access.
2824 Info.setAllowsRegister();
2826 case 'C': // SSE floating point constant.
2827 case 'G': // x87 floating point constant.
2828 case 'e': // 32-bit signed integer constant for use with zero-extending
2829 // x86_64 instructions.
2830 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2831 // x86_64 instructions.
2838 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2839 switch (*Constraint) {
2840 case 'a': return std::string("{ax}");
2841 case 'b': return std::string("{bx}");
2842 case 'c': return std::string("{cx}");
2843 case 'd': return std::string("{dx}");
2844 case 'S': return std::string("{si}");
2845 case 'D': return std::string("{di}");
2846 case 'p': // address
2847 return std::string("im");
2848 case 't': // top of floating point stack.
2849 return std::string("{st}");
2850 case 'u': // second from top of floating point stack.
2851 return std::string("{st(1)}"); // second from top of floating point stack.
2853 return std::string(1, *Constraint);
2856 } // end anonymous namespace
2859 // X86-32 generic target
2860 class X86_32TargetInfo : public X86TargetInfo {
2862 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2863 DoubleAlign = LongLongAlign = 32;
2864 LongDoubleWidth = 96;
2865 LongDoubleAlign = 32;
2866 SuitableAlign = 128;
2867 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2868 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2869 "a0:0:64-f80:32:32-n8:16:32-S128";
2870 SizeType = UnsignedInt;
2871 PtrDiffType = SignedInt;
2872 IntPtrType = SignedInt;
2875 // Use fpret for all types.
2876 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2877 (1 << TargetInfo::Double) |
2878 (1 << TargetInfo::LongDouble));
2880 // x86-32 has atomics up to 8 bytes
2881 // FIXME: Check that we actually have cmpxchg8b before setting
2882 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2883 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2885 virtual BuiltinVaListKind getBuiltinVaListKind() const {
2886 return TargetInfo::CharPtrBuiltinVaList;
2889 int getEHDataRegisterNumber(unsigned RegNo) const {
2890 if (RegNo == 0) return 0;
2891 if (RegNo == 1) return 2;
2894 virtual bool validateInputSize(StringRef Constraint,
2895 unsigned Size) const {
2896 switch (Constraint[0]) {
2908 } // end anonymous namespace
2911 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2913 NetBSDI386TargetInfo(const std::string &triple) :
2914 NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2917 virtual unsigned getFloatEvalMethod() const {
2918 // NetBSD defaults to "double" rounding
2922 } // end anonymous namespace
2925 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2927 OpenBSDI386TargetInfo(const std::string& triple) :
2928 OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2929 SizeType = UnsignedLong;
2930 IntPtrType = SignedLong;
2931 PtrDiffType = SignedLong;
2934 } // end anonymous namespace
2937 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2939 BitrigI386TargetInfo(const std::string& triple) :
2940 BitrigTargetInfo<X86_32TargetInfo>(triple) {
2941 SizeType = UnsignedLong;
2942 IntPtrType = SignedLong;
2943 PtrDiffType = SignedLong;
2946 } // end anonymous namespace
2949 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2951 DarwinI386TargetInfo(const std::string& triple) :
2952 DarwinTargetInfo<X86_32TargetInfo>(triple) {
2953 LongDoubleWidth = 128;
2954 LongDoubleAlign = 128;
2955 SuitableAlign = 128;
2956 MaxVectorAlign = 256;
2957 SizeType = UnsignedLong;
2958 IntPtrType = SignedLong;
2959 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2960 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2961 "a0:0:64-f80:128:128-n8:16:32-S128";
2962 HasAlignMac68kSupport = true;
2966 } // end anonymous namespace
2969 // x86-32 Windows target
2970 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2972 WindowsX86_32TargetInfo(const std::string& triple)
2973 : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2974 TLSSupported = false;
2975 WCharType = UnsignedShort;
2976 DoubleAlign = LongLongAlign = 64;
2977 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2978 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2979 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2981 virtual void getTargetDefines(const LangOptions &Opts,
2982 MacroBuilder &Builder) const {
2983 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2986 } // end anonymous namespace
2990 // x86-32 Windows Visual Studio target
2991 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2993 VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2994 : WindowsX86_32TargetInfo(triple) {
2995 LongDoubleWidth = LongDoubleAlign = 64;
2996 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2998 virtual void getTargetDefines(const LangOptions &Opts,
2999 MacroBuilder &Builder) const {
3000 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3001 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3002 // The value of the following reflects processor type.
3003 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3004 // We lost the original triple, so we use the default.
3005 Builder.defineMacro("_M_IX86", "600");
3008 } // end anonymous namespace
3011 // x86-32 MinGW target
3012 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3014 MinGWX86_32TargetInfo(const std::string& triple)
3015 : WindowsX86_32TargetInfo(triple) {
3017 virtual void getTargetDefines(const LangOptions &Opts,
3018 MacroBuilder &Builder) const {
3019 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3020 DefineStd(Builder, "WIN32", Opts);
3021 DefineStd(Builder, "WINNT", Opts);
3022 Builder.defineMacro("_X86_");
3023 Builder.defineMacro("__MSVCRT__");
3024 Builder.defineMacro("__MINGW32__");
3026 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3027 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3028 if (Opts.MicrosoftExt)
3029 // Provide "as-is" __declspec.
3030 Builder.defineMacro("__declspec", "__declspec");
3032 // Provide alias of __attribute__ like mingw32-gcc.
3033 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3036 } // end anonymous namespace
3039 // x86-32 Cygwin target
3040 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3042 CygwinX86_32TargetInfo(const std::string& triple)
3043 : X86_32TargetInfo(triple) {
3044 TLSSupported = false;
3045 WCharType = UnsignedShort;
3046 DoubleAlign = LongLongAlign = 64;
3047 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3048 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3049 "a0:0:64-f80:32:32-n8:16:32-S32";
3051 virtual void getTargetDefines(const LangOptions &Opts,
3052 MacroBuilder &Builder) const {
3053 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3054 Builder.defineMacro("_X86_");
3055 Builder.defineMacro("__CYGWIN__");
3056 Builder.defineMacro("__CYGWIN32__");
3057 DefineStd(Builder, "unix", Opts);
3059 Builder.defineMacro("_GNU_SOURCE");
3062 } // end anonymous namespace
3065 // x86-32 Haiku target
3066 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3068 HaikuX86_32TargetInfo(const std::string& triple)
3069 : X86_32TargetInfo(triple) {
3070 SizeType = UnsignedLong;
3071 IntPtrType = SignedLong;
3072 PtrDiffType = SignedLong;
3073 ProcessIDType = SignedLong;
3074 this->UserLabelPrefix = "";
3075 this->TLSSupported = false;
3077 virtual void getTargetDefines(const LangOptions &Opts,
3078 MacroBuilder &Builder) const {
3079 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3080 Builder.defineMacro("__INTEL__");
3081 Builder.defineMacro("__HAIKU__");
3084 } // end anonymous namespace
3087 template<typename Target>
3088 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3090 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3091 MacroBuilder &Builder) const {
3092 // RTEMS defines; list based off of gcc output
3094 Builder.defineMacro("__rtems__");
3095 Builder.defineMacro("__ELF__");
3098 RTEMSTargetInfo(const std::string &triple)
3099 : OSTargetInfo<Target>(triple) {
3100 this->UserLabelPrefix = "";
3102 llvm::Triple Triple(triple);
3103 switch (Triple.getArch()) {
3105 case llvm::Triple::x86:
3106 // this->MCountName = ".mcount";
3108 case llvm::Triple::mips:
3109 case llvm::Triple::mipsel:
3110 case llvm::Triple::ppc:
3111 case llvm::Triple::ppc64:
3112 // this->MCountName = "_mcount";
3114 case llvm::Triple::arm:
3115 // this->MCountName = "__mcount";
3123 // x86-32 RTEMS target
3124 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3126 RTEMSX86_32TargetInfo(const std::string& triple)
3127 : X86_32TargetInfo(triple) {
3128 SizeType = UnsignedLong;
3129 IntPtrType = SignedLong;
3130 PtrDiffType = SignedLong;
3131 this->UserLabelPrefix = "";
3133 virtual void getTargetDefines(const LangOptions &Opts,
3134 MacroBuilder &Builder) const {
3135 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3136 Builder.defineMacro("__INTEL__");
3137 Builder.defineMacro("__rtems__");
3140 } // end anonymous namespace
3143 // x86-64 generic target
3144 class X86_64TargetInfo : public X86TargetInfo {
3146 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
3147 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3148 LongDoubleWidth = 128;
3149 LongDoubleAlign = 128;
3150 LargeArrayMinWidth = 128;
3151 LargeArrayAlign = 128;
3152 SuitableAlign = 128;
3153 IntMaxType = SignedLong;
3154 UIntMaxType = UnsignedLong;
3155 Int64Type = SignedLong;
3158 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3159 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3160 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3162 // Use fpret only for long double.
3163 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3165 // Use fp2ret for _Complex long double.
3166 ComplexLongDoubleUsesFP2Ret = true;
3168 // x86-64 has atomics up to 16 bytes.
3169 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3170 // on CPUs with cmpxchg16b
3171 MaxAtomicPromoteWidth = 128;
3172 MaxAtomicInlineWidth = 64;
3174 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3175 return TargetInfo::X86_64ABIBuiltinVaList;
3178 int getEHDataRegisterNumber(unsigned RegNo) const {
3179 if (RegNo == 0) return 0;
3180 if (RegNo == 1) return 1;
3184 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3185 return (CC == CC_Default ||
3187 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3190 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3195 } // end anonymous namespace
3198 // x86-64 Windows target
3199 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3201 WindowsX86_64TargetInfo(const std::string& triple)
3202 : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3203 TLSSupported = false;
3204 WCharType = UnsignedShort;
3205 LongWidth = LongAlign = 32;
3206 DoubleAlign = LongLongAlign = 64;
3207 IntMaxType = SignedLongLong;
3208 UIntMaxType = UnsignedLongLong;
3209 Int64Type = SignedLongLong;
3210 SizeType = UnsignedLongLong;
3211 PtrDiffType = SignedLongLong;
3212 IntPtrType = SignedLongLong;
3213 this->UserLabelPrefix = "";
3215 virtual void getTargetDefines(const LangOptions &Opts,
3216 MacroBuilder &Builder) const {
3217 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3218 Builder.defineMacro("_WIN64");
3220 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3221 return TargetInfo::CharPtrBuiltinVaList;
3224 } // end anonymous namespace
3227 // x86-64 Windows Visual Studio target
3228 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3230 VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3231 : WindowsX86_64TargetInfo(triple) {
3232 LongDoubleWidth = LongDoubleAlign = 64;
3233 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3235 virtual void getTargetDefines(const LangOptions &Opts,
3236 MacroBuilder &Builder) const {
3237 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3238 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3239 Builder.defineMacro("_M_X64");
3240 Builder.defineMacro("_M_AMD64");
3243 } // end anonymous namespace
3246 // x86-64 MinGW target
3247 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3249 MinGWX86_64TargetInfo(const std::string& triple)
3250 : WindowsX86_64TargetInfo(triple) {
3252 virtual void getTargetDefines(const LangOptions &Opts,
3253 MacroBuilder &Builder) const {
3254 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3255 DefineStd(Builder, "WIN64", Opts);
3256 Builder.defineMacro("__MSVCRT__");
3257 Builder.defineMacro("__MINGW32__");
3258 Builder.defineMacro("__MINGW64__");
3260 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3261 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3262 if (Opts.MicrosoftExt)
3263 // Provide "as-is" __declspec.
3264 Builder.defineMacro("__declspec", "__declspec");
3266 // Provide alias of __attribute__ like mingw32-gcc.
3267 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3270 } // end anonymous namespace
3273 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3275 DarwinX86_64TargetInfo(const std::string& triple)
3276 : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3277 Int64Type = SignedLongLong;
3278 MaxVectorAlign = 256;
3281 } // end anonymous namespace
3284 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3286 OpenBSDX86_64TargetInfo(const std::string& triple)
3287 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3288 IntMaxType = SignedLongLong;
3289 UIntMaxType = UnsignedLongLong;
3290 Int64Type = SignedLongLong;
3293 } // end anonymous namespace
3296 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3298 BitrigX86_64TargetInfo(const std::string& triple)
3299 : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3300 IntMaxType = SignedLongLong;
3301 UIntMaxType = UnsignedLongLong;
3302 Int64Type = SignedLongLong;
3308 class AArch64TargetInfo : public TargetInfo {
3309 static const char * const GCCRegNames[];
3310 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3312 static const Builtin::Info BuiltinInfo[];
3314 AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3316 LongWidth = LongAlign = 64;
3317 LongDoubleWidth = LongDoubleAlign = 128;
3318 PointerWidth = PointerAlign = 64;
3319 SuitableAlign = 128;
3320 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3321 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3322 "f128:128:128-n32:64-S128";
3324 WCharType = UnsignedInt;
3325 LongDoubleFormat = &llvm::APFloat::IEEEquad;
3327 // AArch64 backend supports 64-bit operations at the moment. In principle
3328 // 128-bit is possible if register-pairs are used.
3329 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3331 TheCXXABI.set(TargetCXXABI::GenericAArch64);
3333 virtual void getTargetDefines(const LangOptions &Opts,
3334 MacroBuilder &Builder) const {
3335 // GCC defines theses currently
3336 Builder.defineMacro("__aarch64__");
3337 Builder.defineMacro("__AARCH64EL__");
3339 // ACLE predefines. Many can only have one possible value on v8 AArch64.
3341 // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3342 // which was intended to be compatible with a 64-bit implementation. They
3343 // will need updating when a real 64-bit ACLE exists. Particularly pressing
3344 // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3345 Builder.defineMacro("__ARM_ACLE", "101");
3346 Builder.defineMacro("__ARM_ARCH", "8");
3347 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3349 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3350 Builder.defineMacro("__ARM_FEATURE_CLZ");
3351 Builder.defineMacro("__ARM_FEATURE_FMA");
3353 // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3354 // 128-bit LDXP present, at which point this becomes 0x1f.
3355 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3357 // 0xe implies support for half, single and double precision operations.
3358 Builder.defineMacro("__ARM_FP", "0xe");
3360 // PCS specifies this for SysV variants, which is all we support. Other ABIs
3361 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3362 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3364 if (Opts.FastMath || Opts.FiniteMathOnly)
3365 Builder.defineMacro("__ARM_FP_FAST");
3367 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3368 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3370 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3371 Opts.ShortWChar ? "2" : "4");
3373 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3374 Opts.ShortEnums ? "1" : "4");
3377 Builder.defineMacro("__ARM_BIG_ENDIAN");
3379 virtual void getTargetBuiltins(const Builtin::Info *&Records,
3380 unsigned &NumRecords) const {
3381 Records = BuiltinInfo;
3382 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3384 virtual bool hasFeature(StringRef Feature) const {
3385 return Feature == "aarch64";
3387 virtual void getGCCRegNames(const char * const *&Names,
3388 unsigned &NumNames) const;
3389 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3390 unsigned &NumAliases) const;
3392 virtual bool isCLZForZeroUndef() const { return false; }
3394 virtual bool validateAsmConstraint(const char *&Name,
3395 TargetInfo::ConstraintInfo &Info) const {
3397 default: return false;
3398 case 'w': // An FP/SIMD vector register
3399 Info.setAllowsRegister();
3401 case 'I': // Constant that can be used with an ADD instruction
3402 case 'J': // Constant that can be used with a SUB instruction
3403 case 'K': // Constant that can be used with a 32-bit logical instruction
3404 case 'L': // Constant that can be used with a 64-bit logical instruction
3405 case 'M': // Constant that can be used as a 32-bit MOV immediate
3406 case 'N': // Constant that can be used as a 64-bit MOV immediate
3407 case 'Y': // Floating point constant zero
3408 case 'Z': // Integer constant zero
3410 case 'Q': // A memory reference with base register and no offset
3411 Info.setAllowsMemory();
3413 case 'S': // A symbolic address
3414 Info.setAllowsRegister();
3417 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3418 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3419 // Usa: An absolute symbolic address
3420 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3421 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3425 virtual const char *getClobbers() const {
3426 // There are no AArch64 clobbers shared by all asm statements.
3430 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3431 return TargetInfo::AArch64ABIBuiltinVaList;
3435 const char * const AArch64TargetInfo::GCCRegNames[] = {
3436 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3437 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3438 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3439 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3441 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3442 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3443 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3444 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3446 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3447 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3448 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3449 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3451 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3452 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3453 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3454 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3456 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3457 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3458 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3459 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3461 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3462 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3463 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3464 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3466 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3467 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3468 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3469 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3472 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3473 unsigned &NumNames) const {
3474 Names = GCCRegNames;
3475 NumNames = llvm::array_lengthof(GCCRegNames);
3478 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3479 { { "x16" }, "ip0"},
3480 { { "x17" }, "ip1"},
3481 { { "x29" }, "fp" },
3485 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3486 unsigned &NumAliases) const {
3487 Aliases = GCCRegAliases;
3488 NumAliases = llvm::array_lengthof(GCCRegAliases);
3492 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3493 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3494 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3496 #include "clang/Basic/BuiltinsAArch64.def"
3499 } // end anonymous namespace
3502 class ARMTargetInfo : public TargetInfo {
3503 // Possible FPU choices.
3511 static bool FPUModeIsVFP(FPUMode Mode) {
3512 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3515 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3516 static const char * const GCCRegNames[];
3518 std::string ABI, CPU;
3522 unsigned IsAAPCS : 1;
3523 unsigned IsThumb : 1;
3525 // Initialized via features.
3526 unsigned SoftFloat : 1;
3527 unsigned SoftFloatABI : 1;
3529 static const Builtin::Info BuiltinInfo[];
3531 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3532 // On linux, binaries targeting old cpus call functions in libgcc to
3533 // perform atomic operations. The implementation in libgcc then calls into
3534 // the kernel which on armv6 and newer uses ldrex and strex. The net result
3535 // is that if we assume the kernel is at least as recent as the hardware,
3536 // it is safe to use atomic instructions on armv6 and newer.
3537 if (T.getOS() != llvm::Triple::Linux && T.getOS() != llvm::Triple::FreeBSD)
3539 StringRef ArchName = T.getArchName();
3540 if (T.getArch() == llvm::Triple::arm) {
3541 if (!ArchName.startswith("armv"))
3543 StringRef VersionStr = ArchName.substr(4);
3545 if (VersionStr.getAsInteger(10, Version))
3547 return Version >= 6;
3549 assert(T.getArch() == llvm::Triple::thumb);
3550 if (!ArchName.startswith("thumbv"))
3552 StringRef VersionStr = ArchName.substr(6);
3554 if (VersionStr.getAsInteger(10, Version))
3556 return Version >= 7;
3560 ARMTargetInfo(const std::string &TripleStr)
3561 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3564 SizeType = UnsignedInt;
3565 PtrDiffType = SignedInt;
3566 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3567 WCharType = UnsignedInt;
3569 // {} in inline assembly are neon specifiers, not assembly variant
3571 NoAsmVariants = true;
3573 // FIXME: Should we just treat this as a feature?
3574 IsThumb = getTriple().getArchName().startswith("thumb");
3576 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3577 // so set preferred for small types to 32.
3578 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3579 "i64:64:64-f32:32:32-f64:64:64-"
3580 "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3582 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3583 "i64:64:64-f32:32:32-f64:64:64-"
3584 "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3587 // ARM targets default to using the ARM C++ ABI.
3588 TheCXXABI.set(TargetCXXABI::GenericARM);
3590 // ARM has atomics up to 8 bytes
3591 MaxAtomicPromoteWidth = 64;
3592 if (shouldUseInlineAtomic(getTriple()))
3593 MaxAtomicInlineWidth = 64;
3595 // Do force alignment of members that follow zero length bitfields. If
3596 // the alignment of the zero-length bitfield is greater than the member
3597 // that follows it, `bar', `bar' will be aligned as the type of the
3598 // zero length bitfield.
3599 UseZeroLengthBitfieldAlignment = true;
3601 virtual const char *getABI() const { return ABI.c_str(); }
3602 virtual bool setABI(const std::string &Name) {
3605 // The defaults (above) are for AAPCS, check if we need to change them.
3607 // FIXME: We need support for -meabi... we could just mangle it into the
3609 if (Name == "apcs-gnu") {
3610 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3611 // size_t is unsigned int on FreeBSD.
3612 if (getTriple().getOS() != llvm::Triple::FreeBSD)
3613 SizeType = UnsignedLong;
3615 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3616 WCharType = SignedInt;
3618 // Do not respect the alignment of bit-field types when laying out
3619 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3620 UseBitFieldTypeAlignment = false;
3622 /// gcc forces the alignment to 4 bytes, regardless of the type of the
3623 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
3625 ZeroLengthBitfieldBoundary = 32;
3630 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3631 // so set preferred for small types to 32.
3632 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3633 "i64:32:64-f32:32:32-f64:32:64-"
3634 "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3636 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3637 "i64:32:64-f32:32:32-f64:32:64-"
3638 "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3641 // FIXME: Override "preferred align" for double and long long.
3642 } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3644 // FIXME: Enumerated types are variable width in straight AAPCS.
3645 } else if (Name == "aapcs-linux") {
3653 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3654 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3655 Features["vfp2"] = true;
3656 else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3657 CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3658 Features["neon"] = true;
3659 else if (CPU == "swift" || CPU == "cortex-a7") {
3660 Features["vfp4"] = true;
3661 Features["neon"] = true;
3665 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3667 bool Enabled) const {
3668 if (Name == "soft-float" || Name == "soft-float-abi" ||
3669 Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3670 Name == "d16" || Name == "neonfp") {
3671 Features[Name] = Enabled;
3678 virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3680 SoftFloat = SoftFloatABI = false;
3681 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3682 if (Features[i] == "+soft-float")
3684 else if (Features[i] == "+soft-float-abi")
3685 SoftFloatABI = true;
3686 else if (Features[i] == "+vfp2")
3688 else if (Features[i] == "+vfp3")
3690 else if (Features[i] == "+vfp4")
3692 else if (Features[i] == "+neon")
3696 // Remove front-end specific options which the backend handles differently.
3697 std::vector<std::string>::iterator it;
3698 it = std::find(Features.begin(), Features.end(), "+soft-float");
3699 if (it != Features.end())
3701 it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3702 if (it != Features.end())
3706 virtual bool hasFeature(StringRef Feature) const {
3707 return llvm::StringSwitch<bool>(Feature)
3709 .Case("softfloat", SoftFloat)
3710 .Case("thumb", IsThumb)
3711 .Case("neon", FPU == NeonFPU && !SoftFloat &&
3712 StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3715 // FIXME: Should we actually have some table instead of these switches?
3716 static const char *getCPUDefineSuffix(StringRef Name) {
3717 return llvm::StringSwitch<const char*>(Name)
3718 .Cases("arm8", "arm810", "4")
3719 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3720 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3721 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3722 .Case("ep9312", "4T")
3723 .Cases("arm10tdmi", "arm1020t", "5T")
3724 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3725 .Case("arm926ej-s", "5TEJ")
3726 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3727 .Cases("xscale", "iwmmxt", "5TE")
3728 .Case("arm1136j-s", "6J")
3729 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3730 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3731 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3732 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3733 .Cases("cortex-a9", "cortex-a15", "7A")
3734 .Case("cortex-r5", "7R")
3735 .Case("cortex-a9-mp", "7F")
3736 .Case("swift", "7S")
3737 .Cases("cortex-m3", "cortex-m4", "7M")
3738 .Case("cortex-m0", "6M")
3741 static const char *getCPUProfile(StringRef Name) {
3742 return llvm::StringSwitch<const char*>(Name)
3743 .Cases("cortex-a8", "cortex-a9", "A")
3744 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3745 .Case("cortex-r5", "R")
3748 virtual bool setCPU(const std::string &Name) {
3749 if (!getCPUDefineSuffix(Name))
3755 virtual void getTargetDefines(const LangOptions &Opts,
3756 MacroBuilder &Builder) const {
3757 // Target identification.
3758 Builder.defineMacro("__arm");
3759 Builder.defineMacro("__arm__");
3761 // Target properties.
3762 Builder.defineMacro("__ARMEL__");
3763 Builder.defineMacro("__LITTLE_ENDIAN__");
3764 Builder.defineMacro("__REGISTER_PREFIX__", "");
3766 StringRef CPUArch = getCPUDefineSuffix(CPU);
3767 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3768 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3769 StringRef CPUProfile = getCPUProfile(CPU);
3770 if (!CPUProfile.empty())
3771 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3773 // Subtarget options.
3775 // FIXME: It's more complicated than this and we don't really support
3777 if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3778 Builder.defineMacro("__THUMB_INTERWORK__");
3780 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3781 // M-class CPUs on Darwin follow AAPCS, but not EABI.
3782 if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3783 Builder.defineMacro("__ARM_EABI__");
3784 Builder.defineMacro("__ARM_PCS", "1");
3786 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3787 Builder.defineMacro("__ARM_PCS_VFP", "1");
3791 Builder.defineMacro("__SOFTFP__");
3793 if (CPU == "xscale")
3794 Builder.defineMacro("__XSCALE__");
3796 bool IsARMv7 = CPUArch.startswith("7");
3798 Builder.defineMacro("__THUMBEL__");
3799 Builder.defineMacro("__thumb__");
3800 if (CPUArch == "6T2" || IsARMv7)
3801 Builder.defineMacro("__thumb2__");
3804 // Note, this is always on in gcc, even though it doesn't make sense.
3805 Builder.defineMacro("__APCS_32__");
3807 if (FPUModeIsVFP((FPUMode) FPU)) {
3808 Builder.defineMacro("__VFP_FP__");
3810 Builder.defineMacro("__ARM_VFPV2__");
3812 Builder.defineMacro("__ARM_VFPV3__");
3814 Builder.defineMacro("__ARM_VFPV4__");
3817 // This only gets set when Neon instructions are actually available, unlike
3818 // the VFP define, hence the soft float and arch check. This is subtly
3819 // different from gcc, we follow the intent which was that it should be set
3820 // when Neon instructions are actually available.
3821 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3822 Builder.defineMacro("__ARM_NEON__");
3824 virtual void getTargetBuiltins(const Builtin::Info *&Records,
3825 unsigned &NumRecords) const {
3826 Records = BuiltinInfo;
3827 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3829 virtual bool isCLZForZeroUndef() const { return false; }
3830 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3831 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3833 virtual void getGCCRegNames(const char * const *&Names,
3834 unsigned &NumNames) const;
3835 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3836 unsigned &NumAliases) const;
3837 virtual bool validateAsmConstraint(const char *&Name,
3838 TargetInfo::ConstraintInfo &Info) const {
3843 case 'w': // VFP Floating point register single precision
3844 case 'P': // VFP Floating point register double precision
3845 Info.setAllowsRegister();
3847 case 'Q': // A memory address that is a single base register.
3848 Info.setAllowsMemory();
3850 case 'U': // a memory reference...
3852 case 'q': // ...ARMV4 ldrsb
3853 case 'v': // ...VFP load/store (reg+constant offset)
3854 case 'y': // ...iWMMXt load/store
3855 case 't': // address valid for load/store opaque types wider
3857 case 'n': // valid address for Neon doubleword vector load/store
3858 case 'm': // valid address for Neon element and structure load/store
3859 case 's': // valid address for non-offset loads/stores of quad-word
3860 // values in four ARM registers
3861 Info.setAllowsMemory();
3868 virtual std::string convertConstraint(const char *&Constraint) const {
3870 switch (*Constraint) {
3871 case 'U': // Two-character constraint; add "^" hint for later parsing.
3872 R = std::string("^") + std::string(Constraint, 2);
3875 case 'p': // 'p' should be translated to 'r' by default.
3876 R = std::string("r");
3879 return std::string(1, *Constraint);
3883 virtual bool validateConstraintModifier(StringRef Constraint,
3884 const char Modifier,
3885 unsigned Size) const {
3886 bool isOutput = (Constraint[0] == '=');
3887 bool isInOut = (Constraint[0] == '+');
3889 // Strip off constraint modifiers.
3890 while (Constraint[0] == '=' ||
3891 Constraint[0] == '+' ||
3892 Constraint[0] == '&')
3893 Constraint = Constraint.substr(1);
3895 switch (Constraint[0]) {
3900 return isInOut || (isOutput && Size >= 32) ||
3901 (!isOutput && !isInOut && Size <= 32);
3903 // A register of size 32 cannot fit a vector type.
3911 virtual const char *getClobbers() const {
3912 // FIXME: Is this really right?
3916 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3917 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3920 virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3921 if (RegNo == 0) return 0;
3922 if (RegNo == 1) return 1;
3927 const char * const ARMTargetInfo::GCCRegNames[] = {
3928 // Integer registers
3929 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3930 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3933 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3934 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3935 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3936 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3939 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3940 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3941 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3942 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3945 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3946 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3949 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3950 unsigned &NumNames) const {
3951 Names = GCCRegNames;
3952 NumNames = llvm::array_lengthof(GCCRegNames);
3955 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3965 { { "v6", "rfp" }, "r9" },
3966 { { "sl" }, "r10" },
3967 { { "fp" }, "r11" },
3968 { { "ip" }, "r12" },
3969 { { "r13" }, "sp" },
3970 { { "r14" }, "lr" },
3971 { { "r15" }, "pc" },
3972 // The S, D and Q registers overlap, but aren't really aliases; we
3973 // don't want to substitute one of these for a different-sized one.
3976 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3977 unsigned &NumAliases) const {
3978 Aliases = GCCRegAliases;
3979 NumAliases = llvm::array_lengthof(GCCRegAliases);
3982 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3983 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3984 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3986 #include "clang/Basic/BuiltinsARM.def"
3988 } // end anonymous namespace.
3991 class DarwinARMTargetInfo :
3992 public DarwinTargetInfo<ARMTargetInfo> {
3994 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3995 MacroBuilder &Builder) const {
3996 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4000 DarwinARMTargetInfo(const std::string& triple)
4001 : DarwinTargetInfo<ARMTargetInfo>(triple) {
4002 HasAlignMac68kSupport = true;
4003 // iOS always has 64-bit atomic instructions.
4004 // FIXME: This should be based off of the target features in ARMTargetInfo.
4005 MaxAtomicInlineWidth = 64;
4007 // Darwin on iOS uses a variant of the ARM C++ ABI.
4008 TheCXXABI.set(TargetCXXABI::iOS);
4011 } // end anonymous namespace.
4015 // Hexagon abstract base class
4016 class HexagonTargetInfo : public TargetInfo {
4017 static const Builtin::Info BuiltinInfo[];
4018 static const char * const GCCRegNames[];
4019 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4022 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) {
4024 DescriptionString = ("e-p:32:32:32-"
4025 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4026 "f64:64:64-f32:32:32-a0:0-n32");
4028 // {} in inline assembly are packet specifiers, not assembly variant
4030 NoAsmVariants = true;
4033 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4034 unsigned &NumRecords) const {
4035 Records = BuiltinInfo;
4036 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4039 virtual bool validateAsmConstraint(const char *&Name,
4040 TargetInfo::ConstraintInfo &Info) const {
4044 virtual void getTargetDefines(const LangOptions &Opts,
4045 MacroBuilder &Builder) const;
4047 virtual bool hasFeature(StringRef Feature) const {
4048 return Feature == "hexagon";
4051 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4052 return TargetInfo::CharPtrBuiltinVaList;
4054 virtual void getGCCRegNames(const char * const *&Names,
4055 unsigned &NumNames) const;
4056 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4057 unsigned &NumAliases) const;
4058 virtual const char *getClobbers() const {
4062 static const char *getHexagonCPUSuffix(StringRef Name) {
4063 return llvm::StringSwitch<const char*>(Name)
4064 .Case("hexagonv4", "4")
4065 .Case("hexagonv5", "5")
4069 virtual bool setCPU(const std::string &Name) {
4070 if (!getHexagonCPUSuffix(Name))
4078 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4079 MacroBuilder &Builder) const {
4080 Builder.defineMacro("qdsp6");
4081 Builder.defineMacro("__qdsp6", "1");
4082 Builder.defineMacro("__qdsp6__", "1");
4084 Builder.defineMacro("hexagon");
4085 Builder.defineMacro("__hexagon", "1");
4086 Builder.defineMacro("__hexagon__", "1");
4088 if(CPU == "hexagonv1") {
4089 Builder.defineMacro("__HEXAGON_V1__");
4090 Builder.defineMacro("__HEXAGON_ARCH__", "1");
4091 if(Opts.HexagonQdsp6Compat) {
4092 Builder.defineMacro("__QDSP6_V1__");
4093 Builder.defineMacro("__QDSP6_ARCH__", "1");
4096 else if(CPU == "hexagonv2") {
4097 Builder.defineMacro("__HEXAGON_V2__");
4098 Builder.defineMacro("__HEXAGON_ARCH__", "2");
4099 if(Opts.HexagonQdsp6Compat) {
4100 Builder.defineMacro("__QDSP6_V2__");
4101 Builder.defineMacro("__QDSP6_ARCH__", "2");
4104 else if(CPU == "hexagonv3") {
4105 Builder.defineMacro("__HEXAGON_V3__");
4106 Builder.defineMacro("__HEXAGON_ARCH__", "3");
4107 if(Opts.HexagonQdsp6Compat) {
4108 Builder.defineMacro("__QDSP6_V3__");
4109 Builder.defineMacro("__QDSP6_ARCH__", "3");
4112 else if(CPU == "hexagonv4") {
4113 Builder.defineMacro("__HEXAGON_V4__");
4114 Builder.defineMacro("__HEXAGON_ARCH__", "4");
4115 if(Opts.HexagonQdsp6Compat) {
4116 Builder.defineMacro("__QDSP6_V4__");
4117 Builder.defineMacro("__QDSP6_ARCH__", "4");
4120 else if(CPU == "hexagonv5") {
4121 Builder.defineMacro("__HEXAGON_V5__");
4122 Builder.defineMacro("__HEXAGON_ARCH__", "5");
4123 if(Opts.HexagonQdsp6Compat) {
4124 Builder.defineMacro("__QDSP6_V5__");
4125 Builder.defineMacro("__QDSP6_ARCH__", "5");
4130 const char * const HexagonTargetInfo::GCCRegNames[] = {
4131 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4132 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4133 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4134 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4135 "p0", "p1", "p2", "p3",
4136 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4139 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4140 unsigned &NumNames) const {
4141 Names = GCCRegNames;
4142 NumNames = llvm::array_lengthof(GCCRegNames);
4146 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4147 { { "sp" }, "r29" },
4148 { { "fp" }, "r30" },
4149 { { "lr" }, "r31" },
4152 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4153 unsigned &NumAliases) const {
4154 Aliases = GCCRegAliases;
4155 NumAliases = llvm::array_lengthof(GCCRegAliases);
4159 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4160 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4161 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4163 #include "clang/Basic/BuiltinsHexagon.def"
4169 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4170 class SparcTargetInfo : public TargetInfo {
4171 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4172 static const char * const GCCRegNames[];
4175 SparcTargetInfo(const std::string &triple) : TargetInfo(triple) {}
4177 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4179 bool Enabled) const {
4180 if (Name == "soft-float")
4181 Features[Name] = Enabled;
4187 virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4189 for (unsigned i = 0, e = Features.size(); i != e; ++i)
4190 if (Features[i] == "+soft-float")
4193 virtual void getTargetDefines(const LangOptions &Opts,
4194 MacroBuilder &Builder) const {
4195 DefineStd(Builder, "sparc", Opts);
4196 Builder.defineMacro("__REGISTER_PREFIX__", "");
4199 Builder.defineMacro("SOFT_FLOAT", "1");
4202 virtual bool hasFeature(StringRef Feature) const {
4203 return llvm::StringSwitch<bool>(Feature)
4204 .Case("softfloat", SoftFloat)
4205 .Case("sparc", true)
4209 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4210 unsigned &NumRecords) const {
4211 // FIXME: Implement!
4213 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4214 return TargetInfo::VoidPtrBuiltinVaList;
4216 virtual void getGCCRegNames(const char * const *&Names,
4217 unsigned &NumNames) const;
4218 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4219 unsigned &NumAliases) const;
4220 virtual bool validateAsmConstraint(const char *&Name,
4221 TargetInfo::ConstraintInfo &info) const {
4222 // FIXME: Implement!
4225 virtual const char *getClobbers() const {
4226 // FIXME: Implement!
4231 const char * const SparcTargetInfo::GCCRegNames[] = {
4232 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4233 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4234 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4235 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4238 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4239 unsigned &NumNames) const {
4240 Names = GCCRegNames;
4241 NumNames = llvm::array_lengthof(GCCRegNames);
4244 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4255 { { "o2" }, "r10" },
4256 { { "o3" }, "r11" },
4257 { { "o4" }, "r12" },
4258 { { "o5" }, "r13" },
4259 { { "o6", "sp" }, "r14" },
4260 { { "o7" }, "r15" },
4261 { { "l0" }, "r16" },
4262 { { "l1" }, "r17" },
4263 { { "l2" }, "r18" },
4264 { { "l3" }, "r19" },
4265 { { "l4" }, "r20" },
4266 { { "l5" }, "r21" },
4267 { { "l6" }, "r22" },
4268 { { "l7" }, "r23" },
4269 { { "i0" }, "r24" },
4270 { { "i1" }, "r25" },
4271 { { "i2" }, "r26" },
4272 { { "i3" }, "r27" },
4273 { { "i4" }, "r28" },
4274 { { "i5" }, "r29" },
4275 { { "i6", "fp" }, "r30" },
4276 { { "i7" }, "r31" },
4279 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4280 unsigned &NumAliases) const {
4281 Aliases = GCCRegAliases;
4282 NumAliases = llvm::array_lengthof(GCCRegAliases);
4285 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
4286 class SparcV8TargetInfo : public SparcTargetInfo {
4288 SparcV8TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4289 // FIXME: Support Sparc quad-precision long double?
4290 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4291 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4294 virtual void getTargetDefines(const LangOptions &Opts,
4295 MacroBuilder &Builder) const {
4296 SparcTargetInfo::getTargetDefines(Opts, Builder);
4297 Builder.defineMacro("__sparcv8");
4301 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4302 class SparcV9TargetInfo : public SparcTargetInfo {
4304 SparcV9TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4305 // FIXME: Support Sparc quad-precision long double?
4306 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4307 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4310 virtual void getTargetDefines(const LangOptions &Opts,
4311 MacroBuilder &Builder) const {
4312 SparcTargetInfo::getTargetDefines(Opts, Builder);
4313 Builder.defineMacro("__sparcv9");
4314 Builder.defineMacro("__arch64__");
4315 // Solaris and its derivative AuroraUX don't need these variants, but the
4317 if (getTriple().getOS() != llvm::Triple::Solaris &&
4318 getTriple().getOS() != llvm::Triple::AuroraUX) {
4319 Builder.defineMacro("__sparc64__");
4320 Builder.defineMacro("__sparc_v9__");
4321 Builder.defineMacro("__sparcv9__");
4326 } // end anonymous namespace.
4329 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4331 AuroraUXSparcV8TargetInfo(const std::string& triple) :
4332 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4333 SizeType = UnsignedInt;
4334 PtrDiffType = SignedInt;
4337 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4339 SolarisSparcV8TargetInfo(const std::string& triple) :
4340 SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4341 SizeType = UnsignedInt;
4342 PtrDiffType = SignedInt;
4345 } // end anonymous namespace.
4348 class SystemZTargetInfo : public TargetInfo {
4349 static const char *const GCCRegNames[];
4352 SystemZTargetInfo(const std::string& triple) : TargetInfo(triple) {
4353 TLSSupported = true;
4354 IntWidth = IntAlign = 32;
4355 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4356 PointerWidth = PointerAlign = 64;
4357 LongDoubleWidth = 128;
4358 LongDoubleAlign = 64;
4359 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4360 MinGlobalAlign = 16;
4361 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4362 "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4363 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4365 virtual void getTargetDefines(const LangOptions &Opts,
4366 MacroBuilder &Builder) const {
4367 Builder.defineMacro("__s390__");
4368 Builder.defineMacro("__s390x__");
4369 Builder.defineMacro("__zarch__");
4370 Builder.defineMacro("__LONG_DOUBLE_128__");
4372 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4373 unsigned &NumRecords) const {
4374 // FIXME: Implement.
4379 virtual void getGCCRegNames(const char *const *&Names,
4380 unsigned &NumNames) const;
4381 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4382 unsigned &NumAliases) const {
4387 virtual bool validateAsmConstraint(const char *&Name,
4388 TargetInfo::ConstraintInfo &info) const;
4389 virtual const char *getClobbers() const {
4390 // FIXME: Is this really right?
4393 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4394 return TargetInfo::SystemZBuiltinVaList;
4398 const char *const SystemZTargetInfo::GCCRegNames[] = {
4399 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4400 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4401 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
4402 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
4405 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4406 unsigned &NumNames) const {
4407 Names = GCCRegNames;
4408 NumNames = llvm::array_lengthof(GCCRegNames);
4411 bool SystemZTargetInfo::
4412 validateAsmConstraint(const char *&Name,
4413 TargetInfo::ConstraintInfo &Info) const {
4418 case 'a': // Address register
4419 case 'd': // Data register (equivalent to 'r')
4420 case 'f': // Floating-point register
4421 Info.setAllowsRegister();
4424 case 'I': // Unsigned 8-bit constant
4425 case 'J': // Unsigned 12-bit constant
4426 case 'K': // Signed 16-bit constant
4427 case 'L': // Signed 20-bit displacement (on all targets we support)
4428 case 'M': // 0x7fffffff
4431 case 'Q': // Memory with base and unsigned 12-bit displacement
4432 case 'R': // Likewise, plus an index
4433 case 'S': // Memory with base and signed 20-bit displacement
4434 case 'T': // Likewise, plus an index
4435 Info.setAllowsMemory();
4442 class MSP430TargetInfo : public TargetInfo {
4443 static const char * const GCCRegNames[];
4445 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4447 TLSSupported = false;
4448 IntWidth = 16; IntAlign = 16;
4449 LongWidth = 32; LongLongWidth = 64;
4450 LongAlign = LongLongAlign = 16;
4451 PointerWidth = 16; PointerAlign = 16;
4453 SizeType = UnsignedInt;
4454 IntMaxType = SignedLong;
4455 UIntMaxType = UnsignedLong;
4456 IntPtrType = SignedShort;
4457 PtrDiffType = SignedInt;
4458 SigAtomicType = SignedLong;
4459 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4461 virtual void getTargetDefines(const LangOptions &Opts,
4462 MacroBuilder &Builder) const {
4463 Builder.defineMacro("MSP430");
4464 Builder.defineMacro("__MSP430__");
4465 // FIXME: defines for different 'flavours' of MCU
4467 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4468 unsigned &NumRecords) const {
4469 // FIXME: Implement.
4473 virtual bool hasFeature(StringRef Feature) const {
4474 return Feature == "msp430";
4476 virtual void getGCCRegNames(const char * const *&Names,
4477 unsigned &NumNames) const;
4478 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4479 unsigned &NumAliases) const {
4484 virtual bool validateAsmConstraint(const char *&Name,
4485 TargetInfo::ConstraintInfo &info) const {
4486 // No target constraints for now.
4489 virtual const char *getClobbers() const {
4490 // FIXME: Is this really right?
4493 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4495 return TargetInfo::CharPtrBuiltinVaList;
4499 const char * const MSP430TargetInfo::GCCRegNames[] = {
4500 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4501 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4504 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4505 unsigned &NumNames) const {
4506 Names = GCCRegNames;
4507 NumNames = llvm::array_lengthof(GCCRegNames);
4513 // LLVM and Clang cannot be used directly to output native binaries for
4514 // target, but is used to compile C code to llvm bitcode with correct
4515 // type and alignment information.
4517 // TCE uses the llvm bitcode as input and uses it for generating customized
4518 // target processor and program binary. TCE co-design environment is
4519 // publicly available in http://tce.cs.tut.fi
4521 static const unsigned TCEOpenCLAddrSpaceMap[] = {
4524 5, // opencl_constant
4530 class TCETargetInfo : public TargetInfo{
4532 TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4533 TLSSupported = false;
4535 LongWidth = LongLongWidth = 32;
4538 LongAlign = LongLongAlign = 32;
4541 SizeType = UnsignedInt;
4542 IntMaxType = SignedLong;
4543 UIntMaxType = UnsignedLong;
4544 IntPtrType = SignedInt;
4545 PtrDiffType = SignedInt;
4550 LongDoubleWidth = 32;
4551 LongDoubleAlign = 32;
4552 FloatFormat = &llvm::APFloat::IEEEsingle;
4553 DoubleFormat = &llvm::APFloat::IEEEsingle;
4554 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4555 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4556 "i16:16:32-i32:32:32-i64:32:32-"
4557 "f32:32:32-f64:32:32-v64:32:32-"
4558 "v128:32:32-a0:0:32-n32";
4559 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4562 virtual void getTargetDefines(const LangOptions &Opts,
4563 MacroBuilder &Builder) const {
4564 DefineStd(Builder, "tce", Opts);
4565 Builder.defineMacro("__TCE__");
4566 Builder.defineMacro("__TCE_V1__");
4568 virtual bool hasFeature(StringRef Feature) const {
4569 return Feature == "tce";
4572 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4573 unsigned &NumRecords) const {}
4574 virtual const char *getClobbers() const {
4577 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4578 return TargetInfo::VoidPtrBuiltinVaList;
4580 virtual void getGCCRegNames(const char * const *&Names,
4581 unsigned &NumNames) const {}
4582 virtual bool validateAsmConstraint(const char *&Name,
4583 TargetInfo::ConstraintInfo &info) const {
4586 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4587 unsigned &NumAliases) const {}
4592 class MipsTargetInfoBase : public TargetInfo {
4593 static const Builtin::Info BuiltinInfo[];
4599 HardFloat, SoftFloat
4609 MipsTargetInfoBase(const std::string& triple,
4610 const std::string& ABIStr,
4611 const std::string& CPUStr)
4612 : TargetInfo(triple),
4616 IsSingleFloat(false),
4617 FloatABI(HardFloat),
4622 virtual const char *getABI() const { return ABI.c_str(); }
4623 virtual bool setABI(const std::string &Name) = 0;
4624 virtual bool setCPU(const std::string &Name) {
4628 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4629 Features[ABI] = true;
4630 Features[CPU] = true;
4633 virtual void getTargetDefines(const LangOptions &Opts,
4634 MacroBuilder &Builder) const {
4635 DefineStd(Builder, "mips", Opts);
4636 Builder.defineMacro("_mips");
4637 Builder.defineMacro("__REGISTER_PREFIX__", "");
4641 Builder.defineMacro("__mips_hard_float", Twine(1));
4644 Builder.defineMacro("__mips_soft_float", Twine(1));
4649 Builder.defineMacro("__mips_single_float", Twine(1));
4652 Builder.defineMacro("__mips16", Twine(1));
4655 Builder.defineMacro("__mips_micromips", Twine(1));
4661 Builder.defineMacro("__mips_dsp_rev", Twine(1));
4662 Builder.defineMacro("__mips_dsp", Twine(1));
4665 Builder.defineMacro("__mips_dsp_rev", Twine(2));
4666 Builder.defineMacro("__mips_dspr2", Twine(1));
4667 Builder.defineMacro("__mips_dsp", Twine(1));
4671 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4672 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4673 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4675 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4676 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4679 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4680 unsigned &NumRecords) const {
4681 Records = BuiltinInfo;
4682 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4684 virtual bool hasFeature(StringRef Feature) const {
4685 return Feature == "mips";
4687 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4688 return TargetInfo::VoidPtrBuiltinVaList;
4690 virtual void getGCCRegNames(const char * const *&Names,
4691 unsigned &NumNames) const {
4692 static const char * const GCCRegNames[] = {
4693 // CPU register names
4694 // Must match second column of GCCRegAliases
4695 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
4696 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
4697 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
4698 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
4699 // Floating point register names
4700 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
4701 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4702 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4703 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4704 // Hi/lo and condition register names
4705 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4706 "$fcc5","$fcc6","$fcc7"
4708 Names = GCCRegNames;
4709 NumNames = llvm::array_lengthof(GCCRegNames);
4711 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4712 unsigned &NumAliases) const = 0;
4713 virtual bool validateAsmConstraint(const char *&Name,
4714 TargetInfo::ConstraintInfo &Info) const {
4719 case 'r': // CPU registers.
4720 case 'd': // Equivalent to "r" unless generating MIPS16 code.
4721 case 'y': // Equivalent to "r", backwards compatibility only.
4722 case 'f': // floating-point registers.
4723 case 'c': // $25 for indirect jumps
4724 case 'l': // lo register
4725 case 'x': // hilo register pair
4726 Info.setAllowsRegister();
4728 case 'R': // An address that can be used in a non-macro load or store
4729 Info.setAllowsMemory();
4734 virtual const char *getClobbers() const {
4735 // FIXME: Implement!
4739 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4741 bool Enabled) const {
4742 if (Name == "soft-float" || Name == "single-float" ||
4743 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4744 Name == "mips32" || Name == "mips32r2" ||
4745 Name == "mips64" || Name == "mips64r2" ||
4746 Name == "mips16" || Name == "micromips" ||
4747 Name == "dsp" || Name == "dspr2") {
4748 Features[Name] = Enabled;
4750 } else if (Name == "32") {
4751 Features["o32"] = Enabled;
4753 } else if (Name == "64") {
4754 Features["n64"] = Enabled;
4760 virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4762 IsMicromips = false;
4763 IsSingleFloat = false;
4764 FloatABI = HardFloat;
4767 for (std::vector<std::string>::iterator it = Features.begin(),
4768 ie = Features.end(); it != ie; ++it) {
4769 if (*it == "+single-float")
4770 IsSingleFloat = true;
4771 else if (*it == "+soft-float")
4772 FloatABI = SoftFloat;
4773 else if (*it == "+mips16")
4775 else if (*it == "+micromips")
4777 else if (*it == "+dsp")
4778 DspRev = std::max(DspRev, DSP1);
4779 else if (*it == "+dspr2")
4780 DspRev = std::max(DspRev, DSP2);
4783 // Remove front-end specific option.
4784 std::vector<std::string>::iterator it =
4785 std::find(Features.begin(), Features.end(), "+soft-float");
4786 if (it != Features.end())
4790 virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4791 if (RegNo == 0) return 4;
4792 if (RegNo == 1) return 5;
4797 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4798 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4799 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4801 #include "clang/Basic/BuiltinsMips.def"
4804 class Mips32TargetInfoBase : public MipsTargetInfoBase {
4806 Mips32TargetInfoBase(const std::string& triple) :
4807 MipsTargetInfoBase(triple, "o32", "mips32") {
4808 SizeType = UnsignedInt;
4809 PtrDiffType = SignedInt;
4810 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4812 virtual bool setABI(const std::string &Name) {
4813 if ((Name == "o32") || (Name == "eabi")) {
4816 } else if (Name == "32") {
4822 virtual void getTargetDefines(const LangOptions &Opts,
4823 MacroBuilder &Builder) const {
4824 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4827 Builder.defineMacro("__mips_o32");
4828 Builder.defineMacro("_ABIO32", "1");
4829 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4831 else if (ABI == "eabi")
4832 Builder.defineMacro("__mips_eabi");
4834 llvm_unreachable("Invalid ABI for Mips32.");
4836 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4837 unsigned &NumAliases) const {
4838 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4848 { { "t2" }, "$10" },
4849 { { "t3" }, "$11" },
4850 { { "t4" }, "$12" },
4851 { { "t5" }, "$13" },
4852 { { "t6" }, "$14" },
4853 { { "t7" }, "$15" },
4854 { { "s0" }, "$16" },
4855 { { "s1" }, "$17" },
4856 { { "s2" }, "$18" },
4857 { { "s3" }, "$19" },
4858 { { "s4" }, "$20" },
4859 { { "s5" }, "$21" },
4860 { { "s6" }, "$22" },
4861 { { "s7" }, "$23" },
4862 { { "t8" }, "$24" },
4863 { { "t9" }, "$25" },
4864 { { "k0" }, "$26" },
4865 { { "k1" }, "$27" },
4866 { { "gp" }, "$28" },
4867 { { "sp","$sp" }, "$29" },
4868 { { "fp","$fp" }, "$30" },
4871 Aliases = GCCRegAliases;
4872 NumAliases = llvm::array_lengthof(GCCRegAliases);
4876 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4878 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4879 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4880 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4882 virtual void getTargetDefines(const LangOptions &Opts,
4883 MacroBuilder &Builder) const {
4884 DefineStd(Builder, "MIPSEB", Opts);
4885 Builder.defineMacro("_MIPSEB");
4886 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4890 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4892 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4894 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4895 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4897 virtual void getTargetDefines(const LangOptions &Opts,
4898 MacroBuilder &Builder) const {
4899 DefineStd(Builder, "MIPSEL", Opts);
4900 Builder.defineMacro("_MIPSEL");
4901 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4905 class Mips64TargetInfoBase : public MipsTargetInfoBase {
4906 virtual void SetDescriptionString(const std::string &Name) = 0;
4908 Mips64TargetInfoBase(const std::string& triple) :
4909 MipsTargetInfoBase(triple, "n64", "mips64") {
4910 LongWidth = LongAlign = 64;
4911 PointerWidth = PointerAlign = 64;
4912 LongDoubleWidth = LongDoubleAlign = 128;
4913 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4914 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4915 LongDoubleWidth = LongDoubleAlign = 64;
4916 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4918 SuitableAlign = 128;
4919 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4921 virtual bool setABI(const std::string &Name) {
4922 SetDescriptionString(Name);
4923 if (Name == "n32") {
4924 LongWidth = LongAlign = 32;
4925 PointerWidth = PointerAlign = 32;
4928 } else if (Name == "n64") {
4931 } else if (Name == "64") {
4937 virtual void getTargetDefines(const LangOptions &Opts,
4938 MacroBuilder &Builder) const {
4939 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4941 Builder.defineMacro("__mips64");
4942 Builder.defineMacro("__mips64__");
4945 Builder.defineMacro("__mips_n32");
4946 Builder.defineMacro("_ABIN32", "2");
4947 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4949 else if (ABI == "n64") {
4950 Builder.defineMacro("__mips_n64");
4951 Builder.defineMacro("_ABI64", "3");
4952 Builder.defineMacro("_MIPS_SIM", "_ABI64");
4955 llvm_unreachable("Invalid ABI for Mips64.");
4957 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4958 unsigned &NumAliases) const {
4959 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4969 { { "a6" }, "$10" },
4970 { { "a7" }, "$11" },
4971 { { "t0" }, "$12" },
4972 { { "t1" }, "$13" },
4973 { { "t2" }, "$14" },
4974 { { "t3" }, "$15" },
4975 { { "s0" }, "$16" },
4976 { { "s1" }, "$17" },
4977 { { "s2" }, "$18" },
4978 { { "s3" }, "$19" },
4979 { { "s4" }, "$20" },
4980 { { "s5" }, "$21" },
4981 { { "s6" }, "$22" },
4982 { { "s7" }, "$23" },
4983 { { "t8" }, "$24" },
4984 { { "t9" }, "$25" },
4985 { { "k0" }, "$26" },
4986 { { "k1" }, "$27" },
4987 { { "gp" }, "$28" },
4988 { { "sp","$sp" }, "$29" },
4989 { { "fp","$fp" }, "$30" },
4992 Aliases = GCCRegAliases;
4993 NumAliases = llvm::array_lengthof(GCCRegAliases);
4997 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4998 virtual void SetDescriptionString(const std::string &Name) {
4999 // Change DescriptionString only if ABI is n32.
5001 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5002 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5003 "v64:64:64-n32:64-S128";
5006 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
5007 // Default ABI is n64.
5008 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5009 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5010 "v64:64:64-n32:64-S128";
5012 virtual void getTargetDefines(const LangOptions &Opts,
5013 MacroBuilder &Builder) const {
5014 DefineStd(Builder, "MIPSEB", Opts);
5015 Builder.defineMacro("_MIPSEB");
5016 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5020 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5021 virtual void SetDescriptionString(const std::string &Name) {
5022 // Change DescriptionString only if ABI is n32.
5024 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5025 "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5026 "-v64:64:64-n32:64-S128";
5029 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
5030 // Default ABI is n64.
5032 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5033 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5034 "v64:64:64-n32:64-S128";
5036 virtual void getTargetDefines(const LangOptions &Opts,
5037 MacroBuilder &Builder) const {
5038 DefineStd(Builder, "MIPSEL", Opts);
5039 Builder.defineMacro("_MIPSEL");
5040 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5043 } // end anonymous namespace.
5046 class PNaClTargetInfo : public TargetInfo {
5048 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
5050 this->UserLabelPrefix = "";
5051 this->LongAlign = 32;
5052 this->LongWidth = 32;
5053 this->PointerAlign = 32;
5054 this->PointerWidth = 32;
5055 this->IntMaxType = TargetInfo::SignedLongLong;
5056 this->UIntMaxType = TargetInfo::UnsignedLongLong;
5057 this->Int64Type = TargetInfo::SignedLongLong;
5058 this->DoubleAlign = 64;
5059 this->LongDoubleWidth = 64;
5060 this->LongDoubleAlign = 64;
5061 this->SizeType = TargetInfo::UnsignedInt;
5062 this->PtrDiffType = TargetInfo::SignedInt;
5063 this->IntPtrType = TargetInfo::SignedInt;
5064 this->RegParmMax = 0; // Disallow regparm
5065 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5066 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5069 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5071 virtual void getArchDefines(const LangOptions &Opts,
5072 MacroBuilder &Builder) const {
5073 Builder.defineMacro("__le32__");
5074 Builder.defineMacro("__pnacl__");
5076 virtual void getTargetDefines(const LangOptions &Opts,
5077 MacroBuilder &Builder) const {
5078 Builder.defineMacro("__LITTLE_ENDIAN__");
5079 getArchDefines(Opts, Builder);
5081 virtual bool hasFeature(StringRef Feature) const {
5082 return Feature == "pnacl";
5084 virtual void getTargetBuiltins(const Builtin::Info *&Records,
5085 unsigned &NumRecords) const {
5087 virtual BuiltinVaListKind getBuiltinVaListKind() const {
5088 return TargetInfo::PNaClABIBuiltinVaList;
5090 virtual void getGCCRegNames(const char * const *&Names,
5091 unsigned &NumNames) const;
5092 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5093 unsigned &NumAliases) const;
5094 virtual bool validateAsmConstraint(const char *&Name,
5095 TargetInfo::ConstraintInfo &Info) const {
5099 virtual const char *getClobbers() const {
5104 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5105 unsigned &NumNames) const {
5110 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5111 unsigned &NumAliases) const {
5115 } // end anonymous namespace.
5118 static const unsigned SPIRAddrSpaceMap[] = {
5121 2, // opencl_constant
5126 class SPIRTargetInfo : public TargetInfo {
5127 static const char * const GCCRegNames[];
5128 static const Builtin::Info BuiltinInfo[];
5129 std::vector<StringRef> AvailableFeatures;
5131 SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
5132 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5133 "SPIR target must use unknown OS");
5134 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5135 "SPIR target must use unknown environment type");
5137 TLSSupported = false;
5138 LongWidth = LongAlign = 64;
5139 AddrSpaceMap = &SPIRAddrSpaceMap;
5140 // Define available target features
5141 // These must be defined in sorted order!
5142 NoAsmVariants = true;
5144 virtual void getTargetDefines(const LangOptions &Opts,
5145 MacroBuilder &Builder) const {
5146 DefineStd(Builder, "SPIR", Opts);
5148 virtual bool hasFeature(StringRef Feature) const {
5149 return Feature == "spir";
5152 virtual void getTargetBuiltins(const Builtin::Info *&Records,
5153 unsigned &NumRecords) const {}
5154 virtual const char *getClobbers() const {
5157 virtual void getGCCRegNames(const char * const *&Names,
5158 unsigned &NumNames) const {}
5159 virtual bool validateAsmConstraint(const char *&Name,
5160 TargetInfo::ConstraintInfo &info) const {
5163 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5164 unsigned &NumAliases) const {}
5165 virtual BuiltinVaListKind getBuiltinVaListKind() const {
5166 return TargetInfo::VoidPtrBuiltinVaList;
5171 class SPIR32TargetInfo : public SPIRTargetInfo {
5173 SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5174 PointerWidth = PointerAlign = 32;
5175 SizeType = TargetInfo::UnsignedInt;
5176 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5178 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5179 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5180 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5181 "v512:512:512-v1024:1024:1024";
5183 virtual void getTargetDefines(const LangOptions &Opts,
5184 MacroBuilder &Builder) const {
5185 DefineStd(Builder, "SPIR32", Opts);
5189 class SPIR64TargetInfo : public SPIRTargetInfo {
5191 SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5192 PointerWidth = PointerAlign = 64;
5193 SizeType = TargetInfo::UnsignedLong;
5194 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5196 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5197 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5198 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5199 "v512:512:512-v1024:1024:1024";
5201 virtual void getTargetDefines(const LangOptions &Opts,
5202 MacroBuilder &Builder) const {
5203 DefineStd(Builder, "SPIR64", Opts);
5209 //===----------------------------------------------------------------------===//
5211 //===----------------------------------------------------------------------===//
5213 static TargetInfo *AllocateTarget(const std::string &T) {
5214 llvm::Triple Triple(T);
5215 llvm::Triple::OSType os = Triple.getOS();
5217 switch (Triple.getArch()) {
5221 case llvm::Triple::hexagon:
5222 return new HexagonTargetInfo(T);
5224 case llvm::Triple::aarch64:
5226 case llvm::Triple::Linux:
5227 return new LinuxTargetInfo<AArch64TargetInfo>(T);
5229 return new AArch64TargetInfo(T);
5232 case llvm::Triple::arm:
5233 case llvm::Triple::thumb:
5234 if (Triple.isOSDarwin())
5235 return new DarwinARMTargetInfo(T);
5238 case llvm::Triple::Linux:
5239 return new LinuxTargetInfo<ARMTargetInfo>(T);
5240 case llvm::Triple::FreeBSD:
5241 return new FreeBSDTargetInfo<ARMTargetInfo>(T);
5242 case llvm::Triple::NetBSD:
5243 return new NetBSDTargetInfo<ARMTargetInfo>(T);
5244 case llvm::Triple::OpenBSD:
5245 return new OpenBSDTargetInfo<ARMTargetInfo>(T);
5246 case llvm::Triple::Bitrig:
5247 return new BitrigTargetInfo<ARMTargetInfo>(T);
5248 case llvm::Triple::RTEMS:
5249 return new RTEMSTargetInfo<ARMTargetInfo>(T);
5250 case llvm::Triple::NaCl:
5251 return new NaClTargetInfo<ARMTargetInfo>(T);
5253 return new ARMTargetInfo(T);
5256 case llvm::Triple::msp430:
5257 return new MSP430TargetInfo(T);
5259 case llvm::Triple::mips:
5261 case llvm::Triple::Linux:
5262 return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
5263 case llvm::Triple::RTEMS:
5264 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
5265 case llvm::Triple::FreeBSD:
5266 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
5267 case llvm::Triple::NetBSD:
5268 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
5270 return new Mips32EBTargetInfo(T);
5273 case llvm::Triple::mipsel:
5275 case llvm::Triple::Linux:
5276 return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
5277 case llvm::Triple::RTEMS:
5278 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
5279 case llvm::Triple::FreeBSD:
5280 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
5281 case llvm::Triple::NetBSD:
5282 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
5284 return new Mips32ELTargetInfo(T);
5287 case llvm::Triple::mips64:
5289 case llvm::Triple::Linux:
5290 return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
5291 case llvm::Triple::RTEMS:
5292 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
5293 case llvm::Triple::FreeBSD:
5294 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
5295 case llvm::Triple::NetBSD:
5296 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
5297 case llvm::Triple::OpenBSD:
5298 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
5300 return new Mips64EBTargetInfo(T);
5303 case llvm::Triple::mips64el:
5305 case llvm::Triple::Linux:
5306 return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
5307 case llvm::Triple::RTEMS:
5308 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
5309 case llvm::Triple::FreeBSD:
5310 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
5311 case llvm::Triple::NetBSD:
5312 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
5313 case llvm::Triple::OpenBSD:
5314 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
5316 return new Mips64ELTargetInfo(T);
5319 case llvm::Triple::le32:
5321 case llvm::Triple::NaCl:
5322 return new NaClTargetInfo<PNaClTargetInfo>(T);
5327 case llvm::Triple::ppc:
5328 if (Triple.isOSDarwin())
5329 return new DarwinPPC32TargetInfo(T);
5331 case llvm::Triple::Linux:
5332 return new LinuxTargetInfo<PPC32TargetInfo>(T);
5333 case llvm::Triple::FreeBSD:
5334 return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
5335 case llvm::Triple::NetBSD:
5336 return new NetBSDTargetInfo<PPC32TargetInfo>(T);
5337 case llvm::Triple::OpenBSD:
5338 return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
5339 case llvm::Triple::RTEMS:
5340 return new RTEMSTargetInfo<PPC32TargetInfo>(T);
5342 return new PPC32TargetInfo(T);
5345 case llvm::Triple::ppc64:
5346 if (Triple.isOSDarwin())
5347 return new DarwinPPC64TargetInfo(T);
5349 case llvm::Triple::Linux:
5350 return new LinuxTargetInfo<PPC64TargetInfo>(T);
5351 case llvm::Triple::Lv2:
5352 return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5353 case llvm::Triple::FreeBSD:
5354 return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5355 case llvm::Triple::NetBSD:
5356 return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5358 return new PPC64TargetInfo(T);
5361 case llvm::Triple::nvptx:
5362 return new NVPTX32TargetInfo(T);
5363 case llvm::Triple::nvptx64:
5364 return new NVPTX64TargetInfo(T);
5366 case llvm::Triple::mblaze:
5367 return new MBlazeTargetInfo(T);
5369 case llvm::Triple::r600:
5370 return new R600TargetInfo(T);
5372 case llvm::Triple::sparc:
5374 case llvm::Triple::Linux:
5375 return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5376 case llvm::Triple::AuroraUX:
5377 return new AuroraUXSparcV8TargetInfo(T);
5378 case llvm::Triple::Solaris:
5379 return new SolarisSparcV8TargetInfo(T);
5380 case llvm::Triple::NetBSD:
5381 return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5382 case llvm::Triple::OpenBSD:
5383 return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5384 case llvm::Triple::RTEMS:
5385 return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5387 return new SparcV8TargetInfo(T);
5390 case llvm::Triple::sparcv9:
5392 case llvm::Triple::Linux:
5393 return new LinuxTargetInfo<SparcV9TargetInfo>(T);
5394 case llvm::Triple::AuroraUX:
5395 return new AuroraUXTargetInfo<SparcV9TargetInfo>(T);
5396 case llvm::Triple::Solaris:
5397 return new SolarisTargetInfo<SparcV9TargetInfo>(T);
5398 case llvm::Triple::NetBSD:
5399 return new NetBSDTargetInfo<SparcV9TargetInfo>(T);
5400 case llvm::Triple::OpenBSD:
5401 return new OpenBSDTargetInfo<SparcV9TargetInfo>(T);
5402 case llvm::Triple::FreeBSD:
5403 return new FreeBSDTargetInfo<SparcV9TargetInfo>(T);
5405 return new SparcV9TargetInfo(T);
5408 case llvm::Triple::systemz:
5410 case llvm::Triple::Linux:
5411 return new LinuxTargetInfo<SystemZTargetInfo>(T);
5413 return new SystemZTargetInfo(T);
5416 case llvm::Triple::tce:
5417 return new TCETargetInfo(T);
5419 case llvm::Triple::x86:
5420 if (Triple.isOSDarwin())
5421 return new DarwinI386TargetInfo(T);
5424 case llvm::Triple::AuroraUX:
5425 return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5426 case llvm::Triple::Linux:
5427 return new LinuxTargetInfo<X86_32TargetInfo>(T);
5428 case llvm::Triple::DragonFly:
5429 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5430 case llvm::Triple::NetBSD:
5431 return new NetBSDI386TargetInfo(T);
5432 case llvm::Triple::OpenBSD:
5433 return new OpenBSDI386TargetInfo(T);
5434 case llvm::Triple::Bitrig:
5435 return new BitrigI386TargetInfo(T);
5436 case llvm::Triple::FreeBSD:
5437 return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5438 case llvm::Triple::Minix:
5439 return new MinixTargetInfo<X86_32TargetInfo>(T);
5440 case llvm::Triple::Solaris:
5441 return new SolarisTargetInfo<X86_32TargetInfo>(T);
5442 case llvm::Triple::Cygwin:
5443 return new CygwinX86_32TargetInfo(T);
5444 case llvm::Triple::MinGW32:
5445 return new MinGWX86_32TargetInfo(T);
5446 case llvm::Triple::Win32:
5447 return new VisualStudioWindowsX86_32TargetInfo(T);
5448 case llvm::Triple::Haiku:
5449 return new HaikuX86_32TargetInfo(T);
5450 case llvm::Triple::RTEMS:
5451 return new RTEMSX86_32TargetInfo(T);
5452 case llvm::Triple::NaCl:
5453 return new NaClTargetInfo<X86_32TargetInfo>(T);
5455 return new X86_32TargetInfo(T);
5458 case llvm::Triple::x86_64:
5459 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5460 return new DarwinX86_64TargetInfo(T);
5463 case llvm::Triple::AuroraUX:
5464 return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5465 case llvm::Triple::Linux:
5466 return new LinuxTargetInfo<X86_64TargetInfo>(T);
5467 case llvm::Triple::DragonFly:
5468 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5469 case llvm::Triple::NetBSD:
5470 return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5471 case llvm::Triple::OpenBSD:
5472 return new OpenBSDX86_64TargetInfo(T);
5473 case llvm::Triple::Bitrig:
5474 return new BitrigX86_64TargetInfo(T);
5475 case llvm::Triple::FreeBSD:
5476 return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5477 case llvm::Triple::Solaris:
5478 return new SolarisTargetInfo<X86_64TargetInfo>(T);
5479 case llvm::Triple::MinGW32:
5480 return new MinGWX86_64TargetInfo(T);
5481 case llvm::Triple::Win32: // This is what Triple.h supports now.
5482 return new VisualStudioWindowsX86_64TargetInfo(T);
5483 case llvm::Triple::NaCl:
5484 return new NaClTargetInfo<X86_64TargetInfo>(T);
5486 return new X86_64TargetInfo(T);
5489 case llvm::Triple::spir: {
5490 llvm::Triple Triple(T);
5491 if (Triple.getOS() != llvm::Triple::UnknownOS ||
5492 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5494 return new SPIR32TargetInfo(T);
5496 case llvm::Triple::spir64: {
5497 llvm::Triple Triple(T);
5498 if (Triple.getOS() != llvm::Triple::UnknownOS ||
5499 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5501 return new SPIR64TargetInfo(T);
5506 /// CreateTargetInfo - Return the target info object for the specified target
5508 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5509 TargetOptions *Opts) {
5510 llvm::Triple Triple(Opts->Triple);
5512 // Construct the target
5513 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5515 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5518 Target->setTargetOpts(Opts);
5520 // Set the target CPU if specified.
5521 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5522 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5526 // Set the target ABI if specified.
5527 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5528 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5532 // Set the target C++ ABI.
5533 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5534 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5538 // Compute the default target features, we need the target to handle this
5539 // because features may have dependencies on one another.
5540 llvm::StringMap<bool> Features;
5541 Target->getDefaultFeatures(Features);
5543 // Apply the user specified deltas.
5544 // First the enables.
5545 for (std::vector<std::string>::const_iterator
5546 it = Opts->FeaturesAsWritten.begin(),
5547 ie = Opts->FeaturesAsWritten.end();
5549 const char *Name = it->c_str();
5554 // Apply the feature via the target.
5555 if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5556 Diags.Report(diag::err_target_invalid_feature) << Name;
5561 // Then the disables.
5562 for (std::vector<std::string>::const_iterator
5563 it = Opts->FeaturesAsWritten.begin(),
5564 ie = Opts->FeaturesAsWritten.end();
5566 const char *Name = it->c_str();
5571 // Apply the feature via the target.
5572 if (Name[0] != '-' ||
5573 !Target->setFeatureEnabled(Features, Name + 1, false)) {
5574 Diags.Report(diag::err_target_invalid_feature) << Name;
5579 // Add the features to the compile options.
5581 // FIXME: If we are completely confident that we have the right set, we only
5582 // need to pass the minuses.
5583 Opts->Features.clear();
5584 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5585 ie = Features.end(); it != ie; ++it)
5586 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5587 Target->HandleTargetFeatures(Opts->Features);
5589 return Target.take();