2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
152 #include <vm/vm_dumpset.h>
155 #include <machine/intr_machdep.h>
156 #include <x86/apicvar.h>
157 #include <x86/ifunc.h>
158 #include <machine/cpu.h>
159 #include <machine/cputypes.h>
160 #include <machine/intr_machdep.h>
161 #include <machine/md_var.h>
162 #include <machine/pcb.h>
163 #include <machine/specialreg.h>
165 #include <machine/smp.h>
167 #include <machine/sysarch.h>
168 #include <machine/tss.h>
171 #define PMAP_MEMDOM MAXMEMDOM
173 #define PMAP_MEMDOM 1
176 static __inline boolean_t
177 pmap_type_guest(pmap_t pmap)
180 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
183 static __inline boolean_t
184 pmap_emulate_ad_bits(pmap_t pmap)
187 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
190 static __inline pt_entry_t
191 pmap_valid_bit(pmap_t pmap)
195 switch (pmap->pm_type) {
201 if (pmap_emulate_ad_bits(pmap))
202 mask = EPT_PG_EMUL_V;
207 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
213 static __inline pt_entry_t
214 pmap_rw_bit(pmap_t pmap)
218 switch (pmap->pm_type) {
224 if (pmap_emulate_ad_bits(pmap))
225 mask = EPT_PG_EMUL_RW;
230 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
236 static pt_entry_t pg_g;
238 static __inline pt_entry_t
239 pmap_global_bit(pmap_t pmap)
243 switch (pmap->pm_type) {
252 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
258 static __inline pt_entry_t
259 pmap_accessed_bit(pmap_t pmap)
263 switch (pmap->pm_type) {
269 if (pmap_emulate_ad_bits(pmap))
275 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
281 static __inline pt_entry_t
282 pmap_modified_bit(pmap_t pmap)
286 switch (pmap->pm_type) {
292 if (pmap_emulate_ad_bits(pmap))
298 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
304 static __inline pt_entry_t
305 pmap_pku_mask_bit(pmap_t pmap)
308 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
311 #if !defined(DIAGNOSTIC)
312 #ifdef __GNUC_GNU_INLINE__
313 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
315 #define PMAP_INLINE extern inline
322 #define PV_STAT(x) do { x ; } while (0)
324 #define PV_STAT(x) do { } while (0)
329 #define pa_index(pa) ({ \
330 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
331 ("address %lx beyond the last segment", (pa))); \
334 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
335 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
336 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
337 struct rwlock *_lock; \
338 if (__predict_false((pa) > pmap_last_pa)) \
339 _lock = &pv_dummy_large.pv_lock; \
341 _lock = &(pa_to_pmdp(pa)->pv_lock); \
345 #define pa_index(pa) ((pa) >> PDRSHIFT)
346 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
348 #define NPV_LIST_LOCKS MAXCPU
350 #define PHYS_TO_PV_LIST_LOCK(pa) \
351 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
354 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
355 struct rwlock **_lockp = (lockp); \
356 struct rwlock *_new_lock; \
358 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
359 if (_new_lock != *_lockp) { \
360 if (*_lockp != NULL) \
361 rw_wunlock(*_lockp); \
362 *_lockp = _new_lock; \
367 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
368 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
370 #define RELEASE_PV_LIST_LOCK(lockp) do { \
371 struct rwlock **_lockp = (lockp); \
373 if (*_lockp != NULL) { \
374 rw_wunlock(*_lockp); \
379 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
380 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
382 struct pmap kernel_pmap_store;
384 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
385 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
388 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
389 "Number of kernel page table pages allocated on bootup");
392 vm_paddr_t dmaplimit;
393 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
396 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
397 "VM/pmap parameters");
399 static int pg_ps_enabled = 1;
400 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
401 &pg_ps_enabled, 0, "Are large page mappings enabled?");
403 int __read_frequently la57 = 0;
404 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
406 "5-level paging for host is enabled");
409 pmap_is_la57(pmap_t pmap)
411 if (pmap->pm_type == PT_X86)
413 return (false); /* XXXKIB handle EPT */
416 #define PAT_INDEX_SIZE 8
417 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
419 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
420 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
421 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
422 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
423 u_int64_t KPML5phys; /* phys addr of kernel level 5,
426 static pml4_entry_t *kernel_pml4;
427 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
428 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
429 static int ndmpdpphys; /* number of DMPDPphys pages */
431 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
434 * pmap_mapdev support pre initialization (i.e. console)
436 #define PMAP_PREINIT_MAPPING_COUNT 8
437 static struct pmap_preinit_mapping {
442 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
443 static int pmap_initialized;
446 * Data for the pv entry allocation mechanism.
447 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
451 pc_to_domain(struct pv_chunk *pc)
454 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
458 pc_to_domain(struct pv_chunk *pc __unused)
465 struct pv_chunks_list {
467 TAILQ_HEAD(pch, pv_chunk) pvc_list;
469 } __aligned(CACHE_LINE_SIZE);
471 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
474 struct pmap_large_md_page {
475 struct rwlock pv_lock;
476 struct md_page pv_page;
479 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
480 #define pv_dummy pv_dummy_large.pv_page
481 __read_mostly static struct pmap_large_md_page *pv_table;
482 __read_mostly vm_paddr_t pmap_last_pa;
484 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
485 static u_long pv_invl_gen[NPV_LIST_LOCKS];
486 static struct md_page *pv_table;
487 static struct md_page pv_dummy;
491 * All those kernel PT submaps that BSD is so fond of
493 pt_entry_t *CMAP1 = NULL;
495 static vm_offset_t qframe = 0;
496 static struct mtx qframe_mtx;
498 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
500 static vmem_t *large_vmem;
501 static u_int lm_ents;
502 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
503 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
505 int pmap_pcid_enabled = 1;
506 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
507 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
508 int invpcid_works = 0;
509 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
510 "Is the invpcid instruction available ?");
512 int __read_frequently pti = 0;
513 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
515 "Page Table Isolation enabled");
516 static vm_object_t pti_obj;
517 static pml4_entry_t *pti_pml4;
518 static vm_pindex_t pti_pg_idx;
519 static bool pti_finalized;
521 struct pmap_pkru_range {
522 struct rs_el pkru_rs_el;
527 static uma_zone_t pmap_pkru_ranges_zone;
528 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
529 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
530 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
531 static void *pkru_dup_range(void *ctx, void *data);
532 static void pkru_free_range(void *ctx, void *node);
533 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
534 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
535 static void pmap_pkru_deassign_all(pmap_t pmap);
538 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
545 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
547 return (sysctl_handle_64(oidp, &res, 0, req));
549 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
550 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
551 "Count of saved TLB context on switch");
553 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
554 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
555 static struct mtx invl_gen_mtx;
556 /* Fake lock object to satisfy turnstiles interface. */
557 static struct lock_object invl_gen_ts = {
560 static struct pmap_invl_gen pmap_invl_gen_head = {
564 static u_long pmap_invl_gen = 1;
565 static int pmap_invl_waiters;
566 static struct callout pmap_invl_callout;
567 static bool pmap_invl_callout_inited;
569 #define PMAP_ASSERT_NOT_IN_DI() \
570 KASSERT(pmap_not_in_di(), ("DI already started"))
577 if ((cpu_feature2 & CPUID2_CX16) == 0)
580 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
585 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
589 locked = pmap_di_locked();
590 return (sysctl_handle_int(oidp, &locked, 0, req));
592 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
593 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
594 "Locked delayed invalidation");
596 static bool pmap_not_in_di_l(void);
597 static bool pmap_not_in_di_u(void);
598 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
601 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
605 pmap_not_in_di_l(void)
607 struct pmap_invl_gen *invl_gen;
609 invl_gen = &curthread->td_md.md_invl_gen;
610 return (invl_gen->gen == 0);
614 pmap_thread_init_invl_gen_l(struct thread *td)
616 struct pmap_invl_gen *invl_gen;
618 invl_gen = &td->td_md.md_invl_gen;
623 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
625 struct turnstile *ts;
627 ts = turnstile_trywait(&invl_gen_ts);
628 if (*m_gen > atomic_load_long(invl_gen))
629 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
631 turnstile_cancel(ts);
635 pmap_delayed_invl_finish_unblock(u_long new_gen)
637 struct turnstile *ts;
639 turnstile_chain_lock(&invl_gen_ts);
640 ts = turnstile_lookup(&invl_gen_ts);
642 pmap_invl_gen = new_gen;
644 turnstile_broadcast(ts, TS_SHARED_QUEUE);
645 turnstile_unpend(ts);
647 turnstile_chain_unlock(&invl_gen_ts);
651 * Start a new Delayed Invalidation (DI) block of code, executed by
652 * the current thread. Within a DI block, the current thread may
653 * destroy both the page table and PV list entries for a mapping and
654 * then release the corresponding PV list lock before ensuring that
655 * the mapping is flushed from the TLBs of any processors with the
659 pmap_delayed_invl_start_l(void)
661 struct pmap_invl_gen *invl_gen;
664 invl_gen = &curthread->td_md.md_invl_gen;
665 PMAP_ASSERT_NOT_IN_DI();
666 mtx_lock(&invl_gen_mtx);
667 if (LIST_EMPTY(&pmap_invl_gen_tracker))
668 currgen = pmap_invl_gen;
670 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
671 invl_gen->gen = currgen + 1;
672 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
673 mtx_unlock(&invl_gen_mtx);
677 * Finish the DI block, previously started by the current thread. All
678 * required TLB flushes for the pages marked by
679 * pmap_delayed_invl_page() must be finished before this function is
682 * This function works by bumping the global DI generation number to
683 * the generation number of the current thread's DI, unless there is a
684 * pending DI that started earlier. In the latter case, bumping the
685 * global DI generation number would incorrectly signal that the
686 * earlier DI had finished. Instead, this function bumps the earlier
687 * DI's generation number to match the generation number of the
688 * current thread's DI.
691 pmap_delayed_invl_finish_l(void)
693 struct pmap_invl_gen *invl_gen, *next;
695 invl_gen = &curthread->td_md.md_invl_gen;
696 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
697 mtx_lock(&invl_gen_mtx);
698 next = LIST_NEXT(invl_gen, link);
700 pmap_delayed_invl_finish_unblock(invl_gen->gen);
702 next->gen = invl_gen->gen;
703 LIST_REMOVE(invl_gen, link);
704 mtx_unlock(&invl_gen_mtx);
709 pmap_not_in_di_u(void)
711 struct pmap_invl_gen *invl_gen;
713 invl_gen = &curthread->td_md.md_invl_gen;
714 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
718 pmap_thread_init_invl_gen_u(struct thread *td)
720 struct pmap_invl_gen *invl_gen;
722 invl_gen = &td->td_md.md_invl_gen;
724 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
728 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
730 uint64_t new_high, new_low, old_high, old_low;
733 old_low = new_low = 0;
734 old_high = new_high = (uintptr_t)0;
736 __asm volatile("lock;cmpxchg16b\t%1"
737 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
738 : "b"(new_low), "c" (new_high)
741 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
744 out->next = (void *)old_high;
747 out->next = (void *)new_high;
753 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
754 struct pmap_invl_gen *new_val)
756 uint64_t new_high, new_low, old_high, old_low;
759 new_low = new_val->gen;
760 new_high = (uintptr_t)new_val->next;
761 old_low = old_val->gen;
762 old_high = (uintptr_t)old_val->next;
764 __asm volatile("lock;cmpxchg16b\t%1"
765 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
766 : "b"(new_low), "c" (new_high)
772 static long invl_start_restart;
773 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
774 &invl_start_restart, 0,
776 static long invl_finish_restart;
777 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
778 &invl_finish_restart, 0,
780 static int invl_max_qlen;
781 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
786 #define di_delay locks_delay
789 pmap_delayed_invl_start_u(void)
791 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
793 struct lock_delay_arg lda;
801 invl_gen = &td->td_md.md_invl_gen;
802 PMAP_ASSERT_NOT_IN_DI();
803 lock_delay_arg_init(&lda, &di_delay);
804 invl_gen->saved_pri = 0;
805 pri = td->td_base_pri;
808 pri = td->td_base_pri;
810 invl_gen->saved_pri = pri;
817 for (p = &pmap_invl_gen_head;; p = prev.next) {
819 prevl = (uintptr_t)atomic_load_ptr(&p->next);
820 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
821 PV_STAT(atomic_add_long(&invl_start_restart, 1));
827 prev.next = (void *)prevl;
830 if ((ii = invl_max_qlen) < i)
831 atomic_cmpset_int(&invl_max_qlen, ii, i);
834 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
835 PV_STAT(atomic_add_long(&invl_start_restart, 1));
840 new_prev.gen = prev.gen;
841 new_prev.next = invl_gen;
842 invl_gen->gen = prev.gen + 1;
844 /* Formal fence between store to invl->gen and updating *p. */
845 atomic_thread_fence_rel();
848 * After inserting an invl_gen element with invalid bit set,
849 * this thread blocks any other thread trying to enter the
850 * delayed invalidation block. Do not allow to remove us from
851 * the CPU, because it causes starvation for other threads.
856 * ABA for *p is not possible there, since p->gen can only
857 * increase. So if the *p thread finished its di, then
858 * started a new one and got inserted into the list at the
859 * same place, its gen will appear greater than the previously
862 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
864 PV_STAT(atomic_add_long(&invl_start_restart, 1));
870 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
871 * invl_gen->next, allowing other threads to iterate past us.
872 * pmap_di_store_invl() provides fence between the generation
873 * write and the update of next.
875 invl_gen->next = NULL;
880 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
881 struct pmap_invl_gen *p)
883 struct pmap_invl_gen prev, new_prev;
887 * Load invl_gen->gen after setting invl_gen->next
888 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
889 * generations to propagate to our invl_gen->gen. Lock prefix
890 * in atomic_set_ptr() worked as seq_cst fence.
892 mygen = atomic_load_long(&invl_gen->gen);
894 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
897 KASSERT(prev.gen < mygen,
898 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
899 new_prev.gen = mygen;
900 new_prev.next = (void *)((uintptr_t)invl_gen->next &
901 ~PMAP_INVL_GEN_NEXT_INVALID);
903 /* Formal fence between load of prev and storing update to it. */
904 atomic_thread_fence_rel();
906 return (pmap_di_store_invl(p, &prev, &new_prev));
910 pmap_delayed_invl_finish_u(void)
912 struct pmap_invl_gen *invl_gen, *p;
914 struct lock_delay_arg lda;
918 invl_gen = &td->td_md.md_invl_gen;
919 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
920 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
921 ("missed invl_start: INVALID"));
922 lock_delay_arg_init(&lda, &di_delay);
925 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
926 prevl = (uintptr_t)atomic_load_ptr(&p->next);
927 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
928 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
932 if ((void *)prevl == invl_gen)
937 * It is legitimate to not find ourself on the list if a
938 * thread before us finished its DI and started it again.
940 if (__predict_false(p == NULL)) {
941 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
947 atomic_set_ptr((uintptr_t *)&invl_gen->next,
948 PMAP_INVL_GEN_NEXT_INVALID);
949 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
950 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
951 PMAP_INVL_GEN_NEXT_INVALID);
953 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
958 if (atomic_load_int(&pmap_invl_waiters) > 0)
959 pmap_delayed_invl_finish_unblock(0);
960 if (invl_gen->saved_pri != 0) {
962 sched_prio(td, invl_gen->saved_pri);
968 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
970 struct pmap_invl_gen *p, *pn;
975 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
977 nextl = (uintptr_t)atomic_load_ptr(&p->next);
978 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
979 td = first ? NULL : __containerof(p, struct thread,
981 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
982 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
983 td != NULL ? td->td_tid : -1);
989 static long invl_wait;
990 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
991 "Number of times DI invalidation blocked pmap_remove_all/write");
992 static long invl_wait_slow;
993 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
994 "Number of slow invalidation waits for lockless DI");
999 pmap_delayed_invl_genp(vm_page_t m)
1004 pa = VM_PAGE_TO_PHYS(m);
1005 if (__predict_false((pa) > pmap_last_pa))
1006 gen = &pv_dummy_large.pv_invl_gen;
1008 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1014 pmap_delayed_invl_genp(vm_page_t m)
1017 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1022 pmap_delayed_invl_callout_func(void *arg __unused)
1025 if (atomic_load_int(&pmap_invl_waiters) == 0)
1027 pmap_delayed_invl_finish_unblock(0);
1031 pmap_delayed_invl_callout_init(void *arg __unused)
1034 if (pmap_di_locked())
1036 callout_init(&pmap_invl_callout, 1);
1037 pmap_invl_callout_inited = true;
1039 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1040 pmap_delayed_invl_callout_init, NULL);
1043 * Ensure that all currently executing DI blocks, that need to flush
1044 * TLB for the given page m, actually flushed the TLB at the time the
1045 * function returned. If the page m has an empty PV list and we call
1046 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1047 * valid mapping for the page m in either its page table or TLB.
1049 * This function works by blocking until the global DI generation
1050 * number catches up with the generation number associated with the
1051 * given page m and its PV list. Since this function's callers
1052 * typically own an object lock and sometimes own a page lock, it
1053 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1057 pmap_delayed_invl_wait_l(vm_page_t m)
1061 bool accounted = false;
1064 m_gen = pmap_delayed_invl_genp(m);
1065 while (*m_gen > pmap_invl_gen) {
1068 atomic_add_long(&invl_wait, 1);
1072 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1077 pmap_delayed_invl_wait_u(vm_page_t m)
1080 struct lock_delay_arg lda;
1084 m_gen = pmap_delayed_invl_genp(m);
1085 lock_delay_arg_init(&lda, &di_delay);
1086 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1087 if (fast || !pmap_invl_callout_inited) {
1088 PV_STAT(atomic_add_long(&invl_wait, 1));
1093 * The page's invalidation generation number
1094 * is still below the current thread's number.
1095 * Prepare to block so that we do not waste
1096 * CPU cycles or worse, suffer livelock.
1098 * Since it is impossible to block without
1099 * racing with pmap_delayed_invl_finish_u(),
1100 * prepare for the race by incrementing
1101 * pmap_invl_waiters and arming a 1-tick
1102 * callout which will unblock us if we lose
1105 atomic_add_int(&pmap_invl_waiters, 1);
1108 * Re-check the current thread's invalidation
1109 * generation after incrementing
1110 * pmap_invl_waiters, so that there is no race
1111 * with pmap_delayed_invl_finish_u() setting
1112 * the page generation and checking
1113 * pmap_invl_waiters. The only race allowed
1114 * is for a missed unblock, which is handled
1118 atomic_load_long(&pmap_invl_gen_head.gen)) {
1119 callout_reset(&pmap_invl_callout, 1,
1120 pmap_delayed_invl_callout_func, NULL);
1121 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1122 pmap_delayed_invl_wait_block(m_gen,
1123 &pmap_invl_gen_head.gen);
1125 atomic_add_int(&pmap_invl_waiters, -1);
1130 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1133 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1134 pmap_thread_init_invl_gen_u);
1137 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1140 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1141 pmap_delayed_invl_start_u);
1144 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1147 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1148 pmap_delayed_invl_finish_u);
1151 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1154 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1155 pmap_delayed_invl_wait_u);
1159 * Mark the page m's PV list as participating in the current thread's
1160 * DI block. Any threads concurrently using m's PV list to remove or
1161 * restrict all mappings to m will wait for the current thread's DI
1162 * block to complete before proceeding.
1164 * The function works by setting the DI generation number for m's PV
1165 * list to at least the DI generation number of the current thread.
1166 * This forces a caller of pmap_delayed_invl_wait() to block until
1167 * current thread calls pmap_delayed_invl_finish().
1170 pmap_delayed_invl_page(vm_page_t m)
1174 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1175 gen = curthread->td_md.md_invl_gen.gen;
1178 m_gen = pmap_delayed_invl_genp(m);
1186 static caddr_t crashdumpmap;
1189 * Internal flags for pmap_enter()'s helper functions.
1191 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1192 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1195 * Internal flags for pmap_mapdev_internal() and
1196 * pmap_change_props_locked().
1198 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1199 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1200 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1202 TAILQ_HEAD(pv_chunklist, pv_chunk);
1204 static void free_pv_chunk(struct pv_chunk *pc);
1205 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1206 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1207 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1208 static int popcnt_pc_map_pq(uint64_t *map);
1209 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1210 static void reserve_pv_entries(pmap_t pmap, int needed,
1211 struct rwlock **lockp);
1212 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1213 struct rwlock **lockp);
1214 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1215 u_int flags, struct rwlock **lockp);
1216 #if VM_NRESERVLEVEL > 0
1217 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1218 struct rwlock **lockp);
1220 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1221 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1224 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1225 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1226 vm_prot_t prot, int mode, int flags);
1227 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1228 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1229 vm_offset_t va, struct rwlock **lockp);
1230 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1232 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1233 vm_prot_t prot, struct rwlock **lockp);
1234 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1235 u_int flags, vm_page_t m, struct rwlock **lockp);
1236 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1237 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1238 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1239 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1240 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1242 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1244 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1246 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1247 static vm_page_t pmap_large_map_getptp_unlocked(void);
1248 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1249 #if VM_NRESERVLEVEL > 0
1250 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1251 struct rwlock **lockp);
1253 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1255 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1256 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1258 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1259 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1260 static void pmap_pti_wire_pte(void *pte);
1261 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1262 struct spglist *free, struct rwlock **lockp);
1263 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1264 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1265 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1266 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1267 struct spglist *free);
1268 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1269 pd_entry_t *pde, struct spglist *free,
1270 struct rwlock **lockp);
1271 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1272 vm_page_t m, struct rwlock **lockp);
1273 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1275 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1277 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1278 struct rwlock **lockp, vm_offset_t va);
1279 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1280 struct rwlock **lockp);
1281 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1282 struct rwlock **lockp);
1284 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1285 struct spglist *free);
1286 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1288 /********************/
1289 /* Inline functions */
1290 /********************/
1293 * Return a non-clipped indexes for a given VA, which are page table
1294 * pages indexes at the corresponding level.
1296 static __inline vm_pindex_t
1297 pmap_pde_pindex(vm_offset_t va)
1299 return (va >> PDRSHIFT);
1302 static __inline vm_pindex_t
1303 pmap_pdpe_pindex(vm_offset_t va)
1305 return (NUPDE + (va >> PDPSHIFT));
1308 static __inline vm_pindex_t
1309 pmap_pml4e_pindex(vm_offset_t va)
1311 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1314 static __inline vm_pindex_t
1315 pmap_pml5e_pindex(vm_offset_t va)
1317 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1320 static __inline pml4_entry_t *
1321 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1324 MPASS(pmap_is_la57(pmap));
1325 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1328 static __inline pml4_entry_t *
1329 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1332 MPASS(pmap_is_la57(pmap));
1333 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1336 static __inline pml4_entry_t *
1337 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1339 pml4_entry_t *pml4e;
1341 /* XXX MPASS(pmap_is_la57(pmap); */
1342 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1343 return (&pml4e[pmap_pml4e_index(va)]);
1346 /* Return a pointer to the PML4 slot that corresponds to a VA */
1347 static __inline pml4_entry_t *
1348 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1350 pml5_entry_t *pml5e;
1351 pml4_entry_t *pml4e;
1354 if (pmap_is_la57(pmap)) {
1355 pml5e = pmap_pml5e(pmap, va);
1356 PG_V = pmap_valid_bit(pmap);
1357 if ((*pml5e & PG_V) == 0)
1359 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1361 pml4e = pmap->pm_pmltop;
1363 return (&pml4e[pmap_pml4e_index(va)]);
1366 static __inline pml4_entry_t *
1367 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1369 MPASS(!pmap_is_la57(pmap));
1370 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1373 /* Return a pointer to the PDP slot that corresponds to a VA */
1374 static __inline pdp_entry_t *
1375 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1379 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1380 return (&pdpe[pmap_pdpe_index(va)]);
1383 /* Return a pointer to the PDP slot that corresponds to a VA */
1384 static __inline pdp_entry_t *
1385 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1387 pml4_entry_t *pml4e;
1390 PG_V = pmap_valid_bit(pmap);
1391 pml4e = pmap_pml4e(pmap, va);
1392 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1394 return (pmap_pml4e_to_pdpe(pml4e, va));
1397 /* Return a pointer to the PD slot that corresponds to a VA */
1398 static __inline pd_entry_t *
1399 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1403 KASSERT((*pdpe & PG_PS) == 0,
1404 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1405 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1406 return (&pde[pmap_pde_index(va)]);
1409 /* Return a pointer to the PD slot that corresponds to a VA */
1410 static __inline pd_entry_t *
1411 pmap_pde(pmap_t pmap, vm_offset_t va)
1416 PG_V = pmap_valid_bit(pmap);
1417 pdpe = pmap_pdpe(pmap, va);
1418 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1420 KASSERT((*pdpe & PG_PS) == 0,
1421 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1422 return (pmap_pdpe_to_pde(pdpe, va));
1425 /* Return a pointer to the PT slot that corresponds to a VA */
1426 static __inline pt_entry_t *
1427 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1431 KASSERT((*pde & PG_PS) == 0,
1432 ("%s: pde %#lx is a leaf", __func__, *pde));
1433 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1434 return (&pte[pmap_pte_index(va)]);
1437 /* Return a pointer to the PT slot that corresponds to a VA */
1438 static __inline pt_entry_t *
1439 pmap_pte(pmap_t pmap, vm_offset_t va)
1444 PG_V = pmap_valid_bit(pmap);
1445 pde = pmap_pde(pmap, va);
1446 if (pde == NULL || (*pde & PG_V) == 0)
1448 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1449 return ((pt_entry_t *)pde);
1450 return (pmap_pde_to_pte(pde, va));
1453 static __inline void
1454 pmap_resident_count_inc(pmap_t pmap, int count)
1457 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1458 pmap->pm_stats.resident_count += count;
1461 static __inline void
1462 pmap_resident_count_dec(pmap_t pmap, int count)
1465 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1466 KASSERT(pmap->pm_stats.resident_count >= count,
1467 ("pmap %p resident count underflow %ld %d", pmap,
1468 pmap->pm_stats.resident_count, count));
1469 pmap->pm_stats.resident_count -= count;
1472 PMAP_INLINE pt_entry_t *
1473 vtopte(vm_offset_t va)
1477 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1480 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1481 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1482 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1484 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1485 NPML4EPGSHIFT)) - 1);
1486 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1490 static __inline pd_entry_t *
1491 vtopde(vm_offset_t va)
1495 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1498 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1499 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1500 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1502 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1503 NPML4EPGSHIFT)) - 1);
1504 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1509 allocpages(vm_paddr_t *firstaddr, int n)
1514 bzero((void *)ret, n * PAGE_SIZE);
1515 *firstaddr += n * PAGE_SIZE;
1519 CTASSERT(powerof2(NDMPML4E));
1521 /* number of kernel PDP slots */
1522 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1525 nkpt_init(vm_paddr_t addr)
1532 pt_pages = howmany(addr, 1 << PDRSHIFT);
1533 pt_pages += NKPDPE(pt_pages);
1536 * Add some slop beyond the bare minimum required for bootstrapping
1539 * This is quite important when allocating KVA for kernel modules.
1540 * The modules are required to be linked in the negative 2GB of
1541 * the address space. If we run out of KVA in this region then
1542 * pmap_growkernel() will need to allocate page table pages to map
1543 * the entire 512GB of KVA space which is an unnecessary tax on
1546 * Secondly, device memory mapped as part of setting up the low-
1547 * level console(s) is taken from KVA, starting at virtual_avail.
1548 * This is because cninit() is called after pmap_bootstrap() but
1549 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1552 pt_pages += 32; /* 64MB additional slop. */
1558 * Returns the proper write/execute permission for a physical page that is
1559 * part of the initial boot allocations.
1561 * If the page has kernel text, it is marked as read-only. If the page has
1562 * kernel read-only data, it is marked as read-only/not-executable. If the
1563 * page has only read-write data, it is marked as read-write/not-executable.
1564 * If the page is below/above the kernel range, it is marked as read-write.
1566 * This function operates on 2M pages, since we map the kernel space that
1569 static inline pt_entry_t
1570 bootaddr_rwx(vm_paddr_t pa)
1574 * The kernel is loaded at a 2MB-aligned address, and memory below that
1575 * need not be executable. The .bss section is padded to a 2MB
1576 * boundary, so memory following the kernel need not be executable
1577 * either. Preloaded kernel modules have their mapping permissions
1578 * fixed up by the linker.
1580 if (pa < trunc_2mpage(btext - KERNBASE) ||
1581 pa >= trunc_2mpage(_end - KERNBASE))
1582 return (X86_PG_RW | pg_nx);
1585 * The linker should ensure that the read-only and read-write
1586 * portions don't share the same 2M page, so this shouldn't
1587 * impact read-only data. However, in any case, any page with
1588 * read-write data needs to be read-write.
1590 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1591 return (X86_PG_RW | pg_nx);
1594 * Mark any 2M page containing kernel text as read-only. Mark
1595 * other pages with read-only data as read-only and not executable.
1596 * (It is likely a small portion of the read-only data section will
1597 * be marked as read-only, but executable. This should be acceptable
1598 * since the read-only protection will keep the data from changing.)
1599 * Note that fixups to the .text section will still work until we
1602 if (pa < round_2mpage(etext - KERNBASE))
1608 create_pagetables(vm_paddr_t *firstaddr)
1610 int i, j, ndm1g, nkpdpe, nkdmpde;
1614 uint64_t DMPDkernphys;
1616 /* Allocate page table pages for the direct map */
1617 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1618 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1620 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1621 if (ndmpdpphys > NDMPML4E) {
1623 * Each NDMPML4E allows 512 GB, so limit to that,
1624 * and then readjust ndmpdp and ndmpdpphys.
1626 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1627 Maxmem = atop(NDMPML4E * NBPML4);
1628 ndmpdpphys = NDMPML4E;
1629 ndmpdp = NDMPML4E * NPDEPG;
1631 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1633 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1635 * Calculate the number of 1G pages that will fully fit in
1638 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1641 * Allocate 2M pages for the kernel. These will be used in
1642 * place of the first one or more 1G pages from ndm1g.
1644 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1645 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1648 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1649 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1651 /* Allocate pages */
1652 KPML4phys = allocpages(firstaddr, 1);
1653 KPDPphys = allocpages(firstaddr, NKPML4E);
1656 * Allocate the initial number of kernel page table pages required to
1657 * bootstrap. We defer this until after all memory-size dependent
1658 * allocations are done (e.g. direct map), so that we don't have to
1659 * build in too much slop in our estimate.
1661 * Note that when NKPML4E > 1, we have an empty page underneath
1662 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1663 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1665 nkpt_init(*firstaddr);
1666 nkpdpe = NKPDPE(nkpt);
1668 KPTphys = allocpages(firstaddr, nkpt);
1669 KPDphys = allocpages(firstaddr, nkpdpe);
1672 * Connect the zero-filled PT pages to their PD entries. This
1673 * implicitly maps the PT pages at their correct locations within
1676 pd_p = (pd_entry_t *)KPDphys;
1677 for (i = 0; i < nkpt; i++)
1678 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1681 * Map from physical address zero to the end of loader preallocated
1682 * memory using 2MB pages. This replaces some of the PD entries
1685 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1686 /* Preset PG_M and PG_A because demotion expects it. */
1687 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1688 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1691 * Because we map the physical blocks in 2M pages, adjust firstaddr
1692 * to record the physical blocks we've actually mapped into kernel
1693 * virtual address space.
1695 if (*firstaddr < round_2mpage(KERNend))
1696 *firstaddr = round_2mpage(KERNend);
1698 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1699 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1700 for (i = 0; i < nkpdpe; i++)
1701 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1704 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1705 * the end of physical memory is not aligned to a 1GB page boundary,
1706 * then the residual physical memory is mapped with 2MB pages. Later,
1707 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1708 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1709 * that are partially used.
1711 pd_p = (pd_entry_t *)DMPDphys;
1712 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1713 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1714 /* Preset PG_M and PG_A because demotion expects it. */
1715 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1716 X86_PG_M | X86_PG_A | pg_nx;
1718 pdp_p = (pdp_entry_t *)DMPDPphys;
1719 for (i = 0; i < ndm1g; i++) {
1720 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1721 /* Preset PG_M and PG_A because demotion expects it. */
1722 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1723 X86_PG_M | X86_PG_A | pg_nx;
1725 for (j = 0; i < ndmpdp; i++, j++) {
1726 pdp_p[i] = DMPDphys + ptoa(j);
1727 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1731 * Instead of using a 1G page for the memory containing the kernel,
1732 * use 2M pages with read-only and no-execute permissions. (If using 1G
1733 * pages, this will partially overwrite the PDPEs above.)
1736 pd_p = (pd_entry_t *)DMPDkernphys;
1737 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1738 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1739 X86_PG_M | X86_PG_A | pg_nx |
1740 bootaddr_rwx(i << PDRSHIFT);
1741 for (i = 0; i < nkdmpde; i++)
1742 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1746 /* And recursively map PML4 to itself in order to get PTmap */
1747 p4_p = (pml4_entry_t *)KPML4phys;
1748 p4_p[PML4PML4I] = KPML4phys;
1749 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1751 /* Connect the Direct Map slot(s) up to the PML4. */
1752 for (i = 0; i < ndmpdpphys; i++) {
1753 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1754 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1757 /* Connect the KVA slots up to the PML4 */
1758 for (i = 0; i < NKPML4E; i++) {
1759 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1760 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1763 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1767 * Bootstrap the system enough to run with virtual memory.
1769 * On amd64 this is called after mapping has already been enabled
1770 * and just syncs the pmap module with what has already been done.
1771 * [We can't call it easily with mapping off since the kernel is not
1772 * mapped with PA == VA, hence we would have to relocate every address
1773 * from the linked base (virtual) address "KERNBASE" to the actual
1774 * (physical) address starting relative to 0]
1777 pmap_bootstrap(vm_paddr_t *firstaddr)
1780 pt_entry_t *pte, *pcpu_pte;
1781 struct region_descriptor r_gdt;
1782 uint64_t cr4, pcpu_phys;
1786 KERNend = *firstaddr;
1787 res = atop(KERNend - (vm_paddr_t)kernphys);
1793 * Create an initial set of page tables to run the kernel in.
1795 create_pagetables(firstaddr);
1797 pcpu_phys = allocpages(firstaddr, MAXCPU);
1800 * Add a physical memory segment (vm_phys_seg) corresponding to the
1801 * preallocated kernel page table pages so that vm_page structures
1802 * representing these pages will be created. The vm_page structures
1803 * are required for promotion of the corresponding kernel virtual
1804 * addresses to superpage mappings.
1806 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1809 * Account for the virtual addresses mapped by create_pagetables().
1811 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1812 virtual_end = VM_MAX_KERNEL_ADDRESS;
1815 * Enable PG_G global pages, then switch to the kernel page
1816 * table from the bootstrap page table. After the switch, it
1817 * is possible to enable SMEP and SMAP since PG_U bits are
1823 load_cr3(KPML4phys);
1824 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1826 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1831 * Initialize the kernel pmap (which is statically allocated).
1832 * Count bootstrap data as being resident in case any of this data is
1833 * later unmapped (using pmap_remove()) and freed.
1835 PMAP_LOCK_INIT(kernel_pmap);
1836 kernel_pmap->pm_pmltop = kernel_pml4;
1837 kernel_pmap->pm_cr3 = KPML4phys;
1838 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1839 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1840 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1841 kernel_pmap->pm_stats.resident_count = res;
1842 kernel_pmap->pm_flags = pmap_flags;
1845 * Initialize the TLB invalidations generation number lock.
1847 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1850 * Reserve some special page table entries/VA space for temporary
1853 #define SYSMAP(c, p, v, n) \
1854 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1860 * Crashdump maps. The first page is reused as CMAP1 for the
1863 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1864 CADDR1 = crashdumpmap;
1866 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1869 for (i = 0; i < MAXCPU; i++) {
1870 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1871 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1875 * Re-initialize PCPU area for BSP after switching.
1876 * Make hardware use gdt and common_tss from the new PCPU.
1878 STAILQ_INIT(&cpuhead);
1879 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1880 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1881 amd64_bsp_pcpu_init1(&__pcpu[0]);
1882 amd64_bsp_ist_init(&__pcpu[0]);
1883 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1885 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1886 sizeof(struct user_segment_descriptor));
1887 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1888 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1889 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1890 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1891 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1893 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1894 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1895 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1896 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1899 * Initialize the PAT MSR.
1900 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1901 * side-effect, invalidates stale PG_G TLB entries that might
1902 * have been created in our pre-boot environment.
1906 /* Initialize TLB Context Id. */
1907 if (pmap_pcid_enabled) {
1908 for (i = 0; i < MAXCPU; i++) {
1909 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1910 kernel_pmap->pm_pcids[i].pm_gen = 1;
1914 * PMAP_PCID_KERN + 1 is used for initialization of
1915 * proc0 pmap. The pmap' pcid state might be used by
1916 * EFIRT entry before first context switch, so it
1917 * needs to be valid.
1919 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1920 PCPU_SET(pcid_gen, 1);
1923 * pcpu area for APs is zeroed during AP startup.
1924 * pc_pcid_next and pc_pcid_gen are initialized by AP
1925 * during pcpu setup.
1927 load_cr4(rcr4() | CR4_PCIDE);
1932 * Setup the PAT MSR.
1941 /* Bail if this CPU doesn't implement PAT. */
1942 if ((cpu_feature & CPUID_PAT) == 0)
1945 /* Set default PAT index table. */
1946 for (i = 0; i < PAT_INDEX_SIZE; i++)
1948 pat_index[PAT_WRITE_BACK] = 0;
1949 pat_index[PAT_WRITE_THROUGH] = 1;
1950 pat_index[PAT_UNCACHEABLE] = 3;
1951 pat_index[PAT_WRITE_COMBINING] = 6;
1952 pat_index[PAT_WRITE_PROTECTED] = 5;
1953 pat_index[PAT_UNCACHED] = 2;
1956 * Initialize default PAT entries.
1957 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1958 * Program 5 and 6 as WP and WC.
1960 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1961 * mapping for a 2M page uses a PAT value with the bit 3 set due
1962 * to its overload with PG_PS.
1964 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1965 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1966 PAT_VALUE(2, PAT_UNCACHED) |
1967 PAT_VALUE(3, PAT_UNCACHEABLE) |
1968 PAT_VALUE(4, PAT_WRITE_BACK) |
1969 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1970 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1971 PAT_VALUE(7, PAT_UNCACHEABLE);
1975 load_cr4(cr4 & ~CR4_PGE);
1977 /* Disable caches (CD = 1, NW = 0). */
1979 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1981 /* Flushes caches and TLBs. */
1985 /* Update PAT and index table. */
1986 wrmsr(MSR_PAT, pat_msr);
1988 /* Flush caches and TLBs again. */
1992 /* Restore caches and PGE. */
1997 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
1998 la57_trampoline_gdt[], la57_trampoline_end[];
2001 pmap_bootstrap_la57(void *arg __unused)
2004 pml5_entry_t *v_pml5;
2005 pml4_entry_t *v_pml4;
2009 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2010 void (*la57_tramp)(uint64_t pml5);
2011 struct region_descriptor r_gdt;
2013 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2015 if (!TUNABLE_INT_FETCH("vm.pmap.la57", &la57))
2020 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2021 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2023 m_code = vm_page_alloc_contig(NULL, 0,
2024 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2025 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2026 if ((m_code->flags & PG_ZERO) == 0)
2027 pmap_zero_page(m_code);
2028 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2029 m_pml5 = vm_page_alloc_contig(NULL, 0,
2030 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2031 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2032 if ((m_pml5->flags & PG_ZERO) == 0)
2033 pmap_zero_page(m_pml5);
2034 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2035 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2036 m_pml4 = vm_page_alloc_contig(NULL, 0,
2037 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2038 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2039 if ((m_pml4->flags & PG_ZERO) == 0)
2040 pmap_zero_page(m_pml4);
2041 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2042 m_pdp = vm_page_alloc_contig(NULL, 0,
2043 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2044 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2045 if ((m_pdp->flags & PG_ZERO) == 0)
2046 pmap_zero_page(m_pdp);
2047 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2048 m_pd = vm_page_alloc_contig(NULL, 0,
2049 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2050 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2051 if ((m_pd->flags & PG_ZERO) == 0)
2052 pmap_zero_page(m_pd);
2053 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2054 m_pt = vm_page_alloc_contig(NULL, 0,
2055 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2056 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2057 if ((m_pt->flags & PG_ZERO) == 0)
2058 pmap_zero_page(m_pt);
2059 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2062 * Map m_code 1:1, it appears below 4G in KVA due to physical
2063 * address being below 4G. Since kernel KVA is in upper half,
2064 * the pml4e should be zero and free for temporary use.
2066 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2067 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2069 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2070 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2072 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2073 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2075 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2076 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2080 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2081 * entering all existing kernel mappings into level 5 table.
2083 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2084 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2087 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2089 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2090 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2092 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2093 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2097 * Copy and call the 48->57 trampoline, hope we return there, alive.
2099 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2100 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2101 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2102 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2103 la57_tramp(KPML5phys);
2106 * gdt was necessary reset, switch back to our gdt.
2109 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2113 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2114 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2115 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2118 * Now unmap the trampoline, and free the pages.
2119 * Clear pml5 entry used for 1:1 trampoline mapping.
2121 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2122 invlpg((vm_offset_t)v_code);
2123 vm_page_free(m_code);
2124 vm_page_free(m_pdp);
2129 * Recursively map PML5 to itself in order to get PTmap and
2132 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2134 kernel_pmap->pm_cr3 = KPML5phys;
2135 kernel_pmap->pm_pmltop = v_pml5;
2137 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2140 * Initialize a vm_page's machine-dependent fields.
2143 pmap_page_init(vm_page_t m)
2146 TAILQ_INIT(&m->md.pv_list);
2147 m->md.pat_mode = PAT_WRITE_BACK;
2150 static int pmap_allow_2m_x_ept;
2151 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2152 &pmap_allow_2m_x_ept, 0,
2153 "Allow executable superpage mappings in EPT");
2156 pmap_allow_2m_x_ept_recalculate(void)
2159 * SKL002, SKL012S. Since the EPT format is only used by
2160 * Intel CPUs, the vendor check is merely a formality.
2162 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2163 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2164 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2165 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2166 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2167 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2168 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2169 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2170 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2171 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2172 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2173 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2174 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2175 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2176 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2177 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2178 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2179 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2180 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2181 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2182 CPUID_TO_MODEL(cpu_id) == 0x85))))
2183 pmap_allow_2m_x_ept = 1;
2184 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2188 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2191 return (pmap->pm_type != PT_EPT || !executable ||
2192 !pmap_allow_2m_x_ept);
2197 pmap_init_pv_table(void)
2199 struct pmap_large_md_page *pvd;
2201 long start, end, highest, pv_npg;
2202 int domain, i, j, pages;
2205 * We strongly depend on the size being a power of two, so the assert
2206 * is overzealous. However, should the struct be resized to a
2207 * different power of two, the code below needs to be revisited.
2209 CTASSERT((sizeof(*pvd) == 64));
2212 * Calculate the size of the array.
2214 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2215 pv_npg = howmany(pmap_last_pa, NBPDR);
2216 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2218 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2219 if (pv_table == NULL)
2220 panic("%s: kva_alloc failed\n", __func__);
2223 * Iterate physical segments to allocate space for respective pages.
2227 for (i = 0; i < vm_phys_nsegs; i++) {
2228 end = vm_phys_segs[i].end / NBPDR;
2229 domain = vm_phys_segs[i].domain;
2234 start = highest + 1;
2235 pvd = &pv_table[start];
2237 pages = end - start + 1;
2238 s = round_page(pages * sizeof(*pvd));
2239 highest = start + (s / sizeof(*pvd)) - 1;
2241 for (j = 0; j < s; j += PAGE_SIZE) {
2242 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2243 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2245 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2246 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2249 for (j = 0; j < s / sizeof(*pvd); j++) {
2250 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2251 TAILQ_INIT(&pvd->pv_page.pv_list);
2252 pvd->pv_page.pv_gen = 0;
2253 pvd->pv_page.pat_mode = 0;
2254 pvd->pv_invl_gen = 0;
2258 pvd = &pv_dummy_large;
2259 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2260 TAILQ_INIT(&pvd->pv_page.pv_list);
2261 pvd->pv_page.pv_gen = 0;
2262 pvd->pv_page.pat_mode = 0;
2263 pvd->pv_invl_gen = 0;
2267 pmap_init_pv_table(void)
2273 * Initialize the pool of pv list locks.
2275 for (i = 0; i < NPV_LIST_LOCKS; i++)
2276 rw_init(&pv_list_locks[i], "pmap pv list");
2279 * Calculate the size of the pv head table for superpages.
2281 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2284 * Allocate memory for the pv head table for superpages.
2286 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2288 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2289 for (i = 0; i < pv_npg; i++)
2290 TAILQ_INIT(&pv_table[i].pv_list);
2291 TAILQ_INIT(&pv_dummy.pv_list);
2296 * Initialize the pmap module.
2297 * Called by vm_init, to initialize any structures that the pmap
2298 * system needs to map virtual memory.
2303 struct pmap_preinit_mapping *ppim;
2305 int error, i, ret, skz63;
2307 /* L1TF, reserve page @0 unconditionally */
2308 vm_page_blacklist_add(0, bootverbose);
2310 /* Detect bare-metal Skylake Server and Skylake-X. */
2311 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2312 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2314 * Skylake-X errata SKZ63. Processor May Hang When
2315 * Executing Code In an HLE Transaction Region between
2316 * 40000000H and 403FFFFFH.
2318 * Mark the pages in the range as preallocated. It
2319 * seems to be impossible to distinguish between
2320 * Skylake Server and Skylake X.
2323 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2326 printf("SKZ63: skipping 4M RAM starting "
2327 "at physical 1G\n");
2328 for (i = 0; i < atop(0x400000); i++) {
2329 ret = vm_page_blacklist_add(0x40000000 +
2331 if (!ret && bootverbose)
2332 printf("page at %#lx already used\n",
2333 0x40000000 + ptoa(i));
2339 pmap_allow_2m_x_ept_recalculate();
2342 * Initialize the vm page array entries for the kernel pmap's
2345 PMAP_LOCK(kernel_pmap);
2346 for (i = 0; i < nkpt; i++) {
2347 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2348 KASSERT(mpte >= vm_page_array &&
2349 mpte < &vm_page_array[vm_page_array_size],
2350 ("pmap_init: page table page is out of range"));
2351 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2352 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2353 mpte->ref_count = 1;
2356 * Collect the page table pages that were replaced by a 2MB
2357 * page in create_pagetables(). They are zero filled.
2359 if ((vm_paddr_t)i << PDRSHIFT < KERNend &&
2360 pmap_insert_pt_page(kernel_pmap, mpte, false))
2361 panic("pmap_init: pmap_insert_pt_page failed");
2363 PMAP_UNLOCK(kernel_pmap);
2367 * If the kernel is running on a virtual machine, then it must assume
2368 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2369 * be prepared for the hypervisor changing the vendor and family that
2370 * are reported by CPUID. Consequently, the workaround for AMD Family
2371 * 10h Erratum 383 is enabled if the processor's feature set does not
2372 * include at least one feature that is only supported by older Intel
2373 * or newer AMD processors.
2375 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2376 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2377 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2379 workaround_erratum383 = 1;
2382 * Are large page mappings enabled?
2384 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2385 if (pg_ps_enabled) {
2386 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2387 ("pmap_init: can't assign to pagesizes[1]"));
2388 pagesizes[1] = NBPDR;
2389 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2390 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2391 ("pmap_init: can't assign to pagesizes[2]"));
2392 pagesizes[2] = NBPDP;
2397 * Initialize pv chunk lists.
2399 for (i = 0; i < PMAP_MEMDOM; i++) {
2400 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2401 TAILQ_INIT(&pv_chunks[i].pvc_list);
2403 pmap_init_pv_table();
2405 pmap_initialized = 1;
2406 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2407 ppim = pmap_preinit_mapping + i;
2410 /* Make the direct map consistent */
2411 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2412 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2413 ppim->sz, ppim->mode);
2417 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2418 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2421 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2422 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2423 (vmem_addr_t *)&qframe);
2425 panic("qframe allocation failed");
2428 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2429 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2430 lm_ents = LMEPML4I - LMSPML4I + 1;
2432 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2433 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2435 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2436 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2437 if (large_vmem == NULL) {
2438 printf("pmap: cannot create large map\n");
2441 for (i = 0; i < lm_ents; i++) {
2442 m = pmap_large_map_getptp_unlocked();
2444 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2445 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2451 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2452 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2453 "Maximum number of PML4 entries for use by large map (tunable). "
2454 "Each entry corresponds to 512GB of address space.");
2456 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2457 "2MB page mapping counters");
2459 static u_long pmap_pde_demotions;
2460 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2461 &pmap_pde_demotions, 0, "2MB page demotions");
2463 static u_long pmap_pde_mappings;
2464 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2465 &pmap_pde_mappings, 0, "2MB page mappings");
2467 static u_long pmap_pde_p_failures;
2468 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2469 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2471 static u_long pmap_pde_promotions;
2472 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2473 &pmap_pde_promotions, 0, "2MB page promotions");
2475 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2476 "1GB page mapping counters");
2478 static u_long pmap_pdpe_demotions;
2479 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2480 &pmap_pdpe_demotions, 0, "1GB page demotions");
2482 /***************************************************
2483 * Low level helper routines.....
2484 ***************************************************/
2487 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2489 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2491 switch (pmap->pm_type) {
2494 /* Verify that both PAT bits are not set at the same time */
2495 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2496 ("Invalid PAT bits in entry %#lx", entry));
2498 /* Swap the PAT bits if one of them is set */
2499 if ((entry & x86_pat_bits) != 0)
2500 entry ^= x86_pat_bits;
2504 * Nothing to do - the memory attributes are represented
2505 * the same way for regular pages and superpages.
2509 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2516 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2519 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2520 pat_index[(int)mode] >= 0);
2524 * Determine the appropriate bits to set in a PTE or PDE for a specified
2528 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2530 int cache_bits, pat_flag, pat_idx;
2532 if (!pmap_is_valid_memattr(pmap, mode))
2533 panic("Unknown caching mode %d\n", mode);
2535 switch (pmap->pm_type) {
2538 /* The PAT bit is different for PTE's and PDE's. */
2539 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2541 /* Map the caching mode to a PAT index. */
2542 pat_idx = pat_index[mode];
2544 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2547 cache_bits |= pat_flag;
2549 cache_bits |= PG_NC_PCD;
2551 cache_bits |= PG_NC_PWT;
2555 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2559 panic("unsupported pmap type %d", pmap->pm_type);
2562 return (cache_bits);
2566 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2570 switch (pmap->pm_type) {
2573 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2576 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2579 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2586 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2588 int pat_flag, pat_idx;
2591 switch (pmap->pm_type) {
2594 /* The PAT bit is different for PTE's and PDE's. */
2595 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2597 if ((pte & pat_flag) != 0)
2599 if ((pte & PG_NC_PCD) != 0)
2601 if ((pte & PG_NC_PWT) != 0)
2605 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2606 panic("EPT PTE %#lx has no PAT memory type", pte);
2607 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2611 /* See pmap_init_pat(). */
2621 pmap_ps_enabled(pmap_t pmap)
2624 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2628 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2631 switch (pmap->pm_type) {
2638 * This is a little bogus since the generation number is
2639 * supposed to be bumped up when a region of the address
2640 * space is invalidated in the page tables.
2642 * In this case the old PDE entry is valid but yet we want
2643 * to make sure that any mappings using the old entry are
2644 * invalidated in the TLB.
2646 * The reason this works as expected is because we rendezvous
2647 * "all" host cpus and force any vcpu context to exit as a
2650 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2653 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2655 pde_store(pde, newpde);
2659 * After changing the page size for the specified virtual address in the page
2660 * table, flush the corresponding entries from the processor's TLB. Only the
2661 * calling processor's TLB is affected.
2663 * The calling thread must be pinned to a processor.
2666 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2670 if (pmap_type_guest(pmap))
2673 KASSERT(pmap->pm_type == PT_X86,
2674 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2676 PG_G = pmap_global_bit(pmap);
2678 if ((newpde & PG_PS) == 0)
2679 /* Demotion: flush a specific 2MB page mapping. */
2681 else if ((newpde & PG_G) == 0)
2683 * Promotion: flush every 4KB page mapping from the TLB
2684 * because there are too many to flush individually.
2689 * Promotion: flush every 4KB page mapping from the TLB,
2690 * including any global (PG_G) mappings.
2698 * For SMP, these functions have to use the IPI mechanism for coherence.
2700 * N.B.: Before calling any of the following TLB invalidation functions,
2701 * the calling processor must ensure that all stores updating a non-
2702 * kernel page table are globally performed. Otherwise, another
2703 * processor could cache an old, pre-update entry without being
2704 * invalidated. This can happen one of two ways: (1) The pmap becomes
2705 * active on another processor after its pm_active field is checked by
2706 * one of the following functions but before a store updating the page
2707 * table is globally performed. (2) The pmap becomes active on another
2708 * processor before its pm_active field is checked but due to
2709 * speculative loads one of the following functions stills reads the
2710 * pmap as inactive on the other processor.
2712 * The kernel page table is exempt because its pm_active field is
2713 * immutable. The kernel page table is always active on every
2718 * Interrupt the cpus that are executing in the guest context.
2719 * This will force the vcpu to exit and the cached EPT mappings
2720 * will be invalidated by the host before the next vmresume.
2722 static __inline void
2723 pmap_invalidate_ept(pmap_t pmap)
2728 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2729 ("pmap_invalidate_ept: absurd pm_active"));
2732 * The TLB mappings associated with a vcpu context are not
2733 * flushed each time a different vcpu is chosen to execute.
2735 * This is in contrast with a process's vtop mappings that
2736 * are flushed from the TLB on each context switch.
2738 * Therefore we need to do more than just a TLB shootdown on
2739 * the active cpus in 'pmap->pm_active'. To do this we keep
2740 * track of the number of invalidations performed on this pmap.
2742 * Each vcpu keeps a cache of this counter and compares it
2743 * just before a vmresume. If the counter is out-of-date an
2744 * invept will be done to flush stale mappings from the TLB.
2746 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2749 * Force the vcpu to exit and trap back into the hypervisor.
2751 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2752 ipi_selected(pmap->pm_active, ipinum);
2757 pmap_invalidate_cpu_mask(pmap_t pmap)
2760 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2764 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2765 const bool invpcid_works1)
2767 struct invpcid_descr d;
2768 uint64_t kcr3, ucr3;
2772 cpuid = PCPU_GET(cpuid);
2773 if (pmap == PCPU_GET(curpmap)) {
2774 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2776 * If we context-switched right after
2777 * PCPU_GET(ucr3_load_mask), we could read the
2778 * ~CR3_PCID_SAVE mask, which causes us to skip
2779 * the code below to invalidate user pages. This
2780 * is handled in pmap_activate_sw_pcid_pti() by
2781 * clearing pm_gen if ucr3_load_mask is ~CR3_PCID_SAVE.
2783 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2785 * Because pm_pcid is recalculated on a
2786 * context switch, we must disable switching.
2787 * Otherwise, we might use a stale value
2791 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2792 if (invpcid_works1) {
2793 d.pcid = pcid | PMAP_PCID_USER_PT;
2796 invpcid(&d, INVPCID_ADDR);
2798 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2799 ucr3 = pmap->pm_ucr3 | pcid |
2800 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2801 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2806 pmap->pm_pcids[cpuid].pm_gen = 0;
2810 pmap->pm_pcids[i].pm_gen = 0;
2814 * The fence is between stores to pm_gen and the read of the
2815 * pm_active mask. We need to ensure that it is impossible
2816 * for us to miss the bit update in pm_active and
2817 * simultaneously observe a non-zero pm_gen in
2818 * pmap_activate_sw(), otherwise TLB update is missed.
2819 * Without the fence, IA32 allows such an outcome. Note that
2820 * pm_active is updated by a locked operation, which provides
2821 * the reciprocal fence.
2823 atomic_thread_fence_seq_cst();
2827 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2830 pmap_invalidate_page_pcid(pmap, va, true);
2834 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2837 pmap_invalidate_page_pcid(pmap, va, false);
2841 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2845 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2848 if (pmap_pcid_enabled)
2849 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2850 pmap_invalidate_page_pcid_noinvpcid);
2851 return (pmap_invalidate_page_nopcid);
2855 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
2856 vm_offset_t addr2 __unused)
2859 if (pmap == kernel_pmap) {
2862 if (pmap == PCPU_GET(curpmap))
2864 pmap_invalidate_page_mode(pmap, va);
2869 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2872 if (pmap_type_guest(pmap)) {
2873 pmap_invalidate_ept(pmap);
2877 KASSERT(pmap->pm_type == PT_X86,
2878 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2880 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
2881 pmap_invalidate_page_curcpu_cb);
2884 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2885 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2888 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2889 const bool invpcid_works1)
2891 struct invpcid_descr d;
2892 uint64_t kcr3, ucr3;
2896 cpuid = PCPU_GET(cpuid);
2897 if (pmap == PCPU_GET(curpmap)) {
2898 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2899 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2901 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2902 if (invpcid_works1) {
2903 d.pcid = pcid | PMAP_PCID_USER_PT;
2906 for (; d.addr < eva; d.addr += PAGE_SIZE)
2907 invpcid(&d, INVPCID_ADDR);
2909 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2910 ucr3 = pmap->pm_ucr3 | pcid |
2911 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2912 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2917 pmap->pm_pcids[cpuid].pm_gen = 0;
2921 pmap->pm_pcids[i].pm_gen = 0;
2923 /* See the comment in pmap_invalidate_page_pcid(). */
2924 atomic_thread_fence_seq_cst();
2928 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2932 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2936 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2940 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2944 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2948 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2952 if (pmap_pcid_enabled)
2953 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2954 pmap_invalidate_range_pcid_noinvpcid);
2955 return (pmap_invalidate_range_nopcid);
2959 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2963 if (pmap == kernel_pmap) {
2964 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2967 if (pmap == PCPU_GET(curpmap)) {
2968 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2971 pmap_invalidate_range_mode(pmap, sva, eva);
2976 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2979 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2980 pmap_invalidate_all(pmap);
2984 if (pmap_type_guest(pmap)) {
2985 pmap_invalidate_ept(pmap);
2989 KASSERT(pmap->pm_type == PT_X86,
2990 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2992 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
2993 pmap_invalidate_range_curcpu_cb);
2997 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2999 struct invpcid_descr d;
3004 if (pmap == kernel_pmap) {
3005 if (invpcid_works1) {
3006 bzero(&d, sizeof(d));
3007 invpcid(&d, INVPCID_CTXGLOB);
3012 cpuid = PCPU_GET(cpuid);
3013 if (pmap == PCPU_GET(curpmap)) {
3015 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3016 if (invpcid_works1) {
3020 invpcid(&d, INVPCID_CTX);
3022 kcr3 = pmap->pm_cr3 | pcid;
3025 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3026 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3029 pmap->pm_pcids[cpuid].pm_gen = 0;
3032 pmap->pm_pcids[i].pm_gen = 0;
3035 /* See the comment in pmap_invalidate_page_pcid(). */
3036 atomic_thread_fence_seq_cst();
3040 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
3043 pmap_invalidate_all_pcid(pmap, true);
3047 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
3050 pmap_invalidate_all_pcid(pmap, false);
3054 pmap_invalidate_all_nopcid(pmap_t pmap)
3057 if (pmap == kernel_pmap)
3059 else if (pmap == PCPU_GET(curpmap))
3063 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
3066 if (pmap_pcid_enabled)
3067 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
3068 pmap_invalidate_all_pcid_noinvpcid);
3069 return (pmap_invalidate_all_nopcid);
3073 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3074 vm_offset_t addr2 __unused)
3077 pmap_invalidate_all_mode(pmap);
3081 pmap_invalidate_all(pmap_t pmap)
3084 if (pmap_type_guest(pmap)) {
3085 pmap_invalidate_ept(pmap);
3089 KASSERT(pmap->pm_type == PT_X86,
3090 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3092 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3093 pmap_invalidate_all_curcpu_cb);
3097 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3098 vm_offset_t addr2 __unused)
3105 pmap_invalidate_cache(void)
3108 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3112 cpuset_t invalidate; /* processors that invalidate their TLB */
3117 u_int store; /* processor that updates the PDE */
3121 pmap_update_pde_action(void *arg)
3123 struct pde_action *act = arg;
3125 if (act->store == PCPU_GET(cpuid))
3126 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3130 pmap_update_pde_teardown(void *arg)
3132 struct pde_action *act = arg;
3134 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3135 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3139 * Change the page size for the specified virtual address in a way that
3140 * prevents any possibility of the TLB ever having two entries that map the
3141 * same virtual address using different page sizes. This is the recommended
3142 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3143 * machine check exception for a TLB state that is improperly diagnosed as a
3147 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3149 struct pde_action act;
3150 cpuset_t active, other_cpus;
3154 cpuid = PCPU_GET(cpuid);
3155 other_cpus = all_cpus;
3156 CPU_CLR(cpuid, &other_cpus);
3157 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3160 active = pmap->pm_active;
3162 if (CPU_OVERLAP(&active, &other_cpus)) {
3164 act.invalidate = active;
3168 act.newpde = newpde;
3169 CPU_SET(cpuid, &active);
3170 smp_rendezvous_cpus(active,
3171 smp_no_rendezvous_barrier, pmap_update_pde_action,
3172 pmap_update_pde_teardown, &act);
3174 pmap_update_pde_store(pmap, pde, newpde);
3175 if (CPU_ISSET(cpuid, &active))
3176 pmap_update_pde_invalidate(pmap, va, newpde);
3182 * Normal, non-SMP, invalidation functions.
3185 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3187 struct invpcid_descr d;
3188 uint64_t kcr3, ucr3;
3191 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3195 KASSERT(pmap->pm_type == PT_X86,
3196 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3198 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3200 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3201 pmap->pm_ucr3 != PMAP_NO_CR3) {
3203 pcid = pmap->pm_pcids[0].pm_pcid;
3204 if (invpcid_works) {
3205 d.pcid = pcid | PMAP_PCID_USER_PT;
3208 invpcid(&d, INVPCID_ADDR);
3210 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3211 ucr3 = pmap->pm_ucr3 | pcid |
3212 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3213 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3217 } else if (pmap_pcid_enabled)
3218 pmap->pm_pcids[0].pm_gen = 0;
3222 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3224 struct invpcid_descr d;
3226 uint64_t kcr3, ucr3;
3228 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3232 KASSERT(pmap->pm_type == PT_X86,
3233 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3235 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3236 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3238 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3239 pmap->pm_ucr3 != PMAP_NO_CR3) {
3241 if (invpcid_works) {
3242 d.pcid = pmap->pm_pcids[0].pm_pcid |
3246 for (; d.addr < eva; d.addr += PAGE_SIZE)
3247 invpcid(&d, INVPCID_ADDR);
3249 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3250 pm_pcid | CR3_PCID_SAVE;
3251 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3252 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3253 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3257 } else if (pmap_pcid_enabled) {
3258 pmap->pm_pcids[0].pm_gen = 0;
3263 pmap_invalidate_all(pmap_t pmap)
3265 struct invpcid_descr d;
3266 uint64_t kcr3, ucr3;
3268 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3272 KASSERT(pmap->pm_type == PT_X86,
3273 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3275 if (pmap == kernel_pmap) {
3276 if (pmap_pcid_enabled && invpcid_works) {
3277 bzero(&d, sizeof(d));
3278 invpcid(&d, INVPCID_CTXGLOB);
3282 } else if (pmap == PCPU_GET(curpmap)) {
3283 if (pmap_pcid_enabled) {
3285 if (invpcid_works) {
3286 d.pcid = pmap->pm_pcids[0].pm_pcid;
3289 invpcid(&d, INVPCID_CTX);
3290 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3291 d.pcid |= PMAP_PCID_USER_PT;
3292 invpcid(&d, INVPCID_CTX);
3295 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3296 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3297 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3298 0].pm_pcid | PMAP_PCID_USER_PT;
3299 pmap_pti_pcid_invalidate(ucr3, kcr3);
3307 } else if (pmap_pcid_enabled) {
3308 pmap->pm_pcids[0].pm_gen = 0;
3313 pmap_invalidate_cache(void)
3320 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3323 pmap_update_pde_store(pmap, pde, newpde);
3324 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3325 pmap_update_pde_invalidate(pmap, va, newpde);
3327 pmap->pm_pcids[0].pm_gen = 0;
3332 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3336 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3337 * by a promotion that did not invalidate the 512 4KB page mappings
3338 * that might exist in the TLB. Consequently, at this point, the TLB
3339 * may hold both 4KB and 2MB page mappings for the address range [va,
3340 * va + NBPDR). Therefore, the entire range must be invalidated here.
3341 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3342 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3343 * single INVLPG suffices to invalidate the 2MB page mapping from the
3346 if ((pde & PG_PROMOTED) != 0)
3347 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3349 pmap_invalidate_page(pmap, va);
3352 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3353 (vm_offset_t sva, vm_offset_t eva))
3356 if ((cpu_feature & CPUID_SS) != 0)
3357 return (pmap_invalidate_cache_range_selfsnoop);
3358 if ((cpu_feature & CPUID_CLFSH) != 0)
3359 return (pmap_force_invalidate_cache_range);
3360 return (pmap_invalidate_cache_range_all);
3363 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3366 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3369 KASSERT((sva & PAGE_MASK) == 0,
3370 ("pmap_invalidate_cache_range: sva not page-aligned"));
3371 KASSERT((eva & PAGE_MASK) == 0,
3372 ("pmap_invalidate_cache_range: eva not page-aligned"));
3376 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3379 pmap_invalidate_cache_range_check_align(sva, eva);
3383 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3386 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3389 * XXX: Some CPUs fault, hang, or trash the local APIC
3390 * registers if we use CLFLUSH on the local APIC range. The
3391 * local APIC is always uncached, so we don't need to flush
3392 * for that range anyway.
3394 if (pmap_kextract(sva) == lapic_paddr)
3397 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3399 * Do per-cache line flush. Use a locked
3400 * instruction to insure that previous stores are
3401 * included in the write-back. The processor
3402 * propagates flush to other processors in the cache
3405 atomic_thread_fence_seq_cst();
3406 for (; sva < eva; sva += cpu_clflush_line_size)
3408 atomic_thread_fence_seq_cst();
3411 * Writes are ordered by CLFLUSH on Intel CPUs.
3413 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3415 for (; sva < eva; sva += cpu_clflush_line_size)
3417 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3423 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3426 pmap_invalidate_cache_range_check_align(sva, eva);
3427 pmap_invalidate_cache();
3431 * Remove the specified set of pages from the data and instruction caches.
3433 * In contrast to pmap_invalidate_cache_range(), this function does not
3434 * rely on the CPU's self-snoop feature, because it is intended for use
3435 * when moving pages into a different cache domain.
3438 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3440 vm_offset_t daddr, eva;
3444 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3445 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3446 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3447 pmap_invalidate_cache();
3450 atomic_thread_fence_seq_cst();
3451 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3453 for (i = 0; i < count; i++) {
3454 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3455 eva = daddr + PAGE_SIZE;
3456 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3464 atomic_thread_fence_seq_cst();
3465 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3471 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3474 pmap_invalidate_cache_range_check_align(sva, eva);
3476 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3477 pmap_force_invalidate_cache_range(sva, eva);
3481 /* See comment in pmap_force_invalidate_cache_range(). */
3482 if (pmap_kextract(sva) == lapic_paddr)
3485 atomic_thread_fence_seq_cst();
3486 for (; sva < eva; sva += cpu_clflush_line_size)
3488 atomic_thread_fence_seq_cst();
3492 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3496 int error, pte_bits;
3498 KASSERT((spa & PAGE_MASK) == 0,
3499 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3500 KASSERT((epa & PAGE_MASK) == 0,
3501 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3503 if (spa < dmaplimit) {
3504 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3506 if (dmaplimit >= epa)
3511 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3513 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3515 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3516 pte = vtopte(vaddr);
3517 for (; spa < epa; spa += PAGE_SIZE) {
3519 pte_store(pte, spa | pte_bits);
3521 /* XXXKIB atomic inside flush_cache_range are excessive */
3522 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3525 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3529 * Routine: pmap_extract
3531 * Extract the physical page address associated
3532 * with the given map/virtual_address pair.
3535 pmap_extract(pmap_t pmap, vm_offset_t va)
3539 pt_entry_t *pte, PG_V;
3543 PG_V = pmap_valid_bit(pmap);
3545 pdpe = pmap_pdpe(pmap, va);
3546 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3547 if ((*pdpe & PG_PS) != 0)
3548 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3550 pde = pmap_pdpe_to_pde(pdpe, va);
3551 if ((*pde & PG_V) != 0) {
3552 if ((*pde & PG_PS) != 0) {
3553 pa = (*pde & PG_PS_FRAME) |
3556 pte = pmap_pde_to_pte(pde, va);
3557 pa = (*pte & PG_FRAME) |
3568 * Routine: pmap_extract_and_hold
3570 * Atomically extract and hold the physical page
3571 * with the given pmap and virtual address pair
3572 * if that mapping permits the given protection.
3575 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3577 pdp_entry_t pdpe, *pdpep;
3578 pd_entry_t pde, *pdep;
3579 pt_entry_t pte, PG_RW, PG_V;
3583 PG_RW = pmap_rw_bit(pmap);
3584 PG_V = pmap_valid_bit(pmap);
3587 pdpep = pmap_pdpe(pmap, va);
3588 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3590 if ((pdpe & PG_PS) != 0) {
3591 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3593 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3597 pdep = pmap_pdpe_to_pde(pdpep, va);
3598 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3600 if ((pde & PG_PS) != 0) {
3601 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3603 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3607 pte = *pmap_pde_to_pte(pdep, va);
3608 if ((pte & PG_V) == 0 ||
3609 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3611 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3614 if (m != NULL && !vm_page_wire_mapped(m))
3622 pmap_kextract(vm_offset_t va)
3627 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3628 pa = DMAP_TO_PHYS(va);
3629 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3630 pa = pmap_large_map_kextract(va);
3634 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3637 * Beware of a concurrent promotion that changes the
3638 * PDE at this point! For example, vtopte() must not
3639 * be used to access the PTE because it would use the
3640 * new PDE. It is, however, safe to use the old PDE
3641 * because the page table page is preserved by the
3644 pa = *pmap_pde_to_pte(&pde, va);
3645 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3651 /***************************************************
3652 * Low level mapping routines.....
3653 ***************************************************/
3656 * Add a wired page to the kva.
3657 * Note: not SMP coherent.
3660 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3665 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3668 static __inline void
3669 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3675 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3676 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3680 * Remove a page from the kernel pagetables.
3681 * Note: not SMP coherent.
3684 pmap_kremove(vm_offset_t va)
3693 * Used to map a range of physical addresses into kernel
3694 * virtual address space.
3696 * The value passed in '*virt' is a suggested virtual address for
3697 * the mapping. Architectures which can support a direct-mapped
3698 * physical to virtual region can return the appropriate address
3699 * within that region, leaving '*virt' unchanged. Other
3700 * architectures should map the pages starting at '*virt' and
3701 * update '*virt' with the first usable address after the mapped
3705 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3707 return PHYS_TO_DMAP(start);
3711 * Add a list of wired pages to the kva
3712 * this routine is only used for temporary
3713 * kernel mappings that do not need to have
3714 * page modification or references recorded.
3715 * Note that old mappings are simply written
3716 * over. The page *must* be wired.
3717 * Note: SMP coherent. Uses a ranged shootdown IPI.
3720 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3722 pt_entry_t *endpte, oldpte, pa, *pte;
3728 endpte = pte + count;
3729 while (pte < endpte) {
3731 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3732 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3733 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3735 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3739 if (__predict_false((oldpte & X86_PG_V) != 0))
3740 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3745 * This routine tears out page mappings from the
3746 * kernel -- it is meant only for temporary mappings.
3747 * Note: SMP coherent. Uses a ranged shootdown IPI.
3750 pmap_qremove(vm_offset_t sva, int count)
3755 while (count-- > 0) {
3756 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3760 pmap_invalidate_range(kernel_pmap, sva, va);
3763 /***************************************************
3764 * Page table page management routines.....
3765 ***************************************************/
3767 * Schedule the specified unused page table page to be freed. Specifically,
3768 * add the page to the specified list of pages that will be released to the
3769 * physical memory manager after the TLB has been updated.
3771 static __inline void
3772 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3773 boolean_t set_PG_ZERO)
3777 m->flags |= PG_ZERO;
3779 m->flags &= ~PG_ZERO;
3780 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3784 * Inserts the specified page table page into the specified pmap's collection
3785 * of idle page table pages. Each of a pmap's page table pages is responsible
3786 * for mapping a distinct range of virtual addresses. The pmap's collection is
3787 * ordered by this virtual address range.
3789 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3792 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3795 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3796 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3797 return (vm_radix_insert(&pmap->pm_root, mpte));
3801 * Removes the page table page mapping the specified virtual address from the
3802 * specified pmap's collection of idle page table pages, and returns it.
3803 * Otherwise, returns NULL if there is no page table page corresponding to the
3804 * specified virtual address.
3806 static __inline vm_page_t
3807 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3810 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3811 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3815 * Decrements a page table page's reference count, which is used to record the
3816 * number of valid page table entries within the page. If the reference count
3817 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3818 * page table page was unmapped and FALSE otherwise.
3820 static inline boolean_t
3821 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3825 if (m->ref_count == 0) {
3826 _pmap_unwire_ptp(pmap, va, m, free);
3833 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3839 vm_page_t pdpg, pdppg, pml4pg;
3841 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3844 * unmap the page table page
3846 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
3848 MPASS(pmap_is_la57(pmap));
3849 pml5 = pmap_pml5e(pmap, va);
3851 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
3852 pml5 = pmap_pml5e_u(pmap, va);
3855 } else if (m->pindex >= NUPDE + NUPDPE) {
3857 pml4 = pmap_pml4e(pmap, va);
3859 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
3860 va <= VM_MAXUSER_ADDRESS) {
3861 pml4 = pmap_pml4e_u(pmap, va);
3864 } else if (m->pindex >= NUPDE) {
3866 pdp = pmap_pdpe(pmap, va);
3870 pd = pmap_pde(pmap, va);
3873 pmap_resident_count_dec(pmap, 1);
3874 if (m->pindex < NUPDE) {
3875 /* We just released a PT, unhold the matching PD */
3876 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3877 pmap_unwire_ptp(pmap, va, pdpg, free);
3878 } else if (m->pindex < NUPDE + NUPDPE) {
3879 /* We just released a PD, unhold the matching PDP */
3880 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3881 pmap_unwire_ptp(pmap, va, pdppg, free);
3882 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
3883 /* We just released a PDP, unhold the matching PML4 */
3884 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
3885 pmap_unwire_ptp(pmap, va, pml4pg, free);
3889 * Put page on a list so that it is released after
3890 * *ALL* TLB shootdown is done
3892 pmap_add_delayed_free_list(m, free, TRUE);
3896 * After removing a page table entry, this routine is used to
3897 * conditionally free the page, and manage the reference count.
3900 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3901 struct spglist *free)
3905 if (va >= VM_MAXUSER_ADDRESS)
3907 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3908 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3909 return (pmap_unwire_ptp(pmap, va, mpte, free));
3913 * Release a page table page reference after a failed attempt to create a
3917 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3919 struct spglist free;
3922 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3924 * Although "va" was never mapped, paging-structure caches
3925 * could nonetheless have entries that refer to the freed
3926 * page table pages. Invalidate those entries.
3928 pmap_invalidate_page(pmap, va);
3929 vm_page_free_pages_toq(&free, true);
3934 pmap_pinit0(pmap_t pmap)
3940 PMAP_LOCK_INIT(pmap);
3941 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
3942 pmap->pm_pmltopu = NULL;
3943 pmap->pm_cr3 = kernel_pmap->pm_cr3;
3944 /* hack to keep pmap_pti_pcid_invalidate() alive */
3945 pmap->pm_ucr3 = PMAP_NO_CR3;
3946 pmap->pm_root.rt_root = 0;
3947 CPU_ZERO(&pmap->pm_active);
3948 TAILQ_INIT(&pmap->pm_pvchunk);
3949 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3950 pmap->pm_flags = pmap_flags;
3952 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3953 pmap->pm_pcids[i].pm_gen = 1;
3955 pmap_activate_boot(pmap);
3960 p->p_md.md_flags |= P_MD_KPTI;
3963 pmap_thread_init_invl_gen(td);
3965 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3966 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3967 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3973 pmap_pinit_pml4(vm_page_t pml4pg)
3975 pml4_entry_t *pm_pml4;
3978 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3980 /* Wire in kernel global address entries. */
3981 for (i = 0; i < NKPML4E; i++) {
3982 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3985 for (i = 0; i < ndmpdpphys; i++) {
3986 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3990 /* install self-referential address mapping entry(s) */
3991 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3992 X86_PG_A | X86_PG_M;
3994 /* install large map entries if configured */
3995 for (i = 0; i < lm_ents; i++)
3996 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
4000 pmap_pinit_pml5(vm_page_t pml5pg)
4002 pml5_entry_t *pm_pml5;
4004 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4007 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4008 * entering all existing kernel mappings into level 5 table.
4010 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4011 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4012 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4015 * Install self-referential address mapping entry.
4017 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4018 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4019 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4023 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4025 pml4_entry_t *pm_pml4u;
4028 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4029 for (i = 0; i < NPML4EPG; i++)
4030 pm_pml4u[i] = pti_pml4[i];
4034 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4036 pml5_entry_t *pm_pml5u;
4038 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4041 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4042 * table, entering all kernel mappings needed for usermode
4043 * into level 5 table.
4045 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4046 pmap_kextract((vm_offset_t)pti_pml4) |
4047 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4048 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4052 * Initialize a preallocated and zeroed pmap structure,
4053 * such as one in a vmspace structure.
4056 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4058 vm_page_t pmltop_pg, pmltop_pgu;
4059 vm_paddr_t pmltop_phys;
4063 * allocate the page directory page
4065 pmltop_pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4066 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4068 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4069 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4072 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4073 pmap->pm_pcids[i].pm_gen = 0;
4075 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4076 pmap->pm_ucr3 = PMAP_NO_CR3;
4077 pmap->pm_pmltopu = NULL;
4079 pmap->pm_type = pm_type;
4080 if ((pmltop_pg->flags & PG_ZERO) == 0)
4081 pagezero(pmap->pm_pmltop);
4084 * Do not install the host kernel mappings in the nested page
4085 * tables. These mappings are meaningless in the guest physical
4087 * Install minimal kernel mappings in PTI case.
4089 if (pm_type == PT_X86) {
4090 pmap->pm_cr3 = pmltop_phys;
4091 if (pmap_is_la57(pmap))
4092 pmap_pinit_pml5(pmltop_pg);
4094 pmap_pinit_pml4(pmltop_pg);
4095 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4096 pmltop_pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4097 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4098 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4099 VM_PAGE_TO_PHYS(pmltop_pgu));
4100 if (pmap_is_la57(pmap))
4101 pmap_pinit_pml5_pti(pmltop_pgu);
4103 pmap_pinit_pml4_pti(pmltop_pgu);
4104 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4106 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4107 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4108 pkru_free_range, pmap, M_NOWAIT);
4112 pmap->pm_root.rt_root = 0;
4113 CPU_ZERO(&pmap->pm_active);
4114 TAILQ_INIT(&pmap->pm_pvchunk);
4115 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4116 pmap->pm_flags = flags;
4117 pmap->pm_eptgen = 0;
4123 pmap_pinit(pmap_t pmap)
4126 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4130 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4133 struct spglist free;
4135 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4136 if (mpg->ref_count != 0)
4139 _pmap_unwire_ptp(pmap, va, mpg, &free);
4140 pmap_invalidate_page(pmap, va);
4141 vm_page_free_pages_toq(&free, true);
4144 static pml4_entry_t *
4145 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4148 vm_pindex_t pml5index;
4155 if (!pmap_is_la57(pmap))
4156 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4158 PG_V = pmap_valid_bit(pmap);
4159 pml5index = pmap_pml5e_index(va);
4160 pml5 = &pmap->pm_pmltop[pml5index];
4161 if ((*pml5 & PG_V) == 0) {
4162 if (_pmap_allocpte(pmap, pmap_pml5e_pindex(va), lockp, va) ==
4169 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4170 pml4 = &pml4[pmap_pml4e_index(va)];
4171 if ((*pml4 & PG_V) == 0) {
4172 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4173 if (allocated && !addref)
4174 pml4pg->ref_count--;
4175 else if (!allocated && addref)
4176 pml4pg->ref_count++;
4181 static pdp_entry_t *
4182 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4191 PG_V = pmap_valid_bit(pmap);
4193 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4197 if ((*pml4 & PG_V) == 0) {
4198 /* Have to allocate a new pdp, recurse */
4199 if (_pmap_allocpte(pmap, pmap_pml4e_pindex(va), lockp, va) ==
4201 if (pmap_is_la57(pmap))
4202 pmap_allocpte_free_unref(pmap, va,
4203 pmap_pml5e(pmap, va));
4210 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4211 pdp = &pdp[pmap_pdpe_index(va)];
4212 if ((*pdp & PG_V) == 0) {
4213 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4214 if (allocated && !addref)
4216 else if (!allocated && addref)
4223 * This routine is called if the desired page table page does not exist.
4225 * If page table page allocation fails, this routine may sleep before
4226 * returning NULL. It sleeps only if a lock pointer was given.
4228 * Note: If a page allocation fails at page table level two, three, or four,
4229 * up to three pages may be held during the wait, only to be released
4230 * afterwards. This conservative approach is easily argued to avoid
4233 * The ptepindexes, i.e. page indices, of the page table pages encountered
4234 * while translating virtual address va are defined as follows:
4235 * - for the page table page (last level),
4236 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4237 * in other words, it is just the index of the PDE that maps the page
4239 * - for the page directory page,
4240 * ptepindex = NUPDE (number of userland PD entries) +
4241 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4242 * i.e. index of PDPE is put after the last index of PDE,
4243 * - for the page directory pointer page,
4244 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4246 * i.e. index of pml4e is put after the last index of PDPE,
4247 * - for the PML4 page (if LA57 mode is enabled),
4248 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4249 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4250 * i.e. index of pml5e is put after the last index of PML4E.
4252 * Define an order on the paging entries, where all entries of the
4253 * same height are put together, then heights are put from deepest to
4254 * root. Then ptexpindex is the sequential number of the
4255 * corresponding paging entry in this order.
4257 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4258 * LA57 paging structures even in LA48 paging mode. Moreover, the
4259 * ptepindexes are calculated as if the paging structures were 5-level
4260 * regardless of the actual mode of operation.
4262 * The root page at PML4/PML5 does not participate in this indexing scheme,
4263 * since it is statically allocated by pmap_pinit() and not by _pmap_allocpte().
4266 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4267 vm_offset_t va __unused)
4269 vm_pindex_t pml5index, pml4index;
4270 pml5_entry_t *pml5, *pml5u;
4271 pml4_entry_t *pml4, *pml4u;
4275 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4277 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4279 PG_A = pmap_accessed_bit(pmap);
4280 PG_M = pmap_modified_bit(pmap);
4281 PG_V = pmap_valid_bit(pmap);
4282 PG_RW = pmap_rw_bit(pmap);
4285 * Allocate a page table page.
4287 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
4288 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
4289 if (lockp != NULL) {
4290 RELEASE_PV_LIST_LOCK(lockp);
4292 PMAP_ASSERT_NOT_IN_DI();
4298 * Indicate the need to retry. While waiting, the page table
4299 * page may have been allocated.
4303 if ((m->flags & PG_ZERO) == 0)
4307 * Map the pagetable page into the process address space, if
4308 * it isn't already there.
4310 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4311 MPASS(pmap_is_la57(pmap));
4313 pml5index = pmap_pml5e_index(va);
4314 pml5 = &pmap->pm_pmltop[pml5index];
4315 KASSERT((*pml5 & PG_V) == 0,
4316 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4317 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4319 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4320 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4323 pml5u = &pmap->pm_pmltopu[pml5index];
4324 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4327 } else if (ptepindex >= NUPDE + NUPDPE) {
4328 pml4index = pmap_pml4e_index(va);
4329 /* Wire up a new PDPE page */
4330 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4332 vm_page_unwire_noq(m);
4333 vm_page_free_zero(m);
4336 KASSERT((*pml4 & PG_V) == 0,
4337 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4338 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4340 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4341 pml4index < NUPML4E) {
4343 * PTI: Make all user-space mappings in the
4344 * kernel-mode page table no-execute so that
4345 * we detect any programming errors that leave
4346 * the kernel-mode page table active on return
4349 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4352 pml4u = &pmap->pm_pmltopu[pml4index];
4353 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4356 } else if (ptepindex >= NUPDE) {
4357 /* Wire up a new PDE page */
4358 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4360 vm_page_unwire_noq(m);
4361 vm_page_free_zero(m);
4364 KASSERT((*pdp & PG_V) == 0,
4365 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4366 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4368 /* Wire up a new PTE page */
4369 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4371 vm_page_unwire_noq(m);
4372 vm_page_free_zero(m);
4375 if ((*pdp & PG_V) == 0) {
4376 /* Have to allocate a new pd, recurse */
4377 if (_pmap_allocpte(pmap, pmap_pdpe_pindex(va),
4378 lockp, va) == NULL) {
4379 pmap_allocpte_free_unref(pmap, va,
4380 pmap_pml4e(pmap, va));
4381 vm_page_unwire_noq(m);
4382 vm_page_free_zero(m);
4386 /* Add reference to the pd page */
4387 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4390 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4392 /* Now we know where the page directory page is */
4393 pd = &pd[pmap_pde_index(va)];
4394 KASSERT((*pd & PG_V) == 0,
4395 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4396 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4399 pmap_resident_count_inc(pmap, 1);
4405 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4406 struct rwlock **lockp)
4408 pdp_entry_t *pdpe, PG_V;
4411 vm_pindex_t pdpindex;
4413 PG_V = pmap_valid_bit(pmap);
4416 pdpe = pmap_pdpe(pmap, va);
4417 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4418 pde = pmap_pdpe_to_pde(pdpe, va);
4419 if (va < VM_MAXUSER_ADDRESS) {
4420 /* Add a reference to the pd page. */
4421 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4425 } else if (va < VM_MAXUSER_ADDRESS) {
4426 /* Allocate a pd page. */
4427 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4428 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp, va);
4435 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4436 pde = &pde[pmap_pde_index(va)];
4438 panic("pmap_alloc_pde: missing page table page for va %#lx",
4445 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4447 vm_pindex_t ptepindex;
4448 pd_entry_t *pd, PG_V;
4451 PG_V = pmap_valid_bit(pmap);
4454 * Calculate pagetable page index
4456 ptepindex = pmap_pde_pindex(va);
4459 * Get the page directory entry
4461 pd = pmap_pde(pmap, va);
4464 * This supports switching from a 2MB page to a
4467 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4468 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4470 * Invalidation of the 2MB page mapping may have caused
4471 * the deallocation of the underlying PD page.
4478 * If the page table page is mapped, we just increment the
4479 * hold count, and activate it.
4481 if (pd != NULL && (*pd & PG_V) != 0) {
4482 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4486 * Here if the pte page isn't mapped, or if it has been
4489 m = _pmap_allocpte(pmap, ptepindex, lockp, va);
4490 if (m == NULL && lockp != NULL)
4496 /***************************************************
4497 * Pmap allocation/deallocation routines.
4498 ***************************************************/
4501 * Release any resources held by the given physical map.
4502 * Called when a pmap initialized by pmap_pinit is being released.
4503 * Should only be called if the map contains no valid mappings.
4506 pmap_release(pmap_t pmap)
4511 KASSERT(pmap->pm_stats.resident_count == 0,
4512 ("pmap_release: pmap %p resident count %ld != 0",
4513 pmap, pmap->pm_stats.resident_count));
4514 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4515 ("pmap_release: pmap %p has reserved page table page(s)",
4517 KASSERT(CPU_EMPTY(&pmap->pm_active),
4518 ("releasing active pmap %p", pmap));
4520 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4522 if (pmap_is_la57(pmap)) {
4523 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4524 pmap->pm_pmltop[PML5PML5I] = 0;
4526 for (i = 0; i < NKPML4E; i++) /* KVA */
4527 pmap->pm_pmltop[KPML4BASE + i] = 0;
4528 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4529 pmap->pm_pmltop[DMPML4I + i] = 0;
4530 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4531 for (i = 0; i < lm_ents; i++) /* Large Map */
4532 pmap->pm_pmltop[LMSPML4I + i] = 0;
4535 vm_page_unwire_noq(m);
4536 vm_page_free_zero(m);
4538 if (pmap->pm_pmltopu != NULL) {
4539 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4541 vm_page_unwire_noq(m);
4544 if (pmap->pm_type == PT_X86 &&
4545 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4546 rangeset_fini(&pmap->pm_pkru);
4550 kvm_size(SYSCTL_HANDLER_ARGS)
4552 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4554 return sysctl_handle_long(oidp, &ksize, 0, req);
4556 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4557 0, 0, kvm_size, "LU",
4561 kvm_free(SYSCTL_HANDLER_ARGS)
4563 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4565 return sysctl_handle_long(oidp, &kfree, 0, req);
4567 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4568 0, 0, kvm_free, "LU",
4569 "Amount of KVM free");
4572 * Allocate physical memory for the vm_page array and map it into KVA,
4573 * attempting to back the vm_pages with domain-local memory.
4576 pmap_page_array_startup(long pages)
4579 pd_entry_t *pde, newpdir;
4580 vm_offset_t va, start, end;
4585 vm_page_array_size = pages;
4587 start = VM_MIN_KERNEL_ADDRESS;
4588 end = start + pages * sizeof(struct vm_page);
4589 for (va = start; va < end; va += NBPDR) {
4590 pfn = first_page + (va - start) / sizeof(struct vm_page);
4591 domain = _vm_phys_domain(ptoa(pfn));
4592 pdpe = pmap_pdpe(kernel_pmap, va);
4593 if ((*pdpe & X86_PG_V) == 0) {
4594 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4596 pagezero((void *)PHYS_TO_DMAP(pa));
4597 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4598 X86_PG_A | X86_PG_M);
4600 pde = pmap_pdpe_to_pde(pdpe, va);
4601 if ((*pde & X86_PG_V) != 0)
4602 panic("Unexpected pde");
4603 pa = vm_phys_early_alloc(domain, NBPDR);
4604 for (i = 0; i < NPDEPG; i++)
4605 dump_add_page(pa + i * PAGE_SIZE);
4606 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4607 X86_PG_M | PG_PS | pg_g | pg_nx);
4608 pde_store(pde, newpdir);
4610 vm_page_array = (vm_page_t)start;
4614 * grow the number of kernel page table entries, if needed
4617 pmap_growkernel(vm_offset_t addr)
4621 pd_entry_t *pde, newpdir;
4624 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4627 * Return if "addr" is within the range of kernel page table pages
4628 * that were preallocated during pmap bootstrap. Moreover, leave
4629 * "kernel_vm_end" and the kernel page table as they were.
4631 * The correctness of this action is based on the following
4632 * argument: vm_map_insert() allocates contiguous ranges of the
4633 * kernel virtual address space. It calls this function if a range
4634 * ends after "kernel_vm_end". If the kernel is mapped between
4635 * "kernel_vm_end" and "addr", then the range cannot begin at
4636 * "kernel_vm_end". In fact, its beginning address cannot be less
4637 * than the kernel. Thus, there is no immediate need to allocate
4638 * any new kernel page table pages between "kernel_vm_end" and
4641 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4644 addr = roundup2(addr, NBPDR);
4645 if (addr - 1 >= vm_map_max(kernel_map))
4646 addr = vm_map_max(kernel_map);
4647 while (kernel_vm_end < addr) {
4648 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4649 if ((*pdpe & X86_PG_V) == 0) {
4650 /* We need a new PDP entry */
4651 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4652 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4653 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4655 panic("pmap_growkernel: no memory to grow kernel");
4656 if ((nkpg->flags & PG_ZERO) == 0)
4657 pmap_zero_page(nkpg);
4658 paddr = VM_PAGE_TO_PHYS(nkpg);
4659 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4660 X86_PG_A | X86_PG_M);
4661 continue; /* try again */
4663 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4664 if ((*pde & X86_PG_V) != 0) {
4665 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4666 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4667 kernel_vm_end = vm_map_max(kernel_map);
4673 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4674 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4677 panic("pmap_growkernel: no memory to grow kernel");
4678 if ((nkpg->flags & PG_ZERO) == 0)
4679 pmap_zero_page(nkpg);
4680 paddr = VM_PAGE_TO_PHYS(nkpg);
4681 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4682 pde_store(pde, newpdir);
4684 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4685 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4686 kernel_vm_end = vm_map_max(kernel_map);
4692 /***************************************************
4693 * page management routines.
4694 ***************************************************/
4696 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4697 CTASSERT(_NPCM == 3);
4698 CTASSERT(_NPCPV == 168);
4700 static __inline struct pv_chunk *
4701 pv_to_chunk(pv_entry_t pv)
4704 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4707 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4709 #define PC_FREE0 0xfffffffffffffffful
4710 #define PC_FREE1 0xfffffffffffffffful
4711 #define PC_FREE2 0x000000fffffffffful
4713 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4716 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4718 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4719 "Current number of pv entry chunks");
4720 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4721 "Current number of pv entry chunks allocated");
4722 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4723 "Current number of pv entry chunks frees");
4724 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4725 "Number of times tried to get a chunk page but failed.");
4727 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4728 static int pv_entry_spare;
4730 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4731 "Current number of pv entry frees");
4732 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4733 "Current number of pv entry allocs");
4734 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4735 "Current number of pv entries");
4736 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4737 "Current number of spare pv entries");
4741 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4746 pmap_invalidate_all(pmap);
4747 if (pmap != locked_pmap)
4750 pmap_delayed_invl_finish();
4754 * We are in a serious low memory condition. Resort to
4755 * drastic measures to free some pages so we can allocate
4756 * another pv entry chunk.
4758 * Returns NULL if PV entries were reclaimed from the specified pmap.
4760 * We do not, however, unmap 2mpages because subsequent accesses will
4761 * allocate per-page pv entries until repromotion occurs, thereby
4762 * exacerbating the shortage of free pv entries.
4765 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4767 struct pv_chunks_list *pvc;
4768 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4769 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4770 struct md_page *pvh;
4772 pmap_t next_pmap, pmap;
4773 pt_entry_t *pte, tpte;
4774 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4778 struct spglist free;
4780 int bit, field, freed;
4781 bool start_di, restart;
4783 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4784 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4787 PG_G = PG_A = PG_M = PG_RW = 0;
4789 bzero(&pc_marker_b, sizeof(pc_marker_b));
4790 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4791 pc_marker = (struct pv_chunk *)&pc_marker_b;
4792 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4795 * A delayed invalidation block should already be active if
4796 * pmap_advise() or pmap_remove() called this function by way
4797 * of pmap_demote_pde_locked().
4799 start_di = pmap_not_in_di();
4801 pvc = &pv_chunks[domain];
4802 mtx_lock(&pvc->pvc_lock);
4803 pvc->active_reclaims++;
4804 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4805 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4806 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4807 SLIST_EMPTY(&free)) {
4808 next_pmap = pc->pc_pmap;
4809 if (next_pmap == NULL) {
4811 * The next chunk is a marker. However, it is
4812 * not our marker, so active_reclaims must be
4813 * > 1. Consequently, the next_chunk code
4814 * will not rotate the pv_chunks list.
4818 mtx_unlock(&pvc->pvc_lock);
4821 * A pv_chunk can only be removed from the pc_lru list
4822 * when both pc_chunks_mutex is owned and the
4823 * corresponding pmap is locked.
4825 if (pmap != next_pmap) {
4827 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4830 /* Avoid deadlock and lock recursion. */
4831 if (pmap > locked_pmap) {
4832 RELEASE_PV_LIST_LOCK(lockp);
4835 pmap_delayed_invl_start();
4836 mtx_lock(&pvc->pvc_lock);
4838 } else if (pmap != locked_pmap) {
4839 if (PMAP_TRYLOCK(pmap)) {
4841 pmap_delayed_invl_start();
4842 mtx_lock(&pvc->pvc_lock);
4845 pmap = NULL; /* pmap is not locked */
4846 mtx_lock(&pvc->pvc_lock);
4847 pc = TAILQ_NEXT(pc_marker, pc_lru);
4849 pc->pc_pmap != next_pmap)
4853 } else if (start_di)
4854 pmap_delayed_invl_start();
4855 PG_G = pmap_global_bit(pmap);
4856 PG_A = pmap_accessed_bit(pmap);
4857 PG_M = pmap_modified_bit(pmap);
4858 PG_RW = pmap_rw_bit(pmap);
4864 * Destroy every non-wired, 4 KB page mapping in the chunk.
4867 for (field = 0; field < _NPCM; field++) {
4868 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4869 inuse != 0; inuse &= ~(1UL << bit)) {
4871 pv = &pc->pc_pventry[field * 64 + bit];
4873 pde = pmap_pde(pmap, va);
4874 if ((*pde & PG_PS) != 0)
4876 pte = pmap_pde_to_pte(pde, va);
4877 if ((*pte & PG_W) != 0)
4879 tpte = pte_load_clear(pte);
4880 if ((tpte & PG_G) != 0)
4881 pmap_invalidate_page(pmap, va);
4882 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4883 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4885 if ((tpte & PG_A) != 0)
4886 vm_page_aflag_set(m, PGA_REFERENCED);
4887 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4888 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4890 if (TAILQ_EMPTY(&m->md.pv_list) &&
4891 (m->flags & PG_FICTITIOUS) == 0) {
4892 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4893 if (TAILQ_EMPTY(&pvh->pv_list)) {
4894 vm_page_aflag_clear(m,
4898 pmap_delayed_invl_page(m);
4899 pc->pc_map[field] |= 1UL << bit;
4900 pmap_unuse_pt(pmap, va, *pde, &free);
4905 mtx_lock(&pvc->pvc_lock);
4908 /* Every freed mapping is for a 4 KB page. */
4909 pmap_resident_count_dec(pmap, freed);
4910 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4911 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4912 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4913 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4914 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4915 pc->pc_map[2] == PC_FREE2) {
4916 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4917 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4918 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4919 /* Entire chunk is free; return it. */
4920 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4921 dump_drop_page(m_pc->phys_addr);
4922 mtx_lock(&pvc->pvc_lock);
4923 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4926 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4927 mtx_lock(&pvc->pvc_lock);
4928 /* One freed pv entry in locked_pmap is sufficient. */
4929 if (pmap == locked_pmap)
4932 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4933 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4934 if (pvc->active_reclaims == 1 && pmap != NULL) {
4936 * Rotate the pv chunks list so that we do not
4937 * scan the same pv chunks that could not be
4938 * freed (because they contained a wired
4939 * and/or superpage mapping) on every
4940 * invocation of reclaim_pv_chunk().
4942 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4943 MPASS(pc->pc_pmap != NULL);
4944 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4945 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4949 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4950 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4951 pvc->active_reclaims--;
4952 mtx_unlock(&pvc->pvc_lock);
4953 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4954 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4955 m_pc = SLIST_FIRST(&free);
4956 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4957 /* Recycle a freed page table page. */
4958 m_pc->ref_count = 1;
4960 vm_page_free_pages_toq(&free, true);
4965 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4970 domain = PCPU_GET(domain);
4971 for (i = 0; i < vm_ndomains; i++) {
4972 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4975 domain = (domain + 1) % vm_ndomains;
4982 * free the pv_entry back to the free list
4985 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4987 struct pv_chunk *pc;
4988 int idx, field, bit;
4990 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4991 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4992 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4993 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4994 pc = pv_to_chunk(pv);
4995 idx = pv - &pc->pc_pventry[0];
4998 pc->pc_map[field] |= 1ul << bit;
4999 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
5000 pc->pc_map[2] != PC_FREE2) {
5001 /* 98% of the time, pc is already at the head of the list. */
5002 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5003 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5004 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5008 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5013 free_pv_chunk_dequeued(struct pv_chunk *pc)
5017 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
5018 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
5019 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
5020 /* entire chunk is free, return it */
5021 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5022 dump_drop_page(m->phys_addr);
5023 vm_page_unwire_noq(m);
5028 free_pv_chunk(struct pv_chunk *pc)
5030 struct pv_chunks_list *pvc;
5032 pvc = &pv_chunks[pc_to_domain(pc)];
5033 mtx_lock(&pvc->pvc_lock);
5034 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5035 mtx_unlock(&pvc->pvc_lock);
5036 free_pv_chunk_dequeued(pc);
5040 free_pv_chunk_batch(struct pv_chunklist *batch)
5042 struct pv_chunks_list *pvc;
5043 struct pv_chunk *pc, *npc;
5046 for (i = 0; i < vm_ndomains; i++) {
5047 if (TAILQ_EMPTY(&batch[i]))
5049 pvc = &pv_chunks[i];
5050 mtx_lock(&pvc->pvc_lock);
5051 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5052 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5054 mtx_unlock(&pvc->pvc_lock);
5057 for (i = 0; i < vm_ndomains; i++) {
5058 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5059 free_pv_chunk_dequeued(pc);
5065 * Returns a new PV entry, allocating a new PV chunk from the system when
5066 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5067 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5070 * The given PV list lock may be released.
5073 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5075 struct pv_chunks_list *pvc;
5078 struct pv_chunk *pc;
5081 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5082 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
5084 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5086 for (field = 0; field < _NPCM; field++) {
5087 if (pc->pc_map[field]) {
5088 bit = bsfq(pc->pc_map[field]);
5092 if (field < _NPCM) {
5093 pv = &pc->pc_pventry[field * 64 + bit];
5094 pc->pc_map[field] &= ~(1ul << bit);
5095 /* If this was the last item, move it to tail */
5096 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5097 pc->pc_map[2] == 0) {
5098 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5099 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5102 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5103 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
5107 /* No free items, allocate another chunk */
5108 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5111 if (lockp == NULL) {
5112 PV_STAT(pc_chunk_tryfail++);
5115 m = reclaim_pv_chunk(pmap, lockp);
5119 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5120 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5121 dump_add_page(m->phys_addr);
5122 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5124 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5125 pc->pc_map[1] = PC_FREE1;
5126 pc->pc_map[2] = PC_FREE2;
5127 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
5128 mtx_lock(&pvc->pvc_lock);
5129 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5130 mtx_unlock(&pvc->pvc_lock);
5131 pv = &pc->pc_pventry[0];
5132 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5133 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5134 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
5139 * Returns the number of one bits within the given PV chunk map.
5141 * The erratas for Intel processors state that "POPCNT Instruction May
5142 * Take Longer to Execute Than Expected". It is believed that the
5143 * issue is the spurious dependency on the destination register.
5144 * Provide a hint to the register rename logic that the destination
5145 * value is overwritten, by clearing it, as suggested in the
5146 * optimization manual. It should be cheap for unaffected processors
5149 * Reference numbers for erratas are
5150 * 4th Gen Core: HSD146
5151 * 5th Gen Core: BDM85
5152 * 6th Gen Core: SKL029
5155 popcnt_pc_map_pq(uint64_t *map)
5159 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5160 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5161 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5162 : "=&r" (result), "=&r" (tmp)
5163 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5168 * Ensure that the number of spare PV entries in the specified pmap meets or
5169 * exceeds the given count, "needed".
5171 * The given PV list lock may be released.
5174 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5176 struct pv_chunks_list *pvc;
5177 struct pch new_tail[PMAP_MEMDOM];
5178 struct pv_chunk *pc;
5183 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5184 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5187 * Newly allocated PV chunks must be stored in a private list until
5188 * the required number of PV chunks have been allocated. Otherwise,
5189 * reclaim_pv_chunk() could recycle one of these chunks. In
5190 * contrast, these chunks must be added to the pmap upon allocation.
5192 for (i = 0; i < PMAP_MEMDOM; i++)
5193 TAILQ_INIT(&new_tail[i]);
5196 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5198 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5199 bit_count((bitstr_t *)pc->pc_map, 0,
5200 sizeof(pc->pc_map) * NBBY, &free);
5203 free = popcnt_pc_map_pq(pc->pc_map);
5207 if (avail >= needed)
5210 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5211 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5214 m = reclaim_pv_chunk(pmap, lockp);
5219 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5220 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5221 dump_add_page(m->phys_addr);
5222 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5224 pc->pc_map[0] = PC_FREE0;
5225 pc->pc_map[1] = PC_FREE1;
5226 pc->pc_map[2] = PC_FREE2;
5227 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5228 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
5229 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
5232 * The reclaim might have freed a chunk from the current pmap.
5233 * If that chunk contained available entries, we need to
5234 * re-count the number of available entries.
5239 for (i = 0; i < vm_ndomains; i++) {
5240 if (TAILQ_EMPTY(&new_tail[i]))
5242 pvc = &pv_chunks[i];
5243 mtx_lock(&pvc->pvc_lock);
5244 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5245 mtx_unlock(&pvc->pvc_lock);
5250 * First find and then remove the pv entry for the specified pmap and virtual
5251 * address from the specified pv list. Returns the pv entry if found and NULL
5252 * otherwise. This operation can be performed on pv lists for either 4KB or
5253 * 2MB page mappings.
5255 static __inline pv_entry_t
5256 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5260 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5261 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5262 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5271 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5272 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5273 * entries for each of the 4KB page mappings.
5276 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5277 struct rwlock **lockp)
5279 struct md_page *pvh;
5280 struct pv_chunk *pc;
5282 vm_offset_t va_last;
5286 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5287 KASSERT((pa & PDRMASK) == 0,
5288 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5289 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5292 * Transfer the 2mpage's pv entry for this mapping to the first
5293 * page's pv list. Once this transfer begins, the pv list lock
5294 * must not be released until the last pv entry is reinstantiated.
5296 pvh = pa_to_pvh(pa);
5297 va = trunc_2mpage(va);
5298 pv = pmap_pvh_remove(pvh, pmap, va);
5299 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5300 m = PHYS_TO_VM_PAGE(pa);
5301 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5303 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5304 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
5305 va_last = va + NBPDR - PAGE_SIZE;
5307 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5308 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5309 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5310 for (field = 0; field < _NPCM; field++) {
5311 while (pc->pc_map[field]) {
5312 bit = bsfq(pc->pc_map[field]);
5313 pc->pc_map[field] &= ~(1ul << bit);
5314 pv = &pc->pc_pventry[field * 64 + bit];
5318 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5319 ("pmap_pv_demote_pde: page %p is not managed", m));
5320 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5326 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5327 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5330 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5331 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5332 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5334 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
5335 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
5338 #if VM_NRESERVLEVEL > 0
5340 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5341 * replace the many pv entries for the 4KB page mappings by a single pv entry
5342 * for the 2MB page mapping.
5345 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5346 struct rwlock **lockp)
5348 struct md_page *pvh;
5350 vm_offset_t va_last;
5353 KASSERT((pa & PDRMASK) == 0,
5354 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5355 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5358 * Transfer the first page's pv entry for this mapping to the 2mpage's
5359 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5360 * a transfer avoids the possibility that get_pv_entry() calls
5361 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5362 * mappings that is being promoted.
5364 m = PHYS_TO_VM_PAGE(pa);
5365 va = trunc_2mpage(va);
5366 pv = pmap_pvh_remove(&m->md, pmap, va);
5367 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5368 pvh = pa_to_pvh(pa);
5369 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5371 /* Free the remaining NPTEPG - 1 pv entries. */
5372 va_last = va + NBPDR - PAGE_SIZE;
5376 pmap_pvh_free(&m->md, pmap, va);
5377 } while (va < va_last);
5379 #endif /* VM_NRESERVLEVEL > 0 */
5382 * First find and then destroy the pv entry for the specified pmap and virtual
5383 * address. This operation can be performed on pv lists for either 4KB or 2MB
5387 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5391 pv = pmap_pvh_remove(pvh, pmap, va);
5392 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5393 free_pv_entry(pmap, pv);
5397 * Conditionally create the PV entry for a 4KB page mapping if the required
5398 * memory can be allocated without resorting to reclamation.
5401 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5402 struct rwlock **lockp)
5406 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5407 /* Pass NULL instead of the lock pointer to disable reclamation. */
5408 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5410 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5411 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5419 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5420 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5421 * false if the PV entry cannot be allocated without resorting to reclamation.
5424 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5425 struct rwlock **lockp)
5427 struct md_page *pvh;
5431 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5432 /* Pass NULL instead of the lock pointer to disable reclamation. */
5433 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5434 NULL : lockp)) == NULL)
5437 pa = pde & PG_PS_FRAME;
5438 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5439 pvh = pa_to_pvh(pa);
5440 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5446 * Fills a page table page with mappings to consecutive physical pages.
5449 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5453 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5455 newpte += PAGE_SIZE;
5460 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5461 * mapping is invalidated.
5464 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5466 struct rwlock *lock;
5470 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5477 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5481 pt_entry_t *xpte, *ypte;
5483 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5484 xpte++, newpte += PAGE_SIZE) {
5485 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5486 printf("pmap_demote_pde: xpte %zd and newpte map "
5487 "different pages: found %#lx, expected %#lx\n",
5488 xpte - firstpte, *xpte, newpte);
5489 printf("page table dump\n");
5490 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5491 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5496 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5497 ("pmap_demote_pde: firstpte and newpte map different physical"
5504 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5505 pd_entry_t oldpde, struct rwlock **lockp)
5507 struct spglist free;
5511 sva = trunc_2mpage(va);
5512 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5513 if ((oldpde & pmap_global_bit(pmap)) == 0)
5514 pmap_invalidate_pde_page(pmap, sva, oldpde);
5515 vm_page_free_pages_toq(&free, true);
5516 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5521 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5522 struct rwlock **lockp)
5524 pd_entry_t newpde, oldpde;
5525 pt_entry_t *firstpte, newpte;
5526 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5532 PG_A = pmap_accessed_bit(pmap);
5533 PG_G = pmap_global_bit(pmap);
5534 PG_M = pmap_modified_bit(pmap);
5535 PG_RW = pmap_rw_bit(pmap);
5536 PG_V = pmap_valid_bit(pmap);
5537 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5538 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5540 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5541 in_kernel = va >= VM_MAXUSER_ADDRESS;
5543 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5544 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5547 * Invalidate the 2MB page mapping and return "failure" if the
5548 * mapping was never accessed.
5550 if ((oldpde & PG_A) == 0) {
5551 KASSERT((oldpde & PG_W) == 0,
5552 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5553 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5557 mpte = pmap_remove_pt_page(pmap, va);
5559 KASSERT((oldpde & PG_W) == 0,
5560 ("pmap_demote_pde: page table page for a wired mapping"
5564 * If the page table page is missing and the mapping
5565 * is for a kernel address, the mapping must belong to
5566 * the direct map. Page table pages are preallocated
5567 * for every other part of the kernel address space,
5568 * so the direct map region is the only part of the
5569 * kernel address space that must be handled here.
5571 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5572 va < DMAP_MAX_ADDRESS),
5573 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5576 * If the 2MB page mapping belongs to the direct map
5577 * region of the kernel's address space, then the page
5578 * allocation request specifies the highest possible
5579 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5580 * priority is normal.
5582 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5583 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5584 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5587 * If the allocation of the new page table page fails,
5588 * invalidate the 2MB page mapping and return "failure".
5591 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5596 mpte->ref_count = NPTEPG;
5597 pmap_resident_count_inc(pmap, 1);
5600 mptepa = VM_PAGE_TO_PHYS(mpte);
5601 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5602 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5603 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5604 ("pmap_demote_pde: oldpde is missing PG_M"));
5605 newpte = oldpde & ~PG_PS;
5606 newpte = pmap_swap_pat(pmap, newpte);
5609 * If the page table page is not leftover from an earlier promotion,
5612 if (mpte->valid == 0)
5613 pmap_fill_ptp(firstpte, newpte);
5615 pmap_demote_pde_check(firstpte, newpte);
5618 * If the mapping has changed attributes, update the page table
5621 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5622 pmap_fill_ptp(firstpte, newpte);
5625 * The spare PV entries must be reserved prior to demoting the
5626 * mapping, that is, prior to changing the PDE. Otherwise, the state
5627 * of the PDE and the PV lists will be inconsistent, which can result
5628 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5629 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5630 * PV entry for the 2MB page mapping that is being demoted.
5632 if ((oldpde & PG_MANAGED) != 0)
5633 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5636 * Demote the mapping. This pmap is locked. The old PDE has
5637 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5638 * set. Thus, there is no danger of a race with another
5639 * processor changing the setting of PG_A and/or PG_M between
5640 * the read above and the store below.
5642 if (workaround_erratum383)
5643 pmap_update_pde(pmap, va, pde, newpde);
5645 pde_store(pde, newpde);
5648 * Invalidate a stale recursive mapping of the page table page.
5651 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5654 * Demote the PV entry.
5656 if ((oldpde & PG_MANAGED) != 0)
5657 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5659 atomic_add_long(&pmap_pde_demotions, 1);
5660 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5666 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5669 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5675 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5676 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5677 mpte = pmap_remove_pt_page(pmap, va);
5679 panic("pmap_remove_kernel_pde: Missing pt page.");
5681 mptepa = VM_PAGE_TO_PHYS(mpte);
5682 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5685 * If this page table page was unmapped by a promotion, then it
5686 * contains valid mappings. Zero it to invalidate those mappings.
5688 if (mpte->valid != 0)
5689 pagezero((void *)PHYS_TO_DMAP(mptepa));
5692 * Demote the mapping.
5694 if (workaround_erratum383)
5695 pmap_update_pde(pmap, va, pde, newpde);
5697 pde_store(pde, newpde);
5700 * Invalidate a stale recursive mapping of the page table page.
5702 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5706 * pmap_remove_pde: do the things to unmap a superpage in a process
5709 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5710 struct spglist *free, struct rwlock **lockp)
5712 struct md_page *pvh;
5714 vm_offset_t eva, va;
5716 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5718 PG_G = pmap_global_bit(pmap);
5719 PG_A = pmap_accessed_bit(pmap);
5720 PG_M = pmap_modified_bit(pmap);
5721 PG_RW = pmap_rw_bit(pmap);
5723 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5724 KASSERT((sva & PDRMASK) == 0,
5725 ("pmap_remove_pde: sva is not 2mpage aligned"));
5726 oldpde = pte_load_clear(pdq);
5728 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5729 if ((oldpde & PG_G) != 0)
5730 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5731 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5732 if (oldpde & PG_MANAGED) {
5733 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5734 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5735 pmap_pvh_free(pvh, pmap, sva);
5737 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5738 va < eva; va += PAGE_SIZE, m++) {
5739 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5742 vm_page_aflag_set(m, PGA_REFERENCED);
5743 if (TAILQ_EMPTY(&m->md.pv_list) &&
5744 TAILQ_EMPTY(&pvh->pv_list))
5745 vm_page_aflag_clear(m, PGA_WRITEABLE);
5746 pmap_delayed_invl_page(m);
5749 if (pmap == kernel_pmap) {
5750 pmap_remove_kernel_pde(pmap, pdq, sva);
5752 mpte = pmap_remove_pt_page(pmap, sva);
5754 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5755 ("pmap_remove_pde: pte page not promoted"));
5756 pmap_resident_count_dec(pmap, 1);
5757 KASSERT(mpte->ref_count == NPTEPG,
5758 ("pmap_remove_pde: pte page ref count error"));
5759 mpte->ref_count = 0;
5760 pmap_add_delayed_free_list(mpte, free, FALSE);
5763 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5767 * pmap_remove_pte: do the things to unmap a page in a process
5770 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5771 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5773 struct md_page *pvh;
5774 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5777 PG_A = pmap_accessed_bit(pmap);
5778 PG_M = pmap_modified_bit(pmap);
5779 PG_RW = pmap_rw_bit(pmap);
5781 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5782 oldpte = pte_load_clear(ptq);
5784 pmap->pm_stats.wired_count -= 1;
5785 pmap_resident_count_dec(pmap, 1);
5786 if (oldpte & PG_MANAGED) {
5787 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5788 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5791 vm_page_aflag_set(m, PGA_REFERENCED);
5792 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5793 pmap_pvh_free(&m->md, pmap, va);
5794 if (TAILQ_EMPTY(&m->md.pv_list) &&
5795 (m->flags & PG_FICTITIOUS) == 0) {
5796 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5797 if (TAILQ_EMPTY(&pvh->pv_list))
5798 vm_page_aflag_clear(m, PGA_WRITEABLE);
5800 pmap_delayed_invl_page(m);
5802 return (pmap_unuse_pt(pmap, va, ptepde, free));
5806 * Remove a single page from a process address space
5809 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5810 struct spglist *free)
5812 struct rwlock *lock;
5813 pt_entry_t *pte, PG_V;
5815 PG_V = pmap_valid_bit(pmap);
5816 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5817 if ((*pde & PG_V) == 0)
5819 pte = pmap_pde_to_pte(pde, va);
5820 if ((*pte & PG_V) == 0)
5823 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5826 pmap_invalidate_page(pmap, va);
5830 * Removes the specified range of addresses from the page table page.
5833 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5834 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5836 pt_entry_t PG_G, *pte;
5840 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5841 PG_G = pmap_global_bit(pmap);
5844 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5848 pmap_invalidate_range(pmap, va, sva);
5853 if ((*pte & PG_G) == 0)
5857 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5863 pmap_invalidate_range(pmap, va, sva);
5868 * Remove the given range of addresses from the specified map.
5870 * It is assumed that the start and end are properly
5871 * rounded to the page size.
5874 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5876 struct rwlock *lock;
5878 vm_offset_t va_next;
5879 pml5_entry_t *pml5e;
5880 pml4_entry_t *pml4e;
5882 pd_entry_t ptpaddr, *pde;
5883 pt_entry_t PG_G, PG_V;
5884 struct spglist free;
5887 PG_G = pmap_global_bit(pmap);
5888 PG_V = pmap_valid_bit(pmap);
5891 * Perform an unsynchronized read. This is, however, safe.
5893 if (pmap->pm_stats.resident_count == 0)
5899 pmap_delayed_invl_start();
5901 pmap_pkru_on_remove(pmap, sva, eva);
5904 * special handling of removing one page. a very
5905 * common operation and easy to short circuit some
5908 if (sva + PAGE_SIZE == eva) {
5909 pde = pmap_pde(pmap, sva);
5910 if (pde && (*pde & PG_PS) == 0) {
5911 pmap_remove_page(pmap, sva, pde, &free);
5917 for (; sva < eva; sva = va_next) {
5918 if (pmap->pm_stats.resident_count == 0)
5921 if (pmap_is_la57(pmap)) {
5922 pml5e = pmap_pml5e(pmap, sva);
5923 if ((*pml5e & PG_V) == 0) {
5924 va_next = (sva + NBPML5) & ~PML5MASK;
5929 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
5931 pml4e = pmap_pml4e(pmap, sva);
5933 if ((*pml4e & PG_V) == 0) {
5934 va_next = (sva + NBPML4) & ~PML4MASK;
5940 va_next = (sva + NBPDP) & ~PDPMASK;
5943 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5944 if ((*pdpe & PG_V) == 0)
5946 if ((*pdpe & PG_PS) != 0) {
5947 KASSERT(va_next <= eva,
5948 ("partial update of non-transparent 1G mapping "
5949 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
5950 *pdpe, sva, eva, va_next));
5951 MPASS(pmap != kernel_pmap); /* XXXKIB */
5952 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
5955 pmap_resident_count_dec(pmap, NBPDP / PAGE_SIZE);
5956 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
5957 pmap_unwire_ptp(pmap, sva, mt, &free);
5962 * Calculate index for next page table.
5964 va_next = (sva + NBPDR) & ~PDRMASK;
5968 pde = pmap_pdpe_to_pde(pdpe, sva);
5972 * Weed out invalid mappings.
5978 * Check for large page.
5980 if ((ptpaddr & PG_PS) != 0) {
5982 * Are we removing the entire large page? If not,
5983 * demote the mapping and fall through.
5985 if (sva + NBPDR == va_next && eva >= va_next) {
5987 * The TLB entry for a PG_G mapping is
5988 * invalidated by pmap_remove_pde().
5990 if ((ptpaddr & PG_G) == 0)
5992 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5994 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5996 /* The large page mapping was destroyed. */
6003 * Limit our scan to either the end of the va represented
6004 * by the current page table page, or to the end of the
6005 * range being removed.
6010 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6017 pmap_invalidate_all(pmap);
6019 pmap_delayed_invl_finish();
6020 vm_page_free_pages_toq(&free, true);
6024 * Routine: pmap_remove_all
6026 * Removes this physical page from
6027 * all physical maps in which it resides.
6028 * Reflects back modify bits to the pager.
6031 * Original versions of this routine were very
6032 * inefficient because they iteratively called
6033 * pmap_remove (slow...)
6037 pmap_remove_all(vm_page_t m)
6039 struct md_page *pvh;
6042 struct rwlock *lock;
6043 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6046 struct spglist free;
6047 int pvh_gen, md_gen;
6049 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6050 ("pmap_remove_all: page %p is not managed", m));
6052 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6053 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6054 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6057 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6059 if (!PMAP_TRYLOCK(pmap)) {
6060 pvh_gen = pvh->pv_gen;
6064 if (pvh_gen != pvh->pv_gen) {
6071 pde = pmap_pde(pmap, va);
6072 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6075 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6077 if (!PMAP_TRYLOCK(pmap)) {
6078 pvh_gen = pvh->pv_gen;
6079 md_gen = m->md.pv_gen;
6083 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6089 PG_A = pmap_accessed_bit(pmap);
6090 PG_M = pmap_modified_bit(pmap);
6091 PG_RW = pmap_rw_bit(pmap);
6092 pmap_resident_count_dec(pmap, 1);
6093 pde = pmap_pde(pmap, pv->pv_va);
6094 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6095 " a 2mpage in page %p's pv list", m));
6096 pte = pmap_pde_to_pte(pde, pv->pv_va);
6097 tpte = pte_load_clear(pte);
6099 pmap->pm_stats.wired_count--;
6101 vm_page_aflag_set(m, PGA_REFERENCED);
6104 * Update the vm_page_t clean and reference bits.
6106 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6108 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6109 pmap_invalidate_page(pmap, pv->pv_va);
6110 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6112 free_pv_entry(pmap, pv);
6115 vm_page_aflag_clear(m, PGA_WRITEABLE);
6117 pmap_delayed_invl_wait(m);
6118 vm_page_free_pages_toq(&free, true);
6122 * pmap_protect_pde: do the things to protect a 2mpage in a process
6125 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6127 pd_entry_t newpde, oldpde;
6129 boolean_t anychanged;
6130 pt_entry_t PG_G, PG_M, PG_RW;
6132 PG_G = pmap_global_bit(pmap);
6133 PG_M = pmap_modified_bit(pmap);
6134 PG_RW = pmap_rw_bit(pmap);
6136 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6137 KASSERT((sva & PDRMASK) == 0,
6138 ("pmap_protect_pde: sva is not 2mpage aligned"));
6141 oldpde = newpde = *pde;
6142 if ((prot & VM_PROT_WRITE) == 0) {
6143 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6144 (PG_MANAGED | PG_M | PG_RW)) {
6145 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6146 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6149 newpde &= ~(PG_RW | PG_M);
6151 if ((prot & VM_PROT_EXECUTE) == 0)
6153 if (newpde != oldpde) {
6155 * As an optimization to future operations on this PDE, clear
6156 * PG_PROMOTED. The impending invalidation will remove any
6157 * lingering 4KB page mappings from the TLB.
6159 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6161 if ((oldpde & PG_G) != 0)
6162 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6166 return (anychanged);
6170 * Set the physical protection on the
6171 * specified range of this map as requested.
6174 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6177 vm_offset_t va_next;
6178 pml4_entry_t *pml4e;
6180 pd_entry_t ptpaddr, *pde;
6181 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6182 pt_entry_t obits, pbits;
6183 boolean_t anychanged;
6185 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6186 if (prot == VM_PROT_NONE) {
6187 pmap_remove(pmap, sva, eva);
6191 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6192 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6195 PG_G = pmap_global_bit(pmap);
6196 PG_M = pmap_modified_bit(pmap);
6197 PG_V = pmap_valid_bit(pmap);
6198 PG_RW = pmap_rw_bit(pmap);
6202 * Although this function delays and batches the invalidation
6203 * of stale TLB entries, it does not need to call
6204 * pmap_delayed_invl_start() and
6205 * pmap_delayed_invl_finish(), because it does not
6206 * ordinarily destroy mappings. Stale TLB entries from
6207 * protection-only changes need only be invalidated before the
6208 * pmap lock is released, because protection-only changes do
6209 * not destroy PV entries. Even operations that iterate over
6210 * a physical page's PV list of mappings, like
6211 * pmap_remove_write(), acquire the pmap lock for each
6212 * mapping. Consequently, for protection-only changes, the
6213 * pmap lock suffices to synchronize both page table and TLB
6216 * This function only destroys a mapping if pmap_demote_pde()
6217 * fails. In that case, stale TLB entries are immediately
6222 for (; sva < eva; sva = va_next) {
6223 pml4e = pmap_pml4e(pmap, sva);
6224 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6225 va_next = (sva + NBPML4) & ~PML4MASK;
6231 va_next = (sva + NBPDP) & ~PDPMASK;
6234 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6235 if ((*pdpe & PG_V) == 0)
6237 if ((*pdpe & PG_PS) != 0) {
6238 KASSERT(va_next <= eva,
6239 ("partial update of non-transparent 1G mapping "
6240 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6241 *pdpe, sva, eva, va_next));
6243 obits = pbits = *pdpe;
6244 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6245 MPASS(pmap != kernel_pmap); /* XXXKIB */
6246 if ((prot & VM_PROT_WRITE) == 0)
6247 pbits &= ~(PG_RW | PG_M);
6248 if ((prot & VM_PROT_EXECUTE) == 0)
6251 if (pbits != obits) {
6252 if (!atomic_cmpset_long(pdpe, obits, pbits))
6253 /* PG_PS cannot be cleared under us, */
6260 va_next = (sva + NBPDR) & ~PDRMASK;
6264 pde = pmap_pdpe_to_pde(pdpe, sva);
6268 * Weed out invalid mappings.
6274 * Check for large page.
6276 if ((ptpaddr & PG_PS) != 0) {
6278 * Are we protecting the entire large page? If not,
6279 * demote the mapping and fall through.
6281 if (sva + NBPDR == va_next && eva >= va_next) {
6283 * The TLB entry for a PG_G mapping is
6284 * invalidated by pmap_protect_pde().
6286 if (pmap_protect_pde(pmap, pde, sva, prot))
6289 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6291 * The large page mapping was destroyed.
6300 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6303 obits = pbits = *pte;
6304 if ((pbits & PG_V) == 0)
6307 if ((prot & VM_PROT_WRITE) == 0) {
6308 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6309 (PG_MANAGED | PG_M | PG_RW)) {
6310 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6313 pbits &= ~(PG_RW | PG_M);
6315 if ((prot & VM_PROT_EXECUTE) == 0)
6318 if (pbits != obits) {
6319 if (!atomic_cmpset_long(pte, obits, pbits))
6322 pmap_invalidate_page(pmap, sva);
6329 pmap_invalidate_all(pmap);
6333 #if VM_NRESERVLEVEL > 0
6335 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6338 if (pmap->pm_type != PT_EPT)
6340 return ((pde & EPT_PG_EXECUTE) != 0);
6344 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6345 * single page table page (PTP) to a single 2MB page mapping. For promotion
6346 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6347 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6348 * identical characteristics.
6351 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6352 struct rwlock **lockp)
6355 pt_entry_t *firstpte, oldpte, pa, *pte;
6356 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6360 PG_A = pmap_accessed_bit(pmap);
6361 PG_G = pmap_global_bit(pmap);
6362 PG_M = pmap_modified_bit(pmap);
6363 PG_V = pmap_valid_bit(pmap);
6364 PG_RW = pmap_rw_bit(pmap);
6365 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6366 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6368 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6371 * Examine the first PTE in the specified PTP. Abort if this PTE is
6372 * either invalid, unused, or does not map the first 4KB physical page
6373 * within a 2MB page.
6375 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6378 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6379 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6381 atomic_add_long(&pmap_pde_p_failures, 1);
6382 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6383 " in pmap %p", va, pmap);
6386 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6388 * When PG_M is already clear, PG_RW can be cleared without
6389 * a TLB invalidation.
6391 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
6397 * Examine each of the other PTEs in the specified PTP. Abort if this
6398 * PTE maps an unexpected 4KB physical page or does not have identical
6399 * characteristics to the first PTE.
6401 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6402 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6405 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6406 atomic_add_long(&pmap_pde_p_failures, 1);
6407 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6408 " in pmap %p", va, pmap);
6411 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6413 * When PG_M is already clear, PG_RW can be cleared
6414 * without a TLB invalidation.
6416 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
6419 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6420 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6421 (va & ~PDRMASK), pmap);
6423 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6424 atomic_add_long(&pmap_pde_p_failures, 1);
6425 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6426 " in pmap %p", va, pmap);
6433 * Save the page table page in its current state until the PDE
6434 * mapping the superpage is demoted by pmap_demote_pde() or
6435 * destroyed by pmap_remove_pde().
6437 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6438 KASSERT(mpte >= vm_page_array &&
6439 mpte < &vm_page_array[vm_page_array_size],
6440 ("pmap_promote_pde: page table page is out of range"));
6441 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6442 ("pmap_promote_pde: page table page's pindex is wrong"));
6443 if (pmap_insert_pt_page(pmap, mpte, true)) {
6444 atomic_add_long(&pmap_pde_p_failures, 1);
6446 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6452 * Promote the pv entries.
6454 if ((newpde & PG_MANAGED) != 0)
6455 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6458 * Propagate the PAT index to its proper position.
6460 newpde = pmap_swap_pat(pmap, newpde);
6463 * Map the superpage.
6465 if (workaround_erratum383)
6466 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6468 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6470 atomic_add_long(&pmap_pde_promotions, 1);
6471 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6472 " in pmap %p", va, pmap);
6474 #endif /* VM_NRESERVLEVEL > 0 */
6477 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6481 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6483 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6484 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6485 ("psind %d unexpected", psind));
6486 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6487 ("unaligned phys address %#lx newpte %#lx psind %d",
6488 newpte & PG_FRAME, newpte, psind));
6489 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6490 ("unaligned va %#lx psind %d", va, psind));
6491 KASSERT(va < VM_MAXUSER_ADDRESS,
6492 ("kernel mode non-transparent superpage")); /* XXXKIB */
6493 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6494 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6496 PG_V = pmap_valid_bit(pmap);
6499 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6500 return (KERN_PROTECTION_FAILURE);
6502 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6503 pten |= pmap_pkru_get(pmap, va);
6505 if (psind == 2) { /* 1G */
6506 pml4e = pmap_pml4e(pmap, va);
6507 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6508 mp = _pmap_allocpte(pmap, pmap_pml4e_pindex(va),
6512 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6513 pdpe = &pdpe[pmap_pdpe_index(va)];
6515 MPASS(origpte == 0);
6517 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6518 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6520 if ((origpte & PG_V) == 0) {
6521 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6526 } else /* (psind == 1) */ { /* 2M */
6527 pde = pmap_pde(pmap, va);
6529 mp = _pmap_allocpte(pmap, pmap_pdpe_pindex(va),
6533 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6534 pde = &pde[pmap_pde_index(va)];
6536 MPASS(origpte == 0);
6539 if ((origpte & PG_V) == 0) {
6540 pdpe = pmap_pdpe(pmap, va);
6541 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6542 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6548 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6549 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6550 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6551 va, psind == 2 ? "1G" : "2M", origpte, pten));
6552 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6553 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6554 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6555 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6556 if ((origpte & PG_V) == 0)
6557 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
6559 return (KERN_SUCCESS);
6562 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6563 return (KERN_RESOURCE_SHORTAGE);
6571 * Insert the given physical page (p) at
6572 * the specified virtual address (v) in the
6573 * target physical map with the protection requested.
6575 * If specified, the page will be wired down, meaning
6576 * that the related pte can not be reclaimed.
6578 * NB: This is the only routine which MAY NOT lazy-evaluate
6579 * or lose information. That is, this routine must actually
6580 * insert this page into the given map NOW.
6582 * When destroying both a page table and PV entry, this function
6583 * performs the TLB invalidation before releasing the PV list
6584 * lock, so we do not need pmap_delayed_invl_page() calls here.
6587 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6588 u_int flags, int8_t psind)
6590 struct rwlock *lock;
6592 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6593 pt_entry_t newpte, origpte;
6600 PG_A = pmap_accessed_bit(pmap);
6601 PG_G = pmap_global_bit(pmap);
6602 PG_M = pmap_modified_bit(pmap);
6603 PG_V = pmap_valid_bit(pmap);
6604 PG_RW = pmap_rw_bit(pmap);
6606 va = trunc_page(va);
6607 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6608 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6609 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6611 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6612 va >= kmi.clean_eva,
6613 ("pmap_enter: managed mapping within the clean submap"));
6614 if ((m->oflags & VPO_UNMANAGED) == 0)
6615 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6616 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6617 ("pmap_enter: flags %u has reserved bits set", flags));
6618 pa = VM_PAGE_TO_PHYS(m);
6619 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6620 if ((flags & VM_PROT_WRITE) != 0)
6622 if ((prot & VM_PROT_WRITE) != 0)
6624 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6625 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6626 if ((prot & VM_PROT_EXECUTE) == 0)
6628 if ((flags & PMAP_ENTER_WIRED) != 0)
6630 if (va < VM_MAXUSER_ADDRESS)
6632 if (pmap == kernel_pmap)
6634 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6637 * Set modified bit gratuitously for writeable mappings if
6638 * the page is unmanaged. We do not want to take a fault
6639 * to do the dirty bit accounting for these mappings.
6641 if ((m->oflags & VPO_UNMANAGED) != 0) {
6642 if ((newpte & PG_RW) != 0)
6645 newpte |= PG_MANAGED;
6649 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
6650 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
6651 ("managed largepage va %#lx flags %#x", va, flags));
6652 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
6657 /* Assert the required virtual and physical alignment. */
6658 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6659 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6660 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6666 * In the case that a page table page is not
6667 * resident, we are creating it here.
6670 pde = pmap_pde(pmap, va);
6671 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6672 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6673 pte = pmap_pde_to_pte(pde, va);
6674 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6675 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6678 } else if (va < VM_MAXUSER_ADDRESS) {
6680 * Here if the pte page isn't mapped, or if it has been
6683 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6684 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6685 nosleep ? NULL : &lock, va);
6686 if (mpte == NULL && nosleep) {
6687 rv = KERN_RESOURCE_SHORTAGE;
6692 panic("pmap_enter: invalid page directory va=%#lx", va);
6696 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6697 newpte |= pmap_pkru_get(pmap, va);
6700 * Is the specified virtual address already mapped?
6702 if ((origpte & PG_V) != 0) {
6704 * Wiring change, just update stats. We don't worry about
6705 * wiring PT pages as they remain resident as long as there
6706 * are valid mappings in them. Hence, if a user page is wired,
6707 * the PT page will be also.
6709 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6710 pmap->pm_stats.wired_count++;
6711 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6712 pmap->pm_stats.wired_count--;
6715 * Remove the extra PT page reference.
6719 KASSERT(mpte->ref_count > 0,
6720 ("pmap_enter: missing reference to page table page,"
6725 * Has the physical page changed?
6727 opa = origpte & PG_FRAME;
6730 * No, might be a protection or wiring change.
6732 if ((origpte & PG_MANAGED) != 0 &&
6733 (newpte & PG_RW) != 0)
6734 vm_page_aflag_set(m, PGA_WRITEABLE);
6735 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6741 * The physical page has changed. Temporarily invalidate
6742 * the mapping. This ensures that all threads sharing the
6743 * pmap keep a consistent view of the mapping, which is
6744 * necessary for the correct handling of COW faults. It
6745 * also permits reuse of the old mapping's PV entry,
6746 * avoiding an allocation.
6748 * For consistency, handle unmanaged mappings the same way.
6750 origpte = pte_load_clear(pte);
6751 KASSERT((origpte & PG_FRAME) == opa,
6752 ("pmap_enter: unexpected pa update for %#lx", va));
6753 if ((origpte & PG_MANAGED) != 0) {
6754 om = PHYS_TO_VM_PAGE(opa);
6757 * The pmap lock is sufficient to synchronize with
6758 * concurrent calls to pmap_page_test_mappings() and
6759 * pmap_ts_referenced().
6761 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6763 if ((origpte & PG_A) != 0) {
6764 pmap_invalidate_page(pmap, va);
6765 vm_page_aflag_set(om, PGA_REFERENCED);
6767 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6768 pv = pmap_pvh_remove(&om->md, pmap, va);
6770 ("pmap_enter: no PV entry for %#lx", va));
6771 if ((newpte & PG_MANAGED) == 0)
6772 free_pv_entry(pmap, pv);
6773 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6774 TAILQ_EMPTY(&om->md.pv_list) &&
6775 ((om->flags & PG_FICTITIOUS) != 0 ||
6776 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6777 vm_page_aflag_clear(om, PGA_WRITEABLE);
6780 * Since this mapping is unmanaged, assume that PG_A
6783 pmap_invalidate_page(pmap, va);
6788 * Increment the counters.
6790 if ((newpte & PG_W) != 0)
6791 pmap->pm_stats.wired_count++;
6792 pmap_resident_count_inc(pmap, 1);
6796 * Enter on the PV list if part of our managed memory.
6798 if ((newpte & PG_MANAGED) != 0) {
6800 pv = get_pv_entry(pmap, &lock);
6803 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6804 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6806 if ((newpte & PG_RW) != 0)
6807 vm_page_aflag_set(m, PGA_WRITEABLE);
6813 if ((origpte & PG_V) != 0) {
6815 origpte = pte_load_store(pte, newpte);
6816 KASSERT((origpte & PG_FRAME) == pa,
6817 ("pmap_enter: unexpected pa update for %#lx", va));
6818 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6820 if ((origpte & PG_MANAGED) != 0)
6824 * Although the PTE may still have PG_RW set, TLB
6825 * invalidation may nonetheless be required because
6826 * the PTE no longer has PG_M set.
6828 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6830 * This PTE change does not require TLB invalidation.
6834 if ((origpte & PG_A) != 0)
6835 pmap_invalidate_page(pmap, va);
6837 pte_store(pte, newpte);
6841 #if VM_NRESERVLEVEL > 0
6843 * If both the page table page and the reservation are fully
6844 * populated, then attempt promotion.
6846 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6847 pmap_ps_enabled(pmap) &&
6848 (m->flags & PG_FICTITIOUS) == 0 &&
6849 vm_reserv_level_iffullpop(m) == 0)
6850 pmap_promote_pde(pmap, pde, va, &lock);
6862 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6863 * if successful. Returns false if (1) a page table page cannot be allocated
6864 * without sleeping, (2) a mapping already exists at the specified virtual
6865 * address, or (3) a PV entry cannot be allocated without reclaiming another
6869 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6870 struct rwlock **lockp)
6875 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6876 PG_V = pmap_valid_bit(pmap);
6877 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6879 if ((m->oflags & VPO_UNMANAGED) == 0)
6880 newpde |= PG_MANAGED;
6881 if ((prot & VM_PROT_EXECUTE) == 0)
6883 if (va < VM_MAXUSER_ADDRESS)
6885 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6886 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6891 * Returns true if every page table entry in the specified page table page is
6895 pmap_every_pte_zero(vm_paddr_t pa)
6897 pt_entry_t *pt_end, *pte;
6899 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6900 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6901 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6909 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6910 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6911 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6912 * a mapping already exists at the specified virtual address. Returns
6913 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6914 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6915 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6917 * The parameter "m" is only used when creating a managed, writeable mapping.
6920 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6921 vm_page_t m, struct rwlock **lockp)
6923 struct spglist free;
6924 pd_entry_t oldpde, *pde;
6925 pt_entry_t PG_G, PG_RW, PG_V;
6928 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6929 ("pmap_enter_pde: cannot create wired user mapping"));
6930 PG_G = pmap_global_bit(pmap);
6931 PG_RW = pmap_rw_bit(pmap);
6932 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6933 ("pmap_enter_pde: newpde is missing PG_M"));
6934 PG_V = pmap_valid_bit(pmap);
6935 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6937 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6939 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6940 " in pmap %p", va, pmap);
6941 return (KERN_FAILURE);
6943 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6944 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6945 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6946 " in pmap %p", va, pmap);
6947 return (KERN_RESOURCE_SHORTAGE);
6951 * If pkru is not same for the whole pde range, return failure
6952 * and let vm_fault() cope. Check after pde allocation, since
6955 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6956 pmap_abort_ptp(pmap, va, pdpg);
6957 return (KERN_FAILURE);
6959 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6960 newpde &= ~X86_PG_PKU_MASK;
6961 newpde |= pmap_pkru_get(pmap, va);
6965 * If there are existing mappings, either abort or remove them.
6968 if ((oldpde & PG_V) != 0) {
6969 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6970 ("pmap_enter_pde: pdpg's reference count is too low"));
6971 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6972 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6973 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6976 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6977 " in pmap %p", va, pmap);
6978 return (KERN_FAILURE);
6980 /* Break the existing mapping(s). */
6982 if ((oldpde & PG_PS) != 0) {
6984 * The reference to the PD page that was acquired by
6985 * pmap_alloc_pde() ensures that it won't be freed.
6986 * However, if the PDE resulted from a promotion, then
6987 * a reserved PT page could be freed.
6989 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6990 if ((oldpde & PG_G) == 0)
6991 pmap_invalidate_pde_page(pmap, va, oldpde);
6993 pmap_delayed_invl_start();
6994 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6996 pmap_invalidate_all(pmap);
6997 pmap_delayed_invl_finish();
6999 if (va < VM_MAXUSER_ADDRESS) {
7000 vm_page_free_pages_toq(&free, true);
7001 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7004 KASSERT(SLIST_EMPTY(&free),
7005 ("pmap_enter_pde: freed kernel page table page"));
7008 * Both pmap_remove_pde() and pmap_remove_ptes() will
7009 * leave the kernel page table page zero filled.
7011 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7012 if (pmap_insert_pt_page(pmap, mt, false))
7013 panic("pmap_enter_pde: trie insert failed");
7017 if ((newpde & PG_MANAGED) != 0) {
7019 * Abort this mapping if its PV entry could not be created.
7021 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7023 pmap_abort_ptp(pmap, va, pdpg);
7024 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7025 " in pmap %p", va, pmap);
7026 return (KERN_RESOURCE_SHORTAGE);
7028 if ((newpde & PG_RW) != 0) {
7029 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7030 vm_page_aflag_set(mt, PGA_WRITEABLE);
7035 * Increment counters.
7037 if ((newpde & PG_W) != 0)
7038 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7039 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7042 * Map the superpage. (This is not a promoted mapping; there will not
7043 * be any lingering 4KB page mappings in the TLB.)
7045 pde_store(pde, newpde);
7047 atomic_add_long(&pmap_pde_mappings, 1);
7048 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7050 return (KERN_SUCCESS);
7054 * Maps a sequence of resident pages belonging to the same object.
7055 * The sequence begins with the given page m_start. This page is
7056 * mapped at the given virtual address start. Each subsequent page is
7057 * mapped at a virtual address that is offset from start by the same
7058 * amount as the page is offset from m_start within the object. The
7059 * last page in the sequence is the page with the largest offset from
7060 * m_start that can be mapped at a virtual address less than the given
7061 * virtual address end. Not every virtual page between start and end
7062 * is mapped; only those for which a resident page exists with the
7063 * corresponding offset from m_start are mapped.
7066 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7067 vm_page_t m_start, vm_prot_t prot)
7069 struct rwlock *lock;
7072 vm_pindex_t diff, psize;
7074 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7076 psize = atop(end - start);
7081 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7082 va = start + ptoa(diff);
7083 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7084 m->psind == 1 && pmap_ps_enabled(pmap) &&
7085 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
7086 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7087 m = &m[NBPDR / PAGE_SIZE - 1];
7089 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7091 m = TAILQ_NEXT(m, listq);
7099 * this code makes some *MAJOR* assumptions:
7100 * 1. Current pmap & pmap exists.
7103 * 4. No page table pages.
7104 * but is *MUCH* faster than pmap_enter...
7108 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7110 struct rwlock *lock;
7114 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7121 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7122 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7124 pt_entry_t newpte, *pte, PG_V;
7126 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
7127 (m->oflags & VPO_UNMANAGED) != 0,
7128 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7129 PG_V = pmap_valid_bit(pmap);
7130 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7133 * In the case that a page table page is not
7134 * resident, we are creating it here.
7136 if (va < VM_MAXUSER_ADDRESS) {
7137 vm_pindex_t ptepindex;
7141 * Calculate pagetable page index
7143 ptepindex = pmap_pde_pindex(va);
7144 if (mpte && (mpte->pindex == ptepindex)) {
7148 * Get the page directory entry
7150 ptepa = pmap_pde(pmap, va);
7153 * If the page table page is mapped, we just increment
7154 * the hold count, and activate it. Otherwise, we
7155 * attempt to allocate a page table page. If this
7156 * attempt fails, we don't retry. Instead, we give up.
7158 if (ptepa && (*ptepa & PG_V) != 0) {
7161 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7165 * Pass NULL instead of the PV list lock
7166 * pointer, because we don't intend to sleep.
7168 mpte = _pmap_allocpte(pmap, ptepindex, NULL,
7174 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7175 pte = &pte[pmap_pte_index(va)];
7187 * Enter on the PV list if part of our managed memory.
7189 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7190 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7192 pmap_abort_ptp(pmap, va, mpte);
7197 * Increment counters
7199 pmap_resident_count_inc(pmap, 1);
7201 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7202 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7203 if ((m->oflags & VPO_UNMANAGED) == 0)
7204 newpte |= PG_MANAGED;
7205 if ((prot & VM_PROT_EXECUTE) == 0)
7207 if (va < VM_MAXUSER_ADDRESS)
7208 newpte |= PG_U | pmap_pkru_get(pmap, va);
7209 pte_store(pte, newpte);
7214 * Make a temporary mapping for a physical address. This is only intended
7215 * to be used for panic dumps.
7218 pmap_kenter_temporary(vm_paddr_t pa, int i)
7222 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7223 pmap_kenter(va, pa);
7225 return ((void *)crashdumpmap);
7229 * This code maps large physical mmap regions into the
7230 * processor address space. Note that some shortcuts
7231 * are taken, but the code works.
7234 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7235 vm_pindex_t pindex, vm_size_t size)
7238 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7239 vm_paddr_t pa, ptepa;
7243 PG_A = pmap_accessed_bit(pmap);
7244 PG_M = pmap_modified_bit(pmap);
7245 PG_V = pmap_valid_bit(pmap);
7246 PG_RW = pmap_rw_bit(pmap);
7248 VM_OBJECT_ASSERT_WLOCKED(object);
7249 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7250 ("pmap_object_init_pt: non-device object"));
7251 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7252 if (!pmap_ps_enabled(pmap))
7254 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7256 p = vm_page_lookup(object, pindex);
7257 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7258 ("pmap_object_init_pt: invalid page %p", p));
7259 pat_mode = p->md.pat_mode;
7262 * Abort the mapping if the first page is not physically
7263 * aligned to a 2MB page boundary.
7265 ptepa = VM_PAGE_TO_PHYS(p);
7266 if (ptepa & (NBPDR - 1))
7270 * Skip the first page. Abort the mapping if the rest of
7271 * the pages are not physically contiguous or have differing
7272 * memory attributes.
7274 p = TAILQ_NEXT(p, listq);
7275 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7277 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7278 ("pmap_object_init_pt: invalid page %p", p));
7279 if (pa != VM_PAGE_TO_PHYS(p) ||
7280 pat_mode != p->md.pat_mode)
7282 p = TAILQ_NEXT(p, listq);
7286 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7287 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7288 * will not affect the termination of this loop.
7291 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7292 pa < ptepa + size; pa += NBPDR) {
7293 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7296 * The creation of mappings below is only an
7297 * optimization. If a page directory page
7298 * cannot be allocated without blocking,
7299 * continue on to the next mapping rather than
7305 if ((*pde & PG_V) == 0) {
7306 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7307 PG_U | PG_RW | PG_V);
7308 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7309 atomic_add_long(&pmap_pde_mappings, 1);
7311 /* Continue on if the PDE is already valid. */
7313 KASSERT(pdpg->ref_count > 0,
7314 ("pmap_object_init_pt: missing reference "
7315 "to page directory page, va: 0x%lx", addr));
7324 * Clear the wired attribute from the mappings for the specified range of
7325 * addresses in the given pmap. Every valid mapping within that range
7326 * must have the wired attribute set. In contrast, invalid mappings
7327 * cannot have the wired attribute set, so they are ignored.
7329 * The wired attribute of the page table entry is not a hardware
7330 * feature, so there is no need to invalidate any TLB entries.
7331 * Since pmap_demote_pde() for the wired entry must never fail,
7332 * pmap_delayed_invl_start()/finish() calls around the
7333 * function are not needed.
7336 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7338 vm_offset_t va_next;
7339 pml4_entry_t *pml4e;
7342 pt_entry_t *pte, PG_V, PG_G;
7344 PG_V = pmap_valid_bit(pmap);
7345 PG_G = pmap_global_bit(pmap);
7347 for (; sva < eva; sva = va_next) {
7348 pml4e = pmap_pml4e(pmap, sva);
7349 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7350 va_next = (sva + NBPML4) & ~PML4MASK;
7356 va_next = (sva + NBPDP) & ~PDPMASK;
7359 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7360 if ((*pdpe & PG_V) == 0)
7362 if ((*pdpe & PG_PS) != 0) {
7363 KASSERT(va_next <= eva,
7364 ("partial update of non-transparent 1G mapping "
7365 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7366 *pdpe, sva, eva, va_next));
7367 MPASS(pmap != kernel_pmap); /* XXXKIB */
7368 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7369 atomic_clear_long(pdpe, PG_W);
7370 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7374 va_next = (sva + NBPDR) & ~PDRMASK;
7377 pde = pmap_pdpe_to_pde(pdpe, sva);
7378 if ((*pde & PG_V) == 0)
7380 if ((*pde & PG_PS) != 0) {
7381 if ((*pde & PG_W) == 0)
7382 panic("pmap_unwire: pde %#jx is missing PG_W",
7386 * Are we unwiring the entire large page? If not,
7387 * demote the mapping and fall through.
7389 if (sva + NBPDR == va_next && eva >= va_next) {
7390 atomic_clear_long(pde, PG_W);
7391 pmap->pm_stats.wired_count -= NBPDR /
7394 } else if (!pmap_demote_pde(pmap, pde, sva))
7395 panic("pmap_unwire: demotion failed");
7399 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7401 if ((*pte & PG_V) == 0)
7403 if ((*pte & PG_W) == 0)
7404 panic("pmap_unwire: pte %#jx is missing PG_W",
7408 * PG_W must be cleared atomically. Although the pmap
7409 * lock synchronizes access to PG_W, another processor
7410 * could be setting PG_M and/or PG_A concurrently.
7412 atomic_clear_long(pte, PG_W);
7413 pmap->pm_stats.wired_count--;
7420 * Copy the range specified by src_addr/len
7421 * from the source map to the range dst_addr/len
7422 * in the destination map.
7424 * This routine is only advisory and need not do anything.
7427 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7428 vm_offset_t src_addr)
7430 struct rwlock *lock;
7431 pml4_entry_t *pml4e;
7433 pd_entry_t *pde, srcptepaddr;
7434 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7435 vm_offset_t addr, end_addr, va_next;
7436 vm_page_t dst_pdpg, dstmpte, srcmpte;
7438 if (dst_addr != src_addr)
7441 if (dst_pmap->pm_type != src_pmap->pm_type)
7445 * EPT page table entries that require emulation of A/D bits are
7446 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7447 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7448 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7449 * implementations flag an EPT misconfiguration for exec-only
7450 * mappings we skip this function entirely for emulated pmaps.
7452 if (pmap_emulate_ad_bits(dst_pmap))
7455 end_addr = src_addr + len;
7457 if (dst_pmap < src_pmap) {
7458 PMAP_LOCK(dst_pmap);
7459 PMAP_LOCK(src_pmap);
7461 PMAP_LOCK(src_pmap);
7462 PMAP_LOCK(dst_pmap);
7465 PG_A = pmap_accessed_bit(dst_pmap);
7466 PG_M = pmap_modified_bit(dst_pmap);
7467 PG_V = pmap_valid_bit(dst_pmap);
7469 for (addr = src_addr; addr < end_addr; addr = va_next) {
7470 KASSERT(addr < UPT_MIN_ADDRESS,
7471 ("pmap_copy: invalid to pmap_copy page tables"));
7473 pml4e = pmap_pml4e(src_pmap, addr);
7474 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7475 va_next = (addr + NBPML4) & ~PML4MASK;
7481 va_next = (addr + NBPDP) & ~PDPMASK;
7484 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7485 if ((*pdpe & PG_V) == 0)
7487 if ((*pdpe & PG_PS) != 0) {
7488 KASSERT(va_next <= end_addr,
7489 ("partial update of non-transparent 1G mapping "
7490 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7491 *pdpe, addr, end_addr, va_next));
7492 MPASS((addr & PDPMASK) == 0);
7493 MPASS((*pdpe & PG_MANAGED) == 0);
7494 srcptepaddr = *pdpe;
7495 pdpe = pmap_pdpe(dst_pmap, addr);
7497 if (_pmap_allocpte(dst_pmap,
7498 pmap_pml4e_pindex(addr), NULL, addr) ==
7501 pdpe = pmap_pdpe(dst_pmap, addr);
7503 pml4e = pmap_pml4e(dst_pmap, addr);
7504 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7505 dst_pdpg->ref_count++;
7508 ("1G mapping present in dst pmap "
7509 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7510 *pdpe, addr, end_addr, va_next));
7511 *pdpe = srcptepaddr & ~PG_W;
7512 pmap_resident_count_inc(dst_pmap, NBPDP / PAGE_SIZE);
7516 va_next = (addr + NBPDR) & ~PDRMASK;
7520 pde = pmap_pdpe_to_pde(pdpe, addr);
7522 if (srcptepaddr == 0)
7525 if (srcptepaddr & PG_PS) {
7526 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7528 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7531 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7532 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7533 PMAP_ENTER_NORECLAIM, &lock))) {
7534 *pde = srcptepaddr & ~PG_W;
7535 pmap_resident_count_inc(dst_pmap, NBPDR /
7537 atomic_add_long(&pmap_pde_mappings, 1);
7539 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7543 srcptepaddr &= PG_FRAME;
7544 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7545 KASSERT(srcmpte->ref_count > 0,
7546 ("pmap_copy: source page table page is unused"));
7548 if (va_next > end_addr)
7551 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7552 src_pte = &src_pte[pmap_pte_index(addr)];
7554 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7558 * We only virtual copy managed pages.
7560 if ((ptetemp & PG_MANAGED) == 0)
7563 if (dstmpte != NULL) {
7564 KASSERT(dstmpte->pindex ==
7565 pmap_pde_pindex(addr),
7566 ("dstmpte pindex/addr mismatch"));
7567 dstmpte->ref_count++;
7568 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7571 dst_pte = (pt_entry_t *)
7572 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7573 dst_pte = &dst_pte[pmap_pte_index(addr)];
7574 if (*dst_pte == 0 &&
7575 pmap_try_insert_pv_entry(dst_pmap, addr,
7576 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7578 * Clear the wired, modified, and accessed
7579 * (referenced) bits during the copy.
7581 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7582 pmap_resident_count_inc(dst_pmap, 1);
7584 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7587 /* Have we copied all of the valid mappings? */
7588 if (dstmpte->ref_count >= srcmpte->ref_count)
7595 PMAP_UNLOCK(src_pmap);
7596 PMAP_UNLOCK(dst_pmap);
7600 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7604 if (dst_pmap->pm_type != src_pmap->pm_type ||
7605 dst_pmap->pm_type != PT_X86 ||
7606 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7609 if (dst_pmap < src_pmap) {
7610 PMAP_LOCK(dst_pmap);
7611 PMAP_LOCK(src_pmap);
7613 PMAP_LOCK(src_pmap);
7614 PMAP_LOCK(dst_pmap);
7616 error = pmap_pkru_copy(dst_pmap, src_pmap);
7617 /* Clean up partial copy on failure due to no memory. */
7618 if (error == ENOMEM)
7619 pmap_pkru_deassign_all(dst_pmap);
7620 PMAP_UNLOCK(src_pmap);
7621 PMAP_UNLOCK(dst_pmap);
7622 if (error != ENOMEM)
7630 * Zero the specified hardware page.
7633 pmap_zero_page(vm_page_t m)
7635 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7637 pagezero((void *)va);
7641 * Zero an an area within a single hardware page. off and size must not
7642 * cover an area beyond a single hardware page.
7645 pmap_zero_page_area(vm_page_t m, int off, int size)
7647 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7649 if (off == 0 && size == PAGE_SIZE)
7650 pagezero((void *)va);
7652 bzero((char *)va + off, size);
7656 * Copy 1 specified hardware page to another.
7659 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7661 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7662 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7664 pagecopy((void *)src, (void *)dst);
7667 int unmapped_buf_allowed = 1;
7670 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7671 vm_offset_t b_offset, int xfersize)
7675 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7679 while (xfersize > 0) {
7680 a_pg_offset = a_offset & PAGE_MASK;
7681 pages[0] = ma[a_offset >> PAGE_SHIFT];
7682 b_pg_offset = b_offset & PAGE_MASK;
7683 pages[1] = mb[b_offset >> PAGE_SHIFT];
7684 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7685 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7686 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7687 a_cp = (char *)vaddr[0] + a_pg_offset;
7688 b_cp = (char *)vaddr[1] + b_pg_offset;
7689 bcopy(a_cp, b_cp, cnt);
7690 if (__predict_false(mapped))
7691 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7699 * Returns true if the pmap's pv is one of the first
7700 * 16 pvs linked to from this page. This count may
7701 * be changed upwards or downwards in the future; it
7702 * is only necessary that true be returned for a small
7703 * subset of pmaps for proper page aging.
7706 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7708 struct md_page *pvh;
7709 struct rwlock *lock;
7714 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7715 ("pmap_page_exists_quick: page %p is not managed", m));
7717 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7719 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7720 if (PV_PMAP(pv) == pmap) {
7728 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7729 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7730 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7731 if (PV_PMAP(pv) == pmap) {
7745 * pmap_page_wired_mappings:
7747 * Return the number of managed mappings to the given physical page
7751 pmap_page_wired_mappings(vm_page_t m)
7753 struct rwlock *lock;
7754 struct md_page *pvh;
7758 int count, md_gen, pvh_gen;
7760 if ((m->oflags & VPO_UNMANAGED) != 0)
7762 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7766 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7768 if (!PMAP_TRYLOCK(pmap)) {
7769 md_gen = m->md.pv_gen;
7773 if (md_gen != m->md.pv_gen) {
7778 pte = pmap_pte(pmap, pv->pv_va);
7779 if ((*pte & PG_W) != 0)
7783 if ((m->flags & PG_FICTITIOUS) == 0) {
7784 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7785 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7787 if (!PMAP_TRYLOCK(pmap)) {
7788 md_gen = m->md.pv_gen;
7789 pvh_gen = pvh->pv_gen;
7793 if (md_gen != m->md.pv_gen ||
7794 pvh_gen != pvh->pv_gen) {
7799 pte = pmap_pde(pmap, pv->pv_va);
7800 if ((*pte & PG_W) != 0)
7810 * Returns TRUE if the given page is mapped individually or as part of
7811 * a 2mpage. Otherwise, returns FALSE.
7814 pmap_page_is_mapped(vm_page_t m)
7816 struct rwlock *lock;
7819 if ((m->oflags & VPO_UNMANAGED) != 0)
7821 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7823 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7824 ((m->flags & PG_FICTITIOUS) == 0 &&
7825 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7831 * Destroy all managed, non-wired mappings in the given user-space
7832 * pmap. This pmap cannot be active on any processor besides the
7835 * This function cannot be applied to the kernel pmap. Moreover, it
7836 * is not intended for general use. It is only to be used during
7837 * process termination. Consequently, it can be implemented in ways
7838 * that make it faster than pmap_remove(). First, it can more quickly
7839 * destroy mappings by iterating over the pmap's collection of PV
7840 * entries, rather than searching the page table. Second, it doesn't
7841 * have to test and clear the page table entries atomically, because
7842 * no processor is currently accessing the user address space. In
7843 * particular, a page table entry's dirty bit won't change state once
7844 * this function starts.
7846 * Although this function destroys all of the pmap's managed,
7847 * non-wired mappings, it can delay and batch the invalidation of TLB
7848 * entries without calling pmap_delayed_invl_start() and
7849 * pmap_delayed_invl_finish(). Because the pmap is not active on
7850 * any other processor, none of these TLB entries will ever be used
7851 * before their eventual invalidation. Consequently, there is no need
7852 * for either pmap_remove_all() or pmap_remove_write() to wait for
7853 * that eventual TLB invalidation.
7856 pmap_remove_pages(pmap_t pmap)
7859 pt_entry_t *pte, tpte;
7860 pt_entry_t PG_M, PG_RW, PG_V;
7861 struct spglist free;
7862 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7863 vm_page_t m, mpte, mt;
7865 struct md_page *pvh;
7866 struct pv_chunk *pc, *npc;
7867 struct rwlock *lock;
7869 uint64_t inuse, bitmask;
7870 int allfree, field, freed, i, idx;
7871 boolean_t superpage;
7875 * Assert that the given pmap is only active on the current
7876 * CPU. Unfortunately, we cannot block another CPU from
7877 * activating the pmap while this function is executing.
7879 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7882 cpuset_t other_cpus;
7884 other_cpus = all_cpus;
7886 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7887 CPU_AND(&other_cpus, &pmap->pm_active);
7889 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7894 PG_M = pmap_modified_bit(pmap);
7895 PG_V = pmap_valid_bit(pmap);
7896 PG_RW = pmap_rw_bit(pmap);
7898 for (i = 0; i < PMAP_MEMDOM; i++)
7899 TAILQ_INIT(&free_chunks[i]);
7902 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7905 for (field = 0; field < _NPCM; field++) {
7906 inuse = ~pc->pc_map[field] & pc_freemask[field];
7907 while (inuse != 0) {
7909 bitmask = 1UL << bit;
7910 idx = field * 64 + bit;
7911 pv = &pc->pc_pventry[idx];
7914 pte = pmap_pdpe(pmap, pv->pv_va);
7916 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7918 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7921 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7923 pte = &pte[pmap_pte_index(pv->pv_va)];
7927 * Keep track whether 'tpte' is a
7928 * superpage explicitly instead of
7929 * relying on PG_PS being set.
7931 * This is because PG_PS is numerically
7932 * identical to PG_PTE_PAT and thus a
7933 * regular page could be mistaken for
7939 if ((tpte & PG_V) == 0) {
7940 panic("bad pte va %lx pte %lx",
7945 * We cannot remove wired pages from a process' mapping at this time
7953 pa = tpte & PG_PS_FRAME;
7955 pa = tpte & PG_FRAME;
7957 m = PHYS_TO_VM_PAGE(pa);
7958 KASSERT(m->phys_addr == pa,
7959 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7960 m, (uintmax_t)m->phys_addr,
7963 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7964 m < &vm_page_array[vm_page_array_size],
7965 ("pmap_remove_pages: bad tpte %#jx",
7971 * Update the vm_page_t clean/reference bits.
7973 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7975 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7981 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7984 pc->pc_map[field] |= bitmask;
7986 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7987 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7988 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7990 if (TAILQ_EMPTY(&pvh->pv_list)) {
7991 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7992 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
7993 TAILQ_EMPTY(&mt->md.pv_list))
7994 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7996 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7998 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7999 ("pmap_remove_pages: pte page not promoted"));
8000 pmap_resident_count_dec(pmap, 1);
8001 KASSERT(mpte->ref_count == NPTEPG,
8002 ("pmap_remove_pages: pte page reference count error"));
8003 mpte->ref_count = 0;
8004 pmap_add_delayed_free_list(mpte, &free, FALSE);
8007 pmap_resident_count_dec(pmap, 1);
8008 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8010 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8011 TAILQ_EMPTY(&m->md.pv_list) &&
8012 (m->flags & PG_FICTITIOUS) == 0) {
8013 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8014 if (TAILQ_EMPTY(&pvh->pv_list))
8015 vm_page_aflag_clear(m, PGA_WRITEABLE);
8018 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8022 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
8023 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
8024 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
8026 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8027 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8032 pmap_invalidate_all(pmap);
8033 pmap_pkru_deassign_all(pmap);
8034 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8036 vm_page_free_pages_toq(&free, true);
8040 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8042 struct rwlock *lock;
8044 struct md_page *pvh;
8045 pt_entry_t *pte, mask;
8046 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8048 int md_gen, pvh_gen;
8052 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8055 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8057 if (!PMAP_TRYLOCK(pmap)) {
8058 md_gen = m->md.pv_gen;
8062 if (md_gen != m->md.pv_gen) {
8067 pte = pmap_pte(pmap, pv->pv_va);
8070 PG_M = pmap_modified_bit(pmap);
8071 PG_RW = pmap_rw_bit(pmap);
8072 mask |= PG_RW | PG_M;
8075 PG_A = pmap_accessed_bit(pmap);
8076 PG_V = pmap_valid_bit(pmap);
8077 mask |= PG_V | PG_A;
8079 rv = (*pte & mask) == mask;
8084 if ((m->flags & PG_FICTITIOUS) == 0) {
8085 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8086 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8088 if (!PMAP_TRYLOCK(pmap)) {
8089 md_gen = m->md.pv_gen;
8090 pvh_gen = pvh->pv_gen;
8094 if (md_gen != m->md.pv_gen ||
8095 pvh_gen != pvh->pv_gen) {
8100 pte = pmap_pde(pmap, pv->pv_va);
8103 PG_M = pmap_modified_bit(pmap);
8104 PG_RW = pmap_rw_bit(pmap);
8105 mask |= PG_RW | PG_M;
8108 PG_A = pmap_accessed_bit(pmap);
8109 PG_V = pmap_valid_bit(pmap);
8110 mask |= PG_V | PG_A;
8112 rv = (*pte & mask) == mask;
8126 * Return whether or not the specified physical page was modified
8127 * in any physical maps.
8130 pmap_is_modified(vm_page_t m)
8133 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8134 ("pmap_is_modified: page %p is not managed", m));
8137 * If the page is not busied then this check is racy.
8139 if (!pmap_page_is_write_mapped(m))
8141 return (pmap_page_test_mappings(m, FALSE, TRUE));
8145 * pmap_is_prefaultable:
8147 * Return whether or not the specified virtual address is eligible
8151 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8154 pt_entry_t *pte, PG_V;
8157 PG_V = pmap_valid_bit(pmap);
8160 pde = pmap_pde(pmap, addr);
8161 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8162 pte = pmap_pde_to_pte(pde, addr);
8163 rv = (*pte & PG_V) == 0;
8170 * pmap_is_referenced:
8172 * Return whether or not the specified physical page was referenced
8173 * in any physical maps.
8176 pmap_is_referenced(vm_page_t m)
8179 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8180 ("pmap_is_referenced: page %p is not managed", m));
8181 return (pmap_page_test_mappings(m, TRUE, FALSE));
8185 * Clear the write and modified bits in each of the given page's mappings.
8188 pmap_remove_write(vm_page_t m)
8190 struct md_page *pvh;
8192 struct rwlock *lock;
8193 pv_entry_t next_pv, pv;
8195 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8197 int pvh_gen, md_gen;
8199 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8200 ("pmap_remove_write: page %p is not managed", m));
8202 vm_page_assert_busied(m);
8203 if (!pmap_page_is_write_mapped(m))
8206 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8207 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8208 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8211 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8213 if (!PMAP_TRYLOCK(pmap)) {
8214 pvh_gen = pvh->pv_gen;
8218 if (pvh_gen != pvh->pv_gen) {
8224 PG_RW = pmap_rw_bit(pmap);
8226 pde = pmap_pde(pmap, va);
8227 if ((*pde & PG_RW) != 0)
8228 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8229 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8230 ("inconsistent pv lock %p %p for page %p",
8231 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8234 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8236 if (!PMAP_TRYLOCK(pmap)) {
8237 pvh_gen = pvh->pv_gen;
8238 md_gen = m->md.pv_gen;
8242 if (pvh_gen != pvh->pv_gen ||
8243 md_gen != m->md.pv_gen) {
8249 PG_M = pmap_modified_bit(pmap);
8250 PG_RW = pmap_rw_bit(pmap);
8251 pde = pmap_pde(pmap, pv->pv_va);
8252 KASSERT((*pde & PG_PS) == 0,
8253 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8255 pte = pmap_pde_to_pte(pde, pv->pv_va);
8258 if (oldpte & PG_RW) {
8259 if (!atomic_cmpset_long(pte, oldpte, oldpte &
8262 if ((oldpte & PG_M) != 0)
8264 pmap_invalidate_page(pmap, pv->pv_va);
8269 vm_page_aflag_clear(m, PGA_WRITEABLE);
8270 pmap_delayed_invl_wait(m);
8273 static __inline boolean_t
8274 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8277 if (!pmap_emulate_ad_bits(pmap))
8280 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8283 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8284 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8285 * if the EPT_PG_WRITE bit is set.
8287 if ((pte & EPT_PG_WRITE) != 0)
8291 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8293 if ((pte & EPT_PG_EXECUTE) == 0 ||
8294 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8301 * pmap_ts_referenced:
8303 * Return a count of reference bits for a page, clearing those bits.
8304 * It is not necessary for every reference bit to be cleared, but it
8305 * is necessary that 0 only be returned when there are truly no
8306 * reference bits set.
8308 * As an optimization, update the page's dirty field if a modified bit is
8309 * found while counting reference bits. This opportunistic update can be
8310 * performed at low cost and can eliminate the need for some future calls
8311 * to pmap_is_modified(). However, since this function stops after
8312 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8313 * dirty pages. Those dirty pages will only be detected by a future call
8314 * to pmap_is_modified().
8316 * A DI block is not needed within this function, because
8317 * invalidations are performed before the PV list lock is
8321 pmap_ts_referenced(vm_page_t m)
8323 struct md_page *pvh;
8326 struct rwlock *lock;
8327 pd_entry_t oldpde, *pde;
8328 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8331 int cleared, md_gen, not_cleared, pvh_gen;
8332 struct spglist free;
8335 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8336 ("pmap_ts_referenced: page %p is not managed", m));
8339 pa = VM_PAGE_TO_PHYS(m);
8340 lock = PHYS_TO_PV_LIST_LOCK(pa);
8341 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8345 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8346 goto small_mappings;
8352 if (!PMAP_TRYLOCK(pmap)) {
8353 pvh_gen = pvh->pv_gen;
8357 if (pvh_gen != pvh->pv_gen) {
8362 PG_A = pmap_accessed_bit(pmap);
8363 PG_M = pmap_modified_bit(pmap);
8364 PG_RW = pmap_rw_bit(pmap);
8366 pde = pmap_pde(pmap, pv->pv_va);
8368 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8370 * Although "oldpde" is mapping a 2MB page, because
8371 * this function is called at a 4KB page granularity,
8372 * we only update the 4KB page under test.
8376 if ((oldpde & PG_A) != 0) {
8378 * Since this reference bit is shared by 512 4KB
8379 * pages, it should not be cleared every time it is
8380 * tested. Apply a simple "hash" function on the
8381 * physical page number, the virtual superpage number,
8382 * and the pmap address to select one 4KB page out of
8383 * the 512 on which testing the reference bit will
8384 * result in clearing that reference bit. This
8385 * function is designed to avoid the selection of the
8386 * same 4KB page for every 2MB page mapping.
8388 * On demotion, a mapping that hasn't been referenced
8389 * is simply destroyed. To avoid the possibility of a
8390 * subsequent page fault on a demoted wired mapping,
8391 * always leave its reference bit set. Moreover,
8392 * since the superpage is wired, the current state of
8393 * its reference bit won't affect page replacement.
8395 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8396 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8397 (oldpde & PG_W) == 0) {
8398 if (safe_to_clear_referenced(pmap, oldpde)) {
8399 atomic_clear_long(pde, PG_A);
8400 pmap_invalidate_page(pmap, pv->pv_va);
8402 } else if (pmap_demote_pde_locked(pmap, pde,
8403 pv->pv_va, &lock)) {
8405 * Remove the mapping to a single page
8406 * so that a subsequent access may
8407 * repromote. Since the underlying
8408 * page table page is fully populated,
8409 * this removal never frees a page
8413 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8415 pte = pmap_pde_to_pte(pde, va);
8416 pmap_remove_pte(pmap, pte, va, *pde,
8418 pmap_invalidate_page(pmap, va);
8424 * The superpage mapping was removed
8425 * entirely and therefore 'pv' is no
8433 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8434 ("inconsistent pv lock %p %p for page %p",
8435 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8440 /* Rotate the PV list if it has more than one entry. */
8441 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8442 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8443 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8446 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8448 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8450 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8457 if (!PMAP_TRYLOCK(pmap)) {
8458 pvh_gen = pvh->pv_gen;
8459 md_gen = m->md.pv_gen;
8463 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8468 PG_A = pmap_accessed_bit(pmap);
8469 PG_M = pmap_modified_bit(pmap);
8470 PG_RW = pmap_rw_bit(pmap);
8471 pde = pmap_pde(pmap, pv->pv_va);
8472 KASSERT((*pde & PG_PS) == 0,
8473 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8475 pte = pmap_pde_to_pte(pde, pv->pv_va);
8476 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8478 if ((*pte & PG_A) != 0) {
8479 if (safe_to_clear_referenced(pmap, *pte)) {
8480 atomic_clear_long(pte, PG_A);
8481 pmap_invalidate_page(pmap, pv->pv_va);
8483 } else if ((*pte & PG_W) == 0) {
8485 * Wired pages cannot be paged out so
8486 * doing accessed bit emulation for
8487 * them is wasted effort. We do the
8488 * hard work for unwired pages only.
8490 pmap_remove_pte(pmap, pte, pv->pv_va,
8491 *pde, &free, &lock);
8492 pmap_invalidate_page(pmap, pv->pv_va);
8497 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8498 ("inconsistent pv lock %p %p for page %p",
8499 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8504 /* Rotate the PV list if it has more than one entry. */
8505 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8506 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8507 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8510 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8511 not_cleared < PMAP_TS_REFERENCED_MAX);
8514 vm_page_free_pages_toq(&free, true);
8515 return (cleared + not_cleared);
8519 * Apply the given advice to the specified range of addresses within the
8520 * given pmap. Depending on the advice, clear the referenced and/or
8521 * modified flags in each mapping and set the mapped page's dirty field.
8524 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8526 struct rwlock *lock;
8527 pml4_entry_t *pml4e;
8529 pd_entry_t oldpde, *pde;
8530 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8531 vm_offset_t va, va_next;
8535 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8539 * A/D bit emulation requires an alternate code path when clearing
8540 * the modified and accessed bits below. Since this function is
8541 * advisory in nature we skip it entirely for pmaps that require
8542 * A/D bit emulation.
8544 if (pmap_emulate_ad_bits(pmap))
8547 PG_A = pmap_accessed_bit(pmap);
8548 PG_G = pmap_global_bit(pmap);
8549 PG_M = pmap_modified_bit(pmap);
8550 PG_V = pmap_valid_bit(pmap);
8551 PG_RW = pmap_rw_bit(pmap);
8553 pmap_delayed_invl_start();
8555 for (; sva < eva; sva = va_next) {
8556 pml4e = pmap_pml4e(pmap, sva);
8557 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8558 va_next = (sva + NBPML4) & ~PML4MASK;
8564 va_next = (sva + NBPDP) & ~PDPMASK;
8567 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8568 if ((*pdpe & PG_V) == 0)
8570 if ((*pdpe & PG_PS) != 0) {
8571 KASSERT(va_next <= eva,
8572 ("partial update of non-transparent 1G mapping "
8573 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8574 *pdpe, sva, eva, va_next));
8578 va_next = (sva + NBPDR) & ~PDRMASK;
8581 pde = pmap_pdpe_to_pde(pdpe, sva);
8583 if ((oldpde & PG_V) == 0)
8585 else if ((oldpde & PG_PS) != 0) {
8586 if ((oldpde & PG_MANAGED) == 0)
8589 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8594 * The large page mapping was destroyed.
8600 * Unless the page mappings are wired, remove the
8601 * mapping to a single page so that a subsequent
8602 * access may repromote. Choosing the last page
8603 * within the address range [sva, min(va_next, eva))
8604 * generally results in more repromotions. Since the
8605 * underlying page table page is fully populated, this
8606 * removal never frees a page table page.
8608 if ((oldpde & PG_W) == 0) {
8614 ("pmap_advise: no address gap"));
8615 pte = pmap_pde_to_pte(pde, va);
8616 KASSERT((*pte & PG_V) != 0,
8617 ("pmap_advise: invalid PTE"));
8618 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8628 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8630 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8632 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8633 if (advice == MADV_DONTNEED) {
8635 * Future calls to pmap_is_modified()
8636 * can be avoided by making the page
8639 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8642 atomic_clear_long(pte, PG_M | PG_A);
8643 } else if ((*pte & PG_A) != 0)
8644 atomic_clear_long(pte, PG_A);
8648 if ((*pte & PG_G) != 0) {
8655 if (va != va_next) {
8656 pmap_invalidate_range(pmap, va, sva);
8661 pmap_invalidate_range(pmap, va, sva);
8664 pmap_invalidate_all(pmap);
8666 pmap_delayed_invl_finish();
8670 * Clear the modify bits on the specified physical page.
8673 pmap_clear_modify(vm_page_t m)
8675 struct md_page *pvh;
8677 pv_entry_t next_pv, pv;
8678 pd_entry_t oldpde, *pde;
8679 pt_entry_t *pte, PG_M, PG_RW;
8680 struct rwlock *lock;
8682 int md_gen, pvh_gen;
8684 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8685 ("pmap_clear_modify: page %p is not managed", m));
8686 vm_page_assert_busied(m);
8688 if (!pmap_page_is_write_mapped(m))
8690 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8691 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8692 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8695 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8697 if (!PMAP_TRYLOCK(pmap)) {
8698 pvh_gen = pvh->pv_gen;
8702 if (pvh_gen != pvh->pv_gen) {
8707 PG_M = pmap_modified_bit(pmap);
8708 PG_RW = pmap_rw_bit(pmap);
8710 pde = pmap_pde(pmap, va);
8712 /* If oldpde has PG_RW set, then it also has PG_M set. */
8713 if ((oldpde & PG_RW) != 0 &&
8714 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8715 (oldpde & PG_W) == 0) {
8717 * Write protect the mapping to a single page so that
8718 * a subsequent write access may repromote.
8720 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8721 pte = pmap_pde_to_pte(pde, va);
8722 atomic_clear_long(pte, PG_M | PG_RW);
8724 pmap_invalidate_page(pmap, va);
8728 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8730 if (!PMAP_TRYLOCK(pmap)) {
8731 md_gen = m->md.pv_gen;
8732 pvh_gen = pvh->pv_gen;
8736 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8741 PG_M = pmap_modified_bit(pmap);
8742 PG_RW = pmap_rw_bit(pmap);
8743 pde = pmap_pde(pmap, pv->pv_va);
8744 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8745 " a 2mpage in page %p's pv list", m));
8746 pte = pmap_pde_to_pte(pde, pv->pv_va);
8747 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8748 atomic_clear_long(pte, PG_M);
8749 pmap_invalidate_page(pmap, pv->pv_va);
8757 * Miscellaneous support routines follow
8760 /* Adjust the properties for a leaf page table entry. */
8761 static __inline void
8762 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8766 opte = *(u_long *)pte;
8768 npte = opte & ~mask;
8770 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8775 * Map a set of physical memory pages into the kernel virtual
8776 * address space. Return a pointer to where it is mapped. This
8777 * routine is intended to be used for mapping device memory,
8781 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8783 struct pmap_preinit_mapping *ppim;
8784 vm_offset_t va, offset;
8788 offset = pa & PAGE_MASK;
8789 size = round_page(offset + size);
8790 pa = trunc_page(pa);
8792 if (!pmap_initialized) {
8794 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8795 ppim = pmap_preinit_mapping + i;
8796 if (ppim->va == 0) {
8800 ppim->va = virtual_avail;
8801 virtual_avail += size;
8807 panic("%s: too many preinit mappings", __func__);
8810 * If we have a preinit mapping, re-use it.
8812 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8813 ppim = pmap_preinit_mapping + i;
8814 if (ppim->pa == pa && ppim->sz == size &&
8815 (ppim->mode == mode ||
8816 (flags & MAPDEV_SETATTR) == 0))
8817 return ((void *)(ppim->va + offset));
8820 * If the specified range of physical addresses fits within
8821 * the direct map window, use the direct map.
8823 if (pa < dmaplimit && pa + size <= dmaplimit) {
8824 va = PHYS_TO_DMAP(pa);
8825 if ((flags & MAPDEV_SETATTR) != 0) {
8826 PMAP_LOCK(kernel_pmap);
8827 i = pmap_change_props_locked(va, size,
8828 PROT_NONE, mode, flags);
8829 PMAP_UNLOCK(kernel_pmap);
8833 return ((void *)(va + offset));
8835 va = kva_alloc(size);
8837 panic("%s: Couldn't allocate KVA", __func__);
8839 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8840 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8841 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8842 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8843 pmap_invalidate_cache_range(va, va + tmpsize);
8844 return ((void *)(va + offset));
8848 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8851 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8856 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8859 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8863 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8866 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8871 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8874 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8875 MAPDEV_FLUSHCACHE));
8879 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8881 struct pmap_preinit_mapping *ppim;
8885 /* If we gave a direct map region in pmap_mapdev, do nothing */
8886 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8888 offset = va & PAGE_MASK;
8889 size = round_page(offset + size);
8890 va = trunc_page(va);
8891 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8892 ppim = pmap_preinit_mapping + i;
8893 if (ppim->va == va && ppim->sz == size) {
8894 if (pmap_initialized)
8900 if (va + size == virtual_avail)
8905 if (pmap_initialized) {
8906 pmap_qremove(va, atop(size));
8912 * Tries to demote a 1GB page mapping.
8915 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8917 pdp_entry_t newpdpe, oldpdpe;
8918 pd_entry_t *firstpde, newpde, *pde;
8919 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8923 PG_A = pmap_accessed_bit(pmap);
8924 PG_M = pmap_modified_bit(pmap);
8925 PG_V = pmap_valid_bit(pmap);
8926 PG_RW = pmap_rw_bit(pmap);
8928 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8930 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8931 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8932 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8933 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8934 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8935 " in pmap %p", va, pmap);
8938 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8939 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8940 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8941 KASSERT((oldpdpe & PG_A) != 0,
8942 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8943 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8944 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8948 * Initialize the page directory page.
8950 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8956 * Demote the mapping.
8961 * Invalidate a stale recursive mapping of the page directory page.
8963 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8965 pmap_pdpe_demotions++;
8966 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8967 " in pmap %p", va, pmap);
8972 * Sets the memory attribute for the specified page.
8975 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8978 m->md.pat_mode = ma;
8981 * If "m" is a normal page, update its direct mapping. This update
8982 * can be relied upon to perform any cache operations that are
8983 * required for data coherence.
8985 if ((m->flags & PG_FICTITIOUS) == 0 &&
8986 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8988 panic("memory attribute change on the direct map failed");
8992 * Changes the specified virtual address range's memory type to that given by
8993 * the parameter "mode". The specified virtual address range must be
8994 * completely contained within either the direct map or the kernel map. If
8995 * the virtual address range is contained within the kernel map, then the
8996 * memory type for each of the corresponding ranges of the direct map is also
8997 * changed. (The corresponding ranges of the direct map are those ranges that
8998 * map the same physical pages as the specified virtual address range.) These
8999 * changes to the direct map are necessary because Intel describes the
9000 * behavior of their processors as "undefined" if two or more mappings to the
9001 * same physical page have different memory types.
9003 * Returns zero if the change completed successfully, and either EINVAL or
9004 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9005 * of the virtual address range was not mapped, and ENOMEM is returned if
9006 * there was insufficient memory available to complete the change. In the
9007 * latter case, the memory type may have been changed on some part of the
9008 * virtual address range or the direct map.
9011 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9015 PMAP_LOCK(kernel_pmap);
9016 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9018 PMAP_UNLOCK(kernel_pmap);
9023 * Changes the specified virtual address range's protections to those
9024 * specified by "prot". Like pmap_change_attr(), protections for aliases
9025 * in the direct map are updated as well. Protections on aliasing mappings may
9026 * be a subset of the requested protections; for example, mappings in the direct
9027 * map are never executable.
9030 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9034 /* Only supported within the kernel map. */
9035 if (va < VM_MIN_KERNEL_ADDRESS)
9038 PMAP_LOCK(kernel_pmap);
9039 error = pmap_change_props_locked(va, size, prot, -1,
9040 MAPDEV_ASSERTVALID);
9041 PMAP_UNLOCK(kernel_pmap);
9046 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9047 int mode, int flags)
9049 vm_offset_t base, offset, tmpva;
9050 vm_paddr_t pa_start, pa_end, pa_end1;
9052 pd_entry_t *pde, pde_bits, pde_mask;
9053 pt_entry_t *pte, pte_bits, pte_mask;
9057 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9058 base = trunc_page(va);
9059 offset = va & PAGE_MASK;
9060 size = round_page(offset + size);
9063 * Only supported on kernel virtual addresses, including the direct
9064 * map but excluding the recursive map.
9066 if (base < DMAP_MIN_ADDRESS)
9070 * Construct our flag sets and masks. "bits" is the subset of
9071 * "mask" that will be set in each modified PTE.
9073 * Mappings in the direct map are never allowed to be executable.
9075 pde_bits = pte_bits = 0;
9076 pde_mask = pte_mask = 0;
9078 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9079 pde_mask |= X86_PG_PDE_CACHE;
9080 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9081 pte_mask |= X86_PG_PTE_CACHE;
9083 if (prot != VM_PROT_NONE) {
9084 if ((prot & VM_PROT_WRITE) != 0) {
9085 pde_bits |= X86_PG_RW;
9086 pte_bits |= X86_PG_RW;
9088 if ((prot & VM_PROT_EXECUTE) == 0 ||
9089 va < VM_MIN_KERNEL_ADDRESS) {
9093 pde_mask |= X86_PG_RW | pg_nx;
9094 pte_mask |= X86_PG_RW | pg_nx;
9098 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9099 * into 4KB pages if required.
9101 for (tmpva = base; tmpva < base + size; ) {
9102 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9103 if (pdpe == NULL || *pdpe == 0) {
9104 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9105 ("%s: addr %#lx is not mapped", __func__, tmpva));
9108 if (*pdpe & PG_PS) {
9110 * If the current 1GB page already has the required
9111 * properties, then we need not demote this page. Just
9112 * increment tmpva to the next 1GB page frame.
9114 if ((*pdpe & pde_mask) == pde_bits) {
9115 tmpva = trunc_1gpage(tmpva) + NBPDP;
9120 * If the current offset aligns with a 1GB page frame
9121 * and there is at least 1GB left within the range, then
9122 * we need not break down this page into 2MB pages.
9124 if ((tmpva & PDPMASK) == 0 &&
9125 tmpva + PDPMASK < base + size) {
9129 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9132 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9134 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9135 ("%s: addr %#lx is not mapped", __func__, tmpva));
9140 * If the current 2MB page already has the required
9141 * properties, then we need not demote this page. Just
9142 * increment tmpva to the next 2MB page frame.
9144 if ((*pde & pde_mask) == pde_bits) {
9145 tmpva = trunc_2mpage(tmpva) + NBPDR;
9150 * If the current offset aligns with a 2MB page frame
9151 * and there is at least 2MB left within the range, then
9152 * we need not break down this page into 4KB pages.
9154 if ((tmpva & PDRMASK) == 0 &&
9155 tmpva + PDRMASK < base + size) {
9159 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9162 pte = pmap_pde_to_pte(pde, tmpva);
9164 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9165 ("%s: addr %#lx is not mapped", __func__, tmpva));
9173 * Ok, all the pages exist, so run through them updating their
9174 * properties if required.
9177 pa_start = pa_end = 0;
9178 for (tmpva = base; tmpva < base + size; ) {
9179 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9180 if (*pdpe & PG_PS) {
9181 if ((*pdpe & pde_mask) != pde_bits) {
9182 pmap_pte_props(pdpe, pde_bits, pde_mask);
9185 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9186 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9187 if (pa_start == pa_end) {
9188 /* Start physical address run. */
9189 pa_start = *pdpe & PG_PS_FRAME;
9190 pa_end = pa_start + NBPDP;
9191 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9194 /* Run ended, update direct map. */
9195 error = pmap_change_props_locked(
9196 PHYS_TO_DMAP(pa_start),
9197 pa_end - pa_start, prot, mode,
9201 /* Start physical address run. */
9202 pa_start = *pdpe & PG_PS_FRAME;
9203 pa_end = pa_start + NBPDP;
9206 tmpva = trunc_1gpage(tmpva) + NBPDP;
9209 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9211 if ((*pde & pde_mask) != pde_bits) {
9212 pmap_pte_props(pde, pde_bits, pde_mask);
9215 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9216 (*pde & PG_PS_FRAME) < dmaplimit) {
9217 if (pa_start == pa_end) {
9218 /* Start physical address run. */
9219 pa_start = *pde & PG_PS_FRAME;
9220 pa_end = pa_start + NBPDR;
9221 } else if (pa_end == (*pde & PG_PS_FRAME))
9224 /* Run ended, update direct map. */
9225 error = pmap_change_props_locked(
9226 PHYS_TO_DMAP(pa_start),
9227 pa_end - pa_start, prot, mode,
9231 /* Start physical address run. */
9232 pa_start = *pde & PG_PS_FRAME;
9233 pa_end = pa_start + NBPDR;
9236 tmpva = trunc_2mpage(tmpva) + NBPDR;
9238 pte = pmap_pde_to_pte(pde, tmpva);
9239 if ((*pte & pte_mask) != pte_bits) {
9240 pmap_pte_props(pte, pte_bits, pte_mask);
9243 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9244 (*pte & PG_FRAME) < dmaplimit) {
9245 if (pa_start == pa_end) {
9246 /* Start physical address run. */
9247 pa_start = *pte & PG_FRAME;
9248 pa_end = pa_start + PAGE_SIZE;
9249 } else if (pa_end == (*pte & PG_FRAME))
9250 pa_end += PAGE_SIZE;
9252 /* Run ended, update direct map. */
9253 error = pmap_change_props_locked(
9254 PHYS_TO_DMAP(pa_start),
9255 pa_end - pa_start, prot, mode,
9259 /* Start physical address run. */
9260 pa_start = *pte & PG_FRAME;
9261 pa_end = pa_start + PAGE_SIZE;
9267 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9268 pa_end1 = MIN(pa_end, dmaplimit);
9269 if (pa_start != pa_end1)
9270 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9271 pa_end1 - pa_start, prot, mode, flags);
9275 * Flush CPU caches if required to make sure any data isn't cached that
9276 * shouldn't be, etc.
9279 pmap_invalidate_range(kernel_pmap, base, tmpva);
9280 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9281 pmap_invalidate_cache_range(base, tmpva);
9287 * Demotes any mapping within the direct map region that covers more than the
9288 * specified range of physical addresses. This range's size must be a power
9289 * of two and its starting address must be a multiple of its size. Since the
9290 * demotion does not change any attributes of the mapping, a TLB invalidation
9291 * is not mandatory. The caller may, however, request a TLB invalidation.
9294 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9303 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9304 KASSERT((base & (len - 1)) == 0,
9305 ("pmap_demote_DMAP: base is not a multiple of len"));
9306 if (len < NBPDP && base < dmaplimit) {
9307 va = PHYS_TO_DMAP(base);
9309 PMAP_LOCK(kernel_pmap);
9310 pdpe = pmap_pdpe(kernel_pmap, va);
9311 if ((*pdpe & X86_PG_V) == 0)
9312 panic("pmap_demote_DMAP: invalid PDPE");
9313 if ((*pdpe & PG_PS) != 0) {
9314 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9315 panic("pmap_demote_DMAP: PDPE failed");
9319 pde = pmap_pdpe_to_pde(pdpe, va);
9320 if ((*pde & X86_PG_V) == 0)
9321 panic("pmap_demote_DMAP: invalid PDE");
9322 if ((*pde & PG_PS) != 0) {
9323 if (!pmap_demote_pde(kernel_pmap, pde, va))
9324 panic("pmap_demote_DMAP: PDE failed");
9328 if (changed && invalidate)
9329 pmap_invalidate_page(kernel_pmap, va);
9330 PMAP_UNLOCK(kernel_pmap);
9335 * Perform the pmap work for mincore(2). If the page is not both referenced and
9336 * modified by this pmap, returns its physical address so that the caller can
9337 * find other mappings.
9340 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9344 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9348 PG_A = pmap_accessed_bit(pmap);
9349 PG_M = pmap_modified_bit(pmap);
9350 PG_V = pmap_valid_bit(pmap);
9351 PG_RW = pmap_rw_bit(pmap);
9357 pdpe = pmap_pdpe(pmap, addr);
9358 if ((*pdpe & PG_V) != 0) {
9359 if ((*pdpe & PG_PS) != 0) {
9361 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9363 val = MINCORE_PSIND(2);
9365 pdep = pmap_pde(pmap, addr);
9366 if (pdep != NULL && (*pdep & PG_V) != 0) {
9367 if ((*pdep & PG_PS) != 0) {
9369 /* Compute the physical address of the 4KB page. */
9370 pa = ((pte & PG_PS_FRAME) | (addr &
9371 PDRMASK)) & PG_FRAME;
9372 val = MINCORE_PSIND(1);
9374 pte = *pmap_pde_to_pte(pdep, addr);
9375 pa = pte & PG_FRAME;
9381 if ((pte & PG_V) != 0) {
9382 val |= MINCORE_INCORE;
9383 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9384 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9385 if ((pte & PG_A) != 0)
9386 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9388 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9389 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9390 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9398 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9400 uint32_t gen, new_gen, pcid_next;
9402 CRITICAL_ASSERT(curthread);
9403 gen = PCPU_GET(pcid_gen);
9404 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9405 return (pti ? 0 : CR3_PCID_SAVE);
9406 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9407 return (CR3_PCID_SAVE);
9408 pcid_next = PCPU_GET(pcid_next);
9409 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9410 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9411 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9412 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9413 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9417 PCPU_SET(pcid_gen, new_gen);
9418 pcid_next = PMAP_PCID_KERN + 1;
9422 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9423 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9424 PCPU_SET(pcid_next, pcid_next + 1);
9429 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9433 cached = pmap_pcid_alloc(pmap, cpuid);
9434 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9435 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9436 pmap->pm_pcids[cpuid].pm_pcid));
9437 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9438 pmap == kernel_pmap,
9439 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9440 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9445 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9448 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9449 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9453 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9456 uint64_t cached, cr3, kcr3, ucr3;
9458 KASSERT((read_rflags() & PSL_I) == 0,
9459 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9461 /* See the comment in pmap_invalidate_page_pcid(). */
9462 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9463 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9464 old_pmap = PCPU_GET(curpmap);
9465 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9466 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9469 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9471 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9472 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9473 PCPU_SET(curpmap, pmap);
9474 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9475 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9478 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9479 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9481 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9482 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9484 PCPU_INC(pm_save_cnt);
9486 pmap_activate_sw_pti_post(td, pmap);
9490 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9493 uint64_t cached, cr3;
9495 KASSERT((read_rflags() & PSL_I) == 0,
9496 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9498 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9500 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9501 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9503 PCPU_SET(curpmap, pmap);
9505 PCPU_INC(pm_save_cnt);
9509 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9510 u_int cpuid __unused)
9513 load_cr3(pmap->pm_cr3);
9514 PCPU_SET(curpmap, pmap);
9518 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9519 u_int cpuid __unused)
9522 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9523 PCPU_SET(kcr3, pmap->pm_cr3);
9524 PCPU_SET(ucr3, pmap->pm_ucr3);
9525 pmap_activate_sw_pti_post(td, pmap);
9528 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9532 if (pmap_pcid_enabled && pti)
9533 return (pmap_activate_sw_pcid_pti);
9534 else if (pmap_pcid_enabled && !pti)
9535 return (pmap_activate_sw_pcid_nopti);
9536 else if (!pmap_pcid_enabled && pti)
9537 return (pmap_activate_sw_nopcid_pti);
9538 else /* if (!pmap_pcid_enabled && !pti) */
9539 return (pmap_activate_sw_nopcid_nopti);
9543 pmap_activate_sw(struct thread *td)
9545 pmap_t oldpmap, pmap;
9548 oldpmap = PCPU_GET(curpmap);
9549 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9550 if (oldpmap == pmap) {
9551 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9555 cpuid = PCPU_GET(cpuid);
9557 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9559 CPU_SET(cpuid, &pmap->pm_active);
9561 pmap_activate_sw_mode(td, pmap, cpuid);
9563 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9565 CPU_CLR(cpuid, &oldpmap->pm_active);
9570 pmap_activate(struct thread *td)
9573 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9574 * invalidate_all IPI, which checks for curpmap ==
9575 * smp_tlb_pmap. The below sequence of operations has a
9576 * window where %CR3 is loaded with the new pmap's PML4
9577 * address, but the curpmap value has not yet been updated.
9578 * This causes the invltlb IPI handler, which is called
9579 * between the updates, to execute as a NOP, which leaves
9580 * stale TLB entries.
9582 * Note that the most common use of pmap_activate_sw(), from
9583 * a context switch, is immune to this race, because
9584 * interrupts are disabled (while the thread lock is owned),
9585 * so the IPI is delayed until after curpmap is updated. Protect
9586 * other callers in a similar way, by disabling interrupts
9587 * around the %cr3 register reload and curpmap assignment.
9590 pmap_activate_sw(td);
9595 pmap_activate_boot(pmap_t pmap)
9601 * kernel_pmap must be never deactivated, and we ensure that
9602 * by never activating it at all.
9604 MPASS(pmap != kernel_pmap);
9606 cpuid = PCPU_GET(cpuid);
9608 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9610 CPU_SET(cpuid, &pmap->pm_active);
9612 PCPU_SET(curpmap, pmap);
9614 kcr3 = pmap->pm_cr3;
9615 if (pmap_pcid_enabled)
9616 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9620 PCPU_SET(kcr3, kcr3);
9621 PCPU_SET(ucr3, PMAP_NO_CR3);
9625 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9630 * Increase the starting virtual address of the given mapping if a
9631 * different alignment might result in more superpage mappings.
9634 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9635 vm_offset_t *addr, vm_size_t size)
9637 vm_offset_t superpage_offset;
9641 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9642 offset += ptoa(object->pg_color);
9643 superpage_offset = offset & PDRMASK;
9644 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9645 (*addr & PDRMASK) == superpage_offset)
9647 if ((*addr & PDRMASK) < superpage_offset)
9648 *addr = (*addr & ~PDRMASK) + superpage_offset;
9650 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9654 static unsigned long num_dirty_emulations;
9655 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9656 &num_dirty_emulations, 0, NULL);
9658 static unsigned long num_accessed_emulations;
9659 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9660 &num_accessed_emulations, 0, NULL);
9662 static unsigned long num_superpage_accessed_emulations;
9663 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9664 &num_superpage_accessed_emulations, 0, NULL);
9666 static unsigned long ad_emulation_superpage_promotions;
9667 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9668 &ad_emulation_superpage_promotions, 0, NULL);
9669 #endif /* INVARIANTS */
9672 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9675 struct rwlock *lock;
9676 #if VM_NRESERVLEVEL > 0
9680 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9682 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9683 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9685 if (!pmap_emulate_ad_bits(pmap))
9688 PG_A = pmap_accessed_bit(pmap);
9689 PG_M = pmap_modified_bit(pmap);
9690 PG_V = pmap_valid_bit(pmap);
9691 PG_RW = pmap_rw_bit(pmap);
9697 pde = pmap_pde(pmap, va);
9698 if (pde == NULL || (*pde & PG_V) == 0)
9701 if ((*pde & PG_PS) != 0) {
9702 if (ftype == VM_PROT_READ) {
9704 atomic_add_long(&num_superpage_accessed_emulations, 1);
9712 pte = pmap_pde_to_pte(pde, va);
9713 if ((*pte & PG_V) == 0)
9716 if (ftype == VM_PROT_WRITE) {
9717 if ((*pte & PG_RW) == 0)
9720 * Set the modified and accessed bits simultaneously.
9722 * Intel EPT PTEs that do software emulation of A/D bits map
9723 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9724 * An EPT misconfiguration is triggered if the PTE is writable
9725 * but not readable (WR=10). This is avoided by setting PG_A
9726 * and PG_M simultaneously.
9728 *pte |= PG_M | PG_A;
9733 #if VM_NRESERVLEVEL > 0
9734 /* try to promote the mapping */
9735 if (va < VM_MAXUSER_ADDRESS)
9736 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9740 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9742 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9743 pmap_ps_enabled(pmap) &&
9744 (m->flags & PG_FICTITIOUS) == 0 &&
9745 vm_reserv_level_iffullpop(m) == 0) {
9746 pmap_promote_pde(pmap, pde, va, &lock);
9748 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9754 if (ftype == VM_PROT_WRITE)
9755 atomic_add_long(&num_dirty_emulations, 1);
9757 atomic_add_long(&num_accessed_emulations, 1);
9759 rv = 0; /* success */
9768 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9773 pt_entry_t *pte, PG_V;
9777 PG_V = pmap_valid_bit(pmap);
9780 pml4 = pmap_pml4e(pmap, va);
9784 if ((*pml4 & PG_V) == 0)
9787 pdp = pmap_pml4e_to_pdpe(pml4, va);
9789 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9792 pde = pmap_pdpe_to_pde(pdp, va);
9794 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9797 pte = pmap_pde_to_pte(pde, va);
9806 * Get the kernel virtual address of a set of physical pages. If there are
9807 * physical addresses not covered by the DMAP perform a transient mapping
9808 * that will be removed when calling pmap_unmap_io_transient.
9810 * \param page The pages the caller wishes to obtain the virtual
9811 * address on the kernel memory map.
9812 * \param vaddr On return contains the kernel virtual memory address
9813 * of the pages passed in the page parameter.
9814 * \param count Number of pages passed in.
9815 * \param can_fault TRUE if the thread using the mapped pages can take
9816 * page faults, FALSE otherwise.
9818 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9819 * finished or FALSE otherwise.
9823 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9824 boolean_t can_fault)
9827 boolean_t needs_mapping;
9829 int cache_bits, error __unused, i;
9832 * Allocate any KVA space that we need, this is done in a separate
9833 * loop to prevent calling vmem_alloc while pinned.
9835 needs_mapping = FALSE;
9836 for (i = 0; i < count; i++) {
9837 paddr = VM_PAGE_TO_PHYS(page[i]);
9838 if (__predict_false(paddr >= dmaplimit)) {
9839 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9840 M_BESTFIT | M_WAITOK, &vaddr[i]);
9841 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9842 needs_mapping = TRUE;
9844 vaddr[i] = PHYS_TO_DMAP(paddr);
9848 /* Exit early if everything is covered by the DMAP */
9853 * NB: The sequence of updating a page table followed by accesses
9854 * to the corresponding pages used in the !DMAP case is subject to
9855 * the situation described in the "AMD64 Architecture Programmer's
9856 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9857 * Coherency Considerations". Therefore, issuing the INVLPG right
9858 * after modifying the PTE bits is crucial.
9862 for (i = 0; i < count; i++) {
9863 paddr = VM_PAGE_TO_PHYS(page[i]);
9864 if (paddr >= dmaplimit) {
9867 * Slow path, since we can get page faults
9868 * while mappings are active don't pin the
9869 * thread to the CPU and instead add a global
9870 * mapping visible to all CPUs.
9872 pmap_qenter(vaddr[i], &page[i], 1);
9874 pte = vtopte(vaddr[i]);
9875 cache_bits = pmap_cache_bits(kernel_pmap,
9876 page[i]->md.pat_mode, 0);
9877 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9884 return (needs_mapping);
9888 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9889 boolean_t can_fault)
9896 for (i = 0; i < count; i++) {
9897 paddr = VM_PAGE_TO_PHYS(page[i]);
9898 if (paddr >= dmaplimit) {
9900 pmap_qremove(vaddr[i], 1);
9901 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9907 pmap_quick_enter_page(vm_page_t m)
9911 paddr = VM_PAGE_TO_PHYS(m);
9912 if (paddr < dmaplimit)
9913 return (PHYS_TO_DMAP(paddr));
9914 mtx_lock_spin(&qframe_mtx);
9915 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9916 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9917 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9922 pmap_quick_remove_page(vm_offset_t addr)
9927 pte_store(vtopte(qframe), 0);
9929 mtx_unlock_spin(&qframe_mtx);
9933 * Pdp pages from the large map are managed differently from either
9934 * kernel or user page table pages. They are permanently allocated at
9935 * initialization time, and their reference count is permanently set to
9936 * zero. The pml4 entries pointing to those pages are copied into
9937 * each allocated pmap.
9939 * In contrast, pd and pt pages are managed like user page table
9940 * pages. They are dynamically allocated, and their reference count
9941 * represents the number of valid entries within the page.
9944 pmap_large_map_getptp_unlocked(void)
9948 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9950 if (m != NULL && (m->flags & PG_ZERO) == 0)
9956 pmap_large_map_getptp(void)
9960 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9961 m = pmap_large_map_getptp_unlocked();
9963 PMAP_UNLOCK(kernel_pmap);
9965 PMAP_LOCK(kernel_pmap);
9966 /* Callers retry. */
9971 static pdp_entry_t *
9972 pmap_large_map_pdpe(vm_offset_t va)
9974 vm_pindex_t pml4_idx;
9977 pml4_idx = pmap_pml4e_index(va);
9978 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9979 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9981 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9982 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
9983 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9984 "LMSPML4I %#jx lm_ents %d",
9985 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9986 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
9987 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9991 pmap_large_map_pde(vm_offset_t va)
9998 pdpe = pmap_large_map_pdpe(va);
10000 m = pmap_large_map_getptp();
10003 mphys = VM_PAGE_TO_PHYS(m);
10004 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10006 MPASS((*pdpe & X86_PG_PS) == 0);
10007 mphys = *pdpe & PG_FRAME;
10009 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10012 static pt_entry_t *
10013 pmap_large_map_pte(vm_offset_t va)
10020 pde = pmap_large_map_pde(va);
10022 m = pmap_large_map_getptp();
10025 mphys = VM_PAGE_TO_PHYS(m);
10026 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10027 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10029 MPASS((*pde & X86_PG_PS) == 0);
10030 mphys = *pde & PG_FRAME;
10032 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10036 pmap_large_map_kextract(vm_offset_t va)
10038 pdp_entry_t *pdpe, pdp;
10039 pd_entry_t *pde, pd;
10040 pt_entry_t *pte, pt;
10042 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10043 ("not largemap range %#lx", (u_long)va));
10044 pdpe = pmap_large_map_pdpe(va);
10046 KASSERT((pdp & X86_PG_V) != 0,
10047 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10048 (u_long)pdpe, pdp));
10049 if ((pdp & X86_PG_PS) != 0) {
10050 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10051 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10052 (u_long)pdpe, pdp));
10053 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10055 pde = pmap_pdpe_to_pde(pdpe, va);
10057 KASSERT((pd & X86_PG_V) != 0,
10058 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10059 if ((pd & X86_PG_PS) != 0)
10060 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10061 pte = pmap_pde_to_pte(pde, va);
10063 KASSERT((pt & X86_PG_V) != 0,
10064 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10065 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10069 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10070 vmem_addr_t *vmem_res)
10074 * Large mappings are all but static. Consequently, there
10075 * is no point in waiting for an earlier allocation to be
10078 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10079 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10083 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10084 vm_memattr_t mattr)
10089 vm_offset_t va, inc;
10090 vmem_addr_t vmem_res;
10094 if (len == 0 || spa + len < spa)
10097 /* See if DMAP can serve. */
10098 if (spa + len <= dmaplimit) {
10099 va = PHYS_TO_DMAP(spa);
10100 *addr = (void *)va;
10101 return (pmap_change_attr(va, len, mattr));
10105 * No, allocate KVA. Fit the address with best possible
10106 * alignment for superpages. Fall back to worse align if
10110 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10111 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10112 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10114 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10116 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10119 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10124 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10125 * in the pagetable to minimize flushing. No need to
10126 * invalidate TLB, since we only update invalid entries.
10128 PMAP_LOCK(kernel_pmap);
10129 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10131 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10132 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10133 pdpe = pmap_large_map_pdpe(va);
10135 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10136 X86_PG_V | X86_PG_A | pg_nx |
10137 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10139 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10140 (va & PDRMASK) == 0) {
10141 pde = pmap_large_map_pde(va);
10143 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10144 X86_PG_V | X86_PG_A | pg_nx |
10145 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10146 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10150 pte = pmap_large_map_pte(va);
10152 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10153 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10155 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10160 PMAP_UNLOCK(kernel_pmap);
10163 *addr = (void *)vmem_res;
10168 pmap_large_unmap(void *svaa, vm_size_t len)
10170 vm_offset_t sva, va;
10172 pdp_entry_t *pdpe, pdp;
10173 pd_entry_t *pde, pd;
10176 struct spglist spgf;
10178 sva = (vm_offset_t)svaa;
10179 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10180 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10184 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10185 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10186 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10187 PMAP_LOCK(kernel_pmap);
10188 for (va = sva; va < sva + len; va += inc) {
10189 pdpe = pmap_large_map_pdpe(va);
10191 KASSERT((pdp & X86_PG_V) != 0,
10192 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10193 (u_long)pdpe, pdp));
10194 if ((pdp & X86_PG_PS) != 0) {
10195 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10196 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10197 (u_long)pdpe, pdp));
10198 KASSERT((va & PDPMASK) == 0,
10199 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10200 (u_long)pdpe, pdp));
10201 KASSERT(va + NBPDP <= sva + len,
10202 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10203 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10204 (u_long)pdpe, pdp, len));
10209 pde = pmap_pdpe_to_pde(pdpe, va);
10211 KASSERT((pd & X86_PG_V) != 0,
10212 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10214 if ((pd & X86_PG_PS) != 0) {
10215 KASSERT((va & PDRMASK) == 0,
10216 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10218 KASSERT(va + NBPDR <= sva + len,
10219 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10220 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10224 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10226 if (m->ref_count == 0) {
10228 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10232 pte = pmap_pde_to_pte(pde, va);
10233 KASSERT((*pte & X86_PG_V) != 0,
10234 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10235 (u_long)pte, *pte));
10238 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10240 if (m->ref_count == 0) {
10242 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10243 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10245 if (m->ref_count == 0) {
10247 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10251 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10252 PMAP_UNLOCK(kernel_pmap);
10253 vm_page_free_pages_toq(&spgf, false);
10254 vmem_free(large_vmem, sva, len);
10258 pmap_large_map_wb_fence_mfence(void)
10265 pmap_large_map_wb_fence_atomic(void)
10268 atomic_thread_fence_seq_cst();
10272 pmap_large_map_wb_fence_nop(void)
10276 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10279 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10280 return (pmap_large_map_wb_fence_mfence);
10281 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10282 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10283 return (pmap_large_map_wb_fence_atomic);
10285 /* clflush is strongly enough ordered */
10286 return (pmap_large_map_wb_fence_nop);
10290 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10293 for (; len > 0; len -= cpu_clflush_line_size,
10294 va += cpu_clflush_line_size)
10299 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10302 for (; len > 0; len -= cpu_clflush_line_size,
10303 va += cpu_clflush_line_size)
10308 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10311 for (; len > 0; len -= cpu_clflush_line_size,
10312 va += cpu_clflush_line_size)
10317 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10321 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10324 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10325 return (pmap_large_map_flush_range_clwb);
10326 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10327 return (pmap_large_map_flush_range_clflushopt);
10328 else if ((cpu_feature & CPUID_CLFSH) != 0)
10329 return (pmap_large_map_flush_range_clflush);
10331 return (pmap_large_map_flush_range_nop);
10335 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10337 volatile u_long *pe;
10343 for (va = sva; va < eva; va += inc) {
10345 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10346 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10348 if ((p & X86_PG_PS) != 0)
10352 pe = (volatile u_long *)pmap_large_map_pde(va);
10354 if ((p & X86_PG_PS) != 0)
10358 pe = (volatile u_long *)pmap_large_map_pte(va);
10362 seen_other = false;
10364 if ((p & X86_PG_AVAIL1) != 0) {
10366 * Spin-wait for the end of a parallel
10373 * If we saw other write-back
10374 * occuring, we cannot rely on PG_M to
10375 * indicate state of the cache. The
10376 * PG_M bit is cleared before the
10377 * flush to avoid ignoring new writes,
10378 * and writes which are relevant for
10379 * us might happen after.
10385 if ((p & X86_PG_M) != 0 || seen_other) {
10386 if (!atomic_fcmpset_long(pe, &p,
10387 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10389 * If we saw PG_M without
10390 * PG_AVAIL1, and then on the
10391 * next attempt we do not
10392 * observe either PG_M or
10393 * PG_AVAIL1, the other
10394 * write-back started after us
10395 * and finished before us. We
10396 * can rely on it doing our
10400 pmap_large_map_flush_range(va, inc);
10401 atomic_clear_long(pe, X86_PG_AVAIL1);
10410 * Write-back cache lines for the given address range.
10412 * Must be called only on the range or sub-range returned from
10413 * pmap_large_map(). Must not be called on the coalesced ranges.
10415 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10416 * instructions support.
10419 pmap_large_map_wb(void *svap, vm_size_t len)
10421 vm_offset_t eva, sva;
10423 sva = (vm_offset_t)svap;
10425 pmap_large_map_wb_fence();
10426 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10427 pmap_large_map_flush_range(sva, len);
10429 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10430 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10431 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10432 pmap_large_map_wb_large(sva, eva);
10434 pmap_large_map_wb_fence();
10438 pmap_pti_alloc_page(void)
10442 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10443 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10444 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10449 pmap_pti_free_page(vm_page_t m)
10452 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10453 if (!vm_page_unwire_noq(m))
10455 vm_page_free_zero(m);
10460 pmap_pti_init(void)
10469 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10470 VM_OBJECT_WLOCK(pti_obj);
10471 pml4_pg = pmap_pti_alloc_page();
10472 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10473 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10474 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10475 pdpe = pmap_pti_pdpe(va);
10476 pmap_pti_wire_pte(pdpe);
10478 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10479 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10480 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10481 sizeof(struct gate_descriptor) * NIDT, false);
10483 /* Doublefault stack IST 1 */
10484 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10485 pmap_pti_add_kva_locked(va - DBLFAULT_STACK_SIZE, va, false);
10486 /* NMI stack IST 2 */
10487 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10488 pmap_pti_add_kva_locked(va - NMI_STACK_SIZE, va, false);
10489 /* MC# stack IST 3 */
10490 va = __pcpu[i].pc_common_tss.tss_ist3 +
10491 sizeof(struct nmi_pcpu);
10492 pmap_pti_add_kva_locked(va - MCE_STACK_SIZE, va, false);
10493 /* DB# stack IST 4 */
10494 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10495 pmap_pti_add_kva_locked(va - DBG_STACK_SIZE, va, false);
10497 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
10498 (vm_offset_t)etext, true);
10499 pti_finalized = true;
10500 VM_OBJECT_WUNLOCK(pti_obj);
10502 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10504 static pdp_entry_t *
10505 pmap_pti_pdpe(vm_offset_t va)
10507 pml4_entry_t *pml4e;
10510 vm_pindex_t pml4_idx;
10513 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10515 pml4_idx = pmap_pml4e_index(va);
10516 pml4e = &pti_pml4[pml4_idx];
10520 panic("pml4 alloc after finalization\n");
10521 m = pmap_pti_alloc_page();
10523 pmap_pti_free_page(m);
10524 mphys = *pml4e & ~PAGE_MASK;
10526 mphys = VM_PAGE_TO_PHYS(m);
10527 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10530 mphys = *pml4e & ~PAGE_MASK;
10532 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10537 pmap_pti_wire_pte(void *pte)
10541 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10542 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10547 pmap_pti_unwire_pde(void *pde, bool only_ref)
10551 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10552 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10553 MPASS(m->ref_count > 0);
10554 MPASS(only_ref || m->ref_count > 1);
10555 pmap_pti_free_page(m);
10559 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10564 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10565 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10566 MPASS(m->ref_count > 0);
10567 if (pmap_pti_free_page(m)) {
10568 pde = pmap_pti_pde(va);
10569 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10571 pmap_pti_unwire_pde(pde, false);
10575 static pd_entry_t *
10576 pmap_pti_pde(vm_offset_t va)
10581 vm_pindex_t pd_idx;
10584 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10586 pdpe = pmap_pti_pdpe(va);
10588 m = pmap_pti_alloc_page();
10590 pmap_pti_free_page(m);
10591 MPASS((*pdpe & X86_PG_PS) == 0);
10592 mphys = *pdpe & ~PAGE_MASK;
10594 mphys = VM_PAGE_TO_PHYS(m);
10595 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10598 MPASS((*pdpe & X86_PG_PS) == 0);
10599 mphys = *pdpe & ~PAGE_MASK;
10602 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10603 pd_idx = pmap_pde_index(va);
10608 static pt_entry_t *
10609 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10616 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10618 pde = pmap_pti_pde(va);
10619 if (unwire_pde != NULL) {
10620 *unwire_pde = true;
10621 pmap_pti_wire_pte(pde);
10624 m = pmap_pti_alloc_page();
10626 pmap_pti_free_page(m);
10627 MPASS((*pde & X86_PG_PS) == 0);
10628 mphys = *pde & ~(PAGE_MASK | pg_nx);
10630 mphys = VM_PAGE_TO_PHYS(m);
10631 *pde = mphys | X86_PG_RW | X86_PG_V;
10632 if (unwire_pde != NULL)
10633 *unwire_pde = false;
10636 MPASS((*pde & X86_PG_PS) == 0);
10637 mphys = *pde & ~(PAGE_MASK | pg_nx);
10640 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10641 pte += pmap_pte_index(va);
10647 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10651 pt_entry_t *pte, ptev;
10654 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10656 sva = trunc_page(sva);
10657 MPASS(sva > VM_MAXUSER_ADDRESS);
10658 eva = round_page(eva);
10660 for (; sva < eva; sva += PAGE_SIZE) {
10661 pte = pmap_pti_pte(sva, &unwire_pde);
10662 pa = pmap_kextract(sva);
10663 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10664 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10665 VM_MEMATTR_DEFAULT, FALSE);
10667 pte_store(pte, ptev);
10668 pmap_pti_wire_pte(pte);
10670 KASSERT(!pti_finalized,
10671 ("pti overlap after fin %#lx %#lx %#lx",
10673 KASSERT(*pte == ptev,
10674 ("pti non-identical pte after fin %#lx %#lx %#lx",
10678 pde = pmap_pti_pde(sva);
10679 pmap_pti_unwire_pde(pde, true);
10685 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10690 VM_OBJECT_WLOCK(pti_obj);
10691 pmap_pti_add_kva_locked(sva, eva, exec);
10692 VM_OBJECT_WUNLOCK(pti_obj);
10696 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10703 sva = rounddown2(sva, PAGE_SIZE);
10704 MPASS(sva > VM_MAXUSER_ADDRESS);
10705 eva = roundup2(eva, PAGE_SIZE);
10707 VM_OBJECT_WLOCK(pti_obj);
10708 for (va = sva; va < eva; va += PAGE_SIZE) {
10709 pte = pmap_pti_pte(va, NULL);
10710 KASSERT((*pte & X86_PG_V) != 0,
10711 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10712 (u_long)pte, *pte));
10714 pmap_pti_unwire_pte(pte, va);
10716 pmap_invalidate_range(kernel_pmap, sva, eva);
10717 VM_OBJECT_WUNLOCK(pti_obj);
10721 pkru_dup_range(void *ctx __unused, void *data)
10723 struct pmap_pkru_range *node, *new_node;
10725 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10726 if (new_node == NULL)
10729 memcpy(new_node, node, sizeof(*node));
10734 pkru_free_range(void *ctx __unused, void *node)
10737 uma_zfree(pmap_pkru_ranges_zone, node);
10741 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10744 struct pmap_pkru_range *ppr;
10747 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10748 MPASS(pmap->pm_type == PT_X86);
10749 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10750 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10751 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10753 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10756 ppr->pkru_keyidx = keyidx;
10757 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10758 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10760 uma_zfree(pmap_pkru_ranges_zone, ppr);
10765 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10768 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10769 MPASS(pmap->pm_type == PT_X86);
10770 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10771 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10775 pmap_pkru_deassign_all(pmap_t pmap)
10778 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10779 if (pmap->pm_type == PT_X86 &&
10780 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10781 rangeset_remove_all(&pmap->pm_pkru);
10785 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10787 struct pmap_pkru_range *ppr, *prev_ppr;
10790 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10791 if (pmap->pm_type != PT_X86 ||
10792 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10793 sva >= VM_MAXUSER_ADDRESS)
10795 MPASS(eva <= VM_MAXUSER_ADDRESS);
10796 for (va = sva; va < eva; prev_ppr = ppr) {
10797 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10800 else if ((ppr == NULL) ^ (prev_ppr == NULL))
10806 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10808 va = ppr->pkru_rs_el.re_end;
10814 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10816 struct pmap_pkru_range *ppr;
10818 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10819 if (pmap->pm_type != PT_X86 ||
10820 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10821 va >= VM_MAXUSER_ADDRESS)
10823 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10825 return (X86_PG_PKU(ppr->pkru_keyidx));
10830 pred_pkru_on_remove(void *ctx __unused, void *r)
10832 struct pmap_pkru_range *ppr;
10835 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10839 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10842 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10843 if (pmap->pm_type == PT_X86 &&
10844 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10845 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10846 pred_pkru_on_remove);
10851 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10854 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10855 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10856 MPASS(dst_pmap->pm_type == PT_X86);
10857 MPASS(src_pmap->pm_type == PT_X86);
10858 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10859 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10861 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10865 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10868 pml4_entry_t *pml4e;
10870 pd_entry_t newpde, ptpaddr, *pde;
10871 pt_entry_t newpte, *ptep, pte;
10872 vm_offset_t va, va_next;
10875 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10876 MPASS(pmap->pm_type == PT_X86);
10877 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10879 for (changed = false, va = sva; va < eva; va = va_next) {
10880 pml4e = pmap_pml4e(pmap, va);
10881 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
10882 va_next = (va + NBPML4) & ~PML4MASK;
10888 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10889 if ((*pdpe & X86_PG_V) == 0) {
10890 va_next = (va + NBPDP) & ~PDPMASK;
10896 va_next = (va + NBPDR) & ~PDRMASK;
10900 pde = pmap_pdpe_to_pde(pdpe, va);
10905 MPASS((ptpaddr & X86_PG_V) != 0);
10906 if ((ptpaddr & PG_PS) != 0) {
10907 if (va + NBPDR == va_next && eva >= va_next) {
10908 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10909 X86_PG_PKU(keyidx);
10910 if (newpde != ptpaddr) {
10915 } else if (!pmap_demote_pde(pmap, pde, va)) {
10923 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10924 ptep++, va += PAGE_SIZE) {
10926 if ((pte & X86_PG_V) == 0)
10928 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10929 if (newpte != pte) {
10936 pmap_invalidate_range(pmap, sva, eva);
10940 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10941 u_int keyidx, int flags)
10944 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10945 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10947 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10949 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10955 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10960 sva = trunc_page(sva);
10961 eva = round_page(eva);
10962 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10967 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10969 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10971 if (error != ENOMEM)
10979 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10983 sva = trunc_page(sva);
10984 eva = round_page(eva);
10985 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10990 error = pmap_pkru_deassign(pmap, sva, eva);
10992 pmap_pkru_update_range(pmap, sva, eva, 0);
10994 if (error != ENOMEM)
11002 * Track a range of the kernel's virtual address space that is contiguous
11003 * in various mapping attributes.
11005 struct pmap_kernel_map_range {
11014 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11020 if (eva <= range->sva)
11023 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11024 for (i = 0; i < PAT_INDEX_SIZE; i++)
11025 if (pat_index[i] == pat_idx)
11029 case PAT_WRITE_BACK:
11032 case PAT_WRITE_THROUGH:
11035 case PAT_UNCACHEABLE:
11041 case PAT_WRITE_PROTECTED:
11044 case PAT_WRITE_COMBINING:
11048 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11049 __func__, pat_idx, range->sva, eva);
11054 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11056 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11057 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11058 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11059 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11060 mode, range->pdpes, range->pdes, range->ptes);
11062 /* Reset to sentinel value. */
11063 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11064 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11065 NPDEPG - 1, NPTEPG - 1);
11069 * Determine whether the attributes specified by a page table entry match those
11070 * being tracked by the current range. This is not quite as simple as a direct
11071 * flag comparison since some PAT modes have multiple representations.
11074 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11076 pt_entry_t diff, mask;
11078 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11079 diff = (range->attrs ^ attrs) & mask;
11082 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11083 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11084 pmap_pat_index(kernel_pmap, attrs, true))
11090 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11094 memset(range, 0, sizeof(*range));
11096 range->attrs = attrs;
11100 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11101 * those of the current run, dump the address range and its attributes, and
11105 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11106 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11111 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11113 attrs |= pdpe & pg_nx;
11114 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11115 if ((pdpe & PG_PS) != 0) {
11116 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11117 } else if (pde != 0) {
11118 attrs |= pde & pg_nx;
11119 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11121 if ((pde & PG_PS) != 0) {
11122 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11123 } else if (pte != 0) {
11124 attrs |= pte & pg_nx;
11125 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11126 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11128 /* Canonicalize by always using the PDE PAT bit. */
11129 if ((attrs & X86_PG_PTE_PAT) != 0)
11130 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11133 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11134 sysctl_kmaps_dump(sb, range, va);
11135 sysctl_kmaps_reinit(range, va, attrs);
11140 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11142 struct pmap_kernel_map_range range;
11143 struct sbuf sbuf, *sb;
11144 pml4_entry_t pml4e;
11145 pdp_entry_t *pdp, pdpe;
11146 pd_entry_t *pd, pde;
11147 pt_entry_t *pt, pte;
11150 int error, i, j, k, l;
11152 error = sysctl_wire_old_buffer(req, 0);
11156 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11158 /* Sentinel value. */
11159 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11160 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11161 NPDEPG - 1, NPTEPG - 1);
11164 * Iterate over the kernel page tables without holding the kernel pmap
11165 * lock. Outside of the large map, kernel page table pages are never
11166 * freed, so at worst we will observe inconsistencies in the output.
11167 * Within the large map, ensure that PDP and PD page addresses are
11168 * valid before descending.
11170 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11173 sbuf_printf(sb, "\nRecursive map:\n");
11176 sbuf_printf(sb, "\nDirect map:\n");
11179 sbuf_printf(sb, "\nKernel map:\n");
11182 sbuf_printf(sb, "\nLarge map:\n");
11186 /* Convert to canonical form. */
11187 if (sva == 1ul << 47)
11191 pml4e = kernel_pml4[i];
11192 if ((pml4e & X86_PG_V) == 0) {
11193 sva = rounddown2(sva, NBPML4);
11194 sysctl_kmaps_dump(sb, &range, sva);
11198 pa = pml4e & PG_FRAME;
11199 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11201 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11203 if ((pdpe & X86_PG_V) == 0) {
11204 sva = rounddown2(sva, NBPDP);
11205 sysctl_kmaps_dump(sb, &range, sva);
11209 pa = pdpe & PG_FRAME;
11210 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11211 vm_phys_paddr_to_vm_page(pa) == NULL)
11213 if ((pdpe & PG_PS) != 0) {
11214 sva = rounddown2(sva, NBPDP);
11215 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11221 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11223 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11225 if ((pde & X86_PG_V) == 0) {
11226 sva = rounddown2(sva, NBPDR);
11227 sysctl_kmaps_dump(sb, &range, sva);
11231 pa = pde & PG_FRAME;
11232 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11233 vm_phys_paddr_to_vm_page(pa) == NULL)
11235 if ((pde & PG_PS) != 0) {
11236 sva = rounddown2(sva, NBPDR);
11237 sysctl_kmaps_check(sb, &range, sva,
11238 pml4e, pdpe, pde, 0);
11243 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11245 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11246 sva += PAGE_SIZE) {
11248 if ((pte & X86_PG_V) == 0) {
11249 sysctl_kmaps_dump(sb, &range,
11253 sysctl_kmaps_check(sb, &range, sva,
11254 pml4e, pdpe, pde, pte);
11261 error = sbuf_finish(sb);
11265 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11266 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
11267 NULL, 0, sysctl_kmaps, "A",
11268 "Dump kernel address layout");
11271 DB_SHOW_COMMAND(pte, pmap_print_pte)
11274 pml5_entry_t *pml5;
11275 pml4_entry_t *pml4;
11278 pt_entry_t *pte, PG_V;
11282 db_printf("show pte addr\n");
11285 va = (vm_offset_t)addr;
11287 if (kdb_thread != NULL)
11288 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11290 pmap = PCPU_GET(curpmap);
11292 PG_V = pmap_valid_bit(pmap);
11293 db_printf("VA 0x%016lx", va);
11295 if (pmap_is_la57(pmap)) {
11296 pml5 = pmap_pml5e(pmap, va);
11297 db_printf(" pml5e 0x%016lx", *pml5);
11298 if ((*pml5 & PG_V) == 0) {
11302 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11304 pml4 = pmap_pml4e(pmap, va);
11306 db_printf(" pml4e 0x%016lx", *pml4);
11307 if ((*pml4 & PG_V) == 0) {
11311 pdp = pmap_pml4e_to_pdpe(pml4, va);
11312 db_printf(" pdpe 0x%016lx", *pdp);
11313 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11317 pde = pmap_pdpe_to_pde(pdp, va);
11318 db_printf(" pde 0x%016lx", *pde);
11319 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11323 pte = pmap_pde_to_pte(pde, va);
11324 db_printf(" pte 0x%016lx\n", *pte);
11327 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11332 a = (vm_paddr_t)addr;
11333 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11335 db_printf("show phys2dmap addr\n");
11340 ptpages_show_page(int level, int idx, vm_page_t pg)
11342 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11343 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11347 ptpages_show_complain(int level, int idx, uint64_t pte)
11349 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11353 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11355 vm_page_t pg3, pg2, pg1;
11356 pml4_entry_t *pml4;
11361 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11362 for (i4 = 0; i4 < num_entries; i4++) {
11363 if ((pml4[i4] & PG_V) == 0)
11365 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11367 ptpages_show_complain(3, i4, pml4[i4]);
11370 ptpages_show_page(3, i4, pg3);
11371 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11372 for (i3 = 0; i3 < NPDPEPG; i3++) {
11373 if ((pdp[i3] & PG_V) == 0)
11375 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11377 ptpages_show_complain(2, i3, pdp[i3]);
11380 ptpages_show_page(2, i3, pg2);
11381 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11382 for (i2 = 0; i2 < NPDEPG; i2++) {
11383 if ((pd[i2] & PG_V) == 0)
11385 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11387 ptpages_show_complain(1, i2, pd[i2]);
11390 ptpages_show_page(1, i2, pg1);
11396 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11400 pml5_entry_t *pml5;
11405 pmap = (pmap_t)addr;
11407 pmap = PCPU_GET(curpmap);
11409 PG_V = pmap_valid_bit(pmap);
11411 if (pmap_is_la57(pmap)) {
11412 pml5 = pmap->pm_pmltop;
11413 for (i5 = 0; i5 < NUPML5E; i5++) {
11414 if ((pml5[i5] & PG_V) == 0)
11416 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11418 ptpages_show_complain(4, i5, pml5[i5]);
11421 ptpages_show_page(4, i5, pg);
11422 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11425 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11426 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);