2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
6 * This code is derived from software written for Brini by Mark Brinicombe
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * RiscBSD kernel project
39 * Machine dependant functions for kernel setup
41 * This file needs a lot of work.
46 #include <sys/cdefs.h>
47 __FBSDID("$FreeBSD$");
49 #define _ARM32_BUS_DMA_PRIVATE
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/sysproto.h>
53 #include <sys/signalvar.h>
54 #include <sys/imgact.h>
55 #include <sys/kernel.h>
57 #include <sys/linker.h>
59 #include <sys/malloc.h>
60 #include <sys/mutex.h>
63 #include <sys/ptrace.h>
70 #include <sys/msgbuf.h>
71 #include <machine/reg.h>
72 #include <machine/cpu.h>
73 #include <machine/board.h>
77 #include <vm/vm_object.h>
78 #include <vm/vm_page.h>
79 #include <vm/vm_map.h>
80 #include <machine/vmparam.h>
81 #include <machine/pcb.h>
82 #include <machine/undefined.h>
83 #include <machine/machdep.h>
84 #include <machine/metadata.h>
85 #include <machine/armreg.h>
86 #include <machine/bus.h>
87 #include <sys/reboot.h>
89 #include <arm/at91/at91board.h>
90 #include <arm/at91/at91var.h>
91 #include <arm/at91/at91soc.h>
92 #include <arm/at91/at91_usartreg.h>
93 #include <arm/at91/at91rm92reg.h>
94 #include <arm/at91/at91sam9g20reg.h>
95 #include <arm/at91/at91sam9g45reg.h>
101 /* Page table for mapping proc0 zero page */
102 #define KERNEL_PT_SYS 0
103 #define KERNEL_PT_KERN 1
104 #define KERNEL_PT_KERN_NUM 22
105 /* L2 table for mapping after kernel */
106 #define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
107 #define KERNEL_PT_AFKERNEL_NUM 5
109 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
110 #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
112 extern u_int data_abort_handler_address;
113 extern u_int prefetch_abort_handler_address;
114 extern u_int undefined_handler_address;
116 struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
118 /* Physical and virtual addresses for some global pages */
120 vm_paddr_t phys_avail[10];
121 vm_paddr_t dump_avail[4];
123 struct pv_addr systempage;
124 struct pv_addr msgbufpv;
125 struct pv_addr irqstack;
126 struct pv_addr undstack;
127 struct pv_addr abtstack;
128 struct pv_addr kernelstack;
130 /* Static device mappings. */
131 const struct pmap_devmap at91_devmap[] = {
133 * Map the on-board devices VA == PA so that we can access them
134 * with the MMU on or off.
138 * This at least maps the interrupt controller, the UART
139 * and the timer. Other devices should use newbus to
140 * map their memory anyway.
145 VM_PROT_READ|VM_PROT_WRITE,
149 * We can't just map the OHCI registers VA == PA, because
150 * AT91xx_xxx_BASE belongs to the userland address space.
151 * We could just choose a different virtual address, but a better
152 * solution would probably be to just use pmap_mapdev() to allocate
153 * KVA, as we don't need the OHCI controller before the vm
154 * initialization is done. However, the AT91 resource allocation
155 * system doesn't know how to use pmap_mapdev() yet.
156 * Care must be taken to ensure PA and VM address do not overlap
161 * Add the ohci controller, and anything else that might be
162 * on this chip select for a VA/PA mapping.
164 /* Internal Memory 1MB */
166 AT91RM92_OHCI_PA_BASE,
168 VM_PROT_READ|VM_PROT_WRITE,
172 /* CompactFlash controller. Portion of EBI CS4 1MB */
176 VM_PROT_READ|VM_PROT_WRITE,
180 * The next two should be good for the 9260, 9261 and 9G20 since
181 * addresses mapping is the same.
184 /* Internal Memory 1MB */
185 AT91SAM9G20_OHCI_BASE,
186 AT91SAM9G20_OHCI_PA_BASE,
188 VM_PROT_READ|VM_PROT_WRITE,
193 AT91SAM9G20_NAND_BASE,
194 AT91SAM9G20_NAND_PA_BASE,
195 AT91SAM9G20_NAND_SIZE,
196 VM_PROT_READ|VM_PROT_WRITE,
200 * The next should be good for the 9G45.
203 /* Internal Memory 1MB */
204 AT91SAM9G45_OHCI_BASE,
205 AT91SAM9G45_OHCI_PA_BASE,
207 VM_PROT_READ|VM_PROT_WRITE,
213 #ifdef LINUX_BOOT_ABI
215 extern int memstart[];
216 extern int memsize[];
222 uint32_t cr, mdr, mr, *SDRAMC;
223 int banks, rows, cols, bw;
224 #ifdef LINUX_BOOT_ABI
226 * If we found any ATAGs that were for memory, return the first bank.
232 if (at91_is_rm92()) {
233 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
234 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
235 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
236 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
237 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
238 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
239 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
240 } else if (at91_cpu_is(AT91_T_SAM9G45)) {
241 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE);
242 cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4];
243 mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4];
245 rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11;
246 cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8;
247 bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2;
249 /* Fix the calculation for DDR memory */
250 mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK;
251 if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 ||
252 mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) {
253 /* The cols value is 1 higher for DDR */
255 /* DDR has 4 internal banks. */
260 * This should be good for the 9260, 9261, 9G20, 9G35 and 9X25
261 * as addresses and registers are the same.
263 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
264 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
265 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
266 banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
267 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
268 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
269 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
272 return (1 << (cols + rows + banks + bw));
275 static const char *soc_type_name[] = {
276 [AT91_T_CAP9] = "at91cap9",
277 [AT91_T_RM9200] = "at91rm9200",
278 [AT91_T_SAM9260] = "at91sam9260",
279 [AT91_T_SAM9261] = "at91sam9261",
280 [AT91_T_SAM9263] = "at91sam9263",
281 [AT91_T_SAM9G10] = "at91sam9g10",
282 [AT91_T_SAM9G20] = "at91sam9g20",
283 [AT91_T_SAM9G45] = "at91sam9g45",
284 [AT91_T_SAM9N12] = "at91sam9n12",
285 [AT91_T_SAM9RL] = "at91sam9rl",
286 [AT91_T_SAM9X5] = "at91sam9x5",
287 [AT91_T_NONE] = "UNKNOWN"
290 static const char *soc_subtype_name[] = {
291 [AT91_ST_NONE] = "UNKNOWN",
292 [AT91_ST_RM9200_BGA] = "at91rm9200_bga",
293 [AT91_ST_RM9200_PQFP] = "at91rm9200_pqfp",
294 [AT91_ST_SAM9XE] = "at91sam9xe",
295 [AT91_ST_SAM9G45] = "at91sam9g45",
296 [AT91_ST_SAM9M10] = "at91sam9m10",
297 [AT91_ST_SAM9G46] = "at91sam9g46",
298 [AT91_ST_SAM9M11] = "at91sam9m11",
299 [AT91_ST_SAM9G15] = "at91sam9g15",
300 [AT91_ST_SAM9G25] = "at91sam9g25",
301 [AT91_ST_SAM9G35] = "at91sam9g35",
302 [AT91_ST_SAM9X25] = "at91sam9x25",
303 [AT91_ST_SAM9X35] = "at91sam9x35",
306 struct at91_soc_info soc_info;
309 * Read the SoC ID from the CIDR register and try to match it against the
310 * values we know. If we find a good one, we return true. If not, we
311 * return false. When we find a good one, we also find the subtype
315 at91_try_id(uint32_t dbgu_base)
319 soc_info.cidr = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
321 socid = soc_info.cidr & ~AT91_CPU_VERSION_MASK;
323 soc_info.type = AT91_T_NONE;
324 soc_info.subtype = AT91_ST_NONE;
325 soc_info.family = (soc_info.cidr & AT91_CPU_FAMILY_MASK) >> 20;
326 soc_info.exid = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
331 soc_info.type = AT91_T_CAP9;
333 case AT91_CPU_RM9200:
334 soc_info.type = AT91_T_RM9200;
336 case AT91_CPU_SAM9XE128:
337 case AT91_CPU_SAM9XE256:
338 case AT91_CPU_SAM9XE512:
339 case AT91_CPU_SAM9260:
340 soc_info.type = AT91_T_SAM9260;
341 if (soc_info.family == AT91_FAMILY_SAM9XE)
342 soc_info.subtype = AT91_ST_SAM9XE;
344 case AT91_CPU_SAM9261:
345 soc_info.type = AT91_T_SAM9261;
347 case AT91_CPU_SAM9263:
348 soc_info.type = AT91_T_SAM9263;
350 case AT91_CPU_SAM9G10:
351 soc_info.type = AT91_T_SAM9G10;
353 case AT91_CPU_SAM9G20:
354 soc_info.type = AT91_T_SAM9G20;
356 case AT91_CPU_SAM9G45:
357 soc_info.type = AT91_T_SAM9G45;
359 case AT91_CPU_SAM9N12:
360 soc_info.type = AT91_T_SAM9N12;
362 case AT91_CPU_SAM9RL64:
363 soc_info.type = AT91_T_SAM9RL;
365 case AT91_CPU_SAM9X5:
366 soc_info.type = AT91_T_SAM9X5;
372 switch (soc_info.type) {
374 switch (soc_info.exid) {
375 case AT91_EXID_SAM9G45:
376 soc_info.subtype = AT91_ST_SAM9G45;
378 case AT91_EXID_SAM9G46:
379 soc_info.subtype = AT91_ST_SAM9G46;
381 case AT91_EXID_SAM9M10:
382 soc_info.subtype = AT91_ST_SAM9M10;
384 case AT91_EXID_SAM9M11:
385 soc_info.subtype = AT91_ST_SAM9M11;
390 switch (soc_info.exid) {
391 case AT91_EXID_SAM9G15:
392 soc_info.subtype = AT91_ST_SAM9G15;
394 case AT91_EXID_SAM9G25:
395 soc_info.subtype = AT91_ST_SAM9G25;
397 case AT91_EXID_SAM9G35:
398 soc_info.subtype = AT91_ST_SAM9G35;
400 case AT91_EXID_SAM9X25:
401 soc_info.subtype = AT91_ST_SAM9X25;
403 case AT91_EXID_SAM9X35:
404 soc_info.subtype = AT91_ST_SAM9X35;
412 * Disable interrupts in the DBGU unit...
414 *(volatile uint32_t *)(AT91_BASE + dbgu_base + USART_IDR) = 0xffffffff;
417 * Save the name for later...
419 snprintf(soc_info.name, sizeof(soc_info.name), "%s%s%s",
420 soc_type_name[soc_info.type],
421 soc_info.subtype == AT91_ST_NONE ? "" : " subtype ",
422 soc_info.subtype == AT91_ST_NONE ? "" :
423 soc_subtype_name[soc_info.subtype]);
426 * try to get the matching CPU support.
428 soc_info.soc_data = at91_match_soc(soc_info.type, soc_info.subtype);
429 soc_info.dbgu_base = AT91_BASE + dbgu_base;
438 if (!at91_try_id(AT91_DBGU0))
439 at91_try_id(AT91_DBGU1);
442 #ifdef ARM_MANY_BOARD
443 /* likely belongs in arm/arm/machdep.c, but since board_init is still at91 only... */
444 SET_DECLARE(arm_board_set, const struct arm_board);
446 /* Not yet fully functional, but enough to build ATMEL config */
455 initarm(struct arm_boot_params *abp)
457 struct pv_addr kernel_l1pt;
458 struct pv_addr dpcpu;
461 vm_offset_t freemempos;
462 vm_offset_t afterkern;
464 vm_offset_t lastaddr;
466 lastaddr = parse_boot_param(abp);
470 /* Do basic tuning, hz etc */
473 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
474 /* Define a macro to simplify memory allocation */
475 #define valloc_pages(var, np) \
476 alloc_pages((var).pv_va, (np)); \
477 (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR);
479 #define alloc_pages(var, np) \
480 (var) = freemempos; \
481 freemempos += (np * PAGE_SIZE); \
482 memset((char *)(var), 0, ((np) * PAGE_SIZE));
484 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
485 freemempos += PAGE_SIZE;
486 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
487 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
488 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
489 valloc_pages(kernel_pt_table[i],
490 L2_TABLE_SIZE / PAGE_SIZE);
492 kernel_pt_table[i].pv_va = freemempos -
493 (i % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
495 kernel_pt_table[i].pv_pa =
496 kernel_pt_table[i].pv_va - KERNVIRTADDR +
501 * Allocate a page for the system page mapped to 0x00000000
502 * or 0xffff0000. This page will just contain the system vectors
503 * and can be shared by all processes.
505 valloc_pages(systempage, 1);
507 /* Allocate dynamic per-cpu area. */
508 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
509 dpcpu_init((void *)dpcpu.pv_va, 0);
511 /* Allocate stacks for all modes */
512 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU);
513 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU);
514 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU);
515 valloc_pages(kernelstack, KSTACK_PAGES * MAXCPU);
516 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
519 * Now we start construction of the L1 page table
520 * We start by mapping the L2 page tables into the L1.
521 * This means that we can replace L1 mappings later on if necessary
523 l1pagetable = kernel_l1pt.pv_va;
525 /* Map the L2 pages tables in the L1 page table */
526 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
527 &kernel_pt_table[KERNEL_PT_SYS]);
528 for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
529 pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
530 &kernel_pt_table[KERNEL_PT_KERN + i]);
531 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
532 (((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
533 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
534 afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1));
535 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
536 pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
537 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
540 /* Map the vector page. */
541 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
542 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
544 /* Map the DPCPU pages */
545 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE,
546 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
548 /* Map the stack pages */
549 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
550 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
551 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
552 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
553 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
554 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
555 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
556 KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
558 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
559 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
560 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
561 msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
563 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
564 pmap_map_chunk(l1pagetable, kernel_pt_table[i].pv_va,
565 kernel_pt_table[i].pv_pa, L2_TABLE_SIZE,
566 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
569 pmap_devmap_bootstrap(l1pagetable, at91_devmap);
570 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
571 setttb(kernel_l1pt.pv_pa);
573 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
578 * Initialize all the clocks, so that the console can work. We can only
579 * do this if at91_soc_id() was able to fill in the support data. Even
580 * if we can't init the clocks, still try to do a console init so we can
581 * try to print the error message about missing soc support. There's a
582 * chance the printf will work if the bootloader set up the DBGU.
584 if (soc_info.soc_data != NULL) {
585 soc_info.soc_data->soc_clock_init();
586 at91_pmc_init_clock();
591 if (soc_info.soc_data == NULL)
592 printf("Warning: No soc support for %s found.\n", soc_info.name);
594 memsize = board_init();
595 physmem = memsize / PAGE_SIZE;
598 * Pages were allocated during the secondary bootstrap for the
599 * stacks for different CPU modes.
600 * We must now set the r13 registers in the different CPU modes to
601 * point to these stacks.
602 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
603 * of the stack memory.
605 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
610 * We must now clean the cache again....
611 * Cleaning may be done by reading new data to displace any
612 * dirty data in the cache. This will have happened in setttb()
613 * but since we are boot strapping the addresses used for the read
614 * may have just been remapped and thus the cache could be out
615 * of sync. A re-clean after the switch will cure this.
616 * After booting there are no gross relocations of the kernel thus
617 * this problem will not occur after initarm().
619 cpu_idcache_wbinv_all();
621 /* Set stack for exception handlers */
623 data_abort_handler_address = (u_int)data_abort_handler;
624 prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
625 undefined_handler_address = (u_int)undefinedinstruction_bounce;
628 init_proc0(kernelstack.pv_va);
630 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
632 pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1);
633 arm_dump_avail_init(memsize, sizeof(dump_avail)/sizeof(dump_avail[0]));
634 /* Always use the 256MB of KVA we have available between the kernel and devices */
635 vm_max_kernel_address = KERNVIRTADDR + (256 << 20);
636 pmap_bootstrap(freemempos, &kernel_l1pt);
637 msgbufp = (void*)msgbufpv.pv_va;
638 msgbufinit(msgbufp, msgbufsize);
642 #if PHYSADDR != KERNPHYSADDR
643 phys_avail[i++] = PHYSADDR;
644 phys_avail[i++] = KERNPHYSADDR;
646 phys_avail[i++] = virtual_avail - KERNVIRTADDR + KERNPHYSADDR;
647 phys_avail[i++] = PHYSADDR + memsize;
650 init_param2(physmem);
652 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
653 sizeof(struct pcb)));
657 * These functions are handled elsewhere, so make them nops here.
660 cpu_startprofclock(void)
666 cpu_stopprofclock(void)
681 if (soc_info.soc_data)
682 soc_info.soc_data->soc_delay(n);
689 if (soc_info.soc_data)
690 soc_info.soc_data->soc_reset();