2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/physmem.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
125 #include <sys/sbuf.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
131 #include <sys/_unrhdr.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
148 #include <machine/machdep.h>
149 #include <machine/md_var.h>
150 #include <machine/pcb.h>
152 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
153 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
155 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
156 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
158 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
160 #define NUL0E L0_ENTRIES
161 #define NUL1E (NUL0E * NL1PG)
162 #define NUL2E (NUL1E * NL2PG)
164 #if !defined(DIAGNOSTIC)
165 #ifdef __GNUC_GNU_INLINE__
166 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
168 #define PMAP_INLINE extern inline
175 #define PV_STAT(x) do { x ; } while (0)
177 #define PV_STAT(x) do { } while (0)
180 #define pmap_l0_pindex(v) (NUL2E + NUL1E + ((v) >> L0_SHIFT))
181 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT))
182 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
184 static struct md_page *
185 pa_to_pvh(vm_paddr_t pa)
187 struct vm_phys_seg *seg;
190 for (segind = 0; segind < vm_phys_nsegs; segind++) {
191 seg = &vm_phys_segs[segind];
192 if (pa >= seg->start && pa < seg->end)
193 return ((struct md_page *)seg->md_first +
194 pmap_l2_pindex(pa) - pmap_l2_pindex(seg->start));
196 panic("pa 0x%jx not within vm_phys_segs", (uintmax_t)pa);
199 static struct md_page *
200 page_to_pvh(vm_page_t m)
202 struct vm_phys_seg *seg;
204 seg = &vm_phys_segs[m->segind];
205 return ((struct md_page *)seg->md_first +
206 pmap_l2_pindex(VM_PAGE_TO_PHYS(m)) - pmap_l2_pindex(seg->start));
209 #define NPV_LIST_LOCKS MAXCPU
211 #define PHYS_TO_PV_LIST_LOCK(pa) \
212 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
214 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
215 struct rwlock **_lockp = (lockp); \
216 struct rwlock *_new_lock; \
218 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
219 if (_new_lock != *_lockp) { \
220 if (*_lockp != NULL) \
221 rw_wunlock(*_lockp); \
222 *_lockp = _new_lock; \
227 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
228 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
230 #define RELEASE_PV_LIST_LOCK(lockp) do { \
231 struct rwlock **_lockp = (lockp); \
233 if (*_lockp != NULL) { \
234 rw_wunlock(*_lockp); \
239 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
240 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
243 * The presence of this flag indicates that the mapping is writeable.
244 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
245 * it is dirty. This flag may only be set on managed mappings.
247 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
248 * as a software managed bit.
250 #define ATTR_SW_DBM ATTR_DBM
252 struct pmap kernel_pmap_store;
254 /* Used for mapping ACPI memory before VM is initialized */
255 #define PMAP_PREINIT_MAPPING_COUNT 32
256 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
257 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
258 static int vm_initialized = 0; /* No need to use pre-init maps when set */
261 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
262 * Always map entire L2 block for simplicity.
263 * VA of L2 block = preinit_map_va + i * L2_SIZE
265 static struct pmap_preinit_mapping {
269 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
271 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
272 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
273 vm_offset_t kernel_vm_end = 0;
276 * Data for the pv entry allocation mechanism.
278 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
279 static struct mtx pv_chunks_mutex;
280 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
281 static struct md_page *pv_table;
282 static struct md_page pv_dummy;
284 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
285 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
286 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
288 /* This code assumes all L1 DMAP entries will be used */
289 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
290 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
292 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
293 extern pt_entry_t pagetable_dmap[];
295 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
296 static vm_paddr_t physmap[PHYSMAP_SIZE];
297 static u_int physmap_idx;
299 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
300 "VM/pmap parameters");
303 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
304 * that it has currently allocated to a pmap, a cursor ("asid_next") to
305 * optimize its search for a free ASID in the bit vector, and an epoch number
306 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
307 * ASIDs that are not currently active on a processor.
309 * The current epoch number is always in the range [0, INT_MAX). Negative
310 * numbers and INT_MAX are reserved for special cases that are described
319 struct mtx asid_set_mutex;
322 static struct asid_set asids;
323 static struct asid_set vmids;
325 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
327 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
328 "The number of bits in an ASID");
329 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
330 "The last allocated ASID plus one");
331 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
332 "The current epoch number");
334 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
335 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
336 "The number of bits in an VMID");
337 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
338 "The last allocated VMID plus one");
339 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
340 "The current epoch number");
342 void (*pmap_clean_stage2_tlbi)(void);
343 void (*pmap_invalidate_vpipt_icache)(void);
346 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
347 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
348 * dynamically allocated ASIDs have a non-negative epoch number.
350 * An invalid ASID is represented by -1.
352 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
353 * which indicates that an ASID should never be allocated to the pmap, and
354 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
355 * allocated when the pmap is next activated.
357 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
358 ((u_long)(epoch) << 32)))
359 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
360 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
362 static int superpages_enabled = 1;
363 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
364 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
365 "Are large page mappings enabled?");
368 * Internal flags for pmap_enter()'s helper functions.
370 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
371 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
373 static void free_pv_chunk(struct pv_chunk *pc);
374 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
375 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
376 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
377 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
378 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
381 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
382 static bool pmap_activate_int(pmap_t pmap);
383 static void pmap_alloc_asid(pmap_t pmap);
384 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
385 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
386 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
387 vm_offset_t va, struct rwlock **lockp);
388 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
389 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
390 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
391 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
392 u_int flags, vm_page_t m, struct rwlock **lockp);
393 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
394 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
395 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
396 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
397 static void pmap_reset_asid_set(pmap_t pmap);
398 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
399 vm_page_t m, struct rwlock **lockp);
401 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
402 struct rwlock **lockp);
404 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
405 struct spglist *free);
406 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
407 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
410 * These load the old table data and store the new value.
411 * They need to be atomic as the System MMU may write to the table at
412 * the same time as the CPU.
414 #define pmap_clear(table) atomic_store_64(table, 0)
415 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
416 #define pmap_load(table) (*table)
417 #define pmap_load_clear(table) atomic_swap_64(table, 0)
418 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
419 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
420 #define pmap_store(table, entry) atomic_store_64(table, entry)
422 /********************/
423 /* Inline functions */
424 /********************/
427 pagecopy(void *s, void *d)
430 memcpy(d, s, PAGE_SIZE);
433 static __inline pd_entry_t *
434 pmap_l0(pmap_t pmap, vm_offset_t va)
437 return (&pmap->pm_l0[pmap_l0_index(va)]);
440 static __inline pd_entry_t *
441 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
445 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
446 return (&l1[pmap_l1_index(va)]);
449 static __inline pd_entry_t *
450 pmap_l1(pmap_t pmap, vm_offset_t va)
454 l0 = pmap_l0(pmap, va);
455 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
458 return (pmap_l0_to_l1(l0, va));
461 static __inline pd_entry_t *
462 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va)
469 * The valid bit may be clear if pmap_update_entry() is concurrently
470 * modifying the entry, so for KVA only the entry type may be checked.
472 KASSERT(va >= VM_MAX_USER_ADDRESS || (l1 & ATTR_DESCR_VALID) != 0,
473 ("%s: L1 entry %#lx for %#lx is invalid", __func__, l1, va));
474 KASSERT((l1 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
475 ("%s: L1 entry %#lx for %#lx is a leaf", __func__, l1, va));
476 l2p = (pd_entry_t *)PHYS_TO_DMAP(l1 & ~ATTR_MASK);
477 return (&l2p[pmap_l2_index(va)]);
480 static __inline pd_entry_t *
481 pmap_l2(pmap_t pmap, vm_offset_t va)
485 l1 = pmap_l1(pmap, va);
486 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
489 return (pmap_l1_to_l2(l1, va));
492 static __inline pt_entry_t *
493 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va)
501 * The valid bit may be clear if pmap_update_entry() is concurrently
502 * modifying the entry, so for KVA only the entry type may be checked.
504 KASSERT(va >= VM_MAX_USER_ADDRESS || (l2 & ATTR_DESCR_VALID) != 0,
505 ("%s: L2 entry %#lx for %#lx is invalid", __func__, l2, va));
506 KASSERT((l2 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
507 ("%s: L2 entry %#lx for %#lx is a leaf", __func__, l2, va));
508 l3p = (pt_entry_t *)PHYS_TO_DMAP(l2 & ~ATTR_MASK);
509 return (&l3p[pmap_l3_index(va)]);
513 * Returns the lowest valid pde for a given virtual address.
514 * The next level may or may not point to a valid page or block.
516 static __inline pd_entry_t *
517 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
519 pd_entry_t *l0, *l1, *l2, desc;
521 l0 = pmap_l0(pmap, va);
522 desc = pmap_load(l0) & ATTR_DESCR_MASK;
523 if (desc != L0_TABLE) {
528 l1 = pmap_l0_to_l1(l0, va);
529 desc = pmap_load(l1) & ATTR_DESCR_MASK;
530 if (desc != L1_TABLE) {
535 l2 = pmap_l1_to_l2(l1, va);
536 desc = pmap_load(l2) & ATTR_DESCR_MASK;
537 if (desc != L2_TABLE) {
547 * Returns the lowest valid pte block or table entry for a given virtual
548 * address. If there are no valid entries return NULL and set the level to
549 * the first invalid level.
551 static __inline pt_entry_t *
552 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
554 pd_entry_t *l1, *l2, desc;
557 l1 = pmap_l1(pmap, va);
562 desc = pmap_load(l1) & ATTR_DESCR_MASK;
563 if (desc == L1_BLOCK) {
568 if (desc != L1_TABLE) {
573 l2 = pmap_l1_to_l2(l1, va);
574 desc = pmap_load(l2) & ATTR_DESCR_MASK;
575 if (desc == L2_BLOCK) {
580 if (desc != L2_TABLE) {
586 l3 = pmap_l2_to_l3(l2, va);
587 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
594 pmap_ps_enabled(pmap_t pmap __unused)
597 return (superpages_enabled != 0);
601 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
602 pd_entry_t **l2, pt_entry_t **l3)
604 pd_entry_t *l0p, *l1p, *l2p;
606 if (pmap->pm_l0 == NULL)
609 l0p = pmap_l0(pmap, va);
612 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
615 l1p = pmap_l0_to_l1(l0p, va);
618 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
624 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
627 l2p = pmap_l1_to_l2(l1p, va);
630 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
635 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
638 *l3 = pmap_l2_to_l3(l2p, va);
644 pmap_l3_valid(pt_entry_t l3)
647 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
650 CTASSERT(L1_BLOCK == L2_BLOCK);
653 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
657 if (pmap->pm_stage == PM_STAGE1) {
658 val = ATTR_S1_IDX(memattr);
659 if (memattr == VM_MEMATTR_DEVICE)
667 case VM_MEMATTR_DEVICE:
668 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
669 ATTR_S2_XN(ATTR_S2_XN_ALL));
670 case VM_MEMATTR_UNCACHEABLE:
671 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
672 case VM_MEMATTR_WRITE_BACK:
673 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
674 case VM_MEMATTR_WRITE_THROUGH:
675 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
677 panic("%s: invalid memory attribute %x", __func__, memattr);
682 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
687 if (pmap->pm_stage == PM_STAGE1) {
688 if ((prot & VM_PROT_EXECUTE) == 0)
690 if ((prot & VM_PROT_WRITE) == 0)
691 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
693 if ((prot & VM_PROT_WRITE) != 0)
694 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
695 if ((prot & VM_PROT_READ) != 0)
696 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
697 if ((prot & VM_PROT_EXECUTE) == 0)
698 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
705 * Checks if the PTE is dirty.
708 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
711 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
713 if (pmap->pm_stage == PM_STAGE1) {
714 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
715 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
717 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
718 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
721 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
722 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
726 pmap_resident_count_inc(pmap_t pmap, int count)
729 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
730 pmap->pm_stats.resident_count += count;
734 pmap_resident_count_dec(pmap_t pmap, int count)
737 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
738 KASSERT(pmap->pm_stats.resident_count >= count,
739 ("pmap %p resident count underflow %ld %d", pmap,
740 pmap->pm_stats.resident_count, count));
741 pmap->pm_stats.resident_count -= count;
745 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
751 l1 = (pd_entry_t *)l1pt;
752 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
754 /* Check locore has used a table L1 map */
755 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
756 ("Invalid bootstrap L1 table"));
757 /* Find the address of the L2 table */
758 l2 = (pt_entry_t *)init_pt_va;
759 *l2_slot = pmap_l2_index(va);
765 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
767 u_int l1_slot, l2_slot;
770 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
772 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
776 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
777 vm_offset_t freemempos)
781 vm_paddr_t l2_pa, pa;
782 u_int l1_slot, l2_slot, prev_l1_slot;
785 dmap_phys_base = min_pa & ~L1_OFFSET;
791 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
792 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
794 for (i = 0; i < (physmap_idx * 2); i += 2) {
795 pa = physmap[i] & ~L2_OFFSET;
796 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
798 /* Create L2 mappings at the start of the region */
799 if ((pa & L1_OFFSET) != 0) {
800 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
801 if (l1_slot != prev_l1_slot) {
802 prev_l1_slot = l1_slot;
803 l2 = (pt_entry_t *)freemempos;
804 l2_pa = pmap_early_vtophys(kern_l1,
806 freemempos += PAGE_SIZE;
808 pmap_store(&pagetable_dmap[l1_slot],
809 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
811 memset(l2, 0, PAGE_SIZE);
814 ("pmap_bootstrap_dmap: NULL l2 map"));
815 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
816 pa += L2_SIZE, va += L2_SIZE) {
818 * We are on a boundary, stop to
819 * create a level 1 block
821 if ((pa & L1_OFFSET) == 0)
824 l2_slot = pmap_l2_index(va);
825 KASSERT(l2_slot != 0, ("..."));
826 pmap_store(&l2[l2_slot],
827 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
829 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
832 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
836 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
837 (physmap[i + 1] - pa) >= L1_SIZE;
838 pa += L1_SIZE, va += L1_SIZE) {
839 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
840 pmap_store(&pagetable_dmap[l1_slot],
841 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_S1_XN |
842 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
845 /* Create L2 mappings at the end of the region */
846 if (pa < physmap[i + 1]) {
847 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
848 if (l1_slot != prev_l1_slot) {
849 prev_l1_slot = l1_slot;
850 l2 = (pt_entry_t *)freemempos;
851 l2_pa = pmap_early_vtophys(kern_l1,
853 freemempos += PAGE_SIZE;
855 pmap_store(&pagetable_dmap[l1_slot],
856 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
858 memset(l2, 0, PAGE_SIZE);
861 ("pmap_bootstrap_dmap: NULL l2 map"));
862 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
863 pa += L2_SIZE, va += L2_SIZE) {
864 l2_slot = pmap_l2_index(va);
865 pmap_store(&l2[l2_slot],
866 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
868 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
873 if (pa > dmap_phys_max) {
885 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
892 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
894 l1 = (pd_entry_t *)l1pt;
895 l1_slot = pmap_l1_index(va);
898 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
899 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
901 pa = pmap_early_vtophys(l1pt, l2pt);
902 pmap_store(&l1[l1_slot],
903 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
907 /* Clean the L2 page table */
908 memset((void *)l2_start, 0, l2pt - l2_start);
914 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
921 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
923 l2 = pmap_l2(kernel_pmap, va);
924 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
925 l2_slot = pmap_l2_index(va);
928 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
929 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
931 pa = pmap_early_vtophys(l1pt, l3pt);
932 pmap_store(&l2[l2_slot],
933 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
937 /* Clean the L2 page table */
938 memset((void *)l3_start, 0, l3pt - l3_start);
944 * Bootstrap the system enough to run with virtual memory.
947 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
950 vm_offset_t freemempos;
951 vm_offset_t dpcpu, msgbufpv;
952 vm_paddr_t start_pa, pa, min_pa;
956 /* Verify that the ASID is set through TTBR0. */
957 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
958 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
960 kern_delta = KERNBASE - kernstart;
962 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
963 printf("%lx\n", l1pt);
964 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
966 /* Set this early so we can use the pagetable walking functions */
967 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
968 PMAP_LOCK_INIT(kernel_pmap);
969 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
970 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
971 kernel_pmap->pm_stage = PM_STAGE1;
972 kernel_pmap->pm_asid_set = &asids;
974 /* Assume the address we were loaded to is a valid physical address */
975 min_pa = KERNBASE - kern_delta;
977 physmap_idx = physmem_avail(physmap, nitems(physmap));
981 * Find the minimum physical address. physmap is sorted,
982 * but may contain empty ranges.
984 for (i = 0; i < physmap_idx * 2; i += 2) {
985 if (physmap[i] == physmap[i + 1])
987 if (physmap[i] <= min_pa)
991 freemempos = KERNBASE + kernlen;
992 freemempos = roundup2(freemempos, PAGE_SIZE);
994 /* Create a direct map region early so we can use it for pa -> va */
995 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
997 start_pa = pa = KERNBASE - kern_delta;
1000 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
1001 * loader allocated the first and only l2 page table page used to map
1002 * the kernel, preloaded files and module metadata.
1004 freemempos = pmap_bootstrap_l2(l1pt, KERNBASE + L1_SIZE, freemempos);
1005 /* And the l3 tables for the early devmap */
1006 freemempos = pmap_bootstrap_l3(l1pt,
1007 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
1011 #define alloc_pages(var, np) \
1012 (var) = freemempos; \
1013 freemempos += (np * PAGE_SIZE); \
1014 memset((char *)(var), 0, ((np) * PAGE_SIZE));
1016 /* Allocate dynamic per-cpu area. */
1017 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
1018 dpcpu_init((void *)dpcpu, 0);
1020 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
1021 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
1022 msgbufp = (void *)msgbufpv;
1024 /* Reserve some VA space for early BIOS/ACPI mapping */
1025 preinit_map_va = roundup2(freemempos, L2_SIZE);
1027 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
1028 virtual_avail = roundup2(virtual_avail, L1_SIZE);
1029 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
1030 kernel_vm_end = virtual_avail;
1032 pa = pmap_early_vtophys(l1pt, freemempos);
1034 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
1040 * Initialize a vm_page's machine-dependent fields.
1043 pmap_page_init(vm_page_t m)
1046 TAILQ_INIT(&m->md.pv_list);
1047 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1051 pmap_init_asids(struct asid_set *set, int bits)
1055 set->asid_bits = bits;
1058 * We may be too early in the overall initialization process to use
1061 set->asid_set_size = 1 << set->asid_bits;
1062 set->asid_set = (bitstr_t *)kmem_malloc(bitstr_size(set->asid_set_size),
1064 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1065 bit_set(set->asid_set, i);
1066 set->asid_next = ASID_FIRST_AVAILABLE;
1067 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1071 * Initialize the pmap module.
1072 * Called by vm_init, to initialize any structures that the pmap
1073 * system needs to map virtual memory.
1078 struct vm_phys_seg *seg, *next_seg;
1079 struct md_page *pvh;
1082 int i, pv_npg, vmid_bits;
1085 * Are large page mappings enabled?
1087 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1088 if (superpages_enabled) {
1089 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1090 ("pmap_init: can't assign to pagesizes[1]"));
1091 pagesizes[1] = L2_SIZE;
1092 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
1093 ("pmap_init: can't assign to pagesizes[2]"));
1094 pagesizes[2] = L1_SIZE;
1098 * Initialize the ASID allocator.
1100 pmap_init_asids(&asids,
1101 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1104 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1107 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1108 ID_AA64MMFR1_VMIDBits_16)
1110 pmap_init_asids(&vmids, vmid_bits);
1114 * Initialize the pv chunk list mutex.
1116 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1119 * Initialize the pool of pv list locks.
1121 for (i = 0; i < NPV_LIST_LOCKS; i++)
1122 rw_init(&pv_list_locks[i], "pmap pv list");
1125 * Calculate the size of the pv head table for superpages.
1128 for (i = 0; i < vm_phys_nsegs; i++) {
1129 seg = &vm_phys_segs[i];
1130 pv_npg += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1131 pmap_l2_pindex(seg->start);
1135 * Allocate memory for the pv head table for superpages.
1137 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1139 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1140 for (i = 0; i < pv_npg; i++)
1141 TAILQ_INIT(&pv_table[i].pv_list);
1142 TAILQ_INIT(&pv_dummy.pv_list);
1145 * Set pointers from vm_phys_segs to pv_table.
1147 for (i = 0, pvh = pv_table; i < vm_phys_nsegs; i++) {
1148 seg = &vm_phys_segs[i];
1149 seg->md_first = pvh;
1150 pvh += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1151 pmap_l2_pindex(seg->start);
1154 * If there is a following segment, and the final
1155 * superpage of this segment and the initial superpage
1156 * of the next segment are the same then adjust the
1157 * pv_table entry for that next segment down by one so
1158 * that the pv_table entries will be shared.
1160 if (i + 1 < vm_phys_nsegs) {
1161 next_seg = &vm_phys_segs[i + 1];
1162 if (pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1 ==
1163 pmap_l2_pindex(next_seg->start)) {
1172 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1173 "2MB page mapping counters");
1175 static u_long pmap_l2_demotions;
1176 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1177 &pmap_l2_demotions, 0, "2MB page demotions");
1179 static u_long pmap_l2_mappings;
1180 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1181 &pmap_l2_mappings, 0, "2MB page mappings");
1183 static u_long pmap_l2_p_failures;
1184 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1185 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1187 static u_long pmap_l2_promotions;
1188 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1189 &pmap_l2_promotions, 0, "2MB page promotions");
1192 * Invalidate a single TLB entry.
1194 static __inline void
1195 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1199 PMAP_ASSERT_STAGE1(pmap);
1202 if (pmap == kernel_pmap) {
1204 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1206 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1207 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1213 static __inline void
1214 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1216 uint64_t end, r, start;
1218 PMAP_ASSERT_STAGE1(pmap);
1221 if (pmap == kernel_pmap) {
1224 for (r = start; r < end; r++)
1225 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1227 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1230 for (r = start; r < end; r++)
1231 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1237 static __inline void
1238 pmap_invalidate_all(pmap_t pmap)
1242 PMAP_ASSERT_STAGE1(pmap);
1245 if (pmap == kernel_pmap) {
1246 __asm __volatile("tlbi vmalle1is");
1248 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1249 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1256 * Routine: pmap_extract
1258 * Extract the physical page address associated
1259 * with the given map/virtual_address pair.
1262 pmap_extract(pmap_t pmap, vm_offset_t va)
1264 pt_entry_t *pte, tpte;
1271 * Find the block or page map for this virtual address. pmap_pte
1272 * will return either a valid block/page entry, or NULL.
1274 pte = pmap_pte(pmap, va, &lvl);
1276 tpte = pmap_load(pte);
1277 pa = tpte & ~ATTR_MASK;
1280 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1281 ("pmap_extract: Invalid L1 pte found: %lx",
1282 tpte & ATTR_DESCR_MASK));
1283 pa |= (va & L1_OFFSET);
1286 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1287 ("pmap_extract: Invalid L2 pte found: %lx",
1288 tpte & ATTR_DESCR_MASK));
1289 pa |= (va & L2_OFFSET);
1292 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1293 ("pmap_extract: Invalid L3 pte found: %lx",
1294 tpte & ATTR_DESCR_MASK));
1295 pa |= (va & L3_OFFSET);
1304 * Routine: pmap_extract_and_hold
1306 * Atomically extract and hold the physical page
1307 * with the given pmap and virtual address pair
1308 * if that mapping permits the given protection.
1311 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1313 pt_entry_t *pte, tpte;
1321 pte = pmap_pte(pmap, va, &lvl);
1323 tpte = pmap_load(pte);
1325 KASSERT(lvl > 0 && lvl <= 3,
1326 ("pmap_extract_and_hold: Invalid level %d", lvl));
1327 CTASSERT(L1_BLOCK == L2_BLOCK);
1328 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1329 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1330 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1331 tpte & ATTR_DESCR_MASK));
1334 if ((prot & VM_PROT_WRITE) == 0)
1336 else if (pmap->pm_stage == PM_STAGE1 &&
1337 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1339 else if (pmap->pm_stage == PM_STAGE2 &&
1340 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1341 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1347 off = va & L1_OFFSET;
1350 off = va & L2_OFFSET;
1356 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1357 if (m != NULL && !vm_page_wire_mapped(m))
1366 pmap_kextract(vm_offset_t va)
1368 pt_entry_t *pte, tpte;
1370 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1371 return (DMAP_TO_PHYS(va));
1372 pte = pmap_l1(kernel_pmap, va);
1377 * A concurrent pmap_update_entry() will clear the entry's valid bit
1378 * but leave the rest of the entry unchanged. Therefore, we treat a
1379 * non-zero entry as being valid, and we ignore the valid bit when
1380 * determining whether the entry maps a block, page, or table.
1382 tpte = pmap_load(pte);
1385 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1386 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1387 pte = pmap_l1_to_l2(&tpte, va);
1388 tpte = pmap_load(pte);
1391 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1392 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1393 pte = pmap_l2_to_l3(&tpte, va);
1394 tpte = pmap_load(pte);
1397 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1400 /***************************************************
1401 * Low level mapping routines.....
1402 ***************************************************/
1405 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1408 pt_entry_t *pte, attr;
1412 KASSERT((pa & L3_OFFSET) == 0,
1413 ("pmap_kenter: Invalid physical address"));
1414 KASSERT((sva & L3_OFFSET) == 0,
1415 ("pmap_kenter: Invalid virtual address"));
1416 KASSERT((size & PAGE_MASK) == 0,
1417 ("pmap_kenter: Mapping is not page-sized"));
1419 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1420 ATTR_S1_IDX(mode) | L3_PAGE;
1423 pde = pmap_pde(kernel_pmap, va, &lvl);
1424 KASSERT(pde != NULL,
1425 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1426 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1428 pte = pmap_l2_to_l3(pde, va);
1429 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1435 pmap_invalidate_range(kernel_pmap, sva, va);
1439 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1442 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1446 * Remove a page from the kernel pagetables.
1449 pmap_kremove(vm_offset_t va)
1454 pte = pmap_pte(kernel_pmap, va, &lvl);
1455 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1456 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1459 pmap_invalidate_page(kernel_pmap, va);
1463 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1469 KASSERT((sva & L3_OFFSET) == 0,
1470 ("pmap_kremove_device: Invalid virtual address"));
1471 KASSERT((size & PAGE_MASK) == 0,
1472 ("pmap_kremove_device: Mapping is not page-sized"));
1476 pte = pmap_pte(kernel_pmap, va, &lvl);
1477 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1479 ("Invalid device pagetable level: %d != 3", lvl));
1485 pmap_invalidate_range(kernel_pmap, sva, va);
1489 * Used to map a range of physical addresses into kernel
1490 * virtual address space.
1492 * The value passed in '*virt' is a suggested virtual address for
1493 * the mapping. Architectures which can support a direct-mapped
1494 * physical to virtual region can return the appropriate address
1495 * within that region, leaving '*virt' unchanged. Other
1496 * architectures should map the pages starting at '*virt' and
1497 * update '*virt' with the first usable address after the mapped
1501 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1503 return PHYS_TO_DMAP(start);
1507 * Add a list of wired pages to the kva
1508 * this routine is only used for temporary
1509 * kernel mappings that do not need to have
1510 * page modification or references recorded.
1511 * Note that old mappings are simply written
1512 * over. The page *must* be wired.
1513 * Note: SMP coherent. Uses a ranged shootdown IPI.
1516 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1519 pt_entry_t *pte, pa;
1525 for (i = 0; i < count; i++) {
1526 pde = pmap_pde(kernel_pmap, va, &lvl);
1527 KASSERT(pde != NULL,
1528 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1530 ("pmap_qenter: Invalid level %d", lvl));
1533 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1534 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1535 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1536 pte = pmap_l2_to_l3(pde, va);
1537 pmap_load_store(pte, pa);
1541 pmap_invalidate_range(kernel_pmap, sva, va);
1545 * This routine tears out page mappings from the
1546 * kernel -- it is meant only for temporary mappings.
1549 pmap_qremove(vm_offset_t sva, int count)
1555 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1558 while (count-- > 0) {
1559 pte = pmap_pte(kernel_pmap, va, &lvl);
1561 ("Invalid device pagetable level: %d != 3", lvl));
1568 pmap_invalidate_range(kernel_pmap, sva, va);
1571 /***************************************************
1572 * Page table page management routines.....
1573 ***************************************************/
1575 * Schedule the specified unused page table page to be freed. Specifically,
1576 * add the page to the specified list of pages that will be released to the
1577 * physical memory manager after the TLB has been updated.
1579 static __inline void
1580 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1581 boolean_t set_PG_ZERO)
1585 m->flags |= PG_ZERO;
1587 m->flags &= ~PG_ZERO;
1588 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1592 * Decrements a page table page's reference count, which is used to record the
1593 * number of valid page table entries within the page. If the reference count
1594 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1595 * page table page was unmapped and FALSE otherwise.
1597 static inline boolean_t
1598 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1602 if (m->ref_count == 0) {
1603 _pmap_unwire_l3(pmap, va, m, free);
1610 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1613 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1615 * unmap the page table page
1617 if (m->pindex >= (NUL2E + NUL1E)) {
1621 l0 = pmap_l0(pmap, va);
1623 } else if (m->pindex >= NUL2E) {
1627 l1 = pmap_l1(pmap, va);
1633 l2 = pmap_l2(pmap, va);
1636 pmap_resident_count_dec(pmap, 1);
1637 if (m->pindex < NUL2E) {
1638 /* We just released an l3, unhold the matching l2 */
1639 pd_entry_t *l1, tl1;
1642 l1 = pmap_l1(pmap, va);
1643 tl1 = pmap_load(l1);
1644 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1645 pmap_unwire_l3(pmap, va, l2pg, free);
1646 } else if (m->pindex < (NUL2E + NUL1E)) {
1647 /* We just released an l2, unhold the matching l1 */
1648 pd_entry_t *l0, tl0;
1651 l0 = pmap_l0(pmap, va);
1652 tl0 = pmap_load(l0);
1653 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1654 pmap_unwire_l3(pmap, va, l1pg, free);
1656 pmap_invalidate_page(pmap, va);
1659 * Put page on a list so that it is released after
1660 * *ALL* TLB shootdown is done
1662 pmap_add_delayed_free_list(m, free, TRUE);
1666 * After removing a page table entry, this routine is used to
1667 * conditionally free the page, and manage the reference count.
1670 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1671 struct spglist *free)
1675 if (va >= VM_MAXUSER_ADDRESS)
1677 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1678 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1679 return (pmap_unwire_l3(pmap, va, mpte, free));
1683 * Release a page table page reference after a failed attempt to create a
1687 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1689 struct spglist free;
1692 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
1694 * Although "va" was never mapped, the TLB could nonetheless
1695 * have intermediate entries that refer to the freed page
1696 * table pages. Invalidate those entries.
1698 * XXX redundant invalidation (See _pmap_unwire_l3().)
1700 pmap_invalidate_page(pmap, va);
1701 vm_page_free_pages_toq(&free, true);
1706 pmap_pinit0(pmap_t pmap)
1709 PMAP_LOCK_INIT(pmap);
1710 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1711 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1712 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1713 pmap->pm_root.rt_root = 0;
1714 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1715 pmap->pm_stage = PM_STAGE1;
1716 pmap->pm_asid_set = &asids;
1718 PCPU_SET(curpmap, pmap);
1722 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage)
1727 * allocate the l0 page
1729 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1730 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1733 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(l0pt);
1734 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1736 if ((l0pt->flags & PG_ZERO) == 0)
1737 pagezero(pmap->pm_l0);
1739 pmap->pm_root.rt_root = 0;
1740 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1741 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1743 pmap->pm_stage = stage;
1746 pmap->pm_asid_set = &asids;
1749 pmap->pm_asid_set = &vmids;
1752 panic("%s: Invalid pmap type %d", __func__, stage);
1756 /* XXX Temporarily disable deferred ASID allocation. */
1757 pmap_alloc_asid(pmap);
1763 pmap_pinit(pmap_t pmap)
1766 return (pmap_pinit_stage(pmap, PM_STAGE1));
1770 * This routine is called if the desired page table page does not exist.
1772 * If page table page allocation fails, this routine may sleep before
1773 * returning NULL. It sleeps only if a lock pointer was given.
1775 * Note: If a page allocation fails at page table level two or three,
1776 * one or two pages may be held during the wait, only to be released
1777 * afterwards. This conservative approach is easily argued to avoid
1781 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1783 vm_page_t m, l1pg, l2pg;
1785 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1788 * Allocate a page table page.
1790 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1791 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1792 if (lockp != NULL) {
1793 RELEASE_PV_LIST_LOCK(lockp);
1800 * Indicate the need to retry. While waiting, the page table
1801 * page may have been allocated.
1805 if ((m->flags & PG_ZERO) == 0)
1809 * Because of AArch64's weak memory consistency model, we must have a
1810 * barrier here to ensure that the stores for zeroing "m", whether by
1811 * pmap_zero_page() or an earlier function, are visible before adding
1812 * "m" to the page table. Otherwise, a page table walk by another
1813 * processor's MMU could see the mapping to "m" and a stale, non-zero
1819 * Map the pagetable page into the process address space, if
1820 * it isn't already there.
1823 if (ptepindex >= (NUL2E + NUL1E)) {
1825 vm_pindex_t l0index;
1827 l0index = ptepindex - (NUL2E + NUL1E);
1828 l0 = &pmap->pm_l0[l0index];
1829 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1830 } else if (ptepindex >= NUL2E) {
1831 vm_pindex_t l0index, l1index;
1832 pd_entry_t *l0, *l1;
1835 l1index = ptepindex - NUL2E;
1836 l0index = l1index >> L0_ENTRIES_SHIFT;
1838 l0 = &pmap->pm_l0[l0index];
1839 tl0 = pmap_load(l0);
1841 /* recurse for allocating page dir */
1842 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1844 vm_page_unwire_noq(m);
1845 vm_page_free_zero(m);
1849 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1853 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1854 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1855 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1857 vm_pindex_t l0index, l1index;
1858 pd_entry_t *l0, *l1, *l2;
1859 pd_entry_t tl0, tl1;
1861 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1862 l0index = l1index >> L0_ENTRIES_SHIFT;
1864 l0 = &pmap->pm_l0[l0index];
1865 tl0 = pmap_load(l0);
1867 /* recurse for allocating page dir */
1868 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1870 vm_page_unwire_noq(m);
1871 vm_page_free_zero(m);
1874 tl0 = pmap_load(l0);
1875 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1876 l1 = &l1[l1index & Ln_ADDR_MASK];
1878 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1879 l1 = &l1[l1index & Ln_ADDR_MASK];
1880 tl1 = pmap_load(l1);
1882 /* recurse for allocating page dir */
1883 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1885 vm_page_unwire_noq(m);
1886 vm_page_free_zero(m);
1890 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1895 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1896 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1897 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1900 pmap_resident_count_inc(pmap, 1);
1906 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
1907 struct rwlock **lockp)
1909 pd_entry_t *l1, *l2;
1911 vm_pindex_t l2pindex;
1914 l1 = pmap_l1(pmap, va);
1915 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1916 l2 = pmap_l1_to_l2(l1, va);
1917 if (va < VM_MAXUSER_ADDRESS) {
1918 /* Add a reference to the L2 page. */
1919 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1923 } else if (va < VM_MAXUSER_ADDRESS) {
1924 /* Allocate a L2 page. */
1925 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1926 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1933 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
1934 l2 = &l2[pmap_l2_index(va)];
1936 panic("pmap_alloc_l2: missing page table page for va %#lx",
1943 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1945 vm_pindex_t ptepindex;
1946 pd_entry_t *pde, tpde;
1954 * Calculate pagetable page index
1956 ptepindex = pmap_l2_pindex(va);
1959 * Get the page directory entry
1961 pde = pmap_pde(pmap, va, &lvl);
1964 * If the page table page is mapped, we just increment the hold count,
1965 * and activate it. If we get a level 2 pde it will point to a level 3
1973 pte = pmap_l0_to_l1(pde, va);
1974 KASSERT(pmap_load(pte) == 0,
1975 ("pmap_alloc_l3: TODO: l0 superpages"));
1980 pte = pmap_l1_to_l2(pde, va);
1981 KASSERT(pmap_load(pte) == 0,
1982 ("pmap_alloc_l3: TODO: l1 superpages"));
1986 tpde = pmap_load(pde);
1988 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1994 panic("pmap_alloc_l3: Invalid level %d", lvl);
1998 * Here if the pte page isn't mapped, or if it has been deallocated.
2000 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
2001 if (m == NULL && lockp != NULL)
2007 /***************************************************
2008 * Pmap allocation/deallocation routines.
2009 ***************************************************/
2012 * Release any resources held by the given physical map.
2013 * Called when a pmap initialized by pmap_pinit is being released.
2014 * Should only be called if the map contains no valid mappings.
2017 pmap_release(pmap_t pmap)
2019 struct asid_set *set;
2023 KASSERT(pmap->pm_stats.resident_count == 0,
2024 ("pmap_release: pmap resident count %ld != 0",
2025 pmap->pm_stats.resident_count));
2026 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2027 ("pmap_release: pmap has reserved page table page(s)"));
2029 set = pmap->pm_asid_set;
2030 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
2033 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
2034 * the entries when removing them so rely on a later tlb invalidation.
2035 * this will happen when updating the VMID generation. Because of this
2036 * we don't reuse VMIDs within a generation.
2038 if (pmap->pm_stage == PM_STAGE1) {
2039 mtx_lock_spin(&set->asid_set_mutex);
2040 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
2041 asid = COOKIE_TO_ASID(pmap->pm_cookie);
2042 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
2043 asid < set->asid_set_size,
2044 ("pmap_release: pmap cookie has out-of-range asid"));
2045 bit_clear(set->asid_set, asid);
2047 mtx_unlock_spin(&set->asid_set_mutex);
2050 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
2051 vm_page_unwire_noq(m);
2052 vm_page_free_zero(m);
2056 kvm_size(SYSCTL_HANDLER_ARGS)
2058 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2060 return sysctl_handle_long(oidp, &ksize, 0, req);
2062 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2063 0, 0, kvm_size, "LU",
2067 kvm_free(SYSCTL_HANDLER_ARGS)
2069 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2071 return sysctl_handle_long(oidp, &kfree, 0, req);
2073 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2074 0, 0, kvm_free, "LU",
2075 "Amount of KVM free");
2078 * grow the number of kernel page table entries, if needed
2081 pmap_growkernel(vm_offset_t addr)
2085 pd_entry_t *l0, *l1, *l2;
2087 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2089 addr = roundup2(addr, L2_SIZE);
2090 if (addr - 1 >= vm_map_max(kernel_map))
2091 addr = vm_map_max(kernel_map);
2092 while (kernel_vm_end < addr) {
2093 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2094 KASSERT(pmap_load(l0) != 0,
2095 ("pmap_growkernel: No level 0 kernel entry"));
2097 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2098 if (pmap_load(l1) == 0) {
2099 /* We need a new PDP entry */
2100 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
2101 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2102 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2104 panic("pmap_growkernel: no memory to grow kernel");
2105 if ((nkpg->flags & PG_ZERO) == 0)
2106 pmap_zero_page(nkpg);
2107 /* See the dmb() in _pmap_alloc_l3(). */
2109 paddr = VM_PAGE_TO_PHYS(nkpg);
2110 pmap_store(l1, paddr | L1_TABLE);
2111 continue; /* try again */
2113 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2114 if (pmap_load(l2) != 0) {
2115 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2116 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2117 kernel_vm_end = vm_map_max(kernel_map);
2123 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
2124 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2127 panic("pmap_growkernel: no memory to grow kernel");
2128 if ((nkpg->flags & PG_ZERO) == 0)
2129 pmap_zero_page(nkpg);
2130 /* See the dmb() in _pmap_alloc_l3(). */
2132 paddr = VM_PAGE_TO_PHYS(nkpg);
2133 pmap_store(l2, paddr | L2_TABLE);
2135 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2136 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2137 kernel_vm_end = vm_map_max(kernel_map);
2143 /***************************************************
2144 * page management routines.
2145 ***************************************************/
2147 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2148 CTASSERT(_NPCM == 3);
2149 CTASSERT(_NPCPV == 168);
2151 static __inline struct pv_chunk *
2152 pv_to_chunk(pv_entry_t pv)
2155 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2158 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2160 #define PC_FREE0 0xfffffffffffffffful
2161 #define PC_FREE1 0xfffffffffffffffful
2162 #define PC_FREE2 0x000000fffffffffful
2164 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2168 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2170 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2171 "Current number of pv entry chunks");
2172 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2173 "Current number of pv entry chunks allocated");
2174 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2175 "Current number of pv entry chunks frees");
2176 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2177 "Number of times tried to get a chunk page but failed.");
2179 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2180 static int pv_entry_spare;
2182 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2183 "Current number of pv entry frees");
2184 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2185 "Current number of pv entry allocs");
2186 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2187 "Current number of pv entries");
2188 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2189 "Current number of spare pv entries");
2194 * We are in a serious low memory condition. Resort to
2195 * drastic measures to free some pages so we can allocate
2196 * another pv entry chunk.
2198 * Returns NULL if PV entries were reclaimed from the specified pmap.
2200 * We do not, however, unmap 2mpages because subsequent accesses will
2201 * allocate per-page pv entries until repromotion occurs, thereby
2202 * exacerbating the shortage of free pv entries.
2205 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2207 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2208 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2209 struct md_page *pvh;
2211 pmap_t next_pmap, pmap;
2212 pt_entry_t *pte, tpte;
2216 struct spglist free;
2218 int bit, field, freed, lvl;
2219 static int active_reclaims = 0;
2221 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2222 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2227 bzero(&pc_marker_b, sizeof(pc_marker_b));
2228 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2229 pc_marker = (struct pv_chunk *)&pc_marker_b;
2230 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2232 mtx_lock(&pv_chunks_mutex);
2234 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2235 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2236 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2237 SLIST_EMPTY(&free)) {
2238 next_pmap = pc->pc_pmap;
2239 if (next_pmap == NULL) {
2241 * The next chunk is a marker. However, it is
2242 * not our marker, so active_reclaims must be
2243 * > 1. Consequently, the next_chunk code
2244 * will not rotate the pv_chunks list.
2248 mtx_unlock(&pv_chunks_mutex);
2251 * A pv_chunk can only be removed from the pc_lru list
2252 * when both pv_chunks_mutex is owned and the
2253 * corresponding pmap is locked.
2255 if (pmap != next_pmap) {
2256 if (pmap != NULL && pmap != locked_pmap)
2259 /* Avoid deadlock and lock recursion. */
2260 if (pmap > locked_pmap) {
2261 RELEASE_PV_LIST_LOCK(lockp);
2263 mtx_lock(&pv_chunks_mutex);
2265 } else if (pmap != locked_pmap) {
2266 if (PMAP_TRYLOCK(pmap)) {
2267 mtx_lock(&pv_chunks_mutex);
2270 pmap = NULL; /* pmap is not locked */
2271 mtx_lock(&pv_chunks_mutex);
2272 pc = TAILQ_NEXT(pc_marker, pc_lru);
2274 pc->pc_pmap != next_pmap)
2282 * Destroy every non-wired, 4 KB page mapping in the chunk.
2285 for (field = 0; field < _NPCM; field++) {
2286 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2287 inuse != 0; inuse &= ~(1UL << bit)) {
2288 bit = ffsl(inuse) - 1;
2289 pv = &pc->pc_pventry[field * 64 + bit];
2291 pde = pmap_pde(pmap, va, &lvl);
2294 pte = pmap_l2_to_l3(pde, va);
2295 tpte = pmap_load(pte);
2296 if ((tpte & ATTR_SW_WIRED) != 0)
2298 tpte = pmap_load_clear(pte);
2299 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2300 if (pmap_pte_dirty(pmap, tpte))
2302 if ((tpte & ATTR_AF) != 0) {
2303 pmap_invalidate_page(pmap, va);
2304 vm_page_aflag_set(m, PGA_REFERENCED);
2306 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2307 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2309 if (TAILQ_EMPTY(&m->md.pv_list) &&
2310 (m->flags & PG_FICTITIOUS) == 0) {
2311 pvh = page_to_pvh(m);
2312 if (TAILQ_EMPTY(&pvh->pv_list)) {
2313 vm_page_aflag_clear(m,
2317 pc->pc_map[field] |= 1UL << bit;
2318 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2323 mtx_lock(&pv_chunks_mutex);
2326 /* Every freed mapping is for a 4 KB page. */
2327 pmap_resident_count_dec(pmap, freed);
2328 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2329 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2330 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2331 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2332 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2333 pc->pc_map[2] == PC_FREE2) {
2334 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2335 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2336 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2337 /* Entire chunk is free; return it. */
2338 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2339 dump_drop_page(m_pc->phys_addr);
2340 mtx_lock(&pv_chunks_mutex);
2341 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2344 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2345 mtx_lock(&pv_chunks_mutex);
2346 /* One freed pv entry in locked_pmap is sufficient. */
2347 if (pmap == locked_pmap)
2351 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2352 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2353 if (active_reclaims == 1 && pmap != NULL) {
2355 * Rotate the pv chunks list so that we do not
2356 * scan the same pv chunks that could not be
2357 * freed (because they contained a wired
2358 * and/or superpage mapping) on every
2359 * invocation of reclaim_pv_chunk().
2361 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2362 MPASS(pc->pc_pmap != NULL);
2363 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2364 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2368 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2369 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2371 mtx_unlock(&pv_chunks_mutex);
2372 if (pmap != NULL && pmap != locked_pmap)
2374 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2375 m_pc = SLIST_FIRST(&free);
2376 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2377 /* Recycle a freed page table page. */
2378 m_pc->ref_count = 1;
2380 vm_page_free_pages_toq(&free, true);
2385 * free the pv_entry back to the free list
2388 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2390 struct pv_chunk *pc;
2391 int idx, field, bit;
2393 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2394 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2395 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2396 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2397 pc = pv_to_chunk(pv);
2398 idx = pv - &pc->pc_pventry[0];
2401 pc->pc_map[field] |= 1ul << bit;
2402 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2403 pc->pc_map[2] != PC_FREE2) {
2404 /* 98% of the time, pc is already at the head of the list. */
2405 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2406 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2407 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2411 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2416 free_pv_chunk(struct pv_chunk *pc)
2420 mtx_lock(&pv_chunks_mutex);
2421 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2422 mtx_unlock(&pv_chunks_mutex);
2423 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2424 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2425 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2426 /* entire chunk is free, return it */
2427 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2428 dump_drop_page(m->phys_addr);
2429 vm_page_unwire_noq(m);
2434 * Returns a new PV entry, allocating a new PV chunk from the system when
2435 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2436 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2439 * The given PV list lock may be released.
2442 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2446 struct pv_chunk *pc;
2449 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2450 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2452 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2454 for (field = 0; field < _NPCM; field++) {
2455 if (pc->pc_map[field]) {
2456 bit = ffsl(pc->pc_map[field]) - 1;
2460 if (field < _NPCM) {
2461 pv = &pc->pc_pventry[field * 64 + bit];
2462 pc->pc_map[field] &= ~(1ul << bit);
2463 /* If this was the last item, move it to tail */
2464 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2465 pc->pc_map[2] == 0) {
2466 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2467 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2470 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2471 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2475 /* No free items, allocate another chunk */
2476 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2479 if (lockp == NULL) {
2480 PV_STAT(pc_chunk_tryfail++);
2483 m = reclaim_pv_chunk(pmap, lockp);
2487 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2488 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2489 dump_add_page(m->phys_addr);
2490 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2492 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2493 pc->pc_map[1] = PC_FREE1;
2494 pc->pc_map[2] = PC_FREE2;
2495 mtx_lock(&pv_chunks_mutex);
2496 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2497 mtx_unlock(&pv_chunks_mutex);
2498 pv = &pc->pc_pventry[0];
2499 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2500 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2501 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2506 * Ensure that the number of spare PV entries in the specified pmap meets or
2507 * exceeds the given count, "needed".
2509 * The given PV list lock may be released.
2512 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2514 struct pch new_tail;
2515 struct pv_chunk *pc;
2520 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2521 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2524 * Newly allocated PV chunks must be stored in a private list until
2525 * the required number of PV chunks have been allocated. Otherwise,
2526 * reclaim_pv_chunk() could recycle one of these chunks. In
2527 * contrast, these chunks must be added to the pmap upon allocation.
2529 TAILQ_INIT(&new_tail);
2532 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2533 bit_count((bitstr_t *)pc->pc_map, 0,
2534 sizeof(pc->pc_map) * NBBY, &free);
2538 if (avail >= needed)
2541 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2542 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2545 m = reclaim_pv_chunk(pmap, lockp);
2550 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2551 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2552 dump_add_page(m->phys_addr);
2553 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2555 pc->pc_map[0] = PC_FREE0;
2556 pc->pc_map[1] = PC_FREE1;
2557 pc->pc_map[2] = PC_FREE2;
2558 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2559 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2560 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2563 * The reclaim might have freed a chunk from the current pmap.
2564 * If that chunk contained available entries, we need to
2565 * re-count the number of available entries.
2570 if (!TAILQ_EMPTY(&new_tail)) {
2571 mtx_lock(&pv_chunks_mutex);
2572 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2573 mtx_unlock(&pv_chunks_mutex);
2578 * First find and then remove the pv entry for the specified pmap and virtual
2579 * address from the specified pv list. Returns the pv entry if found and NULL
2580 * otherwise. This operation can be performed on pv lists for either 4KB or
2581 * 2MB page mappings.
2583 static __inline pv_entry_t
2584 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2588 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2589 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2590 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2599 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2600 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2601 * entries for each of the 4KB page mappings.
2604 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2605 struct rwlock **lockp)
2607 struct md_page *pvh;
2608 struct pv_chunk *pc;
2610 vm_offset_t va_last;
2614 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2615 KASSERT((va & L2_OFFSET) == 0,
2616 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2617 KASSERT((pa & L2_OFFSET) == 0,
2618 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2619 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2622 * Transfer the 2mpage's pv entry for this mapping to the first
2623 * page's pv list. Once this transfer begins, the pv list lock
2624 * must not be released until the last pv entry is reinstantiated.
2626 pvh = pa_to_pvh(pa);
2627 pv = pmap_pvh_remove(pvh, pmap, va);
2628 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2629 m = PHYS_TO_VM_PAGE(pa);
2630 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2632 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2633 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2634 va_last = va + L2_SIZE - PAGE_SIZE;
2636 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2637 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2638 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2639 for (field = 0; field < _NPCM; field++) {
2640 while (pc->pc_map[field]) {
2641 bit = ffsl(pc->pc_map[field]) - 1;
2642 pc->pc_map[field] &= ~(1ul << bit);
2643 pv = &pc->pc_pventry[field * 64 + bit];
2647 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2648 ("pmap_pv_demote_l2: page %p is not managed", m));
2649 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2655 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2656 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2659 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2660 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2661 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2663 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2664 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2668 * First find and then destroy the pv entry for the specified pmap and virtual
2669 * address. This operation can be performed on pv lists for either 4KB or 2MB
2673 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2677 pv = pmap_pvh_remove(pvh, pmap, va);
2678 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2679 free_pv_entry(pmap, pv);
2683 * Conditionally create the PV entry for a 4KB page mapping if the required
2684 * memory can be allocated without resorting to reclamation.
2687 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2688 struct rwlock **lockp)
2692 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2693 /* Pass NULL instead of the lock pointer to disable reclamation. */
2694 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2696 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2697 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2705 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2706 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2707 * false if the PV entry cannot be allocated without resorting to reclamation.
2710 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2711 struct rwlock **lockp)
2713 struct md_page *pvh;
2717 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2718 /* Pass NULL instead of the lock pointer to disable reclamation. */
2719 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2720 NULL : lockp)) == NULL)
2723 pa = l2e & ~ATTR_MASK;
2724 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2725 pvh = pa_to_pvh(pa);
2726 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2732 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2734 pt_entry_t newl2, oldl2;
2738 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2739 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2740 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2742 ml3 = pmap_remove_pt_page(pmap, va);
2744 panic("pmap_remove_kernel_l2: Missing pt page");
2746 ml3pa = VM_PAGE_TO_PHYS(ml3);
2747 newl2 = ml3pa | L2_TABLE;
2750 * If this page table page was unmapped by a promotion, then it
2751 * contains valid mappings. Zero it to invalidate those mappings.
2753 if (ml3->valid != 0)
2754 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2757 * Demote the mapping. The caller must have already invalidated the
2758 * mapping (i.e., the "break" in break-before-make).
2760 oldl2 = pmap_load_store(l2, newl2);
2761 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2762 __func__, l2, oldl2));
2766 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2769 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2770 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2772 struct md_page *pvh;
2774 vm_offset_t eva, va;
2777 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2778 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2779 old_l2 = pmap_load_clear(l2);
2780 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2781 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2784 * Since a promotion must break the 4KB page mappings before making
2785 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2787 pmap_invalidate_page(pmap, sva);
2789 if (old_l2 & ATTR_SW_WIRED)
2790 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2791 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2792 if (old_l2 & ATTR_SW_MANAGED) {
2793 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2794 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2795 pmap_pvh_free(pvh, pmap, sva);
2796 eva = sva + L2_SIZE;
2797 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2798 va < eva; va += PAGE_SIZE, m++) {
2799 if (pmap_pte_dirty(pmap, old_l2))
2801 if (old_l2 & ATTR_AF)
2802 vm_page_aflag_set(m, PGA_REFERENCED);
2803 if (TAILQ_EMPTY(&m->md.pv_list) &&
2804 TAILQ_EMPTY(&pvh->pv_list))
2805 vm_page_aflag_clear(m, PGA_WRITEABLE);
2808 if (pmap == kernel_pmap) {
2809 pmap_remove_kernel_l2(pmap, l2, sva);
2811 ml3 = pmap_remove_pt_page(pmap, sva);
2813 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2814 ("pmap_remove_l2: l3 page not promoted"));
2815 pmap_resident_count_dec(pmap, 1);
2816 KASSERT(ml3->ref_count == NL3PG,
2817 ("pmap_remove_l2: l3 page ref count error"));
2819 pmap_add_delayed_free_list(ml3, free, FALSE);
2822 return (pmap_unuse_pt(pmap, sva, l1e, free));
2826 * pmap_remove_l3: do the things to unmap a page in a process
2829 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2830 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2832 struct md_page *pvh;
2836 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2837 old_l3 = pmap_load_clear(l3);
2838 pmap_invalidate_page(pmap, va);
2839 if (old_l3 & ATTR_SW_WIRED)
2840 pmap->pm_stats.wired_count -= 1;
2841 pmap_resident_count_dec(pmap, 1);
2842 if (old_l3 & ATTR_SW_MANAGED) {
2843 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2844 if (pmap_pte_dirty(pmap, old_l3))
2846 if (old_l3 & ATTR_AF)
2847 vm_page_aflag_set(m, PGA_REFERENCED);
2848 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2849 pmap_pvh_free(&m->md, pmap, va);
2850 if (TAILQ_EMPTY(&m->md.pv_list) &&
2851 (m->flags & PG_FICTITIOUS) == 0) {
2852 pvh = page_to_pvh(m);
2853 if (TAILQ_EMPTY(&pvh->pv_list))
2854 vm_page_aflag_clear(m, PGA_WRITEABLE);
2857 return (pmap_unuse_pt(pmap, va, l2e, free));
2861 * Remove the specified range of addresses from the L3 page table that is
2862 * identified by the given L2 entry.
2865 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2866 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2868 struct md_page *pvh;
2869 struct rwlock *new_lock;
2870 pt_entry_t *l3, old_l3;
2874 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2875 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2876 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2877 l3pg = sva < VM_MAXUSER_ADDRESS ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) :
2880 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2881 if (!pmap_l3_valid(pmap_load(l3))) {
2883 pmap_invalidate_range(pmap, va, sva);
2888 old_l3 = pmap_load_clear(l3);
2889 if ((old_l3 & ATTR_SW_WIRED) != 0)
2890 pmap->pm_stats.wired_count--;
2891 pmap_resident_count_dec(pmap, 1);
2892 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2893 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2894 if (pmap_pte_dirty(pmap, old_l3))
2896 if ((old_l3 & ATTR_AF) != 0)
2897 vm_page_aflag_set(m, PGA_REFERENCED);
2898 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2899 if (new_lock != *lockp) {
2900 if (*lockp != NULL) {
2902 * Pending TLB invalidations must be
2903 * performed before the PV list lock is
2904 * released. Otherwise, a concurrent
2905 * pmap_remove_all() on a physical page
2906 * could return while a stale TLB entry
2907 * still provides access to that page.
2910 pmap_invalidate_range(pmap, va,
2919 pmap_pvh_free(&m->md, pmap, sva);
2920 if (TAILQ_EMPTY(&m->md.pv_list) &&
2921 (m->flags & PG_FICTITIOUS) == 0) {
2922 pvh = page_to_pvh(m);
2923 if (TAILQ_EMPTY(&pvh->pv_list))
2924 vm_page_aflag_clear(m, PGA_WRITEABLE);
2929 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
2935 pmap_invalidate_range(pmap, va, sva);
2939 * Remove the given range of addresses from the specified map.
2941 * It is assumed that the start and end are properly
2942 * rounded to the page size.
2945 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2947 struct rwlock *lock;
2948 vm_offset_t va_next;
2949 pd_entry_t *l0, *l1, *l2;
2950 pt_entry_t l3_paddr;
2951 struct spglist free;
2954 * Perform an unsynchronized read. This is, however, safe.
2956 if (pmap->pm_stats.resident_count == 0)
2964 for (; sva < eva; sva = va_next) {
2965 if (pmap->pm_stats.resident_count == 0)
2968 l0 = pmap_l0(pmap, sva);
2969 if (pmap_load(l0) == 0) {
2970 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2976 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2979 l1 = pmap_l0_to_l1(l0, sva);
2980 if (pmap_load(l1) == 0)
2982 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
2983 KASSERT(va_next <= eva,
2984 ("partial update of non-transparent 1G page "
2985 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
2986 pmap_load(l1), sva, eva, va_next));
2987 MPASS(pmap != kernel_pmap);
2988 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
2990 pmap_invalidate_page(pmap, sva);
2991 pmap_resident_count_dec(pmap, L1_SIZE / PAGE_SIZE);
2992 pmap_unuse_pt(pmap, sva, pmap_load(l0), &free);
2997 * Calculate index for next page table.
2999 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3003 l2 = pmap_l1_to_l2(l1, sva);
3007 l3_paddr = pmap_load(l2);
3009 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3010 if (sva + L2_SIZE == va_next && eva >= va_next) {
3011 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
3014 } else if (pmap_demote_l2_locked(pmap, l2, sva,
3017 l3_paddr = pmap_load(l2);
3021 * Weed out invalid mappings.
3023 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
3027 * Limit our scan to either the end of the va represented
3028 * by the current page table page, or to the end of the
3029 * range being removed.
3034 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
3040 vm_page_free_pages_toq(&free, true);
3044 * Routine: pmap_remove_all
3046 * Removes this physical page from
3047 * all physical maps in which it resides.
3048 * Reflects back modify bits to the pager.
3051 * Original versions of this routine were very
3052 * inefficient because they iteratively called
3053 * pmap_remove (slow...)
3057 pmap_remove_all(vm_page_t m)
3059 struct md_page *pvh;
3062 struct rwlock *lock;
3063 pd_entry_t *pde, tpde;
3064 pt_entry_t *pte, tpte;
3066 struct spglist free;
3067 int lvl, pvh_gen, md_gen;
3069 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3070 ("pmap_remove_all: page %p is not managed", m));
3072 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3073 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
3076 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3078 if (!PMAP_TRYLOCK(pmap)) {
3079 pvh_gen = pvh->pv_gen;
3083 if (pvh_gen != pvh->pv_gen) {
3090 pte = pmap_pte(pmap, va, &lvl);
3091 KASSERT(pte != NULL,
3092 ("pmap_remove_all: no page table entry found"));
3094 ("pmap_remove_all: invalid pte level %d", lvl));
3096 pmap_demote_l2_locked(pmap, pte, va, &lock);
3099 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3101 PMAP_ASSERT_STAGE1(pmap);
3102 if (!PMAP_TRYLOCK(pmap)) {
3103 pvh_gen = pvh->pv_gen;
3104 md_gen = m->md.pv_gen;
3108 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3114 pmap_resident_count_dec(pmap, 1);
3116 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3117 KASSERT(pde != NULL,
3118 ("pmap_remove_all: no page directory entry found"));
3120 ("pmap_remove_all: invalid pde level %d", lvl));
3121 tpde = pmap_load(pde);
3123 pte = pmap_l2_to_l3(pde, pv->pv_va);
3124 tpte = pmap_load_clear(pte);
3125 if (tpte & ATTR_SW_WIRED)
3126 pmap->pm_stats.wired_count--;
3127 if ((tpte & ATTR_AF) != 0) {
3128 pmap_invalidate_page(pmap, pv->pv_va);
3129 vm_page_aflag_set(m, PGA_REFERENCED);
3133 * Update the vm_page_t clean and reference bits.
3135 if (pmap_pte_dirty(pmap, tpte))
3137 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3138 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3140 free_pv_entry(pmap, pv);
3143 vm_page_aflag_clear(m, PGA_WRITEABLE);
3145 vm_page_free_pages_toq(&free, true);
3149 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
3152 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3158 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3159 PMAP_ASSERT_STAGE1(pmap);
3160 KASSERT((sva & L2_OFFSET) == 0,
3161 ("pmap_protect_l2: sva is not 2mpage aligned"));
3162 old_l2 = pmap_load(l2);
3163 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3164 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3167 * Return if the L2 entry already has the desired access restrictions
3171 if ((old_l2 & mask) == nbits)
3175 * When a dirty read/write superpage mapping is write protected,
3176 * update the dirty field of each of the superpage's constituent 4KB
3179 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3180 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3181 pmap_pte_dirty(pmap, old_l2)) {
3182 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3183 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3187 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3191 * Since a promotion must break the 4KB page mappings before making
3192 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3194 pmap_invalidate_page(pmap, sva);
3198 * Set the physical protection on the
3199 * specified range of this map as requested.
3202 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3204 vm_offset_t va, va_next;
3205 pd_entry_t *l0, *l1, *l2;
3206 pt_entry_t *l3p, l3, mask, nbits;
3208 PMAP_ASSERT_STAGE1(pmap);
3209 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3210 if (prot == VM_PROT_NONE) {
3211 pmap_remove(pmap, sva, eva);
3216 if ((prot & VM_PROT_WRITE) == 0) {
3217 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3218 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3220 if ((prot & VM_PROT_EXECUTE) == 0) {
3222 nbits |= ATTR_S1_XN;
3228 for (; sva < eva; sva = va_next) {
3229 l0 = pmap_l0(pmap, sva);
3230 if (pmap_load(l0) == 0) {
3231 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3237 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3240 l1 = pmap_l0_to_l1(l0, sva);
3241 if (pmap_load(l1) == 0)
3243 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3244 KASSERT(va_next <= eva,
3245 ("partial update of non-transparent 1G page "
3246 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3247 pmap_load(l1), sva, eva, va_next));
3248 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3249 if ((pmap_load(l1) & mask) != nbits) {
3250 pmap_store(l1, (pmap_load(l1) & ~mask) | nbits);
3251 pmap_invalidate_page(pmap, sva);
3256 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3260 l2 = pmap_l1_to_l2(l1, sva);
3261 if (pmap_load(l2) == 0)
3264 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3265 if (sva + L2_SIZE == va_next && eva >= va_next) {
3266 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3268 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3271 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3272 ("pmap_protect: Invalid L2 entry after demotion"));
3278 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3280 l3 = pmap_load(l3p);
3283 * Go to the next L3 entry if the current one is
3284 * invalid or already has the desired access
3285 * restrictions in place. (The latter case occurs
3286 * frequently. For example, in a "buildworld"
3287 * workload, almost 1 out of 4 L3 entries already
3288 * have the desired restrictions.)
3290 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3291 if (va != va_next) {
3292 pmap_invalidate_range(pmap, va, sva);
3299 * When a dirty read/write mapping is write protected,
3300 * update the page's dirty field.
3302 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3303 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3304 pmap_pte_dirty(pmap, l3))
3305 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3307 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3313 pmap_invalidate_range(pmap, va, sva);
3319 * Inserts the specified page table page into the specified pmap's collection
3320 * of idle page table pages. Each of a pmap's page table pages is responsible
3321 * for mapping a distinct range of virtual addresses. The pmap's collection is
3322 * ordered by this virtual address range.
3324 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3327 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3330 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3331 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3332 return (vm_radix_insert(&pmap->pm_root, mpte));
3336 * Removes the page table page mapping the specified virtual address from the
3337 * specified pmap's collection of idle page table pages, and returns it.
3338 * Otherwise, returns NULL if there is no page table page corresponding to the
3339 * specified virtual address.
3341 static __inline vm_page_t
3342 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3345 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3346 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3350 * Performs a break-before-make update of a pmap entry. This is needed when
3351 * either promoting or demoting pages to ensure the TLB doesn't get into an
3352 * inconsistent state.
3355 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3356 vm_offset_t va, vm_size_t size)
3360 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3363 * Ensure we don't get switched out with the page table in an
3364 * inconsistent state. We also need to ensure no interrupts fire
3365 * as they may make use of an address we are about to invalidate.
3367 intr = intr_disable();
3370 * Clear the old mapping's valid bit, but leave the rest of the entry
3371 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3372 * lookup the physical address.
3374 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3375 pmap_invalidate_range(pmap, va, va + size);
3377 /* Create the new mapping */
3378 pmap_store(pte, newpte);
3384 #if VM_NRESERVLEVEL > 0
3386 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3387 * replace the many pv entries for the 4KB page mappings by a single pv entry
3388 * for the 2MB page mapping.
3391 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3392 struct rwlock **lockp)
3394 struct md_page *pvh;
3396 vm_offset_t va_last;
3399 KASSERT((pa & L2_OFFSET) == 0,
3400 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3401 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3404 * Transfer the first page's pv entry for this mapping to the 2mpage's
3405 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3406 * a transfer avoids the possibility that get_pv_entry() calls
3407 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3408 * mappings that is being promoted.
3410 m = PHYS_TO_VM_PAGE(pa);
3411 va = va & ~L2_OFFSET;
3412 pv = pmap_pvh_remove(&m->md, pmap, va);
3413 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3414 pvh = pa_to_pvh(pa);
3415 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3417 /* Free the remaining NPTEPG - 1 pv entries. */
3418 va_last = va + L2_SIZE - PAGE_SIZE;
3422 pmap_pvh_free(&m->md, pmap, va);
3423 } while (va < va_last);
3427 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3428 * single level 2 table entry to a single 2MB page mapping. For promotion
3429 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3430 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3431 * identical characteristics.
3434 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3435 struct rwlock **lockp)
3437 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3441 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3442 PMAP_ASSERT_STAGE1(pmap);
3444 sva = va & ~L2_OFFSET;
3445 firstl3 = pmap_l2_to_l3(l2, sva);
3446 newl2 = pmap_load(firstl3);
3449 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3450 atomic_add_long(&pmap_l2_p_failures, 1);
3451 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3452 " in pmap %p", va, pmap);
3456 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3457 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3458 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3460 newl2 &= ~ATTR_SW_DBM;
3463 pa = newl2 + L2_SIZE - PAGE_SIZE;
3464 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3465 oldl3 = pmap_load(l3);
3467 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3468 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3469 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3472 oldl3 &= ~ATTR_SW_DBM;
3475 atomic_add_long(&pmap_l2_p_failures, 1);
3476 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3477 " in pmap %p", va, pmap);
3484 * Save the page table page in its current state until the L2
3485 * mapping the superpage is demoted by pmap_demote_l2() or
3486 * destroyed by pmap_remove_l3().
3488 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3489 KASSERT(mpte >= vm_page_array &&
3490 mpte < &vm_page_array[vm_page_array_size],
3491 ("pmap_promote_l2: page table page is out of range"));
3492 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3493 ("pmap_promote_l2: page table page's pindex is wrong"));
3494 if (pmap_insert_pt_page(pmap, mpte, true)) {
3495 atomic_add_long(&pmap_l2_p_failures, 1);
3497 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3502 if ((newl2 & ATTR_SW_MANAGED) != 0)
3503 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3505 newl2 &= ~ATTR_DESCR_MASK;
3508 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3510 atomic_add_long(&pmap_l2_promotions, 1);
3511 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3514 #endif /* VM_NRESERVLEVEL > 0 */
3517 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
3520 pd_entry_t *l0p, *l1p, *l2p, origpte;
3523 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3524 KASSERT(psind > 0 && psind < MAXPAGESIZES,
3525 ("psind %d unexpected", psind));
3526 KASSERT(((newpte & ~ATTR_MASK) & (pagesizes[psind] - 1)) == 0,
3527 ("unaligned phys address %#lx newpte %#lx psind %d",
3528 (newpte & ~ATTR_MASK), newpte, psind));
3532 l0p = pmap_l0(pmap, va);
3533 if ((pmap_load(l0p) & ATTR_DESCR_VALID) == 0) {
3534 mp = _pmap_alloc_l3(pmap, pmap_l0_pindex(va), NULL);
3536 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3537 return (KERN_RESOURCE_SHORTAGE);
3543 l1p = pmap_l0_to_l1(l0p, va);
3544 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3545 origpte = pmap_load(l1p);
3547 l1p = pmap_l0_to_l1(l0p, va);
3548 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3549 origpte = pmap_load(l1p);
3550 if ((origpte & ATTR_DESCR_VALID) == 0) {
3551 mp = PHYS_TO_VM_PAGE(pmap_load(l0p) &
3556 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3557 ((origpte & ATTR_DESCR_MASK) == L1_BLOCK &&
3558 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3559 ("va %#lx changing 1G phys page l1 %#lx newpte %#lx",
3560 va, origpte, newpte));
3561 pmap_store(l1p, newpte);
3562 } else /* (psind == 1) */ {
3563 l2p = pmap_l2(pmap, va);
3565 mp = _pmap_alloc_l3(pmap, pmap_l1_pindex(va), NULL);
3567 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3568 return (KERN_RESOURCE_SHORTAGE);
3574 l2p = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
3575 l2p = &l2p[pmap_l2_index(va)];
3576 origpte = pmap_load(l2p);
3578 l1p = pmap_l1(pmap, va);
3579 origpte = pmap_load(l2p);
3580 if ((origpte & ATTR_DESCR_VALID) == 0) {
3581 mp = PHYS_TO_VM_PAGE(pmap_load(l1p) &
3586 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3587 ((origpte & ATTR_DESCR_MASK) == L2_BLOCK &&
3588 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3589 ("va %#lx changing 2M phys page l2 %#lx newpte %#lx",
3590 va, origpte, newpte));
3591 pmap_store(l2p, newpte);
3595 if ((origpte & ATTR_DESCR_VALID) == 0)
3596 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
3597 if ((newpte & ATTR_SW_WIRED) != 0 && (origpte & ATTR_SW_WIRED) == 0)
3598 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
3599 else if ((newpte & ATTR_SW_WIRED) == 0 &&
3600 (origpte & ATTR_SW_WIRED) != 0)
3601 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
3603 return (KERN_SUCCESS);
3607 * Insert the given physical page (p) at
3608 * the specified virtual address (v) in the
3609 * target physical map with the protection requested.
3611 * If specified, the page will be wired down, meaning
3612 * that the related pte can not be reclaimed.
3614 * NB: This is the only routine which MAY NOT lazy-evaluate
3615 * or lose information. That is, this routine must actually
3616 * insert this page into the given map NOW.
3619 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3620 u_int flags, int8_t psind)
3622 struct rwlock *lock;
3624 pt_entry_t new_l3, orig_l3;
3625 pt_entry_t *l2, *l3;
3632 va = trunc_page(va);
3633 if ((m->oflags & VPO_UNMANAGED) == 0)
3634 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3635 pa = VM_PAGE_TO_PHYS(m);
3636 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE);
3637 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
3638 new_l3 |= pmap_pte_prot(pmap, prot);
3640 if ((flags & PMAP_ENTER_WIRED) != 0)
3641 new_l3 |= ATTR_SW_WIRED;
3642 if (pmap->pm_stage == PM_STAGE1) {
3643 if (va < VM_MAXUSER_ADDRESS)
3644 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3646 new_l3 |= ATTR_S1_UXN;
3647 if (pmap != kernel_pmap)
3648 new_l3 |= ATTR_S1_nG;
3651 * Clear the access flag on executable mappings, this will be
3652 * set later when the page is accessed. The fault handler is
3653 * required to invalidate the I-cache.
3655 * TODO: Switch to the valid flag to allow hardware management
3656 * of the access flag. Much of the pmap code assumes the
3657 * valid flag is set and fails to destroy the old page tables
3658 * correctly if it is clear.
3660 if (prot & VM_PROT_EXECUTE)
3663 if ((m->oflags & VPO_UNMANAGED) == 0) {
3664 new_l3 |= ATTR_SW_MANAGED;
3665 if ((prot & VM_PROT_WRITE) != 0) {
3666 new_l3 |= ATTR_SW_DBM;
3667 if ((flags & VM_PROT_WRITE) == 0) {
3668 if (pmap->pm_stage == PM_STAGE1)
3669 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3672 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
3677 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3681 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
3682 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
3683 ("managed largepage va %#lx flags %#x", va, flags));
3687 else /* (psind == 1) */
3689 rv = pmap_enter_largepage(pmap, va, new_l3, flags, psind);
3693 /* Assert the required virtual and physical alignment. */
3694 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3695 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3696 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3703 * In the case that a page table page is not
3704 * resident, we are creating it here.
3707 pde = pmap_pde(pmap, va, &lvl);
3708 if (pde != NULL && lvl == 2) {
3709 l3 = pmap_l2_to_l3(pde, va);
3710 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3711 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3715 } else if (pde != NULL && lvl == 1) {
3716 l2 = pmap_l1_to_l2(pde, va);
3717 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3718 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3719 l3 = &l3[pmap_l3_index(va)];
3720 if (va < VM_MAXUSER_ADDRESS) {
3721 mpte = PHYS_TO_VM_PAGE(
3722 pmap_load(l2) & ~ATTR_MASK);
3727 /* We need to allocate an L3 table. */
3729 if (va < VM_MAXUSER_ADDRESS) {
3730 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3733 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3734 * to handle the possibility that a superpage mapping for "va"
3735 * was created while we slept.
3737 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3738 nosleep ? NULL : &lock);
3739 if (mpte == NULL && nosleep) {
3740 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3741 rv = KERN_RESOURCE_SHORTAGE;
3746 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3749 orig_l3 = pmap_load(l3);
3750 opa = orig_l3 & ~ATTR_MASK;
3754 * Is the specified virtual address already mapped?
3756 if (pmap_l3_valid(orig_l3)) {
3758 * Only allow adding new entries on stage 2 tables for now.
3759 * This simplifies cache invalidation as we may need to call
3760 * into EL2 to perform such actions.
3762 PMAP_ASSERT_STAGE1(pmap);
3764 * Wiring change, just update stats. We don't worry about
3765 * wiring PT pages as they remain resident as long as there
3766 * are valid mappings in them. Hence, if a user page is wired,
3767 * the PT page will be also.
3769 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3770 (orig_l3 & ATTR_SW_WIRED) == 0)
3771 pmap->pm_stats.wired_count++;
3772 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3773 (orig_l3 & ATTR_SW_WIRED) != 0)
3774 pmap->pm_stats.wired_count--;
3777 * Remove the extra PT page reference.
3781 KASSERT(mpte->ref_count > 0,
3782 ("pmap_enter: missing reference to page table page,"
3787 * Has the physical page changed?
3791 * No, might be a protection or wiring change.
3793 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3794 (new_l3 & ATTR_SW_DBM) != 0)
3795 vm_page_aflag_set(m, PGA_WRITEABLE);
3800 * The physical page has changed. Temporarily invalidate
3803 orig_l3 = pmap_load_clear(l3);
3804 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3805 ("pmap_enter: unexpected pa update for %#lx", va));
3806 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3807 om = PHYS_TO_VM_PAGE(opa);
3810 * The pmap lock is sufficient to synchronize with
3811 * concurrent calls to pmap_page_test_mappings() and
3812 * pmap_ts_referenced().
3814 if (pmap_pte_dirty(pmap, orig_l3))
3816 if ((orig_l3 & ATTR_AF) != 0) {
3817 pmap_invalidate_page(pmap, va);
3818 vm_page_aflag_set(om, PGA_REFERENCED);
3820 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3821 pv = pmap_pvh_remove(&om->md, pmap, va);
3822 if ((m->oflags & VPO_UNMANAGED) != 0)
3823 free_pv_entry(pmap, pv);
3824 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3825 TAILQ_EMPTY(&om->md.pv_list) &&
3826 ((om->flags & PG_FICTITIOUS) != 0 ||
3827 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3828 vm_page_aflag_clear(om, PGA_WRITEABLE);
3830 KASSERT((orig_l3 & ATTR_AF) != 0,
3831 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
3832 pmap_invalidate_page(pmap, va);
3837 * Increment the counters.
3839 if ((new_l3 & ATTR_SW_WIRED) != 0)
3840 pmap->pm_stats.wired_count++;
3841 pmap_resident_count_inc(pmap, 1);
3844 * Enter on the PV list if part of our managed memory.
3846 if ((m->oflags & VPO_UNMANAGED) == 0) {
3848 pv = get_pv_entry(pmap, &lock);
3851 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3852 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3854 if ((new_l3 & ATTR_SW_DBM) != 0)
3855 vm_page_aflag_set(m, PGA_WRITEABLE);
3859 if (pmap->pm_stage == PM_STAGE1) {
3861 * Sync icache if exec permission and attribute
3862 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
3863 * is stored and made valid for hardware table walk. If done
3864 * later, then other can access this page before caches are
3865 * properly synced. Don't do it for kernel memory which is
3866 * mapped with exec permission even if the memory isn't going
3867 * to hold executable code. The only time when icache sync is
3868 * needed is after kernel module is loaded and the relocation
3869 * info is processed. And it's done in elf_cpu_load_file().
3871 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3872 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3873 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
3874 PMAP_ASSERT_STAGE1(pmap);
3875 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3878 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3882 * Update the L3 entry
3884 if (pmap_l3_valid(orig_l3)) {
3885 PMAP_ASSERT_STAGE1(pmap);
3886 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3887 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3888 /* same PA, different attributes */
3889 orig_l3 = pmap_load_store(l3, new_l3);
3890 pmap_invalidate_page(pmap, va);
3891 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3892 pmap_pte_dirty(pmap, orig_l3))
3897 * This can happens if multiple threads simultaneously
3898 * access not yet mapped page. This bad for performance
3899 * since this can cause full demotion-NOP-promotion
3901 * Another possible reasons are:
3902 * - VM and pmap memory layout are diverged
3903 * - tlb flush is missing somewhere and CPU doesn't see
3906 CTR4(KTR_PMAP, "%s: already mapped page - "
3907 "pmap %p va 0x%#lx pte 0x%lx",
3908 __func__, pmap, va, new_l3);
3912 pmap_store(l3, new_l3);
3916 #if VM_NRESERVLEVEL > 0
3918 * Try to promote from level 3 pages to a level 2 superpage. This
3919 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at
3920 * stage 1 specific fields and performs a break-before-make sequence
3921 * that is incorrect a stage 2 pmap.
3923 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
3924 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 &&
3925 (m->flags & PG_FICTITIOUS) == 0 &&
3926 vm_reserv_level_iffullpop(m) == 0) {
3927 pmap_promote_l2(pmap, pde, va, &lock);
3940 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3941 * if successful. Returns false if (1) a page table page cannot be allocated
3942 * without sleeping, (2) a mapping already exists at the specified virtual
3943 * address, or (3) a PV entry cannot be allocated without reclaiming another
3947 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3948 struct rwlock **lockp)
3952 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3953 PMAP_ASSERT_STAGE1(pmap);
3955 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3956 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
3958 if ((m->oflags & VPO_UNMANAGED) == 0) {
3959 new_l2 |= ATTR_SW_MANAGED;
3962 if ((prot & VM_PROT_EXECUTE) == 0 ||
3963 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3964 new_l2 |= ATTR_S1_XN;
3965 if (va < VM_MAXUSER_ADDRESS)
3966 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3968 new_l2 |= ATTR_S1_UXN;
3969 if (pmap != kernel_pmap)
3970 new_l2 |= ATTR_S1_nG;
3971 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3972 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3977 * Returns true if every page table entry in the specified page table is
3981 pmap_every_pte_zero(vm_paddr_t pa)
3983 pt_entry_t *pt_end, *pte;
3985 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
3986 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
3987 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
3995 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3996 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3997 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3998 * a mapping already exists at the specified virtual address. Returns
3999 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
4000 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
4001 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
4003 * The parameter "m" is only used when creating a managed, writeable mapping.
4006 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
4007 vm_page_t m, struct rwlock **lockp)
4009 struct spglist free;
4010 pd_entry_t *l2, old_l2;
4013 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4015 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
4016 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
4017 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
4019 return (KERN_RESOURCE_SHORTAGE);
4023 * If there are existing mappings, either abort or remove them.
4025 if ((old_l2 = pmap_load(l2)) != 0) {
4026 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
4027 ("pmap_enter_l2: l2pg's ref count is too low"));
4028 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
4029 VM_MAXUSER_ADDRESS || (old_l2 & ATTR_DESCR_MASK) ==
4030 L2_BLOCK || !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
4033 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
4034 " in pmap %p", va, pmap);
4035 return (KERN_FAILURE);
4038 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
4039 (void)pmap_remove_l2(pmap, l2, va,
4040 pmap_load(pmap_l1(pmap, va)), &free, lockp);
4042 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
4044 if (va < VM_MAXUSER_ADDRESS) {
4045 vm_page_free_pages_toq(&free, true);
4046 KASSERT(pmap_load(l2) == 0,
4047 ("pmap_enter_l2: non-zero L2 entry %p", l2));
4049 KASSERT(SLIST_EMPTY(&free),
4050 ("pmap_enter_l2: freed kernel page table page"));
4053 * Both pmap_remove_l2() and pmap_remove_l3_range()
4054 * will leave the kernel page table page zero filled.
4055 * Nonetheless, the TLB could have an intermediate
4056 * entry for the kernel page table page.
4058 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
4059 if (pmap_insert_pt_page(pmap, mt, false))
4060 panic("pmap_enter_l2: trie insert failed");
4062 pmap_invalidate_page(pmap, va);
4066 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
4068 * Abort this mapping if its PV entry could not be created.
4070 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
4072 pmap_abort_ptp(pmap, va, l2pg);
4074 "pmap_enter_l2: failure for va %#lx in pmap %p",
4076 return (KERN_RESOURCE_SHORTAGE);
4078 if ((new_l2 & ATTR_SW_DBM) != 0)
4079 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4080 vm_page_aflag_set(mt, PGA_WRITEABLE);
4084 * Increment counters.
4086 if ((new_l2 & ATTR_SW_WIRED) != 0)
4087 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
4088 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
4091 * Map the superpage.
4093 pmap_store(l2, new_l2);
4096 atomic_add_long(&pmap_l2_mappings, 1);
4097 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
4100 return (KERN_SUCCESS);
4104 * Maps a sequence of resident pages belonging to the same object.
4105 * The sequence begins with the given page m_start. This page is
4106 * mapped at the given virtual address start. Each subsequent page is
4107 * mapped at a virtual address that is offset from start by the same
4108 * amount as the page is offset from m_start within the object. The
4109 * last page in the sequence is the page with the largest offset from
4110 * m_start that can be mapped at a virtual address less than the given
4111 * virtual address end. Not every virtual page between start and end
4112 * is mapped; only those for which a resident page exists with the
4113 * corresponding offset from m_start are mapped.
4116 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4117 vm_page_t m_start, vm_prot_t prot)
4119 struct rwlock *lock;
4122 vm_pindex_t diff, psize;
4124 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4126 psize = atop(end - start);
4131 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4132 va = start + ptoa(diff);
4133 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
4134 m->psind == 1 && pmap_ps_enabled(pmap) &&
4135 pmap_enter_2mpage(pmap, va, m, prot, &lock))
4136 m = &m[L2_SIZE / PAGE_SIZE - 1];
4138 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
4140 m = TAILQ_NEXT(m, listq);
4148 * this code makes some *MAJOR* assumptions:
4149 * 1. Current pmap & pmap exists.
4152 * 4. No page table pages.
4153 * but is *MUCH* faster than pmap_enter...
4157 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4159 struct rwlock *lock;
4163 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4170 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4171 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4174 pt_entry_t *l2, *l3, l3_val;
4178 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4179 (m->oflags & VPO_UNMANAGED) != 0,
4180 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4181 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4182 PMAP_ASSERT_STAGE1(pmap);
4184 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
4186 * In the case that a page table page is not
4187 * resident, we are creating it here.
4189 if (va < VM_MAXUSER_ADDRESS) {
4190 vm_pindex_t l2pindex;
4193 * Calculate pagetable page index
4195 l2pindex = pmap_l2_pindex(va);
4196 if (mpte && (mpte->pindex == l2pindex)) {
4202 pde = pmap_pde(pmap, va, &lvl);
4205 * If the page table page is mapped, we just increment
4206 * the hold count, and activate it. Otherwise, we
4207 * attempt to allocate a page table page. If this
4208 * attempt fails, we don't retry. Instead, we give up.
4211 l2 = pmap_l1_to_l2(pde, va);
4212 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
4216 if (lvl == 2 && pmap_load(pde) != 0) {
4218 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4222 * Pass NULL instead of the PV list lock
4223 * pointer, because we don't intend to sleep.
4225 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
4230 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4231 l3 = &l3[pmap_l3_index(va)];
4234 pde = pmap_pde(kernel_pmap, va, &lvl);
4235 KASSERT(pde != NULL,
4236 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
4239 ("pmap_enter_quick_locked: Invalid level %d", lvl));
4240 l3 = pmap_l2_to_l3(pde, va);
4244 * Abort if a mapping already exists.
4246 if (pmap_load(l3) != 0) {
4253 * Enter on the PV list if part of our managed memory.
4255 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4256 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4258 pmap_abort_ptp(pmap, va, mpte);
4263 * Increment counters
4265 pmap_resident_count_inc(pmap, 1);
4267 pa = VM_PAGE_TO_PHYS(m);
4268 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
4269 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
4270 if ((prot & VM_PROT_EXECUTE) == 0 ||
4271 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4272 l3_val |= ATTR_S1_XN;
4273 if (va < VM_MAXUSER_ADDRESS)
4274 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4276 l3_val |= ATTR_S1_UXN;
4277 if (pmap != kernel_pmap)
4278 l3_val |= ATTR_S1_nG;
4281 * Now validate mapping with RO protection
4283 if ((m->oflags & VPO_UNMANAGED) == 0) {
4284 l3_val |= ATTR_SW_MANAGED;
4288 /* Sync icache before the mapping is stored to PTE */
4289 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4290 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
4291 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4293 pmap_store(l3, l3_val);
4300 * This code maps large physical mmap regions into the
4301 * processor address space. Note that some shortcuts
4302 * are taken, but the code works.
4305 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4306 vm_pindex_t pindex, vm_size_t size)
4309 VM_OBJECT_ASSERT_WLOCKED(object);
4310 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4311 ("pmap_object_init_pt: non-device object"));
4315 * Clear the wired attribute from the mappings for the specified range of
4316 * addresses in the given pmap. Every valid mapping within that range
4317 * must have the wired attribute set. In contrast, invalid mappings
4318 * cannot have the wired attribute set, so they are ignored.
4320 * The wired attribute of the page table entry is not a hardware feature,
4321 * so there is no need to invalidate any TLB entries.
4324 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4326 vm_offset_t va_next;
4327 pd_entry_t *l0, *l1, *l2;
4331 for (; sva < eva; sva = va_next) {
4332 l0 = pmap_l0(pmap, sva);
4333 if (pmap_load(l0) == 0) {
4334 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4340 l1 = pmap_l0_to_l1(l0, sva);
4341 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4344 if (pmap_load(l1) == 0)
4347 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4348 KASSERT(va_next <= eva,
4349 ("partial update of non-transparent 1G page "
4350 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
4351 pmap_load(l1), sva, eva, va_next));
4352 MPASS(pmap != kernel_pmap);
4353 MPASS((pmap_load(l1) & (ATTR_SW_MANAGED |
4354 ATTR_SW_WIRED)) == ATTR_SW_WIRED);
4355 pmap_clear_bits(l1, ATTR_SW_WIRED);
4356 pmap->pm_stats.wired_count -= L1_SIZE / PAGE_SIZE;
4360 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4364 l2 = pmap_l1_to_l2(l1, sva);
4365 if (pmap_load(l2) == 0)
4368 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4369 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4370 panic("pmap_unwire: l2 %#jx is missing "
4371 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4374 * Are we unwiring the entire large page? If not,
4375 * demote the mapping and fall through.
4377 if (sva + L2_SIZE == va_next && eva >= va_next) {
4378 pmap_clear_bits(l2, ATTR_SW_WIRED);
4379 pmap->pm_stats.wired_count -= L2_SIZE /
4382 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4383 panic("pmap_unwire: demotion failed");
4385 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4386 ("pmap_unwire: Invalid l2 entry after demotion"));
4390 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4392 if (pmap_load(l3) == 0)
4394 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4395 panic("pmap_unwire: l3 %#jx is missing "
4396 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4399 * ATTR_SW_WIRED must be cleared atomically. Although
4400 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4401 * the System MMU may write to the entry concurrently.
4403 pmap_clear_bits(l3, ATTR_SW_WIRED);
4404 pmap->pm_stats.wired_count--;
4411 * Copy the range specified by src_addr/len
4412 * from the source map to the range dst_addr/len
4413 * in the destination map.
4415 * This routine is only advisory and need not do anything.
4417 * Because the executable mappings created by this routine are copied,
4418 * it should not have to flush the instruction cache.
4421 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4422 vm_offset_t src_addr)
4424 struct rwlock *lock;
4425 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4426 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4427 vm_offset_t addr, end_addr, va_next;
4428 vm_page_t dst_m, dstmpte, srcmpte;
4430 PMAP_ASSERT_STAGE1(dst_pmap);
4431 PMAP_ASSERT_STAGE1(src_pmap);
4433 if (dst_addr != src_addr)
4435 end_addr = src_addr + len;
4437 if (dst_pmap < src_pmap) {
4438 PMAP_LOCK(dst_pmap);
4439 PMAP_LOCK(src_pmap);
4441 PMAP_LOCK(src_pmap);
4442 PMAP_LOCK(dst_pmap);
4444 for (addr = src_addr; addr < end_addr; addr = va_next) {
4445 l0 = pmap_l0(src_pmap, addr);
4446 if (pmap_load(l0) == 0) {
4447 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4453 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4456 l1 = pmap_l0_to_l1(l0, addr);
4457 if (pmap_load(l1) == 0)
4459 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4460 KASSERT(va_next <= end_addr,
4461 ("partial update of non-transparent 1G page "
4462 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4463 pmap_load(l1), addr, end_addr, va_next));
4464 srcptepaddr = pmap_load(l1);
4465 l1 = pmap_l1(dst_pmap, addr);
4467 if (_pmap_alloc_l3(dst_pmap,
4468 pmap_l0_pindex(addr), NULL) == NULL)
4470 l1 = pmap_l1(dst_pmap, addr);
4472 l0 = pmap_l0(dst_pmap, addr);
4473 dst_m = PHYS_TO_VM_PAGE(pmap_load(l0) &
4477 KASSERT(pmap_load(l1) == 0,
4478 ("1G mapping present in dst pmap "
4479 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4480 pmap_load(l1), addr, end_addr, va_next));
4481 pmap_store(l1, srcptepaddr & ~ATTR_SW_WIRED);
4482 pmap_resident_count_inc(dst_pmap, L1_SIZE / PAGE_SIZE);
4486 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4489 l2 = pmap_l1_to_l2(l1, addr);
4490 srcptepaddr = pmap_load(l2);
4491 if (srcptepaddr == 0)
4493 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4494 if ((addr & L2_OFFSET) != 0 ||
4495 addr + L2_SIZE > end_addr)
4497 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_m, NULL);
4500 if (pmap_load(l2) == 0 &&
4501 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4502 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4503 PMAP_ENTER_NORECLAIM, &lock))) {
4504 mask = ATTR_AF | ATTR_SW_WIRED;
4506 if ((srcptepaddr & ATTR_SW_DBM) != 0)
4507 nbits |= ATTR_S1_AP_RW_BIT;
4508 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
4509 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4511 atomic_add_long(&pmap_l2_mappings, 1);
4513 pmap_abort_ptp(dst_pmap, addr, dst_m);
4516 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4517 ("pmap_copy: invalid L2 entry"));
4518 srcptepaddr &= ~ATTR_MASK;
4519 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4520 KASSERT(srcmpte->ref_count > 0,
4521 ("pmap_copy: source page table page is unused"));
4522 if (va_next > end_addr)
4524 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4525 src_pte = &src_pte[pmap_l3_index(addr)];
4527 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4528 ptetemp = pmap_load(src_pte);
4531 * We only virtual copy managed pages.
4533 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4536 if (dstmpte != NULL) {
4537 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4538 ("dstmpte pindex/addr mismatch"));
4539 dstmpte->ref_count++;
4540 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4543 dst_pte = (pt_entry_t *)
4544 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4545 dst_pte = &dst_pte[pmap_l3_index(addr)];
4546 if (pmap_load(dst_pte) == 0 &&
4547 pmap_try_insert_pv_entry(dst_pmap, addr,
4548 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4550 * Clear the wired, modified, and accessed
4551 * (referenced) bits during the copy.
4553 mask = ATTR_AF | ATTR_SW_WIRED;
4555 if ((ptetemp & ATTR_SW_DBM) != 0)
4556 nbits |= ATTR_S1_AP_RW_BIT;
4557 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4558 pmap_resident_count_inc(dst_pmap, 1);
4560 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4563 /* Have we copied all of the valid mappings? */
4564 if (dstmpte->ref_count >= srcmpte->ref_count)
4570 * XXX This barrier may not be needed because the destination pmap is
4577 PMAP_UNLOCK(src_pmap);
4578 PMAP_UNLOCK(dst_pmap);
4582 * pmap_zero_page zeros the specified hardware page by mapping
4583 * the page into KVM and using bzero to clear its contents.
4586 pmap_zero_page(vm_page_t m)
4588 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4590 pagezero((void *)va);
4594 * pmap_zero_page_area zeros the specified hardware page by mapping
4595 * the page into KVM and using bzero to clear its contents.
4597 * off and size may not cover an area beyond a single hardware page.
4600 pmap_zero_page_area(vm_page_t m, int off, int size)
4602 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4604 if (off == 0 && size == PAGE_SIZE)
4605 pagezero((void *)va);
4607 bzero((char *)va + off, size);
4611 * pmap_copy_page copies the specified (machine independent)
4612 * page by mapping the page into virtual memory and using
4613 * bcopy to copy the page, one machine dependent page at a
4617 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4619 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4620 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4622 pagecopy((void *)src, (void *)dst);
4625 int unmapped_buf_allowed = 1;
4628 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4629 vm_offset_t b_offset, int xfersize)
4633 vm_paddr_t p_a, p_b;
4634 vm_offset_t a_pg_offset, b_pg_offset;
4637 while (xfersize > 0) {
4638 a_pg_offset = a_offset & PAGE_MASK;
4639 m_a = ma[a_offset >> PAGE_SHIFT];
4640 p_a = m_a->phys_addr;
4641 b_pg_offset = b_offset & PAGE_MASK;
4642 m_b = mb[b_offset >> PAGE_SHIFT];
4643 p_b = m_b->phys_addr;
4644 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4645 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4646 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4647 panic("!DMAP a %lx", p_a);
4649 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4651 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4652 panic("!DMAP b %lx", p_b);
4654 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4656 bcopy(a_cp, b_cp, cnt);
4664 pmap_quick_enter_page(vm_page_t m)
4667 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4671 pmap_quick_remove_page(vm_offset_t addr)
4676 * Returns true if the pmap's pv is one of the first
4677 * 16 pvs linked to from this page. This count may
4678 * be changed upwards or downwards in the future; it
4679 * is only necessary that true be returned for a small
4680 * subset of pmaps for proper page aging.
4683 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4685 struct md_page *pvh;
4686 struct rwlock *lock;
4691 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4692 ("pmap_page_exists_quick: page %p is not managed", m));
4694 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4696 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4697 if (PV_PMAP(pv) == pmap) {
4705 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4706 pvh = page_to_pvh(m);
4707 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4708 if (PV_PMAP(pv) == pmap) {
4722 * pmap_page_wired_mappings:
4724 * Return the number of managed mappings to the given physical page
4728 pmap_page_wired_mappings(vm_page_t m)
4730 struct rwlock *lock;
4731 struct md_page *pvh;
4735 int count, lvl, md_gen, pvh_gen;
4737 if ((m->oflags & VPO_UNMANAGED) != 0)
4739 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4743 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4745 if (!PMAP_TRYLOCK(pmap)) {
4746 md_gen = m->md.pv_gen;
4750 if (md_gen != m->md.pv_gen) {
4755 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4756 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4760 if ((m->flags & PG_FICTITIOUS) == 0) {
4761 pvh = page_to_pvh(m);
4762 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4764 if (!PMAP_TRYLOCK(pmap)) {
4765 md_gen = m->md.pv_gen;
4766 pvh_gen = pvh->pv_gen;
4770 if (md_gen != m->md.pv_gen ||
4771 pvh_gen != pvh->pv_gen) {
4776 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4778 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4788 * Returns true if the given page is mapped individually or as part of
4789 * a 2mpage. Otherwise, returns false.
4792 pmap_page_is_mapped(vm_page_t m)
4794 struct rwlock *lock;
4797 if ((m->oflags & VPO_UNMANAGED) != 0)
4799 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4801 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4802 ((m->flags & PG_FICTITIOUS) == 0 &&
4803 !TAILQ_EMPTY(&page_to_pvh(m)->pv_list));
4809 * Destroy all managed, non-wired mappings in the given user-space
4810 * pmap. This pmap cannot be active on any processor besides the
4813 * This function cannot be applied to the kernel pmap. Moreover, it
4814 * is not intended for general use. It is only to be used during
4815 * process termination. Consequently, it can be implemented in ways
4816 * that make it faster than pmap_remove(). First, it can more quickly
4817 * destroy mappings by iterating over the pmap's collection of PV
4818 * entries, rather than searching the page table. Second, it doesn't
4819 * have to test and clear the page table entries atomically, because
4820 * no processor is currently accessing the user address space. In
4821 * particular, a page table entry's dirty bit won't change state once
4822 * this function starts.
4825 pmap_remove_pages(pmap_t pmap)
4828 pt_entry_t *pte, tpte;
4829 struct spglist free;
4830 vm_page_t m, ml3, mt;
4832 struct md_page *pvh;
4833 struct pv_chunk *pc, *npc;
4834 struct rwlock *lock;
4836 uint64_t inuse, bitmask;
4837 int allfree, field, freed, idx, lvl;
4840 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4846 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4849 for (field = 0; field < _NPCM; field++) {
4850 inuse = ~pc->pc_map[field] & pc_freemask[field];
4851 while (inuse != 0) {
4852 bit = ffsl(inuse) - 1;
4853 bitmask = 1UL << bit;
4854 idx = field * 64 + bit;
4855 pv = &pc->pc_pventry[idx];
4858 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4859 KASSERT(pde != NULL,
4860 ("Attempting to remove an unmapped page"));
4864 pte = pmap_l1_to_l2(pde, pv->pv_va);
4865 tpte = pmap_load(pte);
4866 KASSERT((tpte & ATTR_DESCR_MASK) ==
4868 ("Attempting to remove an invalid "
4869 "block: %lx", tpte));
4872 pte = pmap_l2_to_l3(pde, pv->pv_va);
4873 tpte = pmap_load(pte);
4874 KASSERT((tpte & ATTR_DESCR_MASK) ==
4876 ("Attempting to remove an invalid "
4877 "page: %lx", tpte));
4881 "Invalid page directory level: %d",
4886 * We cannot remove wired pages from a process' mapping at this time
4888 if (tpte & ATTR_SW_WIRED) {
4893 pa = tpte & ~ATTR_MASK;
4895 m = PHYS_TO_VM_PAGE(pa);
4896 KASSERT(m->phys_addr == pa,
4897 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4898 m, (uintmax_t)m->phys_addr,
4901 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4902 m < &vm_page_array[vm_page_array_size],
4903 ("pmap_remove_pages: bad pte %#jx",
4907 * Because this pmap is not active on other
4908 * processors, the dirty bit cannot have
4909 * changed state since we last loaded pte.
4914 * Update the vm_page_t clean/reference bits.
4916 if (pmap_pte_dirty(pmap, tpte)) {
4919 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4928 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4931 pc->pc_map[field] |= bitmask;
4934 pmap_resident_count_dec(pmap,
4935 L2_SIZE / PAGE_SIZE);
4936 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4937 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4939 if (TAILQ_EMPTY(&pvh->pv_list)) {
4940 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4941 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
4942 TAILQ_EMPTY(&mt->md.pv_list))
4943 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4945 ml3 = pmap_remove_pt_page(pmap,
4948 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4949 ("pmap_remove_pages: l3 page not promoted"));
4950 pmap_resident_count_dec(pmap,1);
4951 KASSERT(ml3->ref_count == NL3PG,
4952 ("pmap_remove_pages: l3 page ref count error"));
4954 pmap_add_delayed_free_list(ml3,
4959 pmap_resident_count_dec(pmap, 1);
4960 TAILQ_REMOVE(&m->md.pv_list, pv,
4963 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
4964 TAILQ_EMPTY(&m->md.pv_list) &&
4965 (m->flags & PG_FICTITIOUS) == 0) {
4966 pvh = page_to_pvh(m);
4967 if (TAILQ_EMPTY(&pvh->pv_list))
4968 vm_page_aflag_clear(m,
4973 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4978 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4979 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4980 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4982 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4988 pmap_invalidate_all(pmap);
4990 vm_page_free_pages_toq(&free, true);
4994 * This is used to check if a page has been accessed or modified.
4997 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4999 struct rwlock *lock;
5001 struct md_page *pvh;
5002 pt_entry_t *pte, mask, value;
5004 int lvl, md_gen, pvh_gen;
5008 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5011 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5013 PMAP_ASSERT_STAGE1(pmap);
5014 if (!PMAP_TRYLOCK(pmap)) {
5015 md_gen = m->md.pv_gen;
5019 if (md_gen != m->md.pv_gen) {
5024 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5026 ("pmap_page_test_mappings: Invalid level %d", lvl));
5030 mask |= ATTR_S1_AP_RW_BIT;
5031 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5034 mask |= ATTR_AF | ATTR_DESCR_MASK;
5035 value |= ATTR_AF | L3_PAGE;
5037 rv = (pmap_load(pte) & mask) == value;
5042 if ((m->flags & PG_FICTITIOUS) == 0) {
5043 pvh = page_to_pvh(m);
5044 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5046 PMAP_ASSERT_STAGE1(pmap);
5047 if (!PMAP_TRYLOCK(pmap)) {
5048 md_gen = m->md.pv_gen;
5049 pvh_gen = pvh->pv_gen;
5053 if (md_gen != m->md.pv_gen ||
5054 pvh_gen != pvh->pv_gen) {
5059 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5061 ("pmap_page_test_mappings: Invalid level %d", lvl));
5065 mask |= ATTR_S1_AP_RW_BIT;
5066 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5069 mask |= ATTR_AF | ATTR_DESCR_MASK;
5070 value |= ATTR_AF | L2_BLOCK;
5072 rv = (pmap_load(pte) & mask) == value;
5086 * Return whether or not the specified physical page was modified
5087 * in any physical maps.
5090 pmap_is_modified(vm_page_t m)
5093 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5094 ("pmap_is_modified: page %p is not managed", m));
5097 * If the page is not busied then this check is racy.
5099 if (!pmap_page_is_write_mapped(m))
5101 return (pmap_page_test_mappings(m, FALSE, TRUE));
5105 * pmap_is_prefaultable:
5107 * Return whether or not the specified virtual address is eligible
5111 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5119 pte = pmap_pte(pmap, addr, &lvl);
5120 if (pte != NULL && pmap_load(pte) != 0) {
5128 * pmap_is_referenced:
5130 * Return whether or not the specified physical page was referenced
5131 * in any physical maps.
5134 pmap_is_referenced(vm_page_t m)
5137 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5138 ("pmap_is_referenced: page %p is not managed", m));
5139 return (pmap_page_test_mappings(m, TRUE, FALSE));
5143 * Clear the write and modified bits in each of the given page's mappings.
5146 pmap_remove_write(vm_page_t m)
5148 struct md_page *pvh;
5150 struct rwlock *lock;
5151 pv_entry_t next_pv, pv;
5152 pt_entry_t oldpte, *pte;
5154 int lvl, md_gen, pvh_gen;
5156 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5157 ("pmap_remove_write: page %p is not managed", m));
5158 vm_page_assert_busied(m);
5160 if (!pmap_page_is_write_mapped(m))
5162 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5163 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5166 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5168 PMAP_ASSERT_STAGE1(pmap);
5169 if (!PMAP_TRYLOCK(pmap)) {
5170 pvh_gen = pvh->pv_gen;
5174 if (pvh_gen != pvh->pv_gen) {
5181 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5182 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
5183 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
5184 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5185 ("inconsistent pv lock %p %p for page %p",
5186 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5189 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5191 PMAP_ASSERT_STAGE1(pmap);
5192 if (!PMAP_TRYLOCK(pmap)) {
5193 pvh_gen = pvh->pv_gen;
5194 md_gen = m->md.pv_gen;
5198 if (pvh_gen != pvh->pv_gen ||
5199 md_gen != m->md.pv_gen) {
5205 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5206 oldpte = pmap_load(pte);
5208 if ((oldpte & ATTR_SW_DBM) != 0) {
5209 if (!atomic_fcmpset_long(pte, &oldpte,
5210 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
5212 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
5213 ATTR_S1_AP(ATTR_S1_AP_RW))
5215 pmap_invalidate_page(pmap, pv->pv_va);
5220 vm_page_aflag_clear(m, PGA_WRITEABLE);
5224 * pmap_ts_referenced:
5226 * Return a count of reference bits for a page, clearing those bits.
5227 * It is not necessary for every reference bit to be cleared, but it
5228 * is necessary that 0 only be returned when there are truly no
5229 * reference bits set.
5231 * As an optimization, update the page's dirty field if a modified bit is
5232 * found while counting reference bits. This opportunistic update can be
5233 * performed at low cost and can eliminate the need for some future calls
5234 * to pmap_is_modified(). However, since this function stops after
5235 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5236 * dirty pages. Those dirty pages will only be detected by a future call
5237 * to pmap_is_modified().
5240 pmap_ts_referenced(vm_page_t m)
5242 struct md_page *pvh;
5245 struct rwlock *lock;
5246 pd_entry_t *pde, tpde;
5247 pt_entry_t *pte, tpte;
5250 int cleared, lvl, md_gen, not_cleared, pvh_gen;
5251 struct spglist free;
5253 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5254 ("pmap_ts_referenced: page %p is not managed", m));
5257 pa = VM_PAGE_TO_PHYS(m);
5258 lock = PHYS_TO_PV_LIST_LOCK(pa);
5259 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5263 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5264 goto small_mappings;
5270 if (!PMAP_TRYLOCK(pmap)) {
5271 pvh_gen = pvh->pv_gen;
5275 if (pvh_gen != pvh->pv_gen) {
5281 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5282 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
5284 ("pmap_ts_referenced: invalid pde level %d", lvl));
5285 tpde = pmap_load(pde);
5286 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
5287 ("pmap_ts_referenced: found an invalid l1 table"));
5288 pte = pmap_l1_to_l2(pde, pv->pv_va);
5289 tpte = pmap_load(pte);
5290 if (pmap_pte_dirty(pmap, tpte)) {
5292 * Although "tpte" is mapping a 2MB page, because
5293 * this function is called at a 4KB page granularity,
5294 * we only update the 4KB page under test.
5299 if ((tpte & ATTR_AF) != 0) {
5301 * Since this reference bit is shared by 512 4KB pages,
5302 * it should not be cleared every time it is tested.
5303 * Apply a simple "hash" function on the physical page
5304 * number, the virtual superpage number, and the pmap
5305 * address to select one 4KB page out of the 512 on
5306 * which testing the reference bit will result in
5307 * clearing that reference bit. This function is
5308 * designed to avoid the selection of the same 4KB page
5309 * for every 2MB page mapping.
5311 * On demotion, a mapping that hasn't been referenced
5312 * is simply destroyed. To avoid the possibility of a
5313 * subsequent page fault on a demoted wired mapping,
5314 * always leave its reference bit set. Moreover,
5315 * since the superpage is wired, the current state of
5316 * its reference bit won't affect page replacement.
5318 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
5319 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
5320 (tpte & ATTR_SW_WIRED) == 0) {
5321 pmap_clear_bits(pte, ATTR_AF);
5322 pmap_invalidate_page(pmap, pv->pv_va);
5328 /* Rotate the PV list if it has more than one entry. */
5329 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5330 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5331 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5334 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5336 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5338 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5345 if (!PMAP_TRYLOCK(pmap)) {
5346 pvh_gen = pvh->pv_gen;
5347 md_gen = m->md.pv_gen;
5351 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5356 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5357 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
5359 ("pmap_ts_referenced: invalid pde level %d", lvl));
5360 tpde = pmap_load(pde);
5361 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
5362 ("pmap_ts_referenced: found an invalid l2 table"));
5363 pte = pmap_l2_to_l3(pde, pv->pv_va);
5364 tpte = pmap_load(pte);
5365 if (pmap_pte_dirty(pmap, tpte))
5367 if ((tpte & ATTR_AF) != 0) {
5368 if ((tpte & ATTR_SW_WIRED) == 0) {
5369 pmap_clear_bits(pte, ATTR_AF);
5370 pmap_invalidate_page(pmap, pv->pv_va);
5376 /* Rotate the PV list if it has more than one entry. */
5377 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5378 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5379 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5382 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5383 not_cleared < PMAP_TS_REFERENCED_MAX);
5386 vm_page_free_pages_toq(&free, true);
5387 return (cleared + not_cleared);
5391 * Apply the given advice to the specified range of addresses within the
5392 * given pmap. Depending on the advice, clear the referenced and/or
5393 * modified flags in each mapping and set the mapped page's dirty field.
5396 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5398 struct rwlock *lock;
5399 vm_offset_t va, va_next;
5401 pd_entry_t *l0, *l1, *l2, oldl2;
5402 pt_entry_t *l3, oldl3;
5404 PMAP_ASSERT_STAGE1(pmap);
5406 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5410 for (; sva < eva; sva = va_next) {
5411 l0 = pmap_l0(pmap, sva);
5412 if (pmap_load(l0) == 0) {
5413 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5419 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5422 l1 = pmap_l0_to_l1(l0, sva);
5423 if (pmap_load(l1) == 0)
5425 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
5426 KASSERT(va_next <= eva,
5427 ("partial update of non-transparent 1G page "
5428 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
5429 pmap_load(l1), sva, eva, va_next));
5433 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5436 l2 = pmap_l1_to_l2(l1, sva);
5437 oldl2 = pmap_load(l2);
5440 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5441 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5444 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5449 * The 2MB page mapping was destroyed.
5455 * Unless the page mappings are wired, remove the
5456 * mapping to a single page so that a subsequent
5457 * access may repromote. Choosing the last page
5458 * within the address range [sva, min(va_next, eva))
5459 * generally results in more repromotions. Since the
5460 * underlying page table page is fully populated, this
5461 * removal never frees a page table page.
5463 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5469 ("pmap_advise: no address gap"));
5470 l3 = pmap_l2_to_l3(l2, va);
5471 KASSERT(pmap_load(l3) != 0,
5472 ("pmap_advise: invalid PTE"));
5473 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5479 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5480 ("pmap_advise: invalid L2 entry after demotion"));
5484 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5486 oldl3 = pmap_load(l3);
5487 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5488 (ATTR_SW_MANAGED | L3_PAGE))
5490 else if (pmap_pte_dirty(pmap, oldl3)) {
5491 if (advice == MADV_DONTNEED) {
5493 * Future calls to pmap_is_modified()
5494 * can be avoided by making the page
5497 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5500 while (!atomic_fcmpset_long(l3, &oldl3,
5501 (oldl3 & ~ATTR_AF) |
5502 ATTR_S1_AP(ATTR_S1_AP_RO)))
5504 } else if ((oldl3 & ATTR_AF) != 0)
5505 pmap_clear_bits(l3, ATTR_AF);
5512 if (va != va_next) {
5513 pmap_invalidate_range(pmap, va, sva);
5518 pmap_invalidate_range(pmap, va, sva);
5524 * Clear the modify bits on the specified physical page.
5527 pmap_clear_modify(vm_page_t m)
5529 struct md_page *pvh;
5530 struct rwlock *lock;
5532 pv_entry_t next_pv, pv;
5533 pd_entry_t *l2, oldl2;
5534 pt_entry_t *l3, oldl3;
5536 int md_gen, pvh_gen;
5538 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5539 ("pmap_clear_modify: page %p is not managed", m));
5540 vm_page_assert_busied(m);
5542 if (!pmap_page_is_write_mapped(m))
5544 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5545 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5548 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5550 PMAP_ASSERT_STAGE1(pmap);
5551 if (!PMAP_TRYLOCK(pmap)) {
5552 pvh_gen = pvh->pv_gen;
5556 if (pvh_gen != pvh->pv_gen) {
5562 l2 = pmap_l2(pmap, va);
5563 oldl2 = pmap_load(l2);
5564 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5565 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5566 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5567 (oldl2 & ATTR_SW_WIRED) == 0) {
5569 * Write protect the mapping to a single page so that
5570 * a subsequent write access may repromote.
5572 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5573 l3 = pmap_l2_to_l3(l2, va);
5574 oldl3 = pmap_load(l3);
5575 while (!atomic_fcmpset_long(l3, &oldl3,
5576 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
5579 pmap_invalidate_page(pmap, va);
5583 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5585 PMAP_ASSERT_STAGE1(pmap);
5586 if (!PMAP_TRYLOCK(pmap)) {
5587 md_gen = m->md.pv_gen;
5588 pvh_gen = pvh->pv_gen;
5592 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5597 l2 = pmap_l2(pmap, pv->pv_va);
5598 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5599 oldl3 = pmap_load(l3);
5600 if (pmap_l3_valid(oldl3) &&
5601 (oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
5602 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
5603 pmap_invalidate_page(pmap, pv->pv_va);
5611 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5613 struct pmap_preinit_mapping *ppim;
5614 vm_offset_t va, offset;
5617 int i, lvl, l2_blocks, free_l2_count, start_idx;
5619 if (!vm_initialized) {
5621 * No L3 ptables so map entire L2 blocks where start VA is:
5622 * preinit_map_va + start_idx * L2_SIZE
5623 * There may be duplicate mappings (multiple VA -> same PA) but
5624 * ARM64 dcache is always PIPT so that's acceptable.
5629 /* Calculate how many L2 blocks are needed for the mapping */
5630 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5631 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5633 offset = pa & L2_OFFSET;
5635 if (preinit_map_va == 0)
5638 /* Map 2MiB L2 blocks from reserved VA space */
5642 /* Find enough free contiguous VA space */
5643 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5644 ppim = pmap_preinit_mapping + i;
5645 if (free_l2_count > 0 && ppim->pa != 0) {
5646 /* Not enough space here */
5652 if (ppim->pa == 0) {
5654 if (start_idx == -1)
5657 if (free_l2_count == l2_blocks)
5661 if (free_l2_count != l2_blocks)
5662 panic("%s: too many preinit mappings", __func__);
5664 va = preinit_map_va + (start_idx * L2_SIZE);
5665 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5666 /* Mark entries as allocated */
5667 ppim = pmap_preinit_mapping + i;
5669 ppim->va = va + offset;
5674 pa = rounddown2(pa, L2_SIZE);
5675 for (i = 0; i < l2_blocks; i++) {
5676 pde = pmap_pde(kernel_pmap, va, &lvl);
5677 KASSERT(pde != NULL,
5678 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5681 ("pmap_mapbios: Invalid level %d", lvl));
5683 /* Insert L2_BLOCK */
5684 l2 = pmap_l1_to_l2(pde, va);
5686 pa | ATTR_DEFAULT | ATTR_S1_XN |
5687 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5692 pmap_invalidate_all(kernel_pmap);
5694 va = preinit_map_va + (start_idx * L2_SIZE);
5697 /* kva_alloc may be used to map the pages */
5698 offset = pa & PAGE_MASK;
5699 size = round_page(offset + size);
5701 va = kva_alloc(size);
5703 panic("%s: Couldn't allocate KVA", __func__);
5705 pde = pmap_pde(kernel_pmap, va, &lvl);
5706 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5708 /* L3 table is linked */
5709 va = trunc_page(va);
5710 pa = trunc_page(pa);
5711 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
5714 return ((void *)(va + offset));
5718 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5720 struct pmap_preinit_mapping *ppim;
5721 vm_offset_t offset, tmpsize, va_trunc;
5724 int i, lvl, l2_blocks, block;
5728 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5729 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5731 /* Remove preinit mapping */
5732 preinit_map = false;
5734 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5735 ppim = pmap_preinit_mapping + i;
5736 if (ppim->va == va) {
5737 KASSERT(ppim->size == size,
5738 ("pmap_unmapbios: size mismatch"));
5743 offset = block * L2_SIZE;
5744 va_trunc = rounddown2(va, L2_SIZE) + offset;
5746 /* Remove L2_BLOCK */
5747 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5748 KASSERT(pde != NULL,
5749 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5751 l2 = pmap_l1_to_l2(pde, va_trunc);
5754 if (block == (l2_blocks - 1))
5760 pmap_invalidate_all(kernel_pmap);
5764 /* Unmap the pages reserved with kva_alloc. */
5765 if (vm_initialized) {
5766 offset = va & PAGE_MASK;
5767 size = round_page(offset + size);
5768 va = trunc_page(va);
5770 pde = pmap_pde(kernel_pmap, va, &lvl);
5771 KASSERT(pde != NULL,
5772 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5773 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5775 /* Unmap and invalidate the pages */
5776 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5777 pmap_kremove(va + tmpsize);
5784 * Sets the memory attribute for the specified page.
5787 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5790 m->md.pv_memattr = ma;
5793 * If "m" is a normal page, update its direct mapping. This update
5794 * can be relied upon to perform any cache operations that are
5795 * required for data coherence.
5797 if ((m->flags & PG_FICTITIOUS) == 0 &&
5798 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5799 m->md.pv_memattr) != 0)
5800 panic("memory attribute change on the direct map failed");
5804 * Changes the specified virtual address range's memory type to that given by
5805 * the parameter "mode". The specified virtual address range must be
5806 * completely contained within either the direct map or the kernel map. If
5807 * the virtual address range is contained within the kernel map, then the
5808 * memory type for each of the corresponding ranges of the direct map is also
5809 * changed. (The corresponding ranges of the direct map are those ranges that
5810 * map the same physical pages as the specified virtual address range.) These
5811 * changes to the direct map are necessary because Intel describes the
5812 * behavior of their processors as "undefined" if two or more mappings to the
5813 * same physical page have different memory types.
5815 * Returns zero if the change completed successfully, and either EINVAL or
5816 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5817 * of the virtual address range was not mapped, and ENOMEM is returned if
5818 * there was insufficient memory available to complete the change. In the
5819 * latter case, the memory type may have been changed on some part of the
5820 * virtual address range or the direct map.
5823 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5827 PMAP_LOCK(kernel_pmap);
5828 error = pmap_change_attr_locked(va, size, mode);
5829 PMAP_UNLOCK(kernel_pmap);
5834 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5836 vm_offset_t base, offset, tmpva;
5837 pt_entry_t l3, *pte, *newpte;
5840 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5841 base = trunc_page(va);
5842 offset = va & PAGE_MASK;
5843 size = round_page(offset + size);
5845 if (!VIRT_IN_DMAP(base) &&
5846 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
5849 for (tmpva = base; tmpva < base + size; ) {
5850 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5854 if ((pmap_load(pte) & ATTR_S1_IDX_MASK) == ATTR_S1_IDX(mode)) {
5856 * We already have the correct attribute,
5857 * ignore this entry.
5861 panic("Invalid DMAP table level: %d\n", lvl);
5863 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5866 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5874 * Split the entry to an level 3 table, then
5875 * set the new attribute.
5879 panic("Invalid DMAP table level: %d\n", lvl);
5881 newpte = pmap_demote_l1(kernel_pmap, pte,
5882 tmpva & ~L1_OFFSET);
5885 pte = pmap_l1_to_l2(pte, tmpva);
5887 newpte = pmap_demote_l2(kernel_pmap, pte,
5891 pte = pmap_l2_to_l3(pte, tmpva);
5893 /* Update the entry */
5894 l3 = pmap_load(pte);
5895 l3 &= ~ATTR_S1_IDX_MASK;
5896 l3 |= ATTR_S1_IDX(mode);
5897 if (mode == VM_MEMATTR_DEVICE)
5900 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5904 * If moving to a non-cacheable entry flush
5907 if (mode == VM_MEMATTR_UNCACHEABLE)
5908 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5920 * Create an L2 table to map all addresses within an L1 mapping.
5923 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5925 pt_entry_t *l2, newl2, oldl1;
5927 vm_paddr_t l2phys, phys;
5931 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5932 oldl1 = pmap_load(l1);
5933 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5934 ("pmap_demote_l1: Demoting a non-block entry"));
5935 KASSERT((va & L1_OFFSET) == 0,
5936 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5937 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5938 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5941 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5942 tmpl1 = kva_alloc(PAGE_SIZE);
5947 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5948 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5949 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5950 " in pmap %p", va, pmap);
5954 l2phys = VM_PAGE_TO_PHYS(ml2);
5955 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5957 /* Address the range points at */
5958 phys = oldl1 & ~ATTR_MASK;
5959 /* The attributed from the old l1 table to be copied */
5960 newl2 = oldl1 & ATTR_MASK;
5962 /* Create the new entries */
5963 for (i = 0; i < Ln_ENTRIES; i++) {
5964 l2[i] = newl2 | phys;
5967 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5968 ("Invalid l2 page (%lx != %lx)", l2[0],
5969 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5972 pmap_kenter(tmpl1, PAGE_SIZE,
5973 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
5974 VM_MEMATTR_WRITE_BACK);
5975 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5978 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5981 pmap_kremove(tmpl1);
5982 kva_free(tmpl1, PAGE_SIZE);
5989 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5993 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
6000 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
6001 struct rwlock **lockp)
6003 struct spglist free;
6006 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
6008 vm_page_free_pages_toq(&free, true);
6012 * Create an L3 table to map all addresses within an L2 mapping.
6015 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
6016 struct rwlock **lockp)
6018 pt_entry_t *l3, newl3, oldl2;
6023 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6024 PMAP_ASSERT_STAGE1(pmap);
6026 oldl2 = pmap_load(l2);
6027 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
6028 ("pmap_demote_l2: Demoting a non-block entry"));
6032 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
6033 tmpl2 = kva_alloc(PAGE_SIZE);
6039 * Invalidate the 2MB page mapping and return "failure" if the
6040 * mapping was never accessed.
6042 if ((oldl2 & ATTR_AF) == 0) {
6043 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6044 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
6045 pmap_demote_l2_abort(pmap, va, l2, lockp);
6046 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
6051 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
6052 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6053 ("pmap_demote_l2: page table page for a wired mapping"
6057 * If the page table page is missing and the mapping
6058 * is for a kernel address, the mapping must belong to
6059 * the direct map. Page table pages are preallocated
6060 * for every other part of the kernel address space,
6061 * so the direct map region is the only part of the
6062 * kernel address space that must be handled here.
6064 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
6065 ("pmap_demote_l2: No saved mpte for va %#lx", va));
6068 * If the 2MB page mapping belongs to the direct map
6069 * region of the kernel's address space, then the page
6070 * allocation request specifies the highest possible
6071 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
6072 * priority is normal.
6074 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
6075 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
6076 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
6079 * If the allocation of the new page table page fails,
6080 * invalidate the 2MB page mapping and return "failure".
6083 pmap_demote_l2_abort(pmap, va, l2, lockp);
6084 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
6085 " in pmap %p", va, pmap);
6089 if (va < VM_MAXUSER_ADDRESS) {
6090 ml3->ref_count = NL3PG;
6091 pmap_resident_count_inc(pmap, 1);
6094 l3phys = VM_PAGE_TO_PHYS(ml3);
6095 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
6096 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
6097 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
6098 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
6099 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
6102 * If the page table page is not leftover from an earlier promotion,
6103 * or the mapping attributes have changed, (re)initialize the L3 table.
6105 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
6106 * performs a dsb(). That dsb() ensures that the stores for filling
6107 * "l3" are visible before "l3" is added to the page table.
6109 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
6110 pmap_fill_l3(l3, newl3);
6113 * Map the temporary page so we don't lose access to the l2 table.
6116 pmap_kenter(tmpl2, PAGE_SIZE,
6117 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
6118 VM_MEMATTR_WRITE_BACK);
6119 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
6123 * The spare PV entries must be reserved prior to demoting the
6124 * mapping, that is, prior to changing the PDE. Otherwise, the state
6125 * of the L2 and the PV lists will be inconsistent, which can result
6126 * in reclaim_pv_chunk() attempting to remove a PV entry from the
6127 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
6128 * PV entry for the 2MB page mapping that is being demoted.
6130 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6131 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
6134 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
6135 * the 2MB page mapping.
6137 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
6140 * Demote the PV entry.
6142 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6143 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
6145 atomic_add_long(&pmap_l2_demotions, 1);
6146 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
6147 " in pmap %p %lx", va, pmap, l3[0]);
6151 pmap_kremove(tmpl2);
6152 kva_free(tmpl2, PAGE_SIZE);
6160 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
6162 struct rwlock *lock;
6166 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
6173 * Perform the pmap work for mincore(2). If the page is not both referenced and
6174 * modified by this pmap, returns its physical address so that the caller can
6175 * find other mappings.
6178 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
6180 pt_entry_t *pte, tpte;
6181 vm_paddr_t mask, pa;
6185 PMAP_ASSERT_STAGE1(pmap);
6187 pte = pmap_pte(pmap, addr, &lvl);
6189 tpte = pmap_load(pte);
6202 panic("pmap_mincore: invalid level %d", lvl);
6205 managed = (tpte & ATTR_SW_MANAGED) != 0;
6206 val = MINCORE_INCORE;
6208 val |= MINCORE_PSIND(3 - lvl);
6209 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
6210 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
6211 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6212 if ((tpte & ATTR_AF) == ATTR_AF)
6213 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6215 pa = (tpte & ~ATTR_MASK) | (addr & mask);
6221 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6222 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6230 * Garbage collect every ASID that is neither active on a processor nor
6234 pmap_reset_asid_set(pmap_t pmap)
6237 int asid, cpuid, epoch;
6238 struct asid_set *set;
6239 enum pmap_stage stage;
6241 set = pmap->pm_asid_set;
6242 stage = pmap->pm_stage;
6244 set = pmap->pm_asid_set;
6245 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6246 mtx_assert(&set->asid_set_mutex, MA_OWNED);
6249 * Ensure that the store to asid_epoch is globally visible before the
6250 * loads from pc_curpmap are performed.
6252 epoch = set->asid_epoch + 1;
6253 if (epoch == INT_MAX)
6255 set->asid_epoch = epoch;
6257 if (stage == PM_STAGE1) {
6258 __asm __volatile("tlbi vmalle1is");
6260 KASSERT(pmap_clean_stage2_tlbi != NULL,
6261 ("%s: Unset stage 2 tlb invalidation callback\n",
6263 pmap_clean_stage2_tlbi();
6266 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
6267 set->asid_set_size - 1);
6268 CPU_FOREACH(cpuid) {
6269 if (cpuid == curcpu)
6271 if (stage == PM_STAGE1) {
6272 curpmap = pcpu_find(cpuid)->pc_curpmap;
6273 PMAP_ASSERT_STAGE1(pmap);
6275 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
6276 if (curpmap == NULL)
6278 PMAP_ASSERT_STAGE2(pmap);
6280 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
6281 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
6284 bit_set(set->asid_set, asid);
6285 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
6290 * Allocate a new ASID for the specified pmap.
6293 pmap_alloc_asid(pmap_t pmap)
6295 struct asid_set *set;
6298 set = pmap->pm_asid_set;
6299 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6301 mtx_lock_spin(&set->asid_set_mutex);
6304 * While this processor was waiting to acquire the asid set mutex,
6305 * pmap_reset_asid_set() running on another processor might have
6306 * updated this pmap's cookie to the current epoch. In which case, we
6307 * don't need to allocate a new ASID.
6309 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
6312 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
6314 if (new_asid == -1) {
6315 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6316 set->asid_next, &new_asid);
6317 if (new_asid == -1) {
6318 pmap_reset_asid_set(pmap);
6319 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6320 set->asid_set_size, &new_asid);
6321 KASSERT(new_asid != -1, ("ASID allocation failure"));
6324 bit_set(set->asid_set, new_asid);
6325 set->asid_next = new_asid + 1;
6326 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
6328 mtx_unlock_spin(&set->asid_set_mutex);
6332 * Compute the value that should be stored in ttbr0 to activate the specified
6333 * pmap. This value may change from time to time.
6336 pmap_to_ttbr0(pmap_t pmap)
6339 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
6344 pmap_activate_int(pmap_t pmap)
6346 struct asid_set *set;
6349 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
6350 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
6352 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
6353 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
6355 * Handle the possibility that the old thread was preempted
6356 * after an "ic" or "tlbi" instruction but before it performed
6357 * a "dsb" instruction. If the old thread migrates to a new
6358 * processor, its completion of a "dsb" instruction on that
6359 * new processor does not guarantee that the "ic" or "tlbi"
6360 * instructions performed on the old processor have completed.
6366 set = pmap->pm_asid_set;
6367 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6370 * Ensure that the store to curpmap is globally visible before the
6371 * load from asid_epoch is performed.
6373 if (pmap->pm_stage == PM_STAGE1)
6374 PCPU_SET(curpmap, pmap);
6376 PCPU_SET(curvmpmap, pmap);
6378 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
6379 if (epoch >= 0 && epoch != set->asid_epoch)
6380 pmap_alloc_asid(pmap);
6382 if (pmap->pm_stage == PM_STAGE1) {
6383 set_ttbr0(pmap_to_ttbr0(pmap));
6384 if (PCPU_GET(bcast_tlbi_workaround) != 0)
6385 invalidate_local_icache();
6391 pmap_activate_vm(pmap_t pmap)
6394 PMAP_ASSERT_STAGE2(pmap);
6396 (void)pmap_activate_int(pmap);
6400 pmap_activate(struct thread *td)
6404 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6405 PMAP_ASSERT_STAGE1(pmap);
6407 (void)pmap_activate_int(pmap);
6412 * To eliminate the unused parameter "old", we would have to add an instruction
6416 pmap_switch(struct thread *old __unused, struct thread *new)
6418 pcpu_bp_harden bp_harden;
6421 /* Store the new curthread */
6422 PCPU_SET(curthread, new);
6424 /* And the new pcb */
6426 PCPU_SET(curpcb, pcb);
6429 * TODO: We may need to flush the cache here if switching
6430 * to a user process.
6433 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
6435 * Stop userspace from training the branch predictor against
6436 * other processes. This will call into a CPU specific
6437 * function that clears the branch predictor state.
6439 bp_harden = PCPU_GET(bp_harden);
6440 if (bp_harden != NULL)
6448 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
6451 PMAP_ASSERT_STAGE1(pmap);
6452 if (va >= VM_MIN_KERNEL_ADDRESS) {
6453 cpu_icache_sync_range(va, sz);
6458 /* Find the length of data in this page to flush */
6459 offset = va & PAGE_MASK;
6460 len = imin(PAGE_SIZE - offset, sz);
6463 /* Extract the physical address & find it in the DMAP */
6464 pa = pmap_extract(pmap, va);
6466 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
6468 /* Move to the next page */
6471 /* Set the length for the next iteration */
6472 len = imin(PAGE_SIZE, sz);
6478 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6481 pt_entry_t *ptep, pte;
6484 PMAP_ASSERT_STAGE2(pmap);
6487 /* Data and insn aborts use same encoding for FSC field. */
6488 dfsc = esr & ISS_DATA_DFSC_MASK;
6490 case ISS_DATA_DFSC_TF_L0:
6491 case ISS_DATA_DFSC_TF_L1:
6492 case ISS_DATA_DFSC_TF_L2:
6493 case ISS_DATA_DFSC_TF_L3:
6495 pdep = pmap_pde(pmap, far, &lvl);
6496 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
6503 ptep = pmap_l0_to_l1(pdep, far);
6506 ptep = pmap_l1_to_l2(pdep, far);
6509 ptep = pmap_l2_to_l3(pdep, far);
6512 panic("%s: Invalid pde level %d", __func__,lvl);
6516 case ISS_DATA_DFSC_AFF_L1:
6517 case ISS_DATA_DFSC_AFF_L2:
6518 case ISS_DATA_DFSC_AFF_L3:
6520 ptep = pmap_pte(pmap, far, &lvl);
6522 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
6524 pmap_invalidate_vpipt_icache();
6527 * If accessing an executable page invalidate
6528 * the I-cache so it will be valid when we
6529 * continue execution in the guest. The D-cache
6530 * is assumed to already be clean to the Point
6533 if ((pte & ATTR_S2_XN_MASK) !=
6534 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
6535 invalidate_icache();
6538 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
6549 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6551 pt_entry_t pte, *ptep;
6558 ec = ESR_ELx_EXCEPTION(esr);
6560 case EXCP_INSN_ABORT_L:
6561 case EXCP_INSN_ABORT:
6562 case EXCP_DATA_ABORT_L:
6563 case EXCP_DATA_ABORT:
6569 if (pmap->pm_stage == PM_STAGE2)
6570 return (pmap_stage2_fault(pmap, esr, far));
6572 /* Data and insn aborts use same encoding for FSC field. */
6573 switch (esr & ISS_DATA_DFSC_MASK) {
6574 case ISS_DATA_DFSC_AFF_L1:
6575 case ISS_DATA_DFSC_AFF_L2:
6576 case ISS_DATA_DFSC_AFF_L3:
6578 ptep = pmap_pte(pmap, far, &lvl);
6580 pmap_set_bits(ptep, ATTR_AF);
6583 * XXXMJ as an optimization we could mark the entry
6584 * dirty if this is a write fault.
6589 case ISS_DATA_DFSC_PF_L1:
6590 case ISS_DATA_DFSC_PF_L2:
6591 case ISS_DATA_DFSC_PF_L3:
6592 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6593 (esr & ISS_DATA_WnR) == 0)
6596 ptep = pmap_pte(pmap, far, &lvl);
6598 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6599 if ((pte & ATTR_S1_AP_RW_BIT) ==
6600 ATTR_S1_AP(ATTR_S1_AP_RO)) {
6601 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
6602 pmap_invalidate_page(pmap, far);
6608 case ISS_DATA_DFSC_TF_L0:
6609 case ISS_DATA_DFSC_TF_L1:
6610 case ISS_DATA_DFSC_TF_L2:
6611 case ISS_DATA_DFSC_TF_L3:
6613 * Retry the translation. A break-before-make sequence can
6614 * produce a transient fault.
6616 if (pmap == kernel_pmap) {
6618 * The translation fault may have occurred within a
6619 * critical section. Therefore, we must check the
6620 * address without acquiring the kernel pmap's lock.
6622 if (pmap_kextract(far) != 0)
6626 /* Ask the MMU to check the address. */
6627 intr = intr_disable();
6628 par = arm64_address_translate_s1e0r(far);
6633 * If the translation was successful, then we can
6634 * return success to the trap handler.
6636 if (PAR_SUCCESS(par))
6646 * Increase the starting virtual address of the given mapping if a
6647 * different alignment might result in more superpage mappings.
6650 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6651 vm_offset_t *addr, vm_size_t size)
6653 vm_offset_t superpage_offset;
6657 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6658 offset += ptoa(object->pg_color);
6659 superpage_offset = offset & L2_OFFSET;
6660 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6661 (*addr & L2_OFFSET) == superpage_offset)
6663 if ((*addr & L2_OFFSET) < superpage_offset)
6664 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6666 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6670 * Get the kernel virtual address of a set of physical pages. If there are
6671 * physical addresses not covered by the DMAP perform a transient mapping
6672 * that will be removed when calling pmap_unmap_io_transient.
6674 * \param page The pages the caller wishes to obtain the virtual
6675 * address on the kernel memory map.
6676 * \param vaddr On return contains the kernel virtual memory address
6677 * of the pages passed in the page parameter.
6678 * \param count Number of pages passed in.
6679 * \param can_fault TRUE if the thread using the mapped pages can take
6680 * page faults, FALSE otherwise.
6682 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6683 * finished or FALSE otherwise.
6687 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6688 boolean_t can_fault)
6691 boolean_t needs_mapping;
6695 * Allocate any KVA space that we need, this is done in a separate
6696 * loop to prevent calling vmem_alloc while pinned.
6698 needs_mapping = FALSE;
6699 for (i = 0; i < count; i++) {
6700 paddr = VM_PAGE_TO_PHYS(page[i]);
6701 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6702 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6703 M_BESTFIT | M_WAITOK, &vaddr[i]);
6704 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6705 needs_mapping = TRUE;
6707 vaddr[i] = PHYS_TO_DMAP(paddr);
6711 /* Exit early if everything is covered by the DMAP */
6717 for (i = 0; i < count; i++) {
6718 paddr = VM_PAGE_TO_PHYS(page[i]);
6719 if (!PHYS_IN_DMAP(paddr)) {
6721 "pmap_map_io_transient: TODO: Map out of DMAP data");
6725 return (needs_mapping);
6729 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6730 boolean_t can_fault)
6737 for (i = 0; i < count; i++) {
6738 paddr = VM_PAGE_TO_PHYS(page[i]);
6739 if (!PHYS_IN_DMAP(paddr)) {
6740 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
6746 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
6749 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
6753 * Track a range of the kernel's virtual address space that is contiguous
6754 * in various mapping attributes.
6756 struct pmap_kernel_map_range {
6766 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6772 if (eva <= range->sva)
6775 index = range->attrs & ATTR_S1_IDX_MASK;
6777 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
6780 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
6783 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
6786 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
6791 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
6792 __func__, index, range->sva, eva);
6797 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
6799 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
6800 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
6801 (range->attrs & ATTR_S1_AP_USER) != 0 ? 'u' : 's',
6802 mode, range->l1blocks, range->l2blocks, range->l3contig,
6805 /* Reset to sentinel value. */
6806 range->sva = 0xfffffffffffffffful;
6810 * Determine whether the attributes specified by a page table entry match those
6811 * being tracked by the current range.
6814 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6817 return (range->attrs == attrs);
6821 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6825 memset(range, 0, sizeof(*range));
6827 range->attrs = attrs;
6831 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6832 * those of the current run, dump the address range and its attributes, and
6836 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6837 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
6842 attrs = l0e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6843 attrs |= l1e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6844 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
6845 attrs |= l1e & ATTR_S1_IDX_MASK;
6846 attrs |= l2e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6847 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
6848 attrs |= l2e & ATTR_S1_IDX_MASK;
6849 attrs |= l3e & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK);
6851 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6852 sysctl_kmaps_dump(sb, range, va);
6853 sysctl_kmaps_reinit(range, va, attrs);
6858 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
6860 struct pmap_kernel_map_range range;
6861 struct sbuf sbuf, *sb;
6862 pd_entry_t l0e, *l1, l1e, *l2, l2e;
6863 pt_entry_t *l3, l3e;
6866 int error, i, j, k, l;
6868 error = sysctl_wire_old_buffer(req, 0);
6872 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6874 /* Sentinel value. */
6875 range.sva = 0xfffffffffffffffful;
6878 * Iterate over the kernel page tables without holding the kernel pmap
6879 * lock. Kernel page table pages are never freed, so at worst we will
6880 * observe inconsistencies in the output.
6882 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
6884 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
6885 sbuf_printf(sb, "\nDirect map:\n");
6886 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
6887 sbuf_printf(sb, "\nKernel map:\n");
6889 l0e = kernel_pmap->pm_l0[i];
6890 if ((l0e & ATTR_DESCR_VALID) == 0) {
6891 sysctl_kmaps_dump(sb, &range, sva);
6895 pa = l0e & ~ATTR_MASK;
6896 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6898 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
6900 if ((l1e & ATTR_DESCR_VALID) == 0) {
6901 sysctl_kmaps_dump(sb, &range, sva);
6905 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
6906 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
6912 pa = l1e & ~ATTR_MASK;
6913 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6915 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
6917 if ((l2e & ATTR_DESCR_VALID) == 0) {
6918 sysctl_kmaps_dump(sb, &range, sva);
6922 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
6923 sysctl_kmaps_check(sb, &range, sva,
6929 pa = l2e & ~ATTR_MASK;
6930 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
6932 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
6933 l++, sva += L3_SIZE) {
6935 if ((l3e & ATTR_DESCR_VALID) == 0) {
6936 sysctl_kmaps_dump(sb, &range,
6940 sysctl_kmaps_check(sb, &range, sva,
6941 l0e, l1e, l2e, l3e);
6942 if ((l3e & ATTR_CONTIGUOUS) != 0)
6943 range.l3contig += l % 16 == 0 ?
6952 error = sbuf_finish(sb);
6956 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
6957 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
6958 NULL, 0, sysctl_kmaps, "A",
6959 "Dump kernel address layout");