2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/physmem.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
125 #include <sys/sbuf.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
131 #include <sys/_unrhdr.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
148 #include <machine/machdep.h>
149 #include <machine/md_var.h>
150 #include <machine/pcb.h>
152 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
153 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
155 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
156 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
158 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
160 #define NUL0E L0_ENTRIES
161 #define NUL1E (NUL0E * NL1PG)
162 #define NUL2E (NUL1E * NL2PG)
164 #if !defined(DIAGNOSTIC)
165 #ifdef __GNUC_GNU_INLINE__
166 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
168 #define PMAP_INLINE extern inline
175 #define PV_STAT(x) do { x ; } while (0)
177 #define PV_STAT(x) do { } while (0)
180 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
181 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
183 #define NPV_LIST_LOCKS MAXCPU
185 #define PHYS_TO_PV_LIST_LOCK(pa) \
186 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
188 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
189 struct rwlock **_lockp = (lockp); \
190 struct rwlock *_new_lock; \
192 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
193 if (_new_lock != *_lockp) { \
194 if (*_lockp != NULL) \
195 rw_wunlock(*_lockp); \
196 *_lockp = _new_lock; \
201 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
202 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
204 #define RELEASE_PV_LIST_LOCK(lockp) do { \
205 struct rwlock **_lockp = (lockp); \
207 if (*_lockp != NULL) { \
208 rw_wunlock(*_lockp); \
213 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
214 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
217 * The presence of this flag indicates that the mapping is writeable.
218 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
219 * it is dirty. This flag may only be set on managed mappings.
221 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
222 * as a software managed bit.
224 #define ATTR_SW_DBM ATTR_DBM
226 struct pmap kernel_pmap_store;
228 /* Used for mapping ACPI memory before VM is initialized */
229 #define PMAP_PREINIT_MAPPING_COUNT 32
230 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
231 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
232 static int vm_initialized = 0; /* No need to use pre-init maps when set */
235 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
236 * Always map entire L2 block for simplicity.
237 * VA of L2 block = preinit_map_va + i * L2_SIZE
239 static struct pmap_preinit_mapping {
243 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
245 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
246 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
247 vm_offset_t kernel_vm_end = 0;
250 * Data for the pv entry allocation mechanism.
252 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
253 static struct mtx pv_chunks_mutex;
254 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
255 static struct md_page *pv_table;
256 static struct md_page pv_dummy;
258 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
259 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
260 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
262 /* This code assumes all L1 DMAP entries will be used */
263 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
264 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
266 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
267 extern pt_entry_t pagetable_dmap[];
269 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
270 static vm_paddr_t physmap[PHYSMAP_SIZE];
271 static u_int physmap_idx;
273 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
274 "VM/pmap parameters");
277 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
278 * that it has currently allocated to a pmap, a cursor ("asid_next") to
279 * optimize its search for a free ASID in the bit vector, and an epoch number
280 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
281 * ASIDs that are not currently active on a processor.
283 * The current epoch number is always in the range [0, INT_MAX). Negative
284 * numbers and INT_MAX are reserved for special cases that are described
293 struct mtx asid_set_mutex;
296 static struct asid_set asids;
297 static struct asid_set vmids;
299 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
301 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
302 "The number of bits in an ASID");
303 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
304 "The last allocated ASID plus one");
305 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
306 "The current epoch number");
308 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
309 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
310 "The number of bits in an VMID");
311 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
312 "The last allocated VMID plus one");
313 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
314 "The current epoch number");
316 void (*pmap_clean_stage2_tlbi)(void);
317 void (*pmap_invalidate_vpipt_icache)(void);
320 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
321 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
322 * dynamically allocated ASIDs have a non-negative epoch number.
324 * An invalid ASID is represented by -1.
326 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
327 * which indicates that an ASID should never be allocated to the pmap, and
328 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
329 * allocated when the pmap is next activated.
331 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
332 ((u_long)(epoch) << 32)))
333 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
334 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
336 static int superpages_enabled = 1;
337 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
338 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
339 "Are large page mappings enabled?");
342 * Internal flags for pmap_enter()'s helper functions.
344 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
345 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
347 static void free_pv_chunk(struct pv_chunk *pc);
348 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
349 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
350 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
351 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
352 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
355 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
356 static bool pmap_activate_int(pmap_t pmap);
357 static void pmap_alloc_asid(pmap_t pmap);
358 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
359 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
360 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
361 vm_offset_t va, struct rwlock **lockp);
362 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
363 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
364 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
365 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
366 u_int flags, vm_page_t m, struct rwlock **lockp);
367 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
368 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
369 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
370 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
371 static void pmap_reset_asid_set(pmap_t pmap);
372 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
373 vm_page_t m, struct rwlock **lockp);
375 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
376 struct rwlock **lockp);
378 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
379 struct spglist *free);
380 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
381 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
384 * These load the old table data and store the new value.
385 * They need to be atomic as the System MMU may write to the table at
386 * the same time as the CPU.
388 #define pmap_clear(table) atomic_store_64(table, 0)
389 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
390 #define pmap_load(table) (*table)
391 #define pmap_load_clear(table) atomic_swap_64(table, 0)
392 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
393 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
394 #define pmap_store(table, entry) atomic_store_64(table, entry)
396 /********************/
397 /* Inline functions */
398 /********************/
401 pagecopy(void *s, void *d)
404 memcpy(d, s, PAGE_SIZE);
407 static __inline pd_entry_t *
408 pmap_l0(pmap_t pmap, vm_offset_t va)
411 return (&pmap->pm_l0[pmap_l0_index(va)]);
414 static __inline pd_entry_t *
415 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
419 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
420 return (&l1[pmap_l1_index(va)]);
423 static __inline pd_entry_t *
424 pmap_l1(pmap_t pmap, vm_offset_t va)
428 l0 = pmap_l0(pmap, va);
429 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
432 return (pmap_l0_to_l1(l0, va));
435 static __inline pd_entry_t *
436 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
440 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
441 return (&l2[pmap_l2_index(va)]);
444 static __inline pd_entry_t *
445 pmap_l2(pmap_t pmap, vm_offset_t va)
449 l1 = pmap_l1(pmap, va);
450 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
453 return (pmap_l1_to_l2(l1, va));
456 static __inline pt_entry_t *
457 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
461 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
462 return (&l3[pmap_l3_index(va)]);
466 * Returns the lowest valid pde for a given virtual address.
467 * The next level may or may not point to a valid page or block.
469 static __inline pd_entry_t *
470 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
472 pd_entry_t *l0, *l1, *l2, desc;
474 l0 = pmap_l0(pmap, va);
475 desc = pmap_load(l0) & ATTR_DESCR_MASK;
476 if (desc != L0_TABLE) {
481 l1 = pmap_l0_to_l1(l0, va);
482 desc = pmap_load(l1) & ATTR_DESCR_MASK;
483 if (desc != L1_TABLE) {
488 l2 = pmap_l1_to_l2(l1, va);
489 desc = pmap_load(l2) & ATTR_DESCR_MASK;
490 if (desc != L2_TABLE) {
500 * Returns the lowest valid pte block or table entry for a given virtual
501 * address. If there are no valid entries return NULL and set the level to
502 * the first invalid level.
504 static __inline pt_entry_t *
505 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
507 pd_entry_t *l1, *l2, desc;
510 l1 = pmap_l1(pmap, va);
515 desc = pmap_load(l1) & ATTR_DESCR_MASK;
516 if (desc == L1_BLOCK) {
521 if (desc != L1_TABLE) {
526 l2 = pmap_l1_to_l2(l1, va);
527 desc = pmap_load(l2) & ATTR_DESCR_MASK;
528 if (desc == L2_BLOCK) {
533 if (desc != L2_TABLE) {
539 l3 = pmap_l2_to_l3(l2, va);
540 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
547 pmap_ps_enabled(pmap_t pmap __unused)
550 return (superpages_enabled != 0);
554 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
555 pd_entry_t **l2, pt_entry_t **l3)
557 pd_entry_t *l0p, *l1p, *l2p;
559 if (pmap->pm_l0 == NULL)
562 l0p = pmap_l0(pmap, va);
565 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
568 l1p = pmap_l0_to_l1(l0p, va);
571 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
577 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
580 l2p = pmap_l1_to_l2(l1p, va);
583 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
588 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
591 *l3 = pmap_l2_to_l3(l2p, va);
597 pmap_l3_valid(pt_entry_t l3)
600 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
603 CTASSERT(L1_BLOCK == L2_BLOCK);
606 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
610 if (pmap->pm_stage == PM_STAGE1) {
611 val = ATTR_S1_IDX(memattr);
612 if (memattr == VM_MEMATTR_DEVICE)
620 case VM_MEMATTR_DEVICE:
621 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
622 ATTR_S2_XN(ATTR_S2_XN_ALL));
623 case VM_MEMATTR_UNCACHEABLE:
624 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
625 case VM_MEMATTR_WRITE_BACK:
626 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
627 case VM_MEMATTR_WRITE_THROUGH:
628 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
630 panic("%s: invalid memory attribute %x", __func__, memattr);
635 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
640 if (pmap->pm_stage == PM_STAGE1) {
641 if ((prot & VM_PROT_EXECUTE) == 0)
643 if ((prot & VM_PROT_WRITE) == 0)
644 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
646 if ((prot & VM_PROT_WRITE) != 0)
647 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
648 if ((prot & VM_PROT_READ) != 0)
649 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
650 if ((prot & VM_PROT_EXECUTE) == 0)
651 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
658 * Checks if the PTE is dirty.
661 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
664 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
666 if (pmap->pm_stage == PM_STAGE1) {
667 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
668 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
670 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
671 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
674 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
675 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
679 pmap_resident_count_inc(pmap_t pmap, int count)
682 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
683 pmap->pm_stats.resident_count += count;
687 pmap_resident_count_dec(pmap_t pmap, int count)
690 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
691 KASSERT(pmap->pm_stats.resident_count >= count,
692 ("pmap %p resident count underflow %ld %d", pmap,
693 pmap->pm_stats.resident_count, count));
694 pmap->pm_stats.resident_count -= count;
698 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
704 l1 = (pd_entry_t *)l1pt;
705 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
707 /* Check locore has used a table L1 map */
708 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
709 ("Invalid bootstrap L1 table"));
710 /* Find the address of the L2 table */
711 l2 = (pt_entry_t *)init_pt_va;
712 *l2_slot = pmap_l2_index(va);
718 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
720 u_int l1_slot, l2_slot;
723 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
725 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
729 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
730 vm_offset_t freemempos)
734 vm_paddr_t l2_pa, pa;
735 u_int l1_slot, l2_slot, prev_l1_slot;
738 dmap_phys_base = min_pa & ~L1_OFFSET;
744 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
745 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
747 for (i = 0; i < (physmap_idx * 2); i += 2) {
748 pa = physmap[i] & ~L2_OFFSET;
749 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
751 /* Create L2 mappings at the start of the region */
752 if ((pa & L1_OFFSET) != 0) {
753 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
754 if (l1_slot != prev_l1_slot) {
755 prev_l1_slot = l1_slot;
756 l2 = (pt_entry_t *)freemempos;
757 l2_pa = pmap_early_vtophys(kern_l1,
759 freemempos += PAGE_SIZE;
761 pmap_store(&pagetable_dmap[l1_slot],
762 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
764 memset(l2, 0, PAGE_SIZE);
767 ("pmap_bootstrap_dmap: NULL l2 map"));
768 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
769 pa += L2_SIZE, va += L2_SIZE) {
771 * We are on a boundary, stop to
772 * create a level 1 block
774 if ((pa & L1_OFFSET) == 0)
777 l2_slot = pmap_l2_index(va);
778 KASSERT(l2_slot != 0, ("..."));
779 pmap_store(&l2[l2_slot],
780 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
782 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
785 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
789 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
790 (physmap[i + 1] - pa) >= L1_SIZE;
791 pa += L1_SIZE, va += L1_SIZE) {
792 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
793 pmap_store(&pagetable_dmap[l1_slot],
794 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_S1_XN |
795 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
798 /* Create L2 mappings at the end of the region */
799 if (pa < physmap[i + 1]) {
800 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
801 if (l1_slot != prev_l1_slot) {
802 prev_l1_slot = l1_slot;
803 l2 = (pt_entry_t *)freemempos;
804 l2_pa = pmap_early_vtophys(kern_l1,
806 freemempos += PAGE_SIZE;
808 pmap_store(&pagetable_dmap[l1_slot],
809 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
811 memset(l2, 0, PAGE_SIZE);
814 ("pmap_bootstrap_dmap: NULL l2 map"));
815 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
816 pa += L2_SIZE, va += L2_SIZE) {
817 l2_slot = pmap_l2_index(va);
818 pmap_store(&l2[l2_slot],
819 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
821 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
826 if (pa > dmap_phys_max) {
838 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
845 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
847 l1 = (pd_entry_t *)l1pt;
848 l1_slot = pmap_l1_index(va);
851 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
852 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
854 pa = pmap_early_vtophys(l1pt, l2pt);
855 pmap_store(&l1[l1_slot],
856 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
860 /* Clean the L2 page table */
861 memset((void *)l2_start, 0, l2pt - l2_start);
867 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
874 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
876 l2 = pmap_l2(kernel_pmap, va);
877 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
878 l2_slot = pmap_l2_index(va);
881 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
882 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
884 pa = pmap_early_vtophys(l1pt, l3pt);
885 pmap_store(&l2[l2_slot],
886 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
890 /* Clean the L2 page table */
891 memset((void *)l3_start, 0, l3pt - l3_start);
897 * Bootstrap the system enough to run with virtual memory.
900 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
903 vm_offset_t freemempos;
904 vm_offset_t dpcpu, msgbufpv;
905 vm_paddr_t start_pa, pa, min_pa;
909 /* Verify that the ASID is set through TTBR0. */
910 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
911 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
913 kern_delta = KERNBASE - kernstart;
915 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
916 printf("%lx\n", l1pt);
917 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
919 /* Set this early so we can use the pagetable walking functions */
920 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
921 PMAP_LOCK_INIT(kernel_pmap);
922 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
923 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
924 kernel_pmap->pm_stage = PM_STAGE1;
925 kernel_pmap->pm_asid_set = &asids;
927 /* Assume the address we were loaded to is a valid physical address */
928 min_pa = KERNBASE - kern_delta;
930 physmap_idx = physmem_avail(physmap, nitems(physmap));
934 * Find the minimum physical address. physmap is sorted,
935 * but may contain empty ranges.
937 for (i = 0; i < physmap_idx * 2; i += 2) {
938 if (physmap[i] == physmap[i + 1])
940 if (physmap[i] <= min_pa)
944 freemempos = KERNBASE + kernlen;
945 freemempos = roundup2(freemempos, PAGE_SIZE);
947 /* Create a direct map region early so we can use it for pa -> va */
948 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
950 start_pa = pa = KERNBASE - kern_delta;
953 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
954 * loader allocated the first and only l2 page table page used to map
955 * the kernel, preloaded files and module metadata.
957 freemempos = pmap_bootstrap_l2(l1pt, KERNBASE + L1_SIZE, freemempos);
958 /* And the l3 tables for the early devmap */
959 freemempos = pmap_bootstrap_l3(l1pt,
960 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
964 #define alloc_pages(var, np) \
965 (var) = freemempos; \
966 freemempos += (np * PAGE_SIZE); \
967 memset((char *)(var), 0, ((np) * PAGE_SIZE));
969 /* Allocate dynamic per-cpu area. */
970 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
971 dpcpu_init((void *)dpcpu, 0);
973 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
974 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
975 msgbufp = (void *)msgbufpv;
977 /* Reserve some VA space for early BIOS/ACPI mapping */
978 preinit_map_va = roundup2(freemempos, L2_SIZE);
980 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
981 virtual_avail = roundup2(virtual_avail, L1_SIZE);
982 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
983 kernel_vm_end = virtual_avail;
985 pa = pmap_early_vtophys(l1pt, freemempos);
987 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
993 * Initialize a vm_page's machine-dependent fields.
996 pmap_page_init(vm_page_t m)
999 TAILQ_INIT(&m->md.pv_list);
1000 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1004 pmap_init_asids(struct asid_set *set, int bits)
1008 set->asid_bits = bits;
1011 * We may be too early in the overall initialization process to use
1014 set->asid_set_size = 1 << set->asid_bits;
1015 set->asid_set = (bitstr_t *)kmem_malloc(bitstr_size(set->asid_set_size),
1017 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1018 bit_set(set->asid_set, i);
1019 set->asid_next = ASID_FIRST_AVAILABLE;
1020 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1024 * Initialize the pmap module.
1025 * Called by vm_init, to initialize any structures that the pmap
1026 * system needs to map virtual memory.
1033 int i, pv_npg, vmid_bits;
1036 * Are large page mappings enabled?
1038 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1039 if (superpages_enabled) {
1040 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1041 ("pmap_init: can't assign to pagesizes[1]"));
1042 pagesizes[1] = L2_SIZE;
1046 * Initialize the ASID allocator.
1048 pmap_init_asids(&asids,
1049 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1052 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1055 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1056 ID_AA64MMFR1_VMIDBits_16)
1058 pmap_init_asids(&vmids, vmid_bits);
1062 * Initialize the pv chunk list mutex.
1064 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1067 * Initialize the pool of pv list locks.
1069 for (i = 0; i < NPV_LIST_LOCKS; i++)
1070 rw_init(&pv_list_locks[i], "pmap pv list");
1073 * Calculate the size of the pv head table for superpages.
1075 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
1078 * Allocate memory for the pv head table for superpages.
1080 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1082 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1083 for (i = 0; i < pv_npg; i++)
1084 TAILQ_INIT(&pv_table[i].pv_list);
1085 TAILQ_INIT(&pv_dummy.pv_list);
1090 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1091 "2MB page mapping counters");
1093 static u_long pmap_l2_demotions;
1094 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1095 &pmap_l2_demotions, 0, "2MB page demotions");
1097 static u_long pmap_l2_mappings;
1098 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1099 &pmap_l2_mappings, 0, "2MB page mappings");
1101 static u_long pmap_l2_p_failures;
1102 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1103 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1105 static u_long pmap_l2_promotions;
1106 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1107 &pmap_l2_promotions, 0, "2MB page promotions");
1110 * Invalidate a single TLB entry.
1112 static __inline void
1113 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1117 PMAP_ASSERT_STAGE1(pmap);
1120 if (pmap == kernel_pmap) {
1122 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1124 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1125 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1131 static __inline void
1132 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1134 uint64_t end, r, start;
1136 PMAP_ASSERT_STAGE1(pmap);
1139 if (pmap == kernel_pmap) {
1142 for (r = start; r < end; r++)
1143 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1145 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1148 for (r = start; r < end; r++)
1149 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1155 static __inline void
1156 pmap_invalidate_all(pmap_t pmap)
1160 PMAP_ASSERT_STAGE1(pmap);
1163 if (pmap == kernel_pmap) {
1164 __asm __volatile("tlbi vmalle1is");
1166 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1167 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1174 * Routine: pmap_extract
1176 * Extract the physical page address associated
1177 * with the given map/virtual_address pair.
1180 pmap_extract(pmap_t pmap, vm_offset_t va)
1182 pt_entry_t *pte, tpte;
1189 * Find the block or page map for this virtual address. pmap_pte
1190 * will return either a valid block/page entry, or NULL.
1192 pte = pmap_pte(pmap, va, &lvl);
1194 tpte = pmap_load(pte);
1195 pa = tpte & ~ATTR_MASK;
1198 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1199 ("pmap_extract: Invalid L1 pte found: %lx",
1200 tpte & ATTR_DESCR_MASK));
1201 pa |= (va & L1_OFFSET);
1204 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1205 ("pmap_extract: Invalid L2 pte found: %lx",
1206 tpte & ATTR_DESCR_MASK));
1207 pa |= (va & L2_OFFSET);
1210 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1211 ("pmap_extract: Invalid L3 pte found: %lx",
1212 tpte & ATTR_DESCR_MASK));
1213 pa |= (va & L3_OFFSET);
1222 * Routine: pmap_extract_and_hold
1224 * Atomically extract and hold the physical page
1225 * with the given pmap and virtual address pair
1226 * if that mapping permits the given protection.
1229 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1231 pt_entry_t *pte, tpte;
1239 pte = pmap_pte(pmap, va, &lvl);
1241 tpte = pmap_load(pte);
1243 KASSERT(lvl > 0 && lvl <= 3,
1244 ("pmap_extract_and_hold: Invalid level %d", lvl));
1245 CTASSERT(L1_BLOCK == L2_BLOCK);
1246 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1247 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1248 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1249 tpte & ATTR_DESCR_MASK));
1252 if ((prot & VM_PROT_WRITE) == 0)
1254 else if (pmap->pm_stage == PM_STAGE1 &&
1255 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1257 else if (pmap->pm_stage == PM_STAGE2 &&
1258 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1259 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1265 off = va & L1_OFFSET;
1268 off = va & L2_OFFSET;
1274 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1275 if (!vm_page_wire_mapped(m))
1284 pmap_kextract(vm_offset_t va)
1286 pt_entry_t *pte, tpte;
1288 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1289 return (DMAP_TO_PHYS(va));
1290 pte = pmap_l1(kernel_pmap, va);
1295 * A concurrent pmap_update_entry() will clear the entry's valid bit
1296 * but leave the rest of the entry unchanged. Therefore, we treat a
1297 * non-zero entry as being valid, and we ignore the valid bit when
1298 * determining whether the entry maps a block, page, or table.
1300 tpte = pmap_load(pte);
1303 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1304 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1305 pte = pmap_l1_to_l2(&tpte, va);
1306 tpte = pmap_load(pte);
1309 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1310 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1311 pte = pmap_l2_to_l3(&tpte, va);
1312 tpte = pmap_load(pte);
1315 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1318 /***************************************************
1319 * Low level mapping routines.....
1320 ***************************************************/
1323 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1326 pt_entry_t *pte, attr;
1330 KASSERT((pa & L3_OFFSET) == 0,
1331 ("pmap_kenter: Invalid physical address"));
1332 KASSERT((sva & L3_OFFSET) == 0,
1333 ("pmap_kenter: Invalid virtual address"));
1334 KASSERT((size & PAGE_MASK) == 0,
1335 ("pmap_kenter: Mapping is not page-sized"));
1337 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1338 ATTR_S1_IDX(mode) | L3_PAGE;
1341 pde = pmap_pde(kernel_pmap, va, &lvl);
1342 KASSERT(pde != NULL,
1343 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1344 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1346 pte = pmap_l2_to_l3(pde, va);
1347 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1353 pmap_invalidate_range(kernel_pmap, sva, va);
1357 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1360 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1364 * Remove a page from the kernel pagetables.
1367 pmap_kremove(vm_offset_t va)
1372 pte = pmap_pte(kernel_pmap, va, &lvl);
1373 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1374 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1377 pmap_invalidate_page(kernel_pmap, va);
1381 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1387 KASSERT((sva & L3_OFFSET) == 0,
1388 ("pmap_kremove_device: Invalid virtual address"));
1389 KASSERT((size & PAGE_MASK) == 0,
1390 ("pmap_kremove_device: Mapping is not page-sized"));
1394 pte = pmap_pte(kernel_pmap, va, &lvl);
1395 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1397 ("Invalid device pagetable level: %d != 3", lvl));
1403 pmap_invalidate_range(kernel_pmap, sva, va);
1407 * Used to map a range of physical addresses into kernel
1408 * virtual address space.
1410 * The value passed in '*virt' is a suggested virtual address for
1411 * the mapping. Architectures which can support a direct-mapped
1412 * physical to virtual region can return the appropriate address
1413 * within that region, leaving '*virt' unchanged. Other
1414 * architectures should map the pages starting at '*virt' and
1415 * update '*virt' with the first usable address after the mapped
1419 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1421 return PHYS_TO_DMAP(start);
1425 * Add a list of wired pages to the kva
1426 * this routine is only used for temporary
1427 * kernel mappings that do not need to have
1428 * page modification or references recorded.
1429 * Note that old mappings are simply written
1430 * over. The page *must* be wired.
1431 * Note: SMP coherent. Uses a ranged shootdown IPI.
1434 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1437 pt_entry_t *pte, pa;
1443 for (i = 0; i < count; i++) {
1444 pde = pmap_pde(kernel_pmap, va, &lvl);
1445 KASSERT(pde != NULL,
1446 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1448 ("pmap_qenter: Invalid level %d", lvl));
1451 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1452 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1453 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1454 pte = pmap_l2_to_l3(pde, va);
1455 pmap_load_store(pte, pa);
1459 pmap_invalidate_range(kernel_pmap, sva, va);
1463 * This routine tears out page mappings from the
1464 * kernel -- it is meant only for temporary mappings.
1467 pmap_qremove(vm_offset_t sva, int count)
1473 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1476 while (count-- > 0) {
1477 pte = pmap_pte(kernel_pmap, va, &lvl);
1479 ("Invalid device pagetable level: %d != 3", lvl));
1486 pmap_invalidate_range(kernel_pmap, sva, va);
1489 /***************************************************
1490 * Page table page management routines.....
1491 ***************************************************/
1493 * Schedule the specified unused page table page to be freed. Specifically,
1494 * add the page to the specified list of pages that will be released to the
1495 * physical memory manager after the TLB has been updated.
1497 static __inline void
1498 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1499 boolean_t set_PG_ZERO)
1503 m->flags |= PG_ZERO;
1505 m->flags &= ~PG_ZERO;
1506 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1510 * Decrements a page table page's reference count, which is used to record the
1511 * number of valid page table entries within the page. If the reference count
1512 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1513 * page table page was unmapped and FALSE otherwise.
1515 static inline boolean_t
1516 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1520 if (m->ref_count == 0) {
1521 _pmap_unwire_l3(pmap, va, m, free);
1528 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1531 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1533 * unmap the page table page
1535 if (m->pindex >= (NUL2E + NUL1E)) {
1539 l0 = pmap_l0(pmap, va);
1541 } else if (m->pindex >= NUL2E) {
1545 l1 = pmap_l1(pmap, va);
1551 l2 = pmap_l2(pmap, va);
1554 pmap_resident_count_dec(pmap, 1);
1555 if (m->pindex < NUL2E) {
1556 /* We just released an l3, unhold the matching l2 */
1557 pd_entry_t *l1, tl1;
1560 l1 = pmap_l1(pmap, va);
1561 tl1 = pmap_load(l1);
1562 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1563 pmap_unwire_l3(pmap, va, l2pg, free);
1564 } else if (m->pindex < (NUL2E + NUL1E)) {
1565 /* We just released an l2, unhold the matching l1 */
1566 pd_entry_t *l0, tl0;
1569 l0 = pmap_l0(pmap, va);
1570 tl0 = pmap_load(l0);
1571 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1572 pmap_unwire_l3(pmap, va, l1pg, free);
1574 pmap_invalidate_page(pmap, va);
1577 * Put page on a list so that it is released after
1578 * *ALL* TLB shootdown is done
1580 pmap_add_delayed_free_list(m, free, TRUE);
1584 * After removing a page table entry, this routine is used to
1585 * conditionally free the page, and manage the reference count.
1588 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1589 struct spglist *free)
1593 if (va >= VM_MAXUSER_ADDRESS)
1595 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1596 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1597 return (pmap_unwire_l3(pmap, va, mpte, free));
1601 * Release a page table page reference after a failed attempt to create a
1605 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1607 struct spglist free;
1610 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
1612 * Although "va" was never mapped, the TLB could nonetheless
1613 * have intermediate entries that refer to the freed page
1614 * table pages. Invalidate those entries.
1616 * XXX redundant invalidation (See _pmap_unwire_l3().)
1618 pmap_invalidate_page(pmap, va);
1619 vm_page_free_pages_toq(&free, true);
1624 pmap_pinit0(pmap_t pmap)
1627 PMAP_LOCK_INIT(pmap);
1628 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1629 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1630 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1631 pmap->pm_root.rt_root = 0;
1632 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1633 pmap->pm_stage = PM_STAGE1;
1634 pmap->pm_asid_set = &asids;
1636 PCPU_SET(curpmap, pmap);
1640 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage)
1645 * allocate the l0 page
1647 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1648 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1651 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(l0pt);
1652 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1654 if ((l0pt->flags & PG_ZERO) == 0)
1655 pagezero(pmap->pm_l0);
1657 pmap->pm_root.rt_root = 0;
1658 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1659 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1661 pmap->pm_stage = stage;
1664 pmap->pm_asid_set = &asids;
1667 pmap->pm_asid_set = &vmids;
1670 panic("%s: Invalid pmap type %d", __func__, stage);
1674 /* XXX Temporarily disable deferred ASID allocation. */
1675 pmap_alloc_asid(pmap);
1681 pmap_pinit(pmap_t pmap)
1684 return (pmap_pinit_stage(pmap, PM_STAGE1));
1688 * This routine is called if the desired page table page does not exist.
1690 * If page table page allocation fails, this routine may sleep before
1691 * returning NULL. It sleeps only if a lock pointer was given.
1693 * Note: If a page allocation fails at page table level two or three,
1694 * one or two pages may be held during the wait, only to be released
1695 * afterwards. This conservative approach is easily argued to avoid
1699 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1701 vm_page_t m, l1pg, l2pg;
1703 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1706 * Allocate a page table page.
1708 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1709 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1710 if (lockp != NULL) {
1711 RELEASE_PV_LIST_LOCK(lockp);
1718 * Indicate the need to retry. While waiting, the page table
1719 * page may have been allocated.
1723 if ((m->flags & PG_ZERO) == 0)
1727 * Because of AArch64's weak memory consistency model, we must have a
1728 * barrier here to ensure that the stores for zeroing "m", whether by
1729 * pmap_zero_page() or an earlier function, are visible before adding
1730 * "m" to the page table. Otherwise, a page table walk by another
1731 * processor's MMU could see the mapping to "m" and a stale, non-zero
1737 * Map the pagetable page into the process address space, if
1738 * it isn't already there.
1741 if (ptepindex >= (NUL2E + NUL1E)) {
1743 vm_pindex_t l0index;
1745 l0index = ptepindex - (NUL2E + NUL1E);
1746 l0 = &pmap->pm_l0[l0index];
1747 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1748 } else if (ptepindex >= NUL2E) {
1749 vm_pindex_t l0index, l1index;
1750 pd_entry_t *l0, *l1;
1753 l1index = ptepindex - NUL2E;
1754 l0index = l1index >> L0_ENTRIES_SHIFT;
1756 l0 = &pmap->pm_l0[l0index];
1757 tl0 = pmap_load(l0);
1759 /* recurse for allocating page dir */
1760 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1762 vm_page_unwire_noq(m);
1763 vm_page_free_zero(m);
1767 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1771 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1772 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1773 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1775 vm_pindex_t l0index, l1index;
1776 pd_entry_t *l0, *l1, *l2;
1777 pd_entry_t tl0, tl1;
1779 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1780 l0index = l1index >> L0_ENTRIES_SHIFT;
1782 l0 = &pmap->pm_l0[l0index];
1783 tl0 = pmap_load(l0);
1785 /* recurse for allocating page dir */
1786 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1788 vm_page_unwire_noq(m);
1789 vm_page_free_zero(m);
1792 tl0 = pmap_load(l0);
1793 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1794 l1 = &l1[l1index & Ln_ADDR_MASK];
1796 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1797 l1 = &l1[l1index & Ln_ADDR_MASK];
1798 tl1 = pmap_load(l1);
1800 /* recurse for allocating page dir */
1801 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1803 vm_page_unwire_noq(m);
1804 vm_page_free_zero(m);
1808 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1813 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1814 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1815 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1818 pmap_resident_count_inc(pmap, 1);
1824 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
1825 struct rwlock **lockp)
1827 pd_entry_t *l1, *l2;
1829 vm_pindex_t l2pindex;
1832 l1 = pmap_l1(pmap, va);
1833 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1834 l2 = pmap_l1_to_l2(l1, va);
1835 if (va < VM_MAXUSER_ADDRESS) {
1836 /* Add a reference to the L2 page. */
1837 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1841 } else if (va < VM_MAXUSER_ADDRESS) {
1842 /* Allocate a L2 page. */
1843 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1844 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1851 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
1852 l2 = &l2[pmap_l2_index(va)];
1854 panic("pmap_alloc_l2: missing page table page for va %#lx",
1861 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1863 vm_pindex_t ptepindex;
1864 pd_entry_t *pde, tpde;
1872 * Calculate pagetable page index
1874 ptepindex = pmap_l2_pindex(va);
1877 * Get the page directory entry
1879 pde = pmap_pde(pmap, va, &lvl);
1882 * If the page table page is mapped, we just increment the hold count,
1883 * and activate it. If we get a level 2 pde it will point to a level 3
1891 pte = pmap_l0_to_l1(pde, va);
1892 KASSERT(pmap_load(pte) == 0,
1893 ("pmap_alloc_l3: TODO: l0 superpages"));
1898 pte = pmap_l1_to_l2(pde, va);
1899 KASSERT(pmap_load(pte) == 0,
1900 ("pmap_alloc_l3: TODO: l1 superpages"));
1904 tpde = pmap_load(pde);
1906 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1912 panic("pmap_alloc_l3: Invalid level %d", lvl);
1916 * Here if the pte page isn't mapped, or if it has been deallocated.
1918 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1919 if (m == NULL && lockp != NULL)
1925 /***************************************************
1926 * Pmap allocation/deallocation routines.
1927 ***************************************************/
1930 * Release any resources held by the given physical map.
1931 * Called when a pmap initialized by pmap_pinit is being released.
1932 * Should only be called if the map contains no valid mappings.
1935 pmap_release(pmap_t pmap)
1937 struct asid_set *set;
1941 KASSERT(pmap->pm_stats.resident_count == 0,
1942 ("pmap_release: pmap resident count %ld != 0",
1943 pmap->pm_stats.resident_count));
1944 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1945 ("pmap_release: pmap has reserved page table page(s)"));
1947 set = pmap->pm_asid_set;
1948 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
1951 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
1952 * the entries when removing them so rely on a later tlb invalidation.
1953 * this will happen when updating the VMID generation. Because of this
1954 * we don't reuse VMIDs within a generation.
1956 if (pmap->pm_stage == PM_STAGE1) {
1957 mtx_lock_spin(&set->asid_set_mutex);
1958 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
1959 asid = COOKIE_TO_ASID(pmap->pm_cookie);
1960 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
1961 asid < set->asid_set_size,
1962 ("pmap_release: pmap cookie has out-of-range asid"));
1963 bit_clear(set->asid_set, asid);
1965 mtx_unlock_spin(&set->asid_set_mutex);
1968 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
1969 vm_page_unwire_noq(m);
1970 vm_page_free_zero(m);
1974 kvm_size(SYSCTL_HANDLER_ARGS)
1976 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1978 return sysctl_handle_long(oidp, &ksize, 0, req);
1980 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1981 0, 0, kvm_size, "LU",
1985 kvm_free(SYSCTL_HANDLER_ARGS)
1987 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1989 return sysctl_handle_long(oidp, &kfree, 0, req);
1991 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1992 0, 0, kvm_free, "LU",
1993 "Amount of KVM free");
1996 * grow the number of kernel page table entries, if needed
1999 pmap_growkernel(vm_offset_t addr)
2003 pd_entry_t *l0, *l1, *l2;
2005 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2007 addr = roundup2(addr, L2_SIZE);
2008 if (addr - 1 >= vm_map_max(kernel_map))
2009 addr = vm_map_max(kernel_map);
2010 while (kernel_vm_end < addr) {
2011 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2012 KASSERT(pmap_load(l0) != 0,
2013 ("pmap_growkernel: No level 0 kernel entry"));
2015 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2016 if (pmap_load(l1) == 0) {
2017 /* We need a new PDP entry */
2018 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
2019 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2020 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2022 panic("pmap_growkernel: no memory to grow kernel");
2023 if ((nkpg->flags & PG_ZERO) == 0)
2024 pmap_zero_page(nkpg);
2025 /* See the dmb() in _pmap_alloc_l3(). */
2027 paddr = VM_PAGE_TO_PHYS(nkpg);
2028 pmap_store(l1, paddr | L1_TABLE);
2029 continue; /* try again */
2031 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2032 if (pmap_load(l2) != 0) {
2033 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2034 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2035 kernel_vm_end = vm_map_max(kernel_map);
2041 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
2042 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2045 panic("pmap_growkernel: no memory to grow kernel");
2046 if ((nkpg->flags & PG_ZERO) == 0)
2047 pmap_zero_page(nkpg);
2048 /* See the dmb() in _pmap_alloc_l3(). */
2050 paddr = VM_PAGE_TO_PHYS(nkpg);
2051 pmap_store(l2, paddr | L2_TABLE);
2053 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2054 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2055 kernel_vm_end = vm_map_max(kernel_map);
2061 /***************************************************
2062 * page management routines.
2063 ***************************************************/
2065 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2066 CTASSERT(_NPCM == 3);
2067 CTASSERT(_NPCPV == 168);
2069 static __inline struct pv_chunk *
2070 pv_to_chunk(pv_entry_t pv)
2073 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2076 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2078 #define PC_FREE0 0xfffffffffffffffful
2079 #define PC_FREE1 0xfffffffffffffffful
2080 #define PC_FREE2 0x000000fffffffffful
2082 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2086 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2088 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2089 "Current number of pv entry chunks");
2090 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2091 "Current number of pv entry chunks allocated");
2092 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2093 "Current number of pv entry chunks frees");
2094 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2095 "Number of times tried to get a chunk page but failed.");
2097 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2098 static int pv_entry_spare;
2100 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2101 "Current number of pv entry frees");
2102 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2103 "Current number of pv entry allocs");
2104 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2105 "Current number of pv entries");
2106 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2107 "Current number of spare pv entries");
2112 * We are in a serious low memory condition. Resort to
2113 * drastic measures to free some pages so we can allocate
2114 * another pv entry chunk.
2116 * Returns NULL if PV entries were reclaimed from the specified pmap.
2118 * We do not, however, unmap 2mpages because subsequent accesses will
2119 * allocate per-page pv entries until repromotion occurs, thereby
2120 * exacerbating the shortage of free pv entries.
2123 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2125 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2126 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2127 struct md_page *pvh;
2129 pmap_t next_pmap, pmap;
2130 pt_entry_t *pte, tpte;
2134 struct spglist free;
2136 int bit, field, freed, lvl;
2137 static int active_reclaims = 0;
2139 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2140 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2145 bzero(&pc_marker_b, sizeof(pc_marker_b));
2146 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2147 pc_marker = (struct pv_chunk *)&pc_marker_b;
2148 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2150 mtx_lock(&pv_chunks_mutex);
2152 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2153 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2154 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2155 SLIST_EMPTY(&free)) {
2156 next_pmap = pc->pc_pmap;
2157 if (next_pmap == NULL) {
2159 * The next chunk is a marker. However, it is
2160 * not our marker, so active_reclaims must be
2161 * > 1. Consequently, the next_chunk code
2162 * will not rotate the pv_chunks list.
2166 mtx_unlock(&pv_chunks_mutex);
2169 * A pv_chunk can only be removed from the pc_lru list
2170 * when both pv_chunks_mutex is owned and the
2171 * corresponding pmap is locked.
2173 if (pmap != next_pmap) {
2174 if (pmap != NULL && pmap != locked_pmap)
2177 /* Avoid deadlock and lock recursion. */
2178 if (pmap > locked_pmap) {
2179 RELEASE_PV_LIST_LOCK(lockp);
2181 mtx_lock(&pv_chunks_mutex);
2183 } else if (pmap != locked_pmap) {
2184 if (PMAP_TRYLOCK(pmap)) {
2185 mtx_lock(&pv_chunks_mutex);
2188 pmap = NULL; /* pmap is not locked */
2189 mtx_lock(&pv_chunks_mutex);
2190 pc = TAILQ_NEXT(pc_marker, pc_lru);
2192 pc->pc_pmap != next_pmap)
2200 * Destroy every non-wired, 4 KB page mapping in the chunk.
2203 for (field = 0; field < _NPCM; field++) {
2204 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2205 inuse != 0; inuse &= ~(1UL << bit)) {
2206 bit = ffsl(inuse) - 1;
2207 pv = &pc->pc_pventry[field * 64 + bit];
2209 pde = pmap_pde(pmap, va, &lvl);
2212 pte = pmap_l2_to_l3(pde, va);
2213 tpte = pmap_load(pte);
2214 if ((tpte & ATTR_SW_WIRED) != 0)
2216 tpte = pmap_load_clear(pte);
2217 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2218 if (pmap_pte_dirty(pmap, tpte))
2220 if ((tpte & ATTR_AF) != 0) {
2221 pmap_invalidate_page(pmap, va);
2222 vm_page_aflag_set(m, PGA_REFERENCED);
2224 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2225 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2227 if (TAILQ_EMPTY(&m->md.pv_list) &&
2228 (m->flags & PG_FICTITIOUS) == 0) {
2229 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2230 if (TAILQ_EMPTY(&pvh->pv_list)) {
2231 vm_page_aflag_clear(m,
2235 pc->pc_map[field] |= 1UL << bit;
2236 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2241 mtx_lock(&pv_chunks_mutex);
2244 /* Every freed mapping is for a 4 KB page. */
2245 pmap_resident_count_dec(pmap, freed);
2246 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2247 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2248 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2249 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2250 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2251 pc->pc_map[2] == PC_FREE2) {
2252 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2253 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2254 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2255 /* Entire chunk is free; return it. */
2256 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2257 dump_drop_page(m_pc->phys_addr);
2258 mtx_lock(&pv_chunks_mutex);
2259 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2262 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2263 mtx_lock(&pv_chunks_mutex);
2264 /* One freed pv entry in locked_pmap is sufficient. */
2265 if (pmap == locked_pmap)
2269 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2270 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2271 if (active_reclaims == 1 && pmap != NULL) {
2273 * Rotate the pv chunks list so that we do not
2274 * scan the same pv chunks that could not be
2275 * freed (because they contained a wired
2276 * and/or superpage mapping) on every
2277 * invocation of reclaim_pv_chunk().
2279 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2280 MPASS(pc->pc_pmap != NULL);
2281 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2282 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2286 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2287 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2289 mtx_unlock(&pv_chunks_mutex);
2290 if (pmap != NULL && pmap != locked_pmap)
2292 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2293 m_pc = SLIST_FIRST(&free);
2294 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2295 /* Recycle a freed page table page. */
2296 m_pc->ref_count = 1;
2298 vm_page_free_pages_toq(&free, true);
2303 * free the pv_entry back to the free list
2306 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2308 struct pv_chunk *pc;
2309 int idx, field, bit;
2311 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2312 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2313 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2314 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2315 pc = pv_to_chunk(pv);
2316 idx = pv - &pc->pc_pventry[0];
2319 pc->pc_map[field] |= 1ul << bit;
2320 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2321 pc->pc_map[2] != PC_FREE2) {
2322 /* 98% of the time, pc is already at the head of the list. */
2323 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2324 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2325 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2329 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2334 free_pv_chunk(struct pv_chunk *pc)
2338 mtx_lock(&pv_chunks_mutex);
2339 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2340 mtx_unlock(&pv_chunks_mutex);
2341 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2342 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2343 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2344 /* entire chunk is free, return it */
2345 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2346 dump_drop_page(m->phys_addr);
2347 vm_page_unwire_noq(m);
2352 * Returns a new PV entry, allocating a new PV chunk from the system when
2353 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2354 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2357 * The given PV list lock may be released.
2360 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2364 struct pv_chunk *pc;
2367 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2368 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2370 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2372 for (field = 0; field < _NPCM; field++) {
2373 if (pc->pc_map[field]) {
2374 bit = ffsl(pc->pc_map[field]) - 1;
2378 if (field < _NPCM) {
2379 pv = &pc->pc_pventry[field * 64 + bit];
2380 pc->pc_map[field] &= ~(1ul << bit);
2381 /* If this was the last item, move it to tail */
2382 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2383 pc->pc_map[2] == 0) {
2384 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2385 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2388 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2389 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2393 /* No free items, allocate another chunk */
2394 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2397 if (lockp == NULL) {
2398 PV_STAT(pc_chunk_tryfail++);
2401 m = reclaim_pv_chunk(pmap, lockp);
2405 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2406 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2407 dump_add_page(m->phys_addr);
2408 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2410 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2411 pc->pc_map[1] = PC_FREE1;
2412 pc->pc_map[2] = PC_FREE2;
2413 mtx_lock(&pv_chunks_mutex);
2414 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2415 mtx_unlock(&pv_chunks_mutex);
2416 pv = &pc->pc_pventry[0];
2417 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2418 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2419 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2424 * Ensure that the number of spare PV entries in the specified pmap meets or
2425 * exceeds the given count, "needed".
2427 * The given PV list lock may be released.
2430 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2432 struct pch new_tail;
2433 struct pv_chunk *pc;
2438 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2439 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2442 * Newly allocated PV chunks must be stored in a private list until
2443 * the required number of PV chunks have been allocated. Otherwise,
2444 * reclaim_pv_chunk() could recycle one of these chunks. In
2445 * contrast, these chunks must be added to the pmap upon allocation.
2447 TAILQ_INIT(&new_tail);
2450 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2451 bit_count((bitstr_t *)pc->pc_map, 0,
2452 sizeof(pc->pc_map) * NBBY, &free);
2456 if (avail >= needed)
2459 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2460 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2463 m = reclaim_pv_chunk(pmap, lockp);
2468 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2469 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2470 dump_add_page(m->phys_addr);
2471 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2473 pc->pc_map[0] = PC_FREE0;
2474 pc->pc_map[1] = PC_FREE1;
2475 pc->pc_map[2] = PC_FREE2;
2476 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2477 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2478 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2481 * The reclaim might have freed a chunk from the current pmap.
2482 * If that chunk contained available entries, we need to
2483 * re-count the number of available entries.
2488 if (!TAILQ_EMPTY(&new_tail)) {
2489 mtx_lock(&pv_chunks_mutex);
2490 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2491 mtx_unlock(&pv_chunks_mutex);
2496 * First find and then remove the pv entry for the specified pmap and virtual
2497 * address from the specified pv list. Returns the pv entry if found and NULL
2498 * otherwise. This operation can be performed on pv lists for either 4KB or
2499 * 2MB page mappings.
2501 static __inline pv_entry_t
2502 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2506 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2507 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2508 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2517 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2518 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2519 * entries for each of the 4KB page mappings.
2522 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2523 struct rwlock **lockp)
2525 struct md_page *pvh;
2526 struct pv_chunk *pc;
2528 vm_offset_t va_last;
2532 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2533 KASSERT((va & L2_OFFSET) == 0,
2534 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2535 KASSERT((pa & L2_OFFSET) == 0,
2536 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2537 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2540 * Transfer the 2mpage's pv entry for this mapping to the first
2541 * page's pv list. Once this transfer begins, the pv list lock
2542 * must not be released until the last pv entry is reinstantiated.
2544 pvh = pa_to_pvh(pa);
2545 pv = pmap_pvh_remove(pvh, pmap, va);
2546 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2547 m = PHYS_TO_VM_PAGE(pa);
2548 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2550 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2551 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2552 va_last = va + L2_SIZE - PAGE_SIZE;
2554 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2555 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2556 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2557 for (field = 0; field < _NPCM; field++) {
2558 while (pc->pc_map[field]) {
2559 bit = ffsl(pc->pc_map[field]) - 1;
2560 pc->pc_map[field] &= ~(1ul << bit);
2561 pv = &pc->pc_pventry[field * 64 + bit];
2565 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2566 ("pmap_pv_demote_l2: page %p is not managed", m));
2567 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2573 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2574 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2577 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2578 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2579 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2581 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2582 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2586 * First find and then destroy the pv entry for the specified pmap and virtual
2587 * address. This operation can be performed on pv lists for either 4KB or 2MB
2591 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2595 pv = pmap_pvh_remove(pvh, pmap, va);
2596 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2597 free_pv_entry(pmap, pv);
2601 * Conditionally create the PV entry for a 4KB page mapping if the required
2602 * memory can be allocated without resorting to reclamation.
2605 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2606 struct rwlock **lockp)
2610 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2611 /* Pass NULL instead of the lock pointer to disable reclamation. */
2612 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2614 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2615 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2623 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2624 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2625 * false if the PV entry cannot be allocated without resorting to reclamation.
2628 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2629 struct rwlock **lockp)
2631 struct md_page *pvh;
2635 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2636 /* Pass NULL instead of the lock pointer to disable reclamation. */
2637 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2638 NULL : lockp)) == NULL)
2641 pa = l2e & ~ATTR_MASK;
2642 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2643 pvh = pa_to_pvh(pa);
2644 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2650 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2652 pt_entry_t newl2, oldl2;
2656 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2657 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2658 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2660 ml3 = pmap_remove_pt_page(pmap, va);
2662 panic("pmap_remove_kernel_l2: Missing pt page");
2664 ml3pa = VM_PAGE_TO_PHYS(ml3);
2665 newl2 = ml3pa | L2_TABLE;
2668 * If this page table page was unmapped by a promotion, then it
2669 * contains valid mappings. Zero it to invalidate those mappings.
2671 if (ml3->valid != 0)
2672 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2675 * Demote the mapping. The caller must have already invalidated the
2676 * mapping (i.e., the "break" in break-before-make).
2678 oldl2 = pmap_load_store(l2, newl2);
2679 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2680 __func__, l2, oldl2));
2684 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2687 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2688 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2690 struct md_page *pvh;
2692 vm_offset_t eva, va;
2695 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2696 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2697 old_l2 = pmap_load_clear(l2);
2698 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2699 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2702 * Since a promotion must break the 4KB page mappings before making
2703 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2705 pmap_invalidate_page(pmap, sva);
2707 if (old_l2 & ATTR_SW_WIRED)
2708 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2709 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2710 if (old_l2 & ATTR_SW_MANAGED) {
2711 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2712 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2713 pmap_pvh_free(pvh, pmap, sva);
2714 eva = sva + L2_SIZE;
2715 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2716 va < eva; va += PAGE_SIZE, m++) {
2717 if (pmap_pte_dirty(pmap, old_l2))
2719 if (old_l2 & ATTR_AF)
2720 vm_page_aflag_set(m, PGA_REFERENCED);
2721 if (TAILQ_EMPTY(&m->md.pv_list) &&
2722 TAILQ_EMPTY(&pvh->pv_list))
2723 vm_page_aflag_clear(m, PGA_WRITEABLE);
2726 if (pmap == kernel_pmap) {
2727 pmap_remove_kernel_l2(pmap, l2, sva);
2729 ml3 = pmap_remove_pt_page(pmap, sva);
2731 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2732 ("pmap_remove_l2: l3 page not promoted"));
2733 pmap_resident_count_dec(pmap, 1);
2734 KASSERT(ml3->ref_count == NL3PG,
2735 ("pmap_remove_l2: l3 page ref count error"));
2737 pmap_add_delayed_free_list(ml3, free, FALSE);
2740 return (pmap_unuse_pt(pmap, sva, l1e, free));
2744 * pmap_remove_l3: do the things to unmap a page in a process
2747 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2748 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2750 struct md_page *pvh;
2754 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2755 old_l3 = pmap_load_clear(l3);
2756 pmap_invalidate_page(pmap, va);
2757 if (old_l3 & ATTR_SW_WIRED)
2758 pmap->pm_stats.wired_count -= 1;
2759 pmap_resident_count_dec(pmap, 1);
2760 if (old_l3 & ATTR_SW_MANAGED) {
2761 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2762 if (pmap_pte_dirty(pmap, old_l3))
2764 if (old_l3 & ATTR_AF)
2765 vm_page_aflag_set(m, PGA_REFERENCED);
2766 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2767 pmap_pvh_free(&m->md, pmap, va);
2768 if (TAILQ_EMPTY(&m->md.pv_list) &&
2769 (m->flags & PG_FICTITIOUS) == 0) {
2770 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2771 if (TAILQ_EMPTY(&pvh->pv_list))
2772 vm_page_aflag_clear(m, PGA_WRITEABLE);
2775 return (pmap_unuse_pt(pmap, va, l2e, free));
2779 * Remove the specified range of addresses from the L3 page table that is
2780 * identified by the given L2 entry.
2783 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2784 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2786 struct md_page *pvh;
2787 struct rwlock *new_lock;
2788 pt_entry_t *l3, old_l3;
2792 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2793 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2794 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2795 l3pg = sva < VM_MAXUSER_ADDRESS ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) :
2798 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2799 if (!pmap_l3_valid(pmap_load(l3))) {
2801 pmap_invalidate_range(pmap, va, sva);
2806 old_l3 = pmap_load_clear(l3);
2807 if ((old_l3 & ATTR_SW_WIRED) != 0)
2808 pmap->pm_stats.wired_count--;
2809 pmap_resident_count_dec(pmap, 1);
2810 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2811 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2812 if (pmap_pte_dirty(pmap, old_l3))
2814 if ((old_l3 & ATTR_AF) != 0)
2815 vm_page_aflag_set(m, PGA_REFERENCED);
2816 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2817 if (new_lock != *lockp) {
2818 if (*lockp != NULL) {
2820 * Pending TLB invalidations must be
2821 * performed before the PV list lock is
2822 * released. Otherwise, a concurrent
2823 * pmap_remove_all() on a physical page
2824 * could return while a stale TLB entry
2825 * still provides access to that page.
2828 pmap_invalidate_range(pmap, va,
2837 pmap_pvh_free(&m->md, pmap, sva);
2838 if (TAILQ_EMPTY(&m->md.pv_list) &&
2839 (m->flags & PG_FICTITIOUS) == 0) {
2840 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2841 if (TAILQ_EMPTY(&pvh->pv_list))
2842 vm_page_aflag_clear(m, PGA_WRITEABLE);
2847 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
2853 pmap_invalidate_range(pmap, va, sva);
2857 * Remove the given range of addresses from the specified map.
2859 * It is assumed that the start and end are properly
2860 * rounded to the page size.
2863 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2865 struct rwlock *lock;
2866 vm_offset_t va_next;
2867 pd_entry_t *l0, *l1, *l2;
2868 pt_entry_t l3_paddr;
2869 struct spglist free;
2872 * Perform an unsynchronized read. This is, however, safe.
2874 if (pmap->pm_stats.resident_count == 0)
2882 for (; sva < eva; sva = va_next) {
2883 if (pmap->pm_stats.resident_count == 0)
2886 l0 = pmap_l0(pmap, sva);
2887 if (pmap_load(l0) == 0) {
2888 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2894 l1 = pmap_l0_to_l1(l0, sva);
2895 if (pmap_load(l1) == 0) {
2896 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2903 * Calculate index for next page table.
2905 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2909 l2 = pmap_l1_to_l2(l1, sva);
2913 l3_paddr = pmap_load(l2);
2915 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2916 if (sva + L2_SIZE == va_next && eva >= va_next) {
2917 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2920 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2923 l3_paddr = pmap_load(l2);
2927 * Weed out invalid mappings.
2929 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2933 * Limit our scan to either the end of the va represented
2934 * by the current page table page, or to the end of the
2935 * range being removed.
2940 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2946 vm_page_free_pages_toq(&free, true);
2950 * Routine: pmap_remove_all
2952 * Removes this physical page from
2953 * all physical maps in which it resides.
2954 * Reflects back modify bits to the pager.
2957 * Original versions of this routine were very
2958 * inefficient because they iteratively called
2959 * pmap_remove (slow...)
2963 pmap_remove_all(vm_page_t m)
2965 struct md_page *pvh;
2968 struct rwlock *lock;
2969 pd_entry_t *pde, tpde;
2970 pt_entry_t *pte, tpte;
2972 struct spglist free;
2973 int lvl, pvh_gen, md_gen;
2975 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2976 ("pmap_remove_all: page %p is not managed", m));
2978 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2979 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2980 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2983 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2985 if (!PMAP_TRYLOCK(pmap)) {
2986 pvh_gen = pvh->pv_gen;
2990 if (pvh_gen != pvh->pv_gen) {
2997 pte = pmap_pte(pmap, va, &lvl);
2998 KASSERT(pte != NULL,
2999 ("pmap_remove_all: no page table entry found"));
3001 ("pmap_remove_all: invalid pte level %d", lvl));
3003 pmap_demote_l2_locked(pmap, pte, va, &lock);
3006 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3008 PMAP_ASSERT_STAGE1(pmap);
3009 if (!PMAP_TRYLOCK(pmap)) {
3010 pvh_gen = pvh->pv_gen;
3011 md_gen = m->md.pv_gen;
3015 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3021 pmap_resident_count_dec(pmap, 1);
3023 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3024 KASSERT(pde != NULL,
3025 ("pmap_remove_all: no page directory entry found"));
3027 ("pmap_remove_all: invalid pde level %d", lvl));
3028 tpde = pmap_load(pde);
3030 pte = pmap_l2_to_l3(pde, pv->pv_va);
3031 tpte = pmap_load_clear(pte);
3032 if (tpte & ATTR_SW_WIRED)
3033 pmap->pm_stats.wired_count--;
3034 if ((tpte & ATTR_AF) != 0) {
3035 pmap_invalidate_page(pmap, pv->pv_va);
3036 vm_page_aflag_set(m, PGA_REFERENCED);
3040 * Update the vm_page_t clean and reference bits.
3042 if (pmap_pte_dirty(pmap, tpte))
3044 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3045 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3047 free_pv_entry(pmap, pv);
3050 vm_page_aflag_clear(m, PGA_WRITEABLE);
3052 vm_page_free_pages_toq(&free, true);
3056 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
3059 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3065 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3066 PMAP_ASSERT_STAGE1(pmap);
3067 KASSERT((sva & L2_OFFSET) == 0,
3068 ("pmap_protect_l2: sva is not 2mpage aligned"));
3069 old_l2 = pmap_load(l2);
3070 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3071 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3074 * Return if the L2 entry already has the desired access restrictions
3078 if ((old_l2 & mask) == nbits)
3082 * When a dirty read/write superpage mapping is write protected,
3083 * update the dirty field of each of the superpage's constituent 4KB
3086 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3087 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3088 pmap_pte_dirty(pmap, old_l2)) {
3089 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3090 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3094 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3098 * Since a promotion must break the 4KB page mappings before making
3099 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3101 pmap_invalidate_page(pmap, sva);
3105 * Set the physical protection on the
3106 * specified range of this map as requested.
3109 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3111 vm_offset_t va, va_next;
3112 pd_entry_t *l0, *l1, *l2;
3113 pt_entry_t *l3p, l3, mask, nbits;
3115 PMAP_ASSERT_STAGE1(pmap);
3116 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3117 if (prot == VM_PROT_NONE) {
3118 pmap_remove(pmap, sva, eva);
3123 if ((prot & VM_PROT_WRITE) == 0) {
3124 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3125 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3127 if ((prot & VM_PROT_EXECUTE) == 0) {
3129 nbits |= ATTR_S1_XN;
3135 for (; sva < eva; sva = va_next) {
3136 l0 = pmap_l0(pmap, sva);
3137 if (pmap_load(l0) == 0) {
3138 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3144 l1 = pmap_l0_to_l1(l0, sva);
3145 if (pmap_load(l1) == 0) {
3146 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3152 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3156 l2 = pmap_l1_to_l2(l1, sva);
3157 if (pmap_load(l2) == 0)
3160 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3161 if (sva + L2_SIZE == va_next && eva >= va_next) {
3162 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3164 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3167 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3168 ("pmap_protect: Invalid L2 entry after demotion"));
3174 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3176 l3 = pmap_load(l3p);
3179 * Go to the next L3 entry if the current one is
3180 * invalid or already has the desired access
3181 * restrictions in place. (The latter case occurs
3182 * frequently. For example, in a "buildworld"
3183 * workload, almost 1 out of 4 L3 entries already
3184 * have the desired restrictions.)
3186 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3187 if (va != va_next) {
3188 pmap_invalidate_range(pmap, va, sva);
3195 * When a dirty read/write mapping is write protected,
3196 * update the page's dirty field.
3198 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3199 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3200 pmap_pte_dirty(pmap, l3))
3201 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3203 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3209 pmap_invalidate_range(pmap, va, sva);
3215 * Inserts the specified page table page into the specified pmap's collection
3216 * of idle page table pages. Each of a pmap's page table pages is responsible
3217 * for mapping a distinct range of virtual addresses. The pmap's collection is
3218 * ordered by this virtual address range.
3220 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3223 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3226 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3227 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3228 return (vm_radix_insert(&pmap->pm_root, mpte));
3232 * Removes the page table page mapping the specified virtual address from the
3233 * specified pmap's collection of idle page table pages, and returns it.
3234 * Otherwise, returns NULL if there is no page table page corresponding to the
3235 * specified virtual address.
3237 static __inline vm_page_t
3238 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3241 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3242 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3246 * Performs a break-before-make update of a pmap entry. This is needed when
3247 * either promoting or demoting pages to ensure the TLB doesn't get into an
3248 * inconsistent state.
3251 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3252 vm_offset_t va, vm_size_t size)
3256 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3259 * Ensure we don't get switched out with the page table in an
3260 * inconsistent state. We also need to ensure no interrupts fire
3261 * as they may make use of an address we are about to invalidate.
3263 intr = intr_disable();
3266 * Clear the old mapping's valid bit, but leave the rest of the entry
3267 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3268 * lookup the physical address.
3270 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3271 pmap_invalidate_range(pmap, va, va + size);
3273 /* Create the new mapping */
3274 pmap_store(pte, newpte);
3280 #if VM_NRESERVLEVEL > 0
3282 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3283 * replace the many pv entries for the 4KB page mappings by a single pv entry
3284 * for the 2MB page mapping.
3287 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3288 struct rwlock **lockp)
3290 struct md_page *pvh;
3292 vm_offset_t va_last;
3295 KASSERT((pa & L2_OFFSET) == 0,
3296 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3297 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3300 * Transfer the first page's pv entry for this mapping to the 2mpage's
3301 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3302 * a transfer avoids the possibility that get_pv_entry() calls
3303 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3304 * mappings that is being promoted.
3306 m = PHYS_TO_VM_PAGE(pa);
3307 va = va & ~L2_OFFSET;
3308 pv = pmap_pvh_remove(&m->md, pmap, va);
3309 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3310 pvh = pa_to_pvh(pa);
3311 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3313 /* Free the remaining NPTEPG - 1 pv entries. */
3314 va_last = va + L2_SIZE - PAGE_SIZE;
3318 pmap_pvh_free(&m->md, pmap, va);
3319 } while (va < va_last);
3323 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3324 * single level 2 table entry to a single 2MB page mapping. For promotion
3325 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3326 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3327 * identical characteristics.
3330 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3331 struct rwlock **lockp)
3333 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3337 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3338 PMAP_ASSERT_STAGE1(pmap);
3340 sva = va & ~L2_OFFSET;
3341 firstl3 = pmap_l2_to_l3(l2, sva);
3342 newl2 = pmap_load(firstl3);
3345 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3346 atomic_add_long(&pmap_l2_p_failures, 1);
3347 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3348 " in pmap %p", va, pmap);
3352 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3353 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3354 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3356 newl2 &= ~ATTR_SW_DBM;
3359 pa = newl2 + L2_SIZE - PAGE_SIZE;
3360 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3361 oldl3 = pmap_load(l3);
3363 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3364 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3365 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3368 oldl3 &= ~ATTR_SW_DBM;
3371 atomic_add_long(&pmap_l2_p_failures, 1);
3372 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3373 " in pmap %p", va, pmap);
3380 * Save the page table page in its current state until the L2
3381 * mapping the superpage is demoted by pmap_demote_l2() or
3382 * destroyed by pmap_remove_l3().
3384 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3385 KASSERT(mpte >= vm_page_array &&
3386 mpte < &vm_page_array[vm_page_array_size],
3387 ("pmap_promote_l2: page table page is out of range"));
3388 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3389 ("pmap_promote_l2: page table page's pindex is wrong"));
3390 if (pmap_insert_pt_page(pmap, mpte, true)) {
3391 atomic_add_long(&pmap_l2_p_failures, 1);
3393 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3398 if ((newl2 & ATTR_SW_MANAGED) != 0)
3399 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3401 newl2 &= ~ATTR_DESCR_MASK;
3404 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3406 atomic_add_long(&pmap_l2_promotions, 1);
3407 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3410 #endif /* VM_NRESERVLEVEL > 0 */
3413 * Insert the given physical page (p) at
3414 * the specified virtual address (v) in the
3415 * target physical map with the protection requested.
3417 * If specified, the page will be wired down, meaning
3418 * that the related pte can not be reclaimed.
3420 * NB: This is the only routine which MAY NOT lazy-evaluate
3421 * or lose information. That is, this routine must actually
3422 * insert this page into the given map NOW.
3425 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3426 u_int flags, int8_t psind)
3428 struct rwlock *lock;
3430 pt_entry_t new_l3, orig_l3;
3431 pt_entry_t *l2, *l3;
3438 va = trunc_page(va);
3439 if ((m->oflags & VPO_UNMANAGED) == 0)
3440 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3441 pa = VM_PAGE_TO_PHYS(m);
3442 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE);
3443 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
3444 new_l3 |= pmap_pte_prot(pmap, prot);
3446 if ((flags & PMAP_ENTER_WIRED) != 0)
3447 new_l3 |= ATTR_SW_WIRED;
3448 if (pmap->pm_stage == PM_STAGE1) {
3449 if (va < VM_MAXUSER_ADDRESS)
3450 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3452 new_l3 |= ATTR_S1_UXN;
3453 if (pmap != kernel_pmap)
3454 new_l3 |= ATTR_S1_nG;
3457 * Clear the access flag on executable mappings, this will be
3458 * set later when the page is accessed. The fault handler is
3459 * required to invalidate the I-cache.
3461 * TODO: Switch to the valid flag to allow hardware management
3462 * of the access flag. Much of the pmap code assumes the
3463 * valid flag is set and fails to destroy the old page tables
3464 * correctly if it is clear.
3466 if (prot & VM_PROT_EXECUTE)
3469 if ((m->oflags & VPO_UNMANAGED) == 0) {
3470 new_l3 |= ATTR_SW_MANAGED;
3471 if ((prot & VM_PROT_WRITE) != 0) {
3472 new_l3 |= ATTR_SW_DBM;
3473 if ((flags & VM_PROT_WRITE) == 0) {
3474 if (pmap->pm_stage == PM_STAGE1)
3475 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3478 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
3483 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3488 /* Assert the required virtual and physical alignment. */
3489 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3490 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3491 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3498 * In the case that a page table page is not
3499 * resident, we are creating it here.
3502 pde = pmap_pde(pmap, va, &lvl);
3503 if (pde != NULL && lvl == 2) {
3504 l3 = pmap_l2_to_l3(pde, va);
3505 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3506 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3510 } else if (pde != NULL && lvl == 1) {
3511 l2 = pmap_l1_to_l2(pde, va);
3512 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3513 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3514 l3 = &l3[pmap_l3_index(va)];
3515 if (va < VM_MAXUSER_ADDRESS) {
3516 mpte = PHYS_TO_VM_PAGE(
3517 pmap_load(l2) & ~ATTR_MASK);
3522 /* We need to allocate an L3 table. */
3524 if (va < VM_MAXUSER_ADDRESS) {
3525 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3528 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3529 * to handle the possibility that a superpage mapping for "va"
3530 * was created while we slept.
3532 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3533 nosleep ? NULL : &lock);
3534 if (mpte == NULL && nosleep) {
3535 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3536 rv = KERN_RESOURCE_SHORTAGE;
3541 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3544 orig_l3 = pmap_load(l3);
3545 opa = orig_l3 & ~ATTR_MASK;
3549 * Is the specified virtual address already mapped?
3551 if (pmap_l3_valid(orig_l3)) {
3553 * Only allow adding new entries on stage 2 tables for now.
3554 * This simplifies cache invalidation as we may need to call
3555 * into EL2 to perform such actions.
3557 PMAP_ASSERT_STAGE1(pmap);
3559 * Wiring change, just update stats. We don't worry about
3560 * wiring PT pages as they remain resident as long as there
3561 * are valid mappings in them. Hence, if a user page is wired,
3562 * the PT page will be also.
3564 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3565 (orig_l3 & ATTR_SW_WIRED) == 0)
3566 pmap->pm_stats.wired_count++;
3567 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3568 (orig_l3 & ATTR_SW_WIRED) != 0)
3569 pmap->pm_stats.wired_count--;
3572 * Remove the extra PT page reference.
3576 KASSERT(mpte->ref_count > 0,
3577 ("pmap_enter: missing reference to page table page,"
3582 * Has the physical page changed?
3586 * No, might be a protection or wiring change.
3588 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3589 (new_l3 & ATTR_SW_DBM) != 0)
3590 vm_page_aflag_set(m, PGA_WRITEABLE);
3595 * The physical page has changed. Temporarily invalidate
3598 orig_l3 = pmap_load_clear(l3);
3599 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3600 ("pmap_enter: unexpected pa update for %#lx", va));
3601 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3602 om = PHYS_TO_VM_PAGE(opa);
3605 * The pmap lock is sufficient to synchronize with
3606 * concurrent calls to pmap_page_test_mappings() and
3607 * pmap_ts_referenced().
3609 if (pmap_pte_dirty(pmap, orig_l3))
3611 if ((orig_l3 & ATTR_AF) != 0) {
3612 pmap_invalidate_page(pmap, va);
3613 vm_page_aflag_set(om, PGA_REFERENCED);
3615 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3616 pv = pmap_pvh_remove(&om->md, pmap, va);
3617 if ((m->oflags & VPO_UNMANAGED) != 0)
3618 free_pv_entry(pmap, pv);
3619 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3620 TAILQ_EMPTY(&om->md.pv_list) &&
3621 ((om->flags & PG_FICTITIOUS) != 0 ||
3622 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3623 vm_page_aflag_clear(om, PGA_WRITEABLE);
3625 KASSERT((orig_l3 & ATTR_AF) != 0,
3626 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
3627 pmap_invalidate_page(pmap, va);
3632 * Increment the counters.
3634 if ((new_l3 & ATTR_SW_WIRED) != 0)
3635 pmap->pm_stats.wired_count++;
3636 pmap_resident_count_inc(pmap, 1);
3639 * Enter on the PV list if part of our managed memory.
3641 if ((m->oflags & VPO_UNMANAGED) == 0) {
3643 pv = get_pv_entry(pmap, &lock);
3646 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3647 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3649 if ((new_l3 & ATTR_SW_DBM) != 0)
3650 vm_page_aflag_set(m, PGA_WRITEABLE);
3654 if (pmap->pm_stage == PM_STAGE1) {
3656 * Sync icache if exec permission and attribute
3657 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
3658 * is stored and made valid for hardware table walk. If done
3659 * later, then other can access this page before caches are
3660 * properly synced. Don't do it for kernel memory which is
3661 * mapped with exec permission even if the memory isn't going
3662 * to hold executable code. The only time when icache sync is
3663 * needed is after kernel module is loaded and the relocation
3664 * info is processed. And it's done in elf_cpu_load_file().
3666 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3667 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3668 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
3669 PMAP_ASSERT_STAGE1(pmap);
3670 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3673 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3677 * Update the L3 entry
3679 if (pmap_l3_valid(orig_l3)) {
3680 PMAP_ASSERT_STAGE1(pmap);
3681 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3682 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3683 /* same PA, different attributes */
3684 orig_l3 = pmap_load_store(l3, new_l3);
3685 pmap_invalidate_page(pmap, va);
3686 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3687 pmap_pte_dirty(pmap, orig_l3))
3692 * This can happens if multiple threads simultaneously
3693 * access not yet mapped page. This bad for performance
3694 * since this can cause full demotion-NOP-promotion
3696 * Another possible reasons are:
3697 * - VM and pmap memory layout are diverged
3698 * - tlb flush is missing somewhere and CPU doesn't see
3701 CTR4(KTR_PMAP, "%s: already mapped page - "
3702 "pmap %p va 0x%#lx pte 0x%lx",
3703 __func__, pmap, va, new_l3);
3707 pmap_store(l3, new_l3);
3711 #if VM_NRESERVLEVEL > 0
3713 * Try to promote from level 3 pages to a level 2 superpage. This
3714 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at
3715 * stage 1 specific fields and performs a break-before-make sequence
3716 * that is incorrect a stage 2 pmap.
3718 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
3719 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 &&
3720 (m->flags & PG_FICTITIOUS) == 0 &&
3721 vm_reserv_level_iffullpop(m) == 0) {
3722 pmap_promote_l2(pmap, pde, va, &lock);
3735 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3736 * if successful. Returns false if (1) a page table page cannot be allocated
3737 * without sleeping, (2) a mapping already exists at the specified virtual
3738 * address, or (3) a PV entry cannot be allocated without reclaiming another
3742 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3743 struct rwlock **lockp)
3747 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3748 PMAP_ASSERT_STAGE1(pmap);
3750 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3751 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
3753 if ((m->oflags & VPO_UNMANAGED) == 0) {
3754 new_l2 |= ATTR_SW_MANAGED;
3757 if ((prot & VM_PROT_EXECUTE) == 0 ||
3758 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3759 new_l2 |= ATTR_S1_XN;
3760 if (va < VM_MAXUSER_ADDRESS)
3761 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3763 new_l2 |= ATTR_S1_UXN;
3764 if (pmap != kernel_pmap)
3765 new_l2 |= ATTR_S1_nG;
3766 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3767 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3772 * Returns true if every page table entry in the specified page table is
3776 pmap_every_pte_zero(vm_paddr_t pa)
3778 pt_entry_t *pt_end, *pte;
3780 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
3781 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
3782 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
3790 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3791 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3792 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3793 * a mapping already exists at the specified virtual address. Returns
3794 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3795 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3796 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3798 * The parameter "m" is only used when creating a managed, writeable mapping.
3801 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3802 vm_page_t m, struct rwlock **lockp)
3804 struct spglist free;
3805 pd_entry_t *l2, old_l2;
3808 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3810 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
3811 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
3812 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3814 return (KERN_RESOURCE_SHORTAGE);
3818 * If there are existing mappings, either abort or remove them.
3820 if ((old_l2 = pmap_load(l2)) != 0) {
3821 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
3822 ("pmap_enter_l2: l2pg's ref count is too low"));
3823 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
3824 VM_MAXUSER_ADDRESS || (old_l2 & ATTR_DESCR_MASK) ==
3825 L2_BLOCK || !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
3828 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
3829 " in pmap %p", va, pmap);
3830 return (KERN_FAILURE);
3833 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3834 (void)pmap_remove_l2(pmap, l2, va,
3835 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3837 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3839 if (va < VM_MAXUSER_ADDRESS) {
3840 vm_page_free_pages_toq(&free, true);
3841 KASSERT(pmap_load(l2) == 0,
3842 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3844 KASSERT(SLIST_EMPTY(&free),
3845 ("pmap_enter_l2: freed kernel page table page"));
3848 * Both pmap_remove_l2() and pmap_remove_l3_range()
3849 * will leave the kernel page table page zero filled.
3850 * Nonetheless, the TLB could have an intermediate
3851 * entry for the kernel page table page.
3853 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3854 if (pmap_insert_pt_page(pmap, mt, false))
3855 panic("pmap_enter_l2: trie insert failed");
3857 pmap_invalidate_page(pmap, va);
3861 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3863 * Abort this mapping if its PV entry could not be created.
3865 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3867 pmap_abort_ptp(pmap, va, l2pg);
3869 "pmap_enter_l2: failure for va %#lx in pmap %p",
3871 return (KERN_RESOURCE_SHORTAGE);
3873 if ((new_l2 & ATTR_SW_DBM) != 0)
3874 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3875 vm_page_aflag_set(mt, PGA_WRITEABLE);
3879 * Increment counters.
3881 if ((new_l2 & ATTR_SW_WIRED) != 0)
3882 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3883 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3886 * Map the superpage.
3888 pmap_store(l2, new_l2);
3891 atomic_add_long(&pmap_l2_mappings, 1);
3892 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3895 return (KERN_SUCCESS);
3899 * Maps a sequence of resident pages belonging to the same object.
3900 * The sequence begins with the given page m_start. This page is
3901 * mapped at the given virtual address start. Each subsequent page is
3902 * mapped at a virtual address that is offset from start by the same
3903 * amount as the page is offset from m_start within the object. The
3904 * last page in the sequence is the page with the largest offset from
3905 * m_start that can be mapped at a virtual address less than the given
3906 * virtual address end. Not every virtual page between start and end
3907 * is mapped; only those for which a resident page exists with the
3908 * corresponding offset from m_start are mapped.
3911 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3912 vm_page_t m_start, vm_prot_t prot)
3914 struct rwlock *lock;
3917 vm_pindex_t diff, psize;
3919 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3921 psize = atop(end - start);
3926 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3927 va = start + ptoa(diff);
3928 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3929 m->psind == 1 && pmap_ps_enabled(pmap) &&
3930 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3931 m = &m[L2_SIZE / PAGE_SIZE - 1];
3933 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3935 m = TAILQ_NEXT(m, listq);
3943 * this code makes some *MAJOR* assumptions:
3944 * 1. Current pmap & pmap exists.
3947 * 4. No page table pages.
3948 * but is *MUCH* faster than pmap_enter...
3952 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3954 struct rwlock *lock;
3958 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3965 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3966 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3969 pt_entry_t *l2, *l3, l3_val;
3973 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3974 (m->oflags & VPO_UNMANAGED) != 0,
3975 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3976 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3977 PMAP_ASSERT_STAGE1(pmap);
3979 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3981 * In the case that a page table page is not
3982 * resident, we are creating it here.
3984 if (va < VM_MAXUSER_ADDRESS) {
3985 vm_pindex_t l2pindex;
3988 * Calculate pagetable page index
3990 l2pindex = pmap_l2_pindex(va);
3991 if (mpte && (mpte->pindex == l2pindex)) {
3997 pde = pmap_pde(pmap, va, &lvl);
4000 * If the page table page is mapped, we just increment
4001 * the hold count, and activate it. Otherwise, we
4002 * attempt to allocate a page table page. If this
4003 * attempt fails, we don't retry. Instead, we give up.
4006 l2 = pmap_l1_to_l2(pde, va);
4007 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
4011 if (lvl == 2 && pmap_load(pde) != 0) {
4013 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4017 * Pass NULL instead of the PV list lock
4018 * pointer, because we don't intend to sleep.
4020 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
4025 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4026 l3 = &l3[pmap_l3_index(va)];
4029 pde = pmap_pde(kernel_pmap, va, &lvl);
4030 KASSERT(pde != NULL,
4031 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
4034 ("pmap_enter_quick_locked: Invalid level %d", lvl));
4035 l3 = pmap_l2_to_l3(pde, va);
4039 * Abort if a mapping already exists.
4041 if (pmap_load(l3) != 0) {
4048 * Enter on the PV list if part of our managed memory.
4050 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4051 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4053 pmap_abort_ptp(pmap, va, mpte);
4058 * Increment counters
4060 pmap_resident_count_inc(pmap, 1);
4062 pa = VM_PAGE_TO_PHYS(m);
4063 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
4064 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
4065 if ((prot & VM_PROT_EXECUTE) == 0 ||
4066 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4067 l3_val |= ATTR_S1_XN;
4068 if (va < VM_MAXUSER_ADDRESS)
4069 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4071 l3_val |= ATTR_S1_UXN;
4072 if (pmap != kernel_pmap)
4073 l3_val |= ATTR_S1_nG;
4076 * Now validate mapping with RO protection
4078 if ((m->oflags & VPO_UNMANAGED) == 0) {
4079 l3_val |= ATTR_SW_MANAGED;
4083 /* Sync icache before the mapping is stored to PTE */
4084 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4085 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
4086 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4088 pmap_store(l3, l3_val);
4095 * This code maps large physical mmap regions into the
4096 * processor address space. Note that some shortcuts
4097 * are taken, but the code works.
4100 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4101 vm_pindex_t pindex, vm_size_t size)
4104 VM_OBJECT_ASSERT_WLOCKED(object);
4105 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4106 ("pmap_object_init_pt: non-device object"));
4110 * Clear the wired attribute from the mappings for the specified range of
4111 * addresses in the given pmap. Every valid mapping within that range
4112 * must have the wired attribute set. In contrast, invalid mappings
4113 * cannot have the wired attribute set, so they are ignored.
4115 * The wired attribute of the page table entry is not a hardware feature,
4116 * so there is no need to invalidate any TLB entries.
4119 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4121 vm_offset_t va_next;
4122 pd_entry_t *l0, *l1, *l2;
4126 for (; sva < eva; sva = va_next) {
4127 l0 = pmap_l0(pmap, sva);
4128 if (pmap_load(l0) == 0) {
4129 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4135 l1 = pmap_l0_to_l1(l0, sva);
4136 if (pmap_load(l1) == 0) {
4137 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4143 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4147 l2 = pmap_l1_to_l2(l1, sva);
4148 if (pmap_load(l2) == 0)
4151 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4152 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4153 panic("pmap_unwire: l2 %#jx is missing "
4154 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4157 * Are we unwiring the entire large page? If not,
4158 * demote the mapping and fall through.
4160 if (sva + L2_SIZE == va_next && eva >= va_next) {
4161 pmap_clear_bits(l2, ATTR_SW_WIRED);
4162 pmap->pm_stats.wired_count -= L2_SIZE /
4165 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4166 panic("pmap_unwire: demotion failed");
4168 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4169 ("pmap_unwire: Invalid l2 entry after demotion"));
4173 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4175 if (pmap_load(l3) == 0)
4177 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4178 panic("pmap_unwire: l3 %#jx is missing "
4179 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4182 * ATTR_SW_WIRED must be cleared atomically. Although
4183 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4184 * the System MMU may write to the entry concurrently.
4186 pmap_clear_bits(l3, ATTR_SW_WIRED);
4187 pmap->pm_stats.wired_count--;
4194 * Copy the range specified by src_addr/len
4195 * from the source map to the range dst_addr/len
4196 * in the destination map.
4198 * This routine is only advisory and need not do anything.
4200 * Because the executable mappings created by this routine are copied,
4201 * it should not have to flush the instruction cache.
4204 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4205 vm_offset_t src_addr)
4207 struct rwlock *lock;
4208 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4209 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4210 vm_offset_t addr, end_addr, va_next;
4211 vm_page_t dst_l2pg, dstmpte, srcmpte;
4213 PMAP_ASSERT_STAGE1(dst_pmap);
4214 PMAP_ASSERT_STAGE1(src_pmap);
4216 if (dst_addr != src_addr)
4218 end_addr = src_addr + len;
4220 if (dst_pmap < src_pmap) {
4221 PMAP_LOCK(dst_pmap);
4222 PMAP_LOCK(src_pmap);
4224 PMAP_LOCK(src_pmap);
4225 PMAP_LOCK(dst_pmap);
4227 for (addr = src_addr; addr < end_addr; addr = va_next) {
4228 l0 = pmap_l0(src_pmap, addr);
4229 if (pmap_load(l0) == 0) {
4230 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4235 l1 = pmap_l0_to_l1(l0, addr);
4236 if (pmap_load(l1) == 0) {
4237 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4242 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4245 l2 = pmap_l1_to_l2(l1, addr);
4246 srcptepaddr = pmap_load(l2);
4247 if (srcptepaddr == 0)
4249 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4250 if ((addr & L2_OFFSET) != 0 ||
4251 addr + L2_SIZE > end_addr)
4253 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_l2pg, NULL);
4256 if (pmap_load(l2) == 0 &&
4257 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4258 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4259 PMAP_ENTER_NORECLAIM, &lock))) {
4260 mask = ATTR_AF | ATTR_SW_WIRED;
4262 if ((srcptepaddr & ATTR_SW_DBM) != 0)
4263 nbits |= ATTR_S1_AP_RW_BIT;
4264 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
4265 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4267 atomic_add_long(&pmap_l2_mappings, 1);
4269 pmap_abort_ptp(dst_pmap, addr, dst_l2pg);
4272 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4273 ("pmap_copy: invalid L2 entry"));
4274 srcptepaddr &= ~ATTR_MASK;
4275 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4276 KASSERT(srcmpte->ref_count > 0,
4277 ("pmap_copy: source page table page is unused"));
4278 if (va_next > end_addr)
4280 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4281 src_pte = &src_pte[pmap_l3_index(addr)];
4283 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4284 ptetemp = pmap_load(src_pte);
4287 * We only virtual copy managed pages.
4289 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4292 if (dstmpte != NULL) {
4293 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4294 ("dstmpte pindex/addr mismatch"));
4295 dstmpte->ref_count++;
4296 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4299 dst_pte = (pt_entry_t *)
4300 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4301 dst_pte = &dst_pte[pmap_l3_index(addr)];
4302 if (pmap_load(dst_pte) == 0 &&
4303 pmap_try_insert_pv_entry(dst_pmap, addr,
4304 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4306 * Clear the wired, modified, and accessed
4307 * (referenced) bits during the copy.
4309 mask = ATTR_AF | ATTR_SW_WIRED;
4311 if ((ptetemp & ATTR_SW_DBM) != 0)
4312 nbits |= ATTR_S1_AP_RW_BIT;
4313 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4314 pmap_resident_count_inc(dst_pmap, 1);
4316 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4319 /* Have we copied all of the valid mappings? */
4320 if (dstmpte->ref_count >= srcmpte->ref_count)
4326 * XXX This barrier may not be needed because the destination pmap is
4333 PMAP_UNLOCK(src_pmap);
4334 PMAP_UNLOCK(dst_pmap);
4338 * pmap_zero_page zeros the specified hardware page by mapping
4339 * the page into KVM and using bzero to clear its contents.
4342 pmap_zero_page(vm_page_t m)
4344 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4346 pagezero((void *)va);
4350 * pmap_zero_page_area zeros the specified hardware page by mapping
4351 * the page into KVM and using bzero to clear its contents.
4353 * off and size may not cover an area beyond a single hardware page.
4356 pmap_zero_page_area(vm_page_t m, int off, int size)
4358 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4360 if (off == 0 && size == PAGE_SIZE)
4361 pagezero((void *)va);
4363 bzero((char *)va + off, size);
4367 * pmap_copy_page copies the specified (machine independent)
4368 * page by mapping the page into virtual memory and using
4369 * bcopy to copy the page, one machine dependent page at a
4373 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4375 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4376 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4378 pagecopy((void *)src, (void *)dst);
4381 int unmapped_buf_allowed = 1;
4384 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4385 vm_offset_t b_offset, int xfersize)
4389 vm_paddr_t p_a, p_b;
4390 vm_offset_t a_pg_offset, b_pg_offset;
4393 while (xfersize > 0) {
4394 a_pg_offset = a_offset & PAGE_MASK;
4395 m_a = ma[a_offset >> PAGE_SHIFT];
4396 p_a = m_a->phys_addr;
4397 b_pg_offset = b_offset & PAGE_MASK;
4398 m_b = mb[b_offset >> PAGE_SHIFT];
4399 p_b = m_b->phys_addr;
4400 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4401 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4402 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4403 panic("!DMAP a %lx", p_a);
4405 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4407 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4408 panic("!DMAP b %lx", p_b);
4410 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4412 bcopy(a_cp, b_cp, cnt);
4420 pmap_quick_enter_page(vm_page_t m)
4423 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4427 pmap_quick_remove_page(vm_offset_t addr)
4432 * Returns true if the pmap's pv is one of the first
4433 * 16 pvs linked to from this page. This count may
4434 * be changed upwards or downwards in the future; it
4435 * is only necessary that true be returned for a small
4436 * subset of pmaps for proper page aging.
4439 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4441 struct md_page *pvh;
4442 struct rwlock *lock;
4447 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4448 ("pmap_page_exists_quick: page %p is not managed", m));
4450 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4452 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4453 if (PV_PMAP(pv) == pmap) {
4461 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4462 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4463 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4464 if (PV_PMAP(pv) == pmap) {
4478 * pmap_page_wired_mappings:
4480 * Return the number of managed mappings to the given physical page
4484 pmap_page_wired_mappings(vm_page_t m)
4486 struct rwlock *lock;
4487 struct md_page *pvh;
4491 int count, lvl, md_gen, pvh_gen;
4493 if ((m->oflags & VPO_UNMANAGED) != 0)
4495 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4499 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4501 if (!PMAP_TRYLOCK(pmap)) {
4502 md_gen = m->md.pv_gen;
4506 if (md_gen != m->md.pv_gen) {
4511 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4512 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4516 if ((m->flags & PG_FICTITIOUS) == 0) {
4517 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4518 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4520 if (!PMAP_TRYLOCK(pmap)) {
4521 md_gen = m->md.pv_gen;
4522 pvh_gen = pvh->pv_gen;
4526 if (md_gen != m->md.pv_gen ||
4527 pvh_gen != pvh->pv_gen) {
4532 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4534 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4544 * Returns true if the given page is mapped individually or as part of
4545 * a 2mpage. Otherwise, returns false.
4548 pmap_page_is_mapped(vm_page_t m)
4550 struct rwlock *lock;
4553 if ((m->oflags & VPO_UNMANAGED) != 0)
4555 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4557 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4558 ((m->flags & PG_FICTITIOUS) == 0 &&
4559 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4565 * Destroy all managed, non-wired mappings in the given user-space
4566 * pmap. This pmap cannot be active on any processor besides the
4569 * This function cannot be applied to the kernel pmap. Moreover, it
4570 * is not intended for general use. It is only to be used during
4571 * process termination. Consequently, it can be implemented in ways
4572 * that make it faster than pmap_remove(). First, it can more quickly
4573 * destroy mappings by iterating over the pmap's collection of PV
4574 * entries, rather than searching the page table. Second, it doesn't
4575 * have to test and clear the page table entries atomically, because
4576 * no processor is currently accessing the user address space. In
4577 * particular, a page table entry's dirty bit won't change state once
4578 * this function starts.
4581 pmap_remove_pages(pmap_t pmap)
4584 pt_entry_t *pte, tpte;
4585 struct spglist free;
4586 vm_page_t m, ml3, mt;
4588 struct md_page *pvh;
4589 struct pv_chunk *pc, *npc;
4590 struct rwlock *lock;
4592 uint64_t inuse, bitmask;
4593 int allfree, field, freed, idx, lvl;
4596 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4602 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4605 for (field = 0; field < _NPCM; field++) {
4606 inuse = ~pc->pc_map[field] & pc_freemask[field];
4607 while (inuse != 0) {
4608 bit = ffsl(inuse) - 1;
4609 bitmask = 1UL << bit;
4610 idx = field * 64 + bit;
4611 pv = &pc->pc_pventry[idx];
4614 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4615 KASSERT(pde != NULL,
4616 ("Attempting to remove an unmapped page"));
4620 pte = pmap_l1_to_l2(pde, pv->pv_va);
4621 tpte = pmap_load(pte);
4622 KASSERT((tpte & ATTR_DESCR_MASK) ==
4624 ("Attempting to remove an invalid "
4625 "block: %lx", tpte));
4628 pte = pmap_l2_to_l3(pde, pv->pv_va);
4629 tpte = pmap_load(pte);
4630 KASSERT((tpte & ATTR_DESCR_MASK) ==
4632 ("Attempting to remove an invalid "
4633 "page: %lx", tpte));
4637 "Invalid page directory level: %d",
4642 * We cannot remove wired pages from a process' mapping at this time
4644 if (tpte & ATTR_SW_WIRED) {
4649 pa = tpte & ~ATTR_MASK;
4651 m = PHYS_TO_VM_PAGE(pa);
4652 KASSERT(m->phys_addr == pa,
4653 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4654 m, (uintmax_t)m->phys_addr,
4657 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4658 m < &vm_page_array[vm_page_array_size],
4659 ("pmap_remove_pages: bad pte %#jx",
4663 * Because this pmap is not active on other
4664 * processors, the dirty bit cannot have
4665 * changed state since we last loaded pte.
4670 * Update the vm_page_t clean/reference bits.
4672 if (pmap_pte_dirty(pmap, tpte)) {
4675 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4684 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4687 pc->pc_map[field] |= bitmask;
4690 pmap_resident_count_dec(pmap,
4691 L2_SIZE / PAGE_SIZE);
4692 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4693 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4695 if (TAILQ_EMPTY(&pvh->pv_list)) {
4696 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4697 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
4698 TAILQ_EMPTY(&mt->md.pv_list))
4699 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4701 ml3 = pmap_remove_pt_page(pmap,
4704 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4705 ("pmap_remove_pages: l3 page not promoted"));
4706 pmap_resident_count_dec(pmap,1);
4707 KASSERT(ml3->ref_count == NL3PG,
4708 ("pmap_remove_pages: l3 page ref count error"));
4710 pmap_add_delayed_free_list(ml3,
4715 pmap_resident_count_dec(pmap, 1);
4716 TAILQ_REMOVE(&m->md.pv_list, pv,
4719 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
4720 TAILQ_EMPTY(&m->md.pv_list) &&
4721 (m->flags & PG_FICTITIOUS) == 0) {
4723 VM_PAGE_TO_PHYS(m));
4724 if (TAILQ_EMPTY(&pvh->pv_list))
4725 vm_page_aflag_clear(m,
4730 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4735 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4736 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4737 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4739 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4745 pmap_invalidate_all(pmap);
4747 vm_page_free_pages_toq(&free, true);
4751 * This is used to check if a page has been accessed or modified.
4754 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4756 struct rwlock *lock;
4758 struct md_page *pvh;
4759 pt_entry_t *pte, mask, value;
4761 int lvl, md_gen, pvh_gen;
4765 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4768 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4770 PMAP_ASSERT_STAGE1(pmap);
4771 if (!PMAP_TRYLOCK(pmap)) {
4772 md_gen = m->md.pv_gen;
4776 if (md_gen != m->md.pv_gen) {
4781 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4783 ("pmap_page_test_mappings: Invalid level %d", lvl));
4787 mask |= ATTR_S1_AP_RW_BIT;
4788 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4791 mask |= ATTR_AF | ATTR_DESCR_MASK;
4792 value |= ATTR_AF | L3_PAGE;
4794 rv = (pmap_load(pte) & mask) == value;
4799 if ((m->flags & PG_FICTITIOUS) == 0) {
4800 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4801 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4803 PMAP_ASSERT_STAGE1(pmap);
4804 if (!PMAP_TRYLOCK(pmap)) {
4805 md_gen = m->md.pv_gen;
4806 pvh_gen = pvh->pv_gen;
4810 if (md_gen != m->md.pv_gen ||
4811 pvh_gen != pvh->pv_gen) {
4816 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4818 ("pmap_page_test_mappings: Invalid level %d", lvl));
4822 mask |= ATTR_S1_AP_RW_BIT;
4823 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4826 mask |= ATTR_AF | ATTR_DESCR_MASK;
4827 value |= ATTR_AF | L2_BLOCK;
4829 rv = (pmap_load(pte) & mask) == value;
4843 * Return whether or not the specified physical page was modified
4844 * in any physical maps.
4847 pmap_is_modified(vm_page_t m)
4850 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4851 ("pmap_is_modified: page %p is not managed", m));
4854 * If the page is not busied then this check is racy.
4856 if (!pmap_page_is_write_mapped(m))
4858 return (pmap_page_test_mappings(m, FALSE, TRUE));
4862 * pmap_is_prefaultable:
4864 * Return whether or not the specified virtual address is eligible
4868 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4876 pte = pmap_pte(pmap, addr, &lvl);
4877 if (pte != NULL && pmap_load(pte) != 0) {
4885 * pmap_is_referenced:
4887 * Return whether or not the specified physical page was referenced
4888 * in any physical maps.
4891 pmap_is_referenced(vm_page_t m)
4894 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4895 ("pmap_is_referenced: page %p is not managed", m));
4896 return (pmap_page_test_mappings(m, TRUE, FALSE));
4900 * Clear the write and modified bits in each of the given page's mappings.
4903 pmap_remove_write(vm_page_t m)
4905 struct md_page *pvh;
4907 struct rwlock *lock;
4908 pv_entry_t next_pv, pv;
4909 pt_entry_t oldpte, *pte;
4911 int lvl, md_gen, pvh_gen;
4913 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4914 ("pmap_remove_write: page %p is not managed", m));
4915 vm_page_assert_busied(m);
4917 if (!pmap_page_is_write_mapped(m))
4919 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4920 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4921 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4924 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4926 PMAP_ASSERT_STAGE1(pmap);
4927 if (!PMAP_TRYLOCK(pmap)) {
4928 pvh_gen = pvh->pv_gen;
4932 if (pvh_gen != pvh->pv_gen) {
4939 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4940 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4941 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4942 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4943 ("inconsistent pv lock %p %p for page %p",
4944 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4947 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4949 PMAP_ASSERT_STAGE1(pmap);
4950 if (!PMAP_TRYLOCK(pmap)) {
4951 pvh_gen = pvh->pv_gen;
4952 md_gen = m->md.pv_gen;
4956 if (pvh_gen != pvh->pv_gen ||
4957 md_gen != m->md.pv_gen) {
4963 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4964 oldpte = pmap_load(pte);
4966 if ((oldpte & ATTR_SW_DBM) != 0) {
4967 if (!atomic_fcmpset_long(pte, &oldpte,
4968 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
4970 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
4971 ATTR_S1_AP(ATTR_S1_AP_RW))
4973 pmap_invalidate_page(pmap, pv->pv_va);
4978 vm_page_aflag_clear(m, PGA_WRITEABLE);
4982 * pmap_ts_referenced:
4984 * Return a count of reference bits for a page, clearing those bits.
4985 * It is not necessary for every reference bit to be cleared, but it
4986 * is necessary that 0 only be returned when there are truly no
4987 * reference bits set.
4989 * As an optimization, update the page's dirty field if a modified bit is
4990 * found while counting reference bits. This opportunistic update can be
4991 * performed at low cost and can eliminate the need for some future calls
4992 * to pmap_is_modified(). However, since this function stops after
4993 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4994 * dirty pages. Those dirty pages will only be detected by a future call
4995 * to pmap_is_modified().
4998 pmap_ts_referenced(vm_page_t m)
5000 struct md_page *pvh;
5003 struct rwlock *lock;
5004 pd_entry_t *pde, tpde;
5005 pt_entry_t *pte, tpte;
5008 int cleared, lvl, md_gen, not_cleared, pvh_gen;
5009 struct spglist free;
5011 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5012 ("pmap_ts_referenced: page %p is not managed", m));
5015 pa = VM_PAGE_TO_PHYS(m);
5016 lock = PHYS_TO_PV_LIST_LOCK(pa);
5017 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
5021 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5022 goto small_mappings;
5028 if (!PMAP_TRYLOCK(pmap)) {
5029 pvh_gen = pvh->pv_gen;
5033 if (pvh_gen != pvh->pv_gen) {
5039 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5040 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
5042 ("pmap_ts_referenced: invalid pde level %d", lvl));
5043 tpde = pmap_load(pde);
5044 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
5045 ("pmap_ts_referenced: found an invalid l1 table"));
5046 pte = pmap_l1_to_l2(pde, pv->pv_va);
5047 tpte = pmap_load(pte);
5048 if (pmap_pte_dirty(pmap, tpte)) {
5050 * Although "tpte" is mapping a 2MB page, because
5051 * this function is called at a 4KB page granularity,
5052 * we only update the 4KB page under test.
5057 if ((tpte & ATTR_AF) != 0) {
5059 * Since this reference bit is shared by 512 4KB pages,
5060 * it should not be cleared every time it is tested.
5061 * Apply a simple "hash" function on the physical page
5062 * number, the virtual superpage number, and the pmap
5063 * address to select one 4KB page out of the 512 on
5064 * which testing the reference bit will result in
5065 * clearing that reference bit. This function is
5066 * designed to avoid the selection of the same 4KB page
5067 * for every 2MB page mapping.
5069 * On demotion, a mapping that hasn't been referenced
5070 * is simply destroyed. To avoid the possibility of a
5071 * subsequent page fault on a demoted wired mapping,
5072 * always leave its reference bit set. Moreover,
5073 * since the superpage is wired, the current state of
5074 * its reference bit won't affect page replacement.
5076 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
5077 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
5078 (tpte & ATTR_SW_WIRED) == 0) {
5079 pmap_clear_bits(pte, ATTR_AF);
5080 pmap_invalidate_page(pmap, pv->pv_va);
5086 /* Rotate the PV list if it has more than one entry. */
5087 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5088 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5089 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5092 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5094 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5096 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5103 if (!PMAP_TRYLOCK(pmap)) {
5104 pvh_gen = pvh->pv_gen;
5105 md_gen = m->md.pv_gen;
5109 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5114 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5115 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
5117 ("pmap_ts_referenced: invalid pde level %d", lvl));
5118 tpde = pmap_load(pde);
5119 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
5120 ("pmap_ts_referenced: found an invalid l2 table"));
5121 pte = pmap_l2_to_l3(pde, pv->pv_va);
5122 tpte = pmap_load(pte);
5123 if (pmap_pte_dirty(pmap, tpte))
5125 if ((tpte & ATTR_AF) != 0) {
5126 if ((tpte & ATTR_SW_WIRED) == 0) {
5127 pmap_clear_bits(pte, ATTR_AF);
5128 pmap_invalidate_page(pmap, pv->pv_va);
5134 /* Rotate the PV list if it has more than one entry. */
5135 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5136 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5137 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5140 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5141 not_cleared < PMAP_TS_REFERENCED_MAX);
5144 vm_page_free_pages_toq(&free, true);
5145 return (cleared + not_cleared);
5149 * Apply the given advice to the specified range of addresses within the
5150 * given pmap. Depending on the advice, clear the referenced and/or
5151 * modified flags in each mapping and set the mapped page's dirty field.
5154 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5156 struct rwlock *lock;
5157 vm_offset_t va, va_next;
5159 pd_entry_t *l0, *l1, *l2, oldl2;
5160 pt_entry_t *l3, oldl3;
5162 PMAP_ASSERT_STAGE1(pmap);
5164 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5168 for (; sva < eva; sva = va_next) {
5169 l0 = pmap_l0(pmap, sva);
5170 if (pmap_load(l0) == 0) {
5171 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5176 l1 = pmap_l0_to_l1(l0, sva);
5177 if (pmap_load(l1) == 0) {
5178 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5183 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5186 l2 = pmap_l1_to_l2(l1, sva);
5187 oldl2 = pmap_load(l2);
5190 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5191 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5194 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5199 * The 2MB page mapping was destroyed.
5205 * Unless the page mappings are wired, remove the
5206 * mapping to a single page so that a subsequent
5207 * access may repromote. Choosing the last page
5208 * within the address range [sva, min(va_next, eva))
5209 * generally results in more repromotions. Since the
5210 * underlying page table page is fully populated, this
5211 * removal never frees a page table page.
5213 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5219 ("pmap_advise: no address gap"));
5220 l3 = pmap_l2_to_l3(l2, va);
5221 KASSERT(pmap_load(l3) != 0,
5222 ("pmap_advise: invalid PTE"));
5223 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5229 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5230 ("pmap_advise: invalid L2 entry after demotion"));
5234 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5236 oldl3 = pmap_load(l3);
5237 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5238 (ATTR_SW_MANAGED | L3_PAGE))
5240 else if (pmap_pte_dirty(pmap, oldl3)) {
5241 if (advice == MADV_DONTNEED) {
5243 * Future calls to pmap_is_modified()
5244 * can be avoided by making the page
5247 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5250 while (!atomic_fcmpset_long(l3, &oldl3,
5251 (oldl3 & ~ATTR_AF) |
5252 ATTR_S1_AP(ATTR_S1_AP_RO)))
5254 } else if ((oldl3 & ATTR_AF) != 0)
5255 pmap_clear_bits(l3, ATTR_AF);
5262 if (va != va_next) {
5263 pmap_invalidate_range(pmap, va, sva);
5268 pmap_invalidate_range(pmap, va, sva);
5274 * Clear the modify bits on the specified physical page.
5277 pmap_clear_modify(vm_page_t m)
5279 struct md_page *pvh;
5280 struct rwlock *lock;
5282 pv_entry_t next_pv, pv;
5283 pd_entry_t *l2, oldl2;
5284 pt_entry_t *l3, oldl3;
5286 int md_gen, pvh_gen;
5288 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5289 ("pmap_clear_modify: page %p is not managed", m));
5290 vm_page_assert_busied(m);
5292 if (!pmap_page_is_write_mapped(m))
5294 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5295 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5296 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5299 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5301 PMAP_ASSERT_STAGE1(pmap);
5302 if (!PMAP_TRYLOCK(pmap)) {
5303 pvh_gen = pvh->pv_gen;
5307 if (pvh_gen != pvh->pv_gen) {
5313 l2 = pmap_l2(pmap, va);
5314 oldl2 = pmap_load(l2);
5315 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5316 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5317 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5318 (oldl2 & ATTR_SW_WIRED) == 0) {
5320 * Write protect the mapping to a single page so that
5321 * a subsequent write access may repromote.
5323 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5324 l3 = pmap_l2_to_l3(l2, va);
5325 oldl3 = pmap_load(l3);
5326 while (!atomic_fcmpset_long(l3, &oldl3,
5327 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
5330 pmap_invalidate_page(pmap, va);
5334 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5336 PMAP_ASSERT_STAGE1(pmap);
5337 if (!PMAP_TRYLOCK(pmap)) {
5338 md_gen = m->md.pv_gen;
5339 pvh_gen = pvh->pv_gen;
5343 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5348 l2 = pmap_l2(pmap, pv->pv_va);
5349 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5350 oldl3 = pmap_load(l3);
5351 if (pmap_l3_valid(oldl3) &&
5352 (oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
5353 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
5354 pmap_invalidate_page(pmap, pv->pv_va);
5362 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5364 struct pmap_preinit_mapping *ppim;
5365 vm_offset_t va, offset;
5368 int i, lvl, l2_blocks, free_l2_count, start_idx;
5370 if (!vm_initialized) {
5372 * No L3 ptables so map entire L2 blocks where start VA is:
5373 * preinit_map_va + start_idx * L2_SIZE
5374 * There may be duplicate mappings (multiple VA -> same PA) but
5375 * ARM64 dcache is always PIPT so that's acceptable.
5380 /* Calculate how many L2 blocks are needed for the mapping */
5381 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5382 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5384 offset = pa & L2_OFFSET;
5386 if (preinit_map_va == 0)
5389 /* Map 2MiB L2 blocks from reserved VA space */
5393 /* Find enough free contiguous VA space */
5394 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5395 ppim = pmap_preinit_mapping + i;
5396 if (free_l2_count > 0 && ppim->pa != 0) {
5397 /* Not enough space here */
5403 if (ppim->pa == 0) {
5405 if (start_idx == -1)
5408 if (free_l2_count == l2_blocks)
5412 if (free_l2_count != l2_blocks)
5413 panic("%s: too many preinit mappings", __func__);
5415 va = preinit_map_va + (start_idx * L2_SIZE);
5416 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5417 /* Mark entries as allocated */
5418 ppim = pmap_preinit_mapping + i;
5420 ppim->va = va + offset;
5425 pa = rounddown2(pa, L2_SIZE);
5426 for (i = 0; i < l2_blocks; i++) {
5427 pde = pmap_pde(kernel_pmap, va, &lvl);
5428 KASSERT(pde != NULL,
5429 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5432 ("pmap_mapbios: Invalid level %d", lvl));
5434 /* Insert L2_BLOCK */
5435 l2 = pmap_l1_to_l2(pde, va);
5437 pa | ATTR_DEFAULT | ATTR_S1_XN |
5438 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5443 pmap_invalidate_all(kernel_pmap);
5445 va = preinit_map_va + (start_idx * L2_SIZE);
5448 /* kva_alloc may be used to map the pages */
5449 offset = pa & PAGE_MASK;
5450 size = round_page(offset + size);
5452 va = kva_alloc(size);
5454 panic("%s: Couldn't allocate KVA", __func__);
5456 pde = pmap_pde(kernel_pmap, va, &lvl);
5457 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5459 /* L3 table is linked */
5460 va = trunc_page(va);
5461 pa = trunc_page(pa);
5462 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
5465 return ((void *)(va + offset));
5469 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5471 struct pmap_preinit_mapping *ppim;
5472 vm_offset_t offset, tmpsize, va_trunc;
5475 int i, lvl, l2_blocks, block;
5479 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5480 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5482 /* Remove preinit mapping */
5483 preinit_map = false;
5485 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5486 ppim = pmap_preinit_mapping + i;
5487 if (ppim->va == va) {
5488 KASSERT(ppim->size == size,
5489 ("pmap_unmapbios: size mismatch"));
5494 offset = block * L2_SIZE;
5495 va_trunc = rounddown2(va, L2_SIZE) + offset;
5497 /* Remove L2_BLOCK */
5498 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5499 KASSERT(pde != NULL,
5500 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5502 l2 = pmap_l1_to_l2(pde, va_trunc);
5505 if (block == (l2_blocks - 1))
5511 pmap_invalidate_all(kernel_pmap);
5515 /* Unmap the pages reserved with kva_alloc. */
5516 if (vm_initialized) {
5517 offset = va & PAGE_MASK;
5518 size = round_page(offset + size);
5519 va = trunc_page(va);
5521 pde = pmap_pde(kernel_pmap, va, &lvl);
5522 KASSERT(pde != NULL,
5523 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5524 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5526 /* Unmap and invalidate the pages */
5527 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5528 pmap_kremove(va + tmpsize);
5535 * Sets the memory attribute for the specified page.
5538 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5541 m->md.pv_memattr = ma;
5544 * If "m" is a normal page, update its direct mapping. This update
5545 * can be relied upon to perform any cache operations that are
5546 * required for data coherence.
5548 if ((m->flags & PG_FICTITIOUS) == 0 &&
5549 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5550 m->md.pv_memattr) != 0)
5551 panic("memory attribute change on the direct map failed");
5555 * Changes the specified virtual address range's memory type to that given by
5556 * the parameter "mode". The specified virtual address range must be
5557 * completely contained within either the direct map or the kernel map. If
5558 * the virtual address range is contained within the kernel map, then the
5559 * memory type for each of the corresponding ranges of the direct map is also
5560 * changed. (The corresponding ranges of the direct map are those ranges that
5561 * map the same physical pages as the specified virtual address range.) These
5562 * changes to the direct map are necessary because Intel describes the
5563 * behavior of their processors as "undefined" if two or more mappings to the
5564 * same physical page have different memory types.
5566 * Returns zero if the change completed successfully, and either EINVAL or
5567 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5568 * of the virtual address range was not mapped, and ENOMEM is returned if
5569 * there was insufficient memory available to complete the change. In the
5570 * latter case, the memory type may have been changed on some part of the
5571 * virtual address range or the direct map.
5574 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5578 PMAP_LOCK(kernel_pmap);
5579 error = pmap_change_attr_locked(va, size, mode);
5580 PMAP_UNLOCK(kernel_pmap);
5585 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5587 vm_offset_t base, offset, tmpva;
5588 pt_entry_t l3, *pte, *newpte;
5591 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5592 base = trunc_page(va);
5593 offset = va & PAGE_MASK;
5594 size = round_page(offset + size);
5596 if (!VIRT_IN_DMAP(base) &&
5597 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
5600 for (tmpva = base; tmpva < base + size; ) {
5601 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5605 if ((pmap_load(pte) & ATTR_S1_IDX_MASK) == ATTR_S1_IDX(mode)) {
5607 * We already have the correct attribute,
5608 * ignore this entry.
5612 panic("Invalid DMAP table level: %d\n", lvl);
5614 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5617 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5625 * Split the entry to an level 3 table, then
5626 * set the new attribute.
5630 panic("Invalid DMAP table level: %d\n", lvl);
5632 newpte = pmap_demote_l1(kernel_pmap, pte,
5633 tmpva & ~L1_OFFSET);
5636 pte = pmap_l1_to_l2(pte, tmpva);
5638 newpte = pmap_demote_l2(kernel_pmap, pte,
5642 pte = pmap_l2_to_l3(pte, tmpva);
5644 /* Update the entry */
5645 l3 = pmap_load(pte);
5646 l3 &= ~ATTR_S1_IDX_MASK;
5647 l3 |= ATTR_S1_IDX(mode);
5648 if (mode == VM_MEMATTR_DEVICE)
5651 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5655 * If moving to a non-cacheable entry flush
5658 if (mode == VM_MEMATTR_UNCACHEABLE)
5659 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5671 * Create an L2 table to map all addresses within an L1 mapping.
5674 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5676 pt_entry_t *l2, newl2, oldl1;
5678 vm_paddr_t l2phys, phys;
5682 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5683 oldl1 = pmap_load(l1);
5684 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5685 ("pmap_demote_l1: Demoting a non-block entry"));
5686 KASSERT((va & L1_OFFSET) == 0,
5687 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5688 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5689 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5692 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5693 tmpl1 = kva_alloc(PAGE_SIZE);
5698 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5699 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5700 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5701 " in pmap %p", va, pmap);
5705 l2phys = VM_PAGE_TO_PHYS(ml2);
5706 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5708 /* Address the range points at */
5709 phys = oldl1 & ~ATTR_MASK;
5710 /* The attributed from the old l1 table to be copied */
5711 newl2 = oldl1 & ATTR_MASK;
5713 /* Create the new entries */
5714 for (i = 0; i < Ln_ENTRIES; i++) {
5715 l2[i] = newl2 | phys;
5718 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5719 ("Invalid l2 page (%lx != %lx)", l2[0],
5720 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5723 pmap_kenter(tmpl1, PAGE_SIZE,
5724 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
5725 VM_MEMATTR_WRITE_BACK);
5726 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5729 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5732 pmap_kremove(tmpl1);
5733 kva_free(tmpl1, PAGE_SIZE);
5740 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5744 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5751 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5752 struct rwlock **lockp)
5754 struct spglist free;
5757 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5759 vm_page_free_pages_toq(&free, true);
5763 * Create an L3 table to map all addresses within an L2 mapping.
5766 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5767 struct rwlock **lockp)
5769 pt_entry_t *l3, newl3, oldl2;
5774 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5775 PMAP_ASSERT_STAGE1(pmap);
5777 oldl2 = pmap_load(l2);
5778 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5779 ("pmap_demote_l2: Demoting a non-block entry"));
5783 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5784 tmpl2 = kva_alloc(PAGE_SIZE);
5790 * Invalidate the 2MB page mapping and return "failure" if the
5791 * mapping was never accessed.
5793 if ((oldl2 & ATTR_AF) == 0) {
5794 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5795 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5796 pmap_demote_l2_abort(pmap, va, l2, lockp);
5797 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5802 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5803 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5804 ("pmap_demote_l2: page table page for a wired mapping"
5808 * If the page table page is missing and the mapping
5809 * is for a kernel address, the mapping must belong to
5810 * the direct map. Page table pages are preallocated
5811 * for every other part of the kernel address space,
5812 * so the direct map region is the only part of the
5813 * kernel address space that must be handled here.
5815 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5816 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5819 * If the 2MB page mapping belongs to the direct map
5820 * region of the kernel's address space, then the page
5821 * allocation request specifies the highest possible
5822 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5823 * priority is normal.
5825 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5826 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5827 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5830 * If the allocation of the new page table page fails,
5831 * invalidate the 2MB page mapping and return "failure".
5834 pmap_demote_l2_abort(pmap, va, l2, lockp);
5835 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5836 " in pmap %p", va, pmap);
5840 if (va < VM_MAXUSER_ADDRESS) {
5841 ml3->ref_count = NL3PG;
5842 pmap_resident_count_inc(pmap, 1);
5845 l3phys = VM_PAGE_TO_PHYS(ml3);
5846 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5847 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5848 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
5849 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
5850 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5853 * If the page table page is not leftover from an earlier promotion,
5854 * or the mapping attributes have changed, (re)initialize the L3 table.
5856 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5857 * performs a dsb(). That dsb() ensures that the stores for filling
5858 * "l3" are visible before "l3" is added to the page table.
5860 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5861 pmap_fill_l3(l3, newl3);
5864 * Map the temporary page so we don't lose access to the l2 table.
5867 pmap_kenter(tmpl2, PAGE_SIZE,
5868 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
5869 VM_MEMATTR_WRITE_BACK);
5870 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5874 * The spare PV entries must be reserved prior to demoting the
5875 * mapping, that is, prior to changing the PDE. Otherwise, the state
5876 * of the L2 and the PV lists will be inconsistent, which can result
5877 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5878 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5879 * PV entry for the 2MB page mapping that is being demoted.
5881 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5882 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5885 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5886 * the 2MB page mapping.
5888 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5891 * Demote the PV entry.
5893 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5894 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5896 atomic_add_long(&pmap_l2_demotions, 1);
5897 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5898 " in pmap %p %lx", va, pmap, l3[0]);
5902 pmap_kremove(tmpl2);
5903 kva_free(tmpl2, PAGE_SIZE);
5911 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5913 struct rwlock *lock;
5917 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5924 * Perform the pmap work for mincore(2). If the page is not both referenced and
5925 * modified by this pmap, returns its physical address so that the caller can
5926 * find other mappings.
5929 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
5931 pt_entry_t *pte, tpte;
5932 vm_paddr_t mask, pa;
5936 PMAP_ASSERT_STAGE1(pmap);
5938 pte = pmap_pte(pmap, addr, &lvl);
5940 tpte = pmap_load(pte);
5953 panic("pmap_mincore: invalid level %d", lvl);
5956 managed = (tpte & ATTR_SW_MANAGED) != 0;
5957 val = MINCORE_INCORE;
5959 val |= MINCORE_PSIND(3 - lvl);
5960 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
5961 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
5962 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5963 if ((tpte & ATTR_AF) == ATTR_AF)
5964 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5966 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5972 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5973 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5981 * Garbage collect every ASID that is neither active on a processor nor
5985 pmap_reset_asid_set(pmap_t pmap)
5988 int asid, cpuid, epoch;
5989 struct asid_set *set;
5990 enum pmap_stage stage;
5992 set = pmap->pm_asid_set;
5993 stage = pmap->pm_stage;
5995 set = pmap->pm_asid_set;
5996 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
5997 mtx_assert(&set->asid_set_mutex, MA_OWNED);
6000 * Ensure that the store to asid_epoch is globally visible before the
6001 * loads from pc_curpmap are performed.
6003 epoch = set->asid_epoch + 1;
6004 if (epoch == INT_MAX)
6006 set->asid_epoch = epoch;
6008 if (stage == PM_STAGE1) {
6009 __asm __volatile("tlbi vmalle1is");
6011 KASSERT(pmap_clean_stage2_tlbi != NULL,
6012 ("%s: Unset stage 2 tlb invalidation callback\n",
6014 pmap_clean_stage2_tlbi();
6017 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
6018 set->asid_set_size - 1);
6019 CPU_FOREACH(cpuid) {
6020 if (cpuid == curcpu)
6022 if (stage == PM_STAGE1) {
6023 curpmap = pcpu_find(cpuid)->pc_curpmap;
6024 PMAP_ASSERT_STAGE1(pmap);
6026 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
6027 if (curpmap == NULL)
6029 PMAP_ASSERT_STAGE2(pmap);
6031 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
6032 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
6035 bit_set(set->asid_set, asid);
6036 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
6041 * Allocate a new ASID for the specified pmap.
6044 pmap_alloc_asid(pmap_t pmap)
6046 struct asid_set *set;
6049 set = pmap->pm_asid_set;
6050 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6052 mtx_lock_spin(&set->asid_set_mutex);
6055 * While this processor was waiting to acquire the asid set mutex,
6056 * pmap_reset_asid_set() running on another processor might have
6057 * updated this pmap's cookie to the current epoch. In which case, we
6058 * don't need to allocate a new ASID.
6060 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
6063 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
6065 if (new_asid == -1) {
6066 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6067 set->asid_next, &new_asid);
6068 if (new_asid == -1) {
6069 pmap_reset_asid_set(pmap);
6070 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6071 set->asid_set_size, &new_asid);
6072 KASSERT(new_asid != -1, ("ASID allocation failure"));
6075 bit_set(set->asid_set, new_asid);
6076 set->asid_next = new_asid + 1;
6077 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
6079 mtx_unlock_spin(&set->asid_set_mutex);
6083 * Compute the value that should be stored in ttbr0 to activate the specified
6084 * pmap. This value may change from time to time.
6087 pmap_to_ttbr0(pmap_t pmap)
6090 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
6095 pmap_activate_int(pmap_t pmap)
6097 struct asid_set *set;
6100 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
6101 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
6103 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
6104 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
6106 * Handle the possibility that the old thread was preempted
6107 * after an "ic" or "tlbi" instruction but before it performed
6108 * a "dsb" instruction. If the old thread migrates to a new
6109 * processor, its completion of a "dsb" instruction on that
6110 * new processor does not guarantee that the "ic" or "tlbi"
6111 * instructions performed on the old processor have completed.
6117 set = pmap->pm_asid_set;
6118 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6121 * Ensure that the store to curpmap is globally visible before the
6122 * load from asid_epoch is performed.
6124 if (pmap->pm_stage == PM_STAGE1)
6125 PCPU_SET(curpmap, pmap);
6127 PCPU_SET(curvmpmap, pmap);
6129 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
6130 if (epoch >= 0 && epoch != set->asid_epoch)
6131 pmap_alloc_asid(pmap);
6133 if (pmap->pm_stage == PM_STAGE1) {
6134 set_ttbr0(pmap_to_ttbr0(pmap));
6135 if (PCPU_GET(bcast_tlbi_workaround) != 0)
6136 invalidate_local_icache();
6142 pmap_activate_vm(pmap_t pmap)
6145 PMAP_ASSERT_STAGE2(pmap);
6147 (void)pmap_activate_int(pmap);
6151 pmap_activate(struct thread *td)
6155 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6156 PMAP_ASSERT_STAGE1(pmap);
6158 (void)pmap_activate_int(pmap);
6163 * To eliminate the unused parameter "old", we would have to add an instruction
6167 pmap_switch(struct thread *old __unused, struct thread *new)
6169 pcpu_bp_harden bp_harden;
6172 /* Store the new curthread */
6173 PCPU_SET(curthread, new);
6175 /* And the new pcb */
6177 PCPU_SET(curpcb, pcb);
6180 * TODO: We may need to flush the cache here if switching
6181 * to a user process.
6184 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
6186 * Stop userspace from training the branch predictor against
6187 * other processes. This will call into a CPU specific
6188 * function that clears the branch predictor state.
6190 bp_harden = PCPU_GET(bp_harden);
6191 if (bp_harden != NULL)
6199 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
6202 PMAP_ASSERT_STAGE1(pmap);
6203 if (va >= VM_MIN_KERNEL_ADDRESS) {
6204 cpu_icache_sync_range(va, sz);
6209 /* Find the length of data in this page to flush */
6210 offset = va & PAGE_MASK;
6211 len = imin(PAGE_SIZE - offset, sz);
6214 /* Extract the physical address & find it in the DMAP */
6215 pa = pmap_extract(pmap, va);
6217 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
6219 /* Move to the next page */
6222 /* Set the length for the next iteration */
6223 len = imin(PAGE_SIZE, sz);
6229 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6232 pt_entry_t *ptep, pte;
6235 PMAP_ASSERT_STAGE2(pmap);
6238 /* Data and insn aborts use same encoding for FSC field. */
6239 dfsc = esr & ISS_DATA_DFSC_MASK;
6241 case ISS_DATA_DFSC_TF_L0:
6242 case ISS_DATA_DFSC_TF_L1:
6243 case ISS_DATA_DFSC_TF_L2:
6244 case ISS_DATA_DFSC_TF_L3:
6246 pdep = pmap_pde(pmap, far, &lvl);
6247 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
6254 ptep = pmap_l0_to_l1(pdep, far);
6257 ptep = pmap_l1_to_l2(pdep, far);
6260 ptep = pmap_l2_to_l3(pdep, far);
6263 panic("%s: Invalid pde level %d", __func__,lvl);
6267 case ISS_DATA_DFSC_AFF_L1:
6268 case ISS_DATA_DFSC_AFF_L2:
6269 case ISS_DATA_DFSC_AFF_L3:
6271 ptep = pmap_pte(pmap, far, &lvl);
6273 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
6275 pmap_invalidate_vpipt_icache();
6278 * If accessing an executable page invalidate
6279 * the I-cache so it will be valid when we
6280 * continue execution in the guest. The D-cache
6281 * is assumed to already be clean to the Point
6284 if ((pte & ATTR_S2_XN_MASK) !=
6285 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
6286 invalidate_icache();
6289 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
6300 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6302 pt_entry_t pte, *ptep;
6309 ec = ESR_ELx_EXCEPTION(esr);
6311 case EXCP_INSN_ABORT_L:
6312 case EXCP_INSN_ABORT:
6313 case EXCP_DATA_ABORT_L:
6314 case EXCP_DATA_ABORT:
6320 if (pmap->pm_stage == PM_STAGE2)
6321 return (pmap_stage2_fault(pmap, esr, far));
6323 /* Data and insn aborts use same encoding for FSC field. */
6324 switch (esr & ISS_DATA_DFSC_MASK) {
6325 case ISS_DATA_DFSC_AFF_L1:
6326 case ISS_DATA_DFSC_AFF_L2:
6327 case ISS_DATA_DFSC_AFF_L3:
6329 ptep = pmap_pte(pmap, far, &lvl);
6331 pmap_set_bits(ptep, ATTR_AF);
6334 * XXXMJ as an optimization we could mark the entry
6335 * dirty if this is a write fault.
6340 case ISS_DATA_DFSC_PF_L1:
6341 case ISS_DATA_DFSC_PF_L2:
6342 case ISS_DATA_DFSC_PF_L3:
6343 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6344 (esr & ISS_DATA_WnR) == 0)
6347 ptep = pmap_pte(pmap, far, &lvl);
6349 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6350 if ((pte & ATTR_S1_AP_RW_BIT) ==
6351 ATTR_S1_AP(ATTR_S1_AP_RO)) {
6352 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
6353 pmap_invalidate_page(pmap, far);
6359 case ISS_DATA_DFSC_TF_L0:
6360 case ISS_DATA_DFSC_TF_L1:
6361 case ISS_DATA_DFSC_TF_L2:
6362 case ISS_DATA_DFSC_TF_L3:
6364 * Retry the translation. A break-before-make sequence can
6365 * produce a transient fault.
6367 if (pmap == kernel_pmap) {
6369 * The translation fault may have occurred within a
6370 * critical section. Therefore, we must check the
6371 * address without acquiring the kernel pmap's lock.
6373 if (pmap_kextract(far) != 0)
6377 /* Ask the MMU to check the address. */
6378 intr = intr_disable();
6379 par = arm64_address_translate_s1e0r(far);
6384 * If the translation was successful, then we can
6385 * return success to the trap handler.
6387 if (PAR_SUCCESS(par))
6397 * Increase the starting virtual address of the given mapping if a
6398 * different alignment might result in more superpage mappings.
6401 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6402 vm_offset_t *addr, vm_size_t size)
6404 vm_offset_t superpage_offset;
6408 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6409 offset += ptoa(object->pg_color);
6410 superpage_offset = offset & L2_OFFSET;
6411 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6412 (*addr & L2_OFFSET) == superpage_offset)
6414 if ((*addr & L2_OFFSET) < superpage_offset)
6415 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6417 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6421 * Get the kernel virtual address of a set of physical pages. If there are
6422 * physical addresses not covered by the DMAP perform a transient mapping
6423 * that will be removed when calling pmap_unmap_io_transient.
6425 * \param page The pages the caller wishes to obtain the virtual
6426 * address on the kernel memory map.
6427 * \param vaddr On return contains the kernel virtual memory address
6428 * of the pages passed in the page parameter.
6429 * \param count Number of pages passed in.
6430 * \param can_fault TRUE if the thread using the mapped pages can take
6431 * page faults, FALSE otherwise.
6433 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6434 * finished or FALSE otherwise.
6438 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6439 boolean_t can_fault)
6442 boolean_t needs_mapping;
6446 * Allocate any KVA space that we need, this is done in a separate
6447 * loop to prevent calling vmem_alloc while pinned.
6449 needs_mapping = FALSE;
6450 for (i = 0; i < count; i++) {
6451 paddr = VM_PAGE_TO_PHYS(page[i]);
6452 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6453 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6454 M_BESTFIT | M_WAITOK, &vaddr[i]);
6455 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6456 needs_mapping = TRUE;
6458 vaddr[i] = PHYS_TO_DMAP(paddr);
6462 /* Exit early if everything is covered by the DMAP */
6468 for (i = 0; i < count; i++) {
6469 paddr = VM_PAGE_TO_PHYS(page[i]);
6470 if (!PHYS_IN_DMAP(paddr)) {
6472 "pmap_map_io_transient: TODO: Map out of DMAP data");
6476 return (needs_mapping);
6480 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6481 boolean_t can_fault)
6488 for (i = 0; i < count; i++) {
6489 paddr = VM_PAGE_TO_PHYS(page[i]);
6490 if (!PHYS_IN_DMAP(paddr)) {
6491 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
6497 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
6500 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
6504 * Track a range of the kernel's virtual address space that is contiguous
6505 * in various mapping attributes.
6507 struct pmap_kernel_map_range {
6517 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6523 if (eva <= range->sva)
6526 index = range->attrs & ATTR_S1_IDX_MASK;
6528 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
6531 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
6534 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
6537 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
6542 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
6543 __func__, index, range->sva, eva);
6548 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
6550 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
6551 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
6552 (range->attrs & ATTR_S1_AP_USER) != 0 ? 'u' : 's',
6553 mode, range->l1blocks, range->l2blocks, range->l3contig,
6556 /* Reset to sentinel value. */
6557 range->sva = 0xfffffffffffffffful;
6561 * Determine whether the attributes specified by a page table entry match those
6562 * being tracked by the current range.
6565 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6568 return (range->attrs == attrs);
6572 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6576 memset(range, 0, sizeof(*range));
6578 range->attrs = attrs;
6582 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6583 * those of the current run, dump the address range and its attributes, and
6587 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6588 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
6593 attrs = l0e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6594 attrs |= l1e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6595 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
6596 attrs |= l1e & ATTR_S1_IDX_MASK;
6597 attrs |= l2e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6598 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
6599 attrs |= l2e & ATTR_S1_IDX_MASK;
6600 attrs |= l3e & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK);
6602 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6603 sysctl_kmaps_dump(sb, range, va);
6604 sysctl_kmaps_reinit(range, va, attrs);
6609 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
6611 struct pmap_kernel_map_range range;
6612 struct sbuf sbuf, *sb;
6613 pd_entry_t l0e, *l1, l1e, *l2, l2e;
6614 pt_entry_t *l3, l3e;
6617 int error, i, j, k, l;
6619 error = sysctl_wire_old_buffer(req, 0);
6623 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6625 /* Sentinel value. */
6626 range.sva = 0xfffffffffffffffful;
6629 * Iterate over the kernel page tables without holding the kernel pmap
6630 * lock. Kernel page table pages are never freed, so at worst we will
6631 * observe inconsistencies in the output.
6633 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
6635 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
6636 sbuf_printf(sb, "\nDirect map:\n");
6637 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
6638 sbuf_printf(sb, "\nKernel map:\n");
6640 l0e = kernel_pmap->pm_l0[i];
6641 if ((l0e & ATTR_DESCR_VALID) == 0) {
6642 sysctl_kmaps_dump(sb, &range, sva);
6646 pa = l0e & ~ATTR_MASK;
6647 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6649 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
6651 if ((l1e & ATTR_DESCR_VALID) == 0) {
6652 sysctl_kmaps_dump(sb, &range, sva);
6656 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
6657 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
6663 pa = l1e & ~ATTR_MASK;
6664 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6666 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
6668 if ((l2e & ATTR_DESCR_VALID) == 0) {
6669 sysctl_kmaps_dump(sb, &range, sva);
6673 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
6674 sysctl_kmaps_check(sb, &range, sva,
6680 pa = l2e & ~ATTR_MASK;
6681 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
6683 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
6684 l++, sva += L3_SIZE) {
6686 if ((l3e & ATTR_DESCR_VALID) == 0) {
6687 sysctl_kmaps_dump(sb, &range,
6691 sysctl_kmaps_check(sb, &range, sva,
6692 l0e, l1e, l2e, l3e);
6693 if ((l3e & ATTR_CONTIGUOUS) != 0)
6694 range.l3contig += l % 16 == 0 ?
6703 error = sbuf_finish(sb);
6707 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
6708 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
6709 NULL, 0, sysctl_kmaps, "A",
6710 "Dump kernel address layout");