2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/physmem.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
125 #include <sys/sbuf.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
131 #include <sys/_unrhdr.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
146 #include <vm/vm_dumpset.h>
149 #include <machine/machdep.h>
150 #include <machine/md_var.h>
151 #include <machine/pcb.h>
153 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
154 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
156 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
158 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
159 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
161 #define NUL0E L0_ENTRIES
162 #define NUL1E (NUL0E * NL1PG)
163 #define NUL2E (NUL1E * NL2PG)
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pmap_l0_pindex(v) (NUL2E + NUL1E + ((v) >> L0_SHIFT))
182 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT))
183 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 static struct md_page *
186 pa_to_pvh(vm_paddr_t pa)
188 struct vm_phys_seg *seg;
191 for (segind = 0; segind < vm_phys_nsegs; segind++) {
192 seg = &vm_phys_segs[segind];
193 if (pa >= seg->start && pa < seg->end)
194 return ((struct md_page *)seg->md_first +
195 pmap_l2_pindex(pa) - pmap_l2_pindex(seg->start));
197 panic("pa 0x%jx not within vm_phys_segs", (uintmax_t)pa);
200 static struct md_page *
201 page_to_pvh(vm_page_t m)
203 struct vm_phys_seg *seg;
205 seg = &vm_phys_segs[m->segind];
206 return ((struct md_page *)seg->md_first +
207 pmap_l2_pindex(VM_PAGE_TO_PHYS(m)) - pmap_l2_pindex(seg->start));
210 #define NPV_LIST_LOCKS MAXCPU
212 #define PHYS_TO_PV_LIST_LOCK(pa) \
213 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
215 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
216 struct rwlock **_lockp = (lockp); \
217 struct rwlock *_new_lock; \
219 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
220 if (_new_lock != *_lockp) { \
221 if (*_lockp != NULL) \
222 rw_wunlock(*_lockp); \
223 *_lockp = _new_lock; \
228 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
229 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
231 #define RELEASE_PV_LIST_LOCK(lockp) do { \
232 struct rwlock **_lockp = (lockp); \
234 if (*_lockp != NULL) { \
235 rw_wunlock(*_lockp); \
240 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
241 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
244 * The presence of this flag indicates that the mapping is writeable.
245 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
246 * it is dirty. This flag may only be set on managed mappings.
248 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
249 * as a software managed bit.
251 #define ATTR_SW_DBM ATTR_DBM
253 struct pmap kernel_pmap_store;
255 /* Used for mapping ACPI memory before VM is initialized */
256 #define PMAP_PREINIT_MAPPING_COUNT 32
257 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
258 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
259 static int vm_initialized = 0; /* No need to use pre-init maps when set */
262 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
263 * Always map entire L2 block for simplicity.
264 * VA of L2 block = preinit_map_va + i * L2_SIZE
266 static struct pmap_preinit_mapping {
270 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
272 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
273 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
274 vm_offset_t kernel_vm_end = 0;
277 * Data for the pv entry allocation mechanism.
279 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
280 static struct mtx pv_chunks_mutex;
281 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
282 static struct md_page *pv_table;
283 static struct md_page pv_dummy;
285 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
286 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
287 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
289 /* This code assumes all L1 DMAP entries will be used */
290 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
291 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
293 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
294 extern pt_entry_t pagetable_dmap[];
296 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
297 static vm_paddr_t physmap[PHYSMAP_SIZE];
298 static u_int physmap_idx;
300 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
301 "VM/pmap parameters");
304 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
305 * that it has currently allocated to a pmap, a cursor ("asid_next") to
306 * optimize its search for a free ASID in the bit vector, and an epoch number
307 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
308 * ASIDs that are not currently active on a processor.
310 * The current epoch number is always in the range [0, INT_MAX). Negative
311 * numbers and INT_MAX are reserved for special cases that are described
320 struct mtx asid_set_mutex;
323 static struct asid_set asids;
324 static struct asid_set vmids;
326 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
328 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
329 "The number of bits in an ASID");
330 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
331 "The last allocated ASID plus one");
332 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
333 "The current epoch number");
335 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
336 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
337 "The number of bits in an VMID");
338 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
339 "The last allocated VMID plus one");
340 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
341 "The current epoch number");
343 void (*pmap_clean_stage2_tlbi)(void);
344 void (*pmap_invalidate_vpipt_icache)(void);
347 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
348 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
349 * dynamically allocated ASIDs have a non-negative epoch number.
351 * An invalid ASID is represented by -1.
353 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
354 * which indicates that an ASID should never be allocated to the pmap, and
355 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
356 * allocated when the pmap is next activated.
358 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
359 ((u_long)(epoch) << 32)))
360 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
361 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
363 static int superpages_enabled = 1;
364 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
365 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
366 "Are large page mappings enabled?");
369 * Internal flags for pmap_enter()'s helper functions.
371 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
372 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
374 static void free_pv_chunk(struct pv_chunk *pc);
375 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
376 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
377 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
378 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
379 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
382 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
383 static bool pmap_activate_int(pmap_t pmap);
384 static void pmap_alloc_asid(pmap_t pmap);
385 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
386 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
387 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
388 vm_offset_t va, struct rwlock **lockp);
389 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
390 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
391 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
392 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
393 u_int flags, vm_page_t m, struct rwlock **lockp);
394 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
395 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
396 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
397 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
398 static void pmap_reset_asid_set(pmap_t pmap);
399 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
400 vm_page_t m, struct rwlock **lockp);
402 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
403 struct rwlock **lockp);
405 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
406 struct spglist *free);
407 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
408 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
411 * These load the old table data and store the new value.
412 * They need to be atomic as the System MMU may write to the table at
413 * the same time as the CPU.
415 #define pmap_clear(table) atomic_store_64(table, 0)
416 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
417 #define pmap_load(table) (*table)
418 #define pmap_load_clear(table) atomic_swap_64(table, 0)
419 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
420 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
421 #define pmap_store(table, entry) atomic_store_64(table, entry)
423 /********************/
424 /* Inline functions */
425 /********************/
428 pagecopy(void *s, void *d)
431 memcpy(d, s, PAGE_SIZE);
434 static __inline pd_entry_t *
435 pmap_l0(pmap_t pmap, vm_offset_t va)
438 return (&pmap->pm_l0[pmap_l0_index(va)]);
441 static __inline pd_entry_t *
442 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
446 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
447 return (&l1[pmap_l1_index(va)]);
450 static __inline pd_entry_t *
451 pmap_l1(pmap_t pmap, vm_offset_t va)
455 l0 = pmap_l0(pmap, va);
456 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
459 return (pmap_l0_to_l1(l0, va));
462 static __inline pd_entry_t *
463 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va)
470 * The valid bit may be clear if pmap_update_entry() is concurrently
471 * modifying the entry, so for KVA only the entry type may be checked.
473 KASSERT(va >= VM_MAX_USER_ADDRESS || (l1 & ATTR_DESCR_VALID) != 0,
474 ("%s: L1 entry %#lx for %#lx is invalid", __func__, l1, va));
475 KASSERT((l1 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
476 ("%s: L1 entry %#lx for %#lx is a leaf", __func__, l1, va));
477 l2p = (pd_entry_t *)PHYS_TO_DMAP(l1 & ~ATTR_MASK);
478 return (&l2p[pmap_l2_index(va)]);
481 static __inline pd_entry_t *
482 pmap_l2(pmap_t pmap, vm_offset_t va)
486 l1 = pmap_l1(pmap, va);
487 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
490 return (pmap_l1_to_l2(l1, va));
493 static __inline pt_entry_t *
494 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va)
502 * The valid bit may be clear if pmap_update_entry() is concurrently
503 * modifying the entry, so for KVA only the entry type may be checked.
505 KASSERT(va >= VM_MAX_USER_ADDRESS || (l2 & ATTR_DESCR_VALID) != 0,
506 ("%s: L2 entry %#lx for %#lx is invalid", __func__, l2, va));
507 KASSERT((l2 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
508 ("%s: L2 entry %#lx for %#lx is a leaf", __func__, l2, va));
509 l3p = (pt_entry_t *)PHYS_TO_DMAP(l2 & ~ATTR_MASK);
510 return (&l3p[pmap_l3_index(va)]);
514 * Returns the lowest valid pde for a given virtual address.
515 * The next level may or may not point to a valid page or block.
517 static __inline pd_entry_t *
518 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
520 pd_entry_t *l0, *l1, *l2, desc;
522 l0 = pmap_l0(pmap, va);
523 desc = pmap_load(l0) & ATTR_DESCR_MASK;
524 if (desc != L0_TABLE) {
529 l1 = pmap_l0_to_l1(l0, va);
530 desc = pmap_load(l1) & ATTR_DESCR_MASK;
531 if (desc != L1_TABLE) {
536 l2 = pmap_l1_to_l2(l1, va);
537 desc = pmap_load(l2) & ATTR_DESCR_MASK;
538 if (desc != L2_TABLE) {
548 * Returns the lowest valid pte block or table entry for a given virtual
549 * address. If there are no valid entries return NULL and set the level to
550 * the first invalid level.
552 static __inline pt_entry_t *
553 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
555 pd_entry_t *l1, *l2, desc;
558 l1 = pmap_l1(pmap, va);
563 desc = pmap_load(l1) & ATTR_DESCR_MASK;
564 if (desc == L1_BLOCK) {
569 if (desc != L1_TABLE) {
574 l2 = pmap_l1_to_l2(l1, va);
575 desc = pmap_load(l2) & ATTR_DESCR_MASK;
576 if (desc == L2_BLOCK) {
581 if (desc != L2_TABLE) {
587 l3 = pmap_l2_to_l3(l2, va);
588 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
595 pmap_ps_enabled(pmap_t pmap __unused)
598 return (superpages_enabled != 0);
602 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
603 pd_entry_t **l2, pt_entry_t **l3)
605 pd_entry_t *l0p, *l1p, *l2p;
607 if (pmap->pm_l0 == NULL)
610 l0p = pmap_l0(pmap, va);
613 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
616 l1p = pmap_l0_to_l1(l0p, va);
619 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
625 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
628 l2p = pmap_l1_to_l2(l1p, va);
631 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
636 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
639 *l3 = pmap_l2_to_l3(l2p, va);
645 pmap_l3_valid(pt_entry_t l3)
648 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
651 CTASSERT(L1_BLOCK == L2_BLOCK);
654 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
658 if (pmap->pm_stage == PM_STAGE1) {
659 val = ATTR_S1_IDX(memattr);
660 if (memattr == VM_MEMATTR_DEVICE)
668 case VM_MEMATTR_DEVICE:
669 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
670 ATTR_S2_XN(ATTR_S2_XN_ALL));
671 case VM_MEMATTR_UNCACHEABLE:
672 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
673 case VM_MEMATTR_WRITE_BACK:
674 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
675 case VM_MEMATTR_WRITE_THROUGH:
676 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
678 panic("%s: invalid memory attribute %x", __func__, memattr);
683 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
688 if (pmap->pm_stage == PM_STAGE1) {
689 if ((prot & VM_PROT_EXECUTE) == 0)
691 if ((prot & VM_PROT_WRITE) == 0)
692 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
694 if ((prot & VM_PROT_WRITE) != 0)
695 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
696 if ((prot & VM_PROT_READ) != 0)
697 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
698 if ((prot & VM_PROT_EXECUTE) == 0)
699 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
706 * Checks if the PTE is dirty.
709 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
712 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
714 if (pmap->pm_stage == PM_STAGE1) {
715 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
716 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
718 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
719 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
722 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
723 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
727 pmap_resident_count_inc(pmap_t pmap, int count)
730 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
731 pmap->pm_stats.resident_count += count;
735 pmap_resident_count_dec(pmap_t pmap, int count)
738 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
739 KASSERT(pmap->pm_stats.resident_count >= count,
740 ("pmap %p resident count underflow %ld %d", pmap,
741 pmap->pm_stats.resident_count, count));
742 pmap->pm_stats.resident_count -= count;
746 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
752 l1 = (pd_entry_t *)l1pt;
753 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
755 /* Check locore has used a table L1 map */
756 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
757 ("Invalid bootstrap L1 table"));
758 /* Find the address of the L2 table */
759 l2 = (pt_entry_t *)init_pt_va;
760 *l2_slot = pmap_l2_index(va);
766 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
768 u_int l1_slot, l2_slot;
771 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
773 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
777 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
778 vm_offset_t freemempos)
782 vm_paddr_t l2_pa, pa;
783 u_int l1_slot, l2_slot, prev_l1_slot;
786 dmap_phys_base = min_pa & ~L1_OFFSET;
792 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
793 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
795 for (i = 0; i < (physmap_idx * 2); i += 2) {
796 pa = physmap[i] & ~L2_OFFSET;
797 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
799 /* Create L2 mappings at the start of the region */
800 if ((pa & L1_OFFSET) != 0) {
801 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
802 if (l1_slot != prev_l1_slot) {
803 prev_l1_slot = l1_slot;
804 l2 = (pt_entry_t *)freemempos;
805 l2_pa = pmap_early_vtophys(kern_l1,
807 freemempos += PAGE_SIZE;
809 pmap_store(&pagetable_dmap[l1_slot],
810 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
812 memset(l2, 0, PAGE_SIZE);
815 ("pmap_bootstrap_dmap: NULL l2 map"));
816 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
817 pa += L2_SIZE, va += L2_SIZE) {
819 * We are on a boundary, stop to
820 * create a level 1 block
822 if ((pa & L1_OFFSET) == 0)
825 l2_slot = pmap_l2_index(va);
826 KASSERT(l2_slot != 0, ("..."));
827 pmap_store(&l2[l2_slot],
828 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
830 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
833 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
837 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
838 (physmap[i + 1] - pa) >= L1_SIZE;
839 pa += L1_SIZE, va += L1_SIZE) {
840 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
841 pmap_store(&pagetable_dmap[l1_slot],
842 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_S1_XN |
843 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
846 /* Create L2 mappings at the end of the region */
847 if (pa < physmap[i + 1]) {
848 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
849 if (l1_slot != prev_l1_slot) {
850 prev_l1_slot = l1_slot;
851 l2 = (pt_entry_t *)freemempos;
852 l2_pa = pmap_early_vtophys(kern_l1,
854 freemempos += PAGE_SIZE;
856 pmap_store(&pagetable_dmap[l1_slot],
857 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
859 memset(l2, 0, PAGE_SIZE);
862 ("pmap_bootstrap_dmap: NULL l2 map"));
863 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
864 pa += L2_SIZE, va += L2_SIZE) {
865 l2_slot = pmap_l2_index(va);
866 pmap_store(&l2[l2_slot],
867 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
869 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
874 if (pa > dmap_phys_max) {
886 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
893 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
895 l1 = (pd_entry_t *)l1pt;
896 l1_slot = pmap_l1_index(va);
899 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
900 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
902 pa = pmap_early_vtophys(l1pt, l2pt);
903 pmap_store(&l1[l1_slot],
904 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
908 /* Clean the L2 page table */
909 memset((void *)l2_start, 0, l2pt - l2_start);
915 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
922 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
924 l2 = pmap_l2(kernel_pmap, va);
925 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
926 l2_slot = pmap_l2_index(va);
929 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
930 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
932 pa = pmap_early_vtophys(l1pt, l3pt);
933 pmap_store(&l2[l2_slot],
934 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
938 /* Clean the L2 page table */
939 memset((void *)l3_start, 0, l3pt - l3_start);
945 * Bootstrap the system enough to run with virtual memory.
948 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
951 vm_offset_t freemempos;
952 vm_offset_t dpcpu, msgbufpv;
953 vm_paddr_t start_pa, pa, min_pa;
957 /* Verify that the ASID is set through TTBR0. */
958 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
959 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
961 kern_delta = KERNBASE - kernstart;
963 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
964 printf("%lx\n", l1pt);
965 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
967 /* Set this early so we can use the pagetable walking functions */
968 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
969 PMAP_LOCK_INIT(kernel_pmap);
970 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
971 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
972 kernel_pmap->pm_stage = PM_STAGE1;
973 kernel_pmap->pm_asid_set = &asids;
975 /* Assume the address we were loaded to is a valid physical address */
976 min_pa = KERNBASE - kern_delta;
978 physmap_idx = physmem_avail(physmap, nitems(physmap));
982 * Find the minimum physical address. physmap is sorted,
983 * but may contain empty ranges.
985 for (i = 0; i < physmap_idx * 2; i += 2) {
986 if (physmap[i] == physmap[i + 1])
988 if (physmap[i] <= min_pa)
992 freemempos = KERNBASE + kernlen;
993 freemempos = roundup2(freemempos, PAGE_SIZE);
995 /* Create a direct map region early so we can use it for pa -> va */
996 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
998 start_pa = pa = KERNBASE - kern_delta;
1001 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
1002 * loader allocated the first and only l2 page table page used to map
1003 * the kernel, preloaded files and module metadata.
1005 freemempos = pmap_bootstrap_l2(l1pt, KERNBASE + L1_SIZE, freemempos);
1006 /* And the l3 tables for the early devmap */
1007 freemempos = pmap_bootstrap_l3(l1pt,
1008 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
1012 #define alloc_pages(var, np) \
1013 (var) = freemempos; \
1014 freemempos += (np * PAGE_SIZE); \
1015 memset((char *)(var), 0, ((np) * PAGE_SIZE));
1017 /* Allocate dynamic per-cpu area. */
1018 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
1019 dpcpu_init((void *)dpcpu, 0);
1021 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
1022 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
1023 msgbufp = (void *)msgbufpv;
1025 /* Reserve some VA space for early BIOS/ACPI mapping */
1026 preinit_map_va = roundup2(freemempos, L2_SIZE);
1028 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
1029 virtual_avail = roundup2(virtual_avail, L1_SIZE);
1030 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
1031 kernel_vm_end = virtual_avail;
1033 pa = pmap_early_vtophys(l1pt, freemempos);
1035 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
1041 * Initialize a vm_page's machine-dependent fields.
1044 pmap_page_init(vm_page_t m)
1047 TAILQ_INIT(&m->md.pv_list);
1048 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1052 pmap_init_asids(struct asid_set *set, int bits)
1056 set->asid_bits = bits;
1059 * We may be too early in the overall initialization process to use
1062 set->asid_set_size = 1 << set->asid_bits;
1063 set->asid_set = (bitstr_t *)kmem_malloc(bitstr_size(set->asid_set_size),
1065 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1066 bit_set(set->asid_set, i);
1067 set->asid_next = ASID_FIRST_AVAILABLE;
1068 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1072 * Initialize the pmap module.
1073 * Called by vm_init, to initialize any structures that the pmap
1074 * system needs to map virtual memory.
1079 struct vm_phys_seg *seg, *next_seg;
1080 struct md_page *pvh;
1083 int i, pv_npg, vmid_bits;
1086 * Are large page mappings enabled?
1088 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1089 if (superpages_enabled) {
1090 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1091 ("pmap_init: can't assign to pagesizes[1]"));
1092 pagesizes[1] = L2_SIZE;
1093 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
1094 ("pmap_init: can't assign to pagesizes[2]"));
1095 pagesizes[2] = L1_SIZE;
1099 * Initialize the ASID allocator.
1101 pmap_init_asids(&asids,
1102 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1105 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1108 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1109 ID_AA64MMFR1_VMIDBits_16)
1111 pmap_init_asids(&vmids, vmid_bits);
1115 * Initialize the pv chunk list mutex.
1117 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1120 * Initialize the pool of pv list locks.
1122 for (i = 0; i < NPV_LIST_LOCKS; i++)
1123 rw_init(&pv_list_locks[i], "pmap pv list");
1126 * Calculate the size of the pv head table for superpages.
1129 for (i = 0; i < vm_phys_nsegs; i++) {
1130 seg = &vm_phys_segs[i];
1131 pv_npg += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1132 pmap_l2_pindex(seg->start);
1136 * Allocate memory for the pv head table for superpages.
1138 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1140 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1141 for (i = 0; i < pv_npg; i++)
1142 TAILQ_INIT(&pv_table[i].pv_list);
1143 TAILQ_INIT(&pv_dummy.pv_list);
1146 * Set pointers from vm_phys_segs to pv_table.
1148 for (i = 0, pvh = pv_table; i < vm_phys_nsegs; i++) {
1149 seg = &vm_phys_segs[i];
1150 seg->md_first = pvh;
1151 pvh += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1152 pmap_l2_pindex(seg->start);
1155 * If there is a following segment, and the final
1156 * superpage of this segment and the initial superpage
1157 * of the next segment are the same then adjust the
1158 * pv_table entry for that next segment down by one so
1159 * that the pv_table entries will be shared.
1161 if (i + 1 < vm_phys_nsegs) {
1162 next_seg = &vm_phys_segs[i + 1];
1163 if (pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1 ==
1164 pmap_l2_pindex(next_seg->start)) {
1173 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1174 "2MB page mapping counters");
1176 static u_long pmap_l2_demotions;
1177 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1178 &pmap_l2_demotions, 0, "2MB page demotions");
1180 static u_long pmap_l2_mappings;
1181 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1182 &pmap_l2_mappings, 0, "2MB page mappings");
1184 static u_long pmap_l2_p_failures;
1185 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1186 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1188 static u_long pmap_l2_promotions;
1189 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1190 &pmap_l2_promotions, 0, "2MB page promotions");
1193 * Invalidate a single TLB entry.
1195 static __inline void
1196 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1200 PMAP_ASSERT_STAGE1(pmap);
1203 if (pmap == kernel_pmap) {
1205 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1207 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1208 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1214 static __inline void
1215 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1217 uint64_t end, r, start;
1219 PMAP_ASSERT_STAGE1(pmap);
1222 if (pmap == kernel_pmap) {
1225 for (r = start; r < end; r++)
1226 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1228 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1231 for (r = start; r < end; r++)
1232 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1238 static __inline void
1239 pmap_invalidate_all(pmap_t pmap)
1243 PMAP_ASSERT_STAGE1(pmap);
1246 if (pmap == kernel_pmap) {
1247 __asm __volatile("tlbi vmalle1is");
1249 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1250 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1257 * Routine: pmap_extract
1259 * Extract the physical page address associated
1260 * with the given map/virtual_address pair.
1263 pmap_extract(pmap_t pmap, vm_offset_t va)
1265 pt_entry_t *pte, tpte;
1272 * Find the block or page map for this virtual address. pmap_pte
1273 * will return either a valid block/page entry, or NULL.
1275 pte = pmap_pte(pmap, va, &lvl);
1277 tpte = pmap_load(pte);
1278 pa = tpte & ~ATTR_MASK;
1281 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1282 ("pmap_extract: Invalid L1 pte found: %lx",
1283 tpte & ATTR_DESCR_MASK));
1284 pa |= (va & L1_OFFSET);
1287 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1288 ("pmap_extract: Invalid L2 pte found: %lx",
1289 tpte & ATTR_DESCR_MASK));
1290 pa |= (va & L2_OFFSET);
1293 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1294 ("pmap_extract: Invalid L3 pte found: %lx",
1295 tpte & ATTR_DESCR_MASK));
1296 pa |= (va & L3_OFFSET);
1305 * Routine: pmap_extract_and_hold
1307 * Atomically extract and hold the physical page
1308 * with the given pmap and virtual address pair
1309 * if that mapping permits the given protection.
1312 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1314 pt_entry_t *pte, tpte;
1322 pte = pmap_pte(pmap, va, &lvl);
1324 tpte = pmap_load(pte);
1326 KASSERT(lvl > 0 && lvl <= 3,
1327 ("pmap_extract_and_hold: Invalid level %d", lvl));
1328 CTASSERT(L1_BLOCK == L2_BLOCK);
1329 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1330 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1331 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1332 tpte & ATTR_DESCR_MASK));
1335 if ((prot & VM_PROT_WRITE) == 0)
1337 else if (pmap->pm_stage == PM_STAGE1 &&
1338 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1340 else if (pmap->pm_stage == PM_STAGE2 &&
1341 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1342 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1348 off = va & L1_OFFSET;
1351 off = va & L2_OFFSET;
1357 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1358 if (m != NULL && !vm_page_wire_mapped(m))
1367 pmap_kextract(vm_offset_t va)
1369 pt_entry_t *pte, tpte;
1371 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1372 return (DMAP_TO_PHYS(va));
1373 pte = pmap_l1(kernel_pmap, va);
1378 * A concurrent pmap_update_entry() will clear the entry's valid bit
1379 * but leave the rest of the entry unchanged. Therefore, we treat a
1380 * non-zero entry as being valid, and we ignore the valid bit when
1381 * determining whether the entry maps a block, page, or table.
1383 tpte = pmap_load(pte);
1386 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1387 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1388 pte = pmap_l1_to_l2(&tpte, va);
1389 tpte = pmap_load(pte);
1392 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1393 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1394 pte = pmap_l2_to_l3(&tpte, va);
1395 tpte = pmap_load(pte);
1398 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1401 /***************************************************
1402 * Low level mapping routines.....
1403 ***************************************************/
1406 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1409 pt_entry_t *pte, attr;
1413 KASSERT((pa & L3_OFFSET) == 0,
1414 ("pmap_kenter: Invalid physical address"));
1415 KASSERT((sva & L3_OFFSET) == 0,
1416 ("pmap_kenter: Invalid virtual address"));
1417 KASSERT((size & PAGE_MASK) == 0,
1418 ("pmap_kenter: Mapping is not page-sized"));
1420 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1421 ATTR_S1_IDX(mode) | L3_PAGE;
1424 pde = pmap_pde(kernel_pmap, va, &lvl);
1425 KASSERT(pde != NULL,
1426 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1427 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1429 pte = pmap_l2_to_l3(pde, va);
1430 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1436 pmap_invalidate_range(kernel_pmap, sva, va);
1440 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1443 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1447 * Remove a page from the kernel pagetables.
1450 pmap_kremove(vm_offset_t va)
1455 pte = pmap_pte(kernel_pmap, va, &lvl);
1456 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1457 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1460 pmap_invalidate_page(kernel_pmap, va);
1464 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1470 KASSERT((sva & L3_OFFSET) == 0,
1471 ("pmap_kremove_device: Invalid virtual address"));
1472 KASSERT((size & PAGE_MASK) == 0,
1473 ("pmap_kremove_device: Mapping is not page-sized"));
1477 pte = pmap_pte(kernel_pmap, va, &lvl);
1478 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1480 ("Invalid device pagetable level: %d != 3", lvl));
1486 pmap_invalidate_range(kernel_pmap, sva, va);
1490 * Used to map a range of physical addresses into kernel
1491 * virtual address space.
1493 * The value passed in '*virt' is a suggested virtual address for
1494 * the mapping. Architectures which can support a direct-mapped
1495 * physical to virtual region can return the appropriate address
1496 * within that region, leaving '*virt' unchanged. Other
1497 * architectures should map the pages starting at '*virt' and
1498 * update '*virt' with the first usable address after the mapped
1502 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1504 return PHYS_TO_DMAP(start);
1508 * Add a list of wired pages to the kva
1509 * this routine is only used for temporary
1510 * kernel mappings that do not need to have
1511 * page modification or references recorded.
1512 * Note that old mappings are simply written
1513 * over. The page *must* be wired.
1514 * Note: SMP coherent. Uses a ranged shootdown IPI.
1517 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1520 pt_entry_t *pte, pa;
1526 for (i = 0; i < count; i++) {
1527 pde = pmap_pde(kernel_pmap, va, &lvl);
1528 KASSERT(pde != NULL,
1529 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1531 ("pmap_qenter: Invalid level %d", lvl));
1534 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1535 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1536 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1537 pte = pmap_l2_to_l3(pde, va);
1538 pmap_load_store(pte, pa);
1542 pmap_invalidate_range(kernel_pmap, sva, va);
1546 * This routine tears out page mappings from the
1547 * kernel -- it is meant only for temporary mappings.
1550 pmap_qremove(vm_offset_t sva, int count)
1556 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1559 while (count-- > 0) {
1560 pte = pmap_pte(kernel_pmap, va, &lvl);
1562 ("Invalid device pagetable level: %d != 3", lvl));
1569 pmap_invalidate_range(kernel_pmap, sva, va);
1572 /***************************************************
1573 * Page table page management routines.....
1574 ***************************************************/
1576 * Schedule the specified unused page table page to be freed. Specifically,
1577 * add the page to the specified list of pages that will be released to the
1578 * physical memory manager after the TLB has been updated.
1580 static __inline void
1581 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1582 boolean_t set_PG_ZERO)
1586 m->flags |= PG_ZERO;
1588 m->flags &= ~PG_ZERO;
1589 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1593 * Decrements a page table page's reference count, which is used to record the
1594 * number of valid page table entries within the page. If the reference count
1595 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1596 * page table page was unmapped and FALSE otherwise.
1598 static inline boolean_t
1599 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1603 if (m->ref_count == 0) {
1604 _pmap_unwire_l3(pmap, va, m, free);
1611 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1614 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1616 * unmap the page table page
1618 if (m->pindex >= (NUL2E + NUL1E)) {
1622 l0 = pmap_l0(pmap, va);
1624 } else if (m->pindex >= NUL2E) {
1628 l1 = pmap_l1(pmap, va);
1634 l2 = pmap_l2(pmap, va);
1637 pmap_resident_count_dec(pmap, 1);
1638 if (m->pindex < NUL2E) {
1639 /* We just released an l3, unhold the matching l2 */
1640 pd_entry_t *l1, tl1;
1643 l1 = pmap_l1(pmap, va);
1644 tl1 = pmap_load(l1);
1645 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1646 pmap_unwire_l3(pmap, va, l2pg, free);
1647 } else if (m->pindex < (NUL2E + NUL1E)) {
1648 /* We just released an l2, unhold the matching l1 */
1649 pd_entry_t *l0, tl0;
1652 l0 = pmap_l0(pmap, va);
1653 tl0 = pmap_load(l0);
1654 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1655 pmap_unwire_l3(pmap, va, l1pg, free);
1657 pmap_invalidate_page(pmap, va);
1660 * Put page on a list so that it is released after
1661 * *ALL* TLB shootdown is done
1663 pmap_add_delayed_free_list(m, free, TRUE);
1667 * After removing a page table entry, this routine is used to
1668 * conditionally free the page, and manage the reference count.
1671 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1672 struct spglist *free)
1676 if (va >= VM_MAXUSER_ADDRESS)
1678 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1679 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1680 return (pmap_unwire_l3(pmap, va, mpte, free));
1684 * Release a page table page reference after a failed attempt to create a
1688 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1690 struct spglist free;
1693 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
1695 * Although "va" was never mapped, the TLB could nonetheless
1696 * have intermediate entries that refer to the freed page
1697 * table pages. Invalidate those entries.
1699 * XXX redundant invalidation (See _pmap_unwire_l3().)
1701 pmap_invalidate_page(pmap, va);
1702 vm_page_free_pages_toq(&free, true);
1707 pmap_pinit0(pmap_t pmap)
1710 PMAP_LOCK_INIT(pmap);
1711 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1712 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1713 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1714 pmap->pm_root.rt_root = 0;
1715 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1716 pmap->pm_stage = PM_STAGE1;
1717 pmap->pm_asid_set = &asids;
1719 PCPU_SET(curpmap, pmap);
1723 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage)
1728 * allocate the l0 page
1730 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1731 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1734 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(l0pt);
1735 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1737 if ((l0pt->flags & PG_ZERO) == 0)
1738 pagezero(pmap->pm_l0);
1740 pmap->pm_root.rt_root = 0;
1741 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1742 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1744 pmap->pm_stage = stage;
1747 pmap->pm_asid_set = &asids;
1750 pmap->pm_asid_set = &vmids;
1753 panic("%s: Invalid pmap type %d", __func__, stage);
1757 /* XXX Temporarily disable deferred ASID allocation. */
1758 pmap_alloc_asid(pmap);
1764 pmap_pinit(pmap_t pmap)
1767 return (pmap_pinit_stage(pmap, PM_STAGE1));
1771 * This routine is called if the desired page table page does not exist.
1773 * If page table page allocation fails, this routine may sleep before
1774 * returning NULL. It sleeps only if a lock pointer was given.
1776 * Note: If a page allocation fails at page table level two or three,
1777 * one or two pages may be held during the wait, only to be released
1778 * afterwards. This conservative approach is easily argued to avoid
1782 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1784 vm_page_t m, l1pg, l2pg;
1786 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1789 * Allocate a page table page.
1791 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1792 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1793 if (lockp != NULL) {
1794 RELEASE_PV_LIST_LOCK(lockp);
1801 * Indicate the need to retry. While waiting, the page table
1802 * page may have been allocated.
1806 if ((m->flags & PG_ZERO) == 0)
1810 * Because of AArch64's weak memory consistency model, we must have a
1811 * barrier here to ensure that the stores for zeroing "m", whether by
1812 * pmap_zero_page() or an earlier function, are visible before adding
1813 * "m" to the page table. Otherwise, a page table walk by another
1814 * processor's MMU could see the mapping to "m" and a stale, non-zero
1820 * Map the pagetable page into the process address space, if
1821 * it isn't already there.
1824 if (ptepindex >= (NUL2E + NUL1E)) {
1826 vm_pindex_t l0index;
1828 l0index = ptepindex - (NUL2E + NUL1E);
1829 l0 = &pmap->pm_l0[l0index];
1830 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1831 } else if (ptepindex >= NUL2E) {
1832 vm_pindex_t l0index, l1index;
1833 pd_entry_t *l0, *l1;
1836 l1index = ptepindex - NUL2E;
1837 l0index = l1index >> L0_ENTRIES_SHIFT;
1839 l0 = &pmap->pm_l0[l0index];
1840 tl0 = pmap_load(l0);
1842 /* recurse for allocating page dir */
1843 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1845 vm_page_unwire_noq(m);
1846 vm_page_free_zero(m);
1850 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1854 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1855 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1856 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1858 vm_pindex_t l0index, l1index;
1859 pd_entry_t *l0, *l1, *l2;
1860 pd_entry_t tl0, tl1;
1862 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1863 l0index = l1index >> L0_ENTRIES_SHIFT;
1865 l0 = &pmap->pm_l0[l0index];
1866 tl0 = pmap_load(l0);
1868 /* recurse for allocating page dir */
1869 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1871 vm_page_unwire_noq(m);
1872 vm_page_free_zero(m);
1875 tl0 = pmap_load(l0);
1876 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1877 l1 = &l1[l1index & Ln_ADDR_MASK];
1879 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1880 l1 = &l1[l1index & Ln_ADDR_MASK];
1881 tl1 = pmap_load(l1);
1883 /* recurse for allocating page dir */
1884 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1886 vm_page_unwire_noq(m);
1887 vm_page_free_zero(m);
1891 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1896 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1897 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1898 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1901 pmap_resident_count_inc(pmap, 1);
1907 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
1908 struct rwlock **lockp)
1910 pd_entry_t *l1, *l2;
1912 vm_pindex_t l2pindex;
1915 l1 = pmap_l1(pmap, va);
1916 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1917 l2 = pmap_l1_to_l2(l1, va);
1918 if (va < VM_MAXUSER_ADDRESS) {
1919 /* Add a reference to the L2 page. */
1920 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1924 } else if (va < VM_MAXUSER_ADDRESS) {
1925 /* Allocate a L2 page. */
1926 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1927 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1934 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
1935 l2 = &l2[pmap_l2_index(va)];
1937 panic("pmap_alloc_l2: missing page table page for va %#lx",
1944 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1946 vm_pindex_t ptepindex;
1947 pd_entry_t *pde, tpde;
1955 * Calculate pagetable page index
1957 ptepindex = pmap_l2_pindex(va);
1960 * Get the page directory entry
1962 pde = pmap_pde(pmap, va, &lvl);
1965 * If the page table page is mapped, we just increment the hold count,
1966 * and activate it. If we get a level 2 pde it will point to a level 3
1974 pte = pmap_l0_to_l1(pde, va);
1975 KASSERT(pmap_load(pte) == 0,
1976 ("pmap_alloc_l3: TODO: l0 superpages"));
1981 pte = pmap_l1_to_l2(pde, va);
1982 KASSERT(pmap_load(pte) == 0,
1983 ("pmap_alloc_l3: TODO: l1 superpages"));
1987 tpde = pmap_load(pde);
1989 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1995 panic("pmap_alloc_l3: Invalid level %d", lvl);
1999 * Here if the pte page isn't mapped, or if it has been deallocated.
2001 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
2002 if (m == NULL && lockp != NULL)
2008 /***************************************************
2009 * Pmap allocation/deallocation routines.
2010 ***************************************************/
2013 * Release any resources held by the given physical map.
2014 * Called when a pmap initialized by pmap_pinit is being released.
2015 * Should only be called if the map contains no valid mappings.
2018 pmap_release(pmap_t pmap)
2020 struct asid_set *set;
2024 KASSERT(pmap->pm_stats.resident_count == 0,
2025 ("pmap_release: pmap resident count %ld != 0",
2026 pmap->pm_stats.resident_count));
2027 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2028 ("pmap_release: pmap has reserved page table page(s)"));
2030 set = pmap->pm_asid_set;
2031 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
2034 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
2035 * the entries when removing them so rely on a later tlb invalidation.
2036 * this will happen when updating the VMID generation. Because of this
2037 * we don't reuse VMIDs within a generation.
2039 if (pmap->pm_stage == PM_STAGE1) {
2040 mtx_lock_spin(&set->asid_set_mutex);
2041 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
2042 asid = COOKIE_TO_ASID(pmap->pm_cookie);
2043 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
2044 asid < set->asid_set_size,
2045 ("pmap_release: pmap cookie has out-of-range asid"));
2046 bit_clear(set->asid_set, asid);
2048 mtx_unlock_spin(&set->asid_set_mutex);
2051 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
2052 vm_page_unwire_noq(m);
2053 vm_page_free_zero(m);
2057 kvm_size(SYSCTL_HANDLER_ARGS)
2059 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2061 return sysctl_handle_long(oidp, &ksize, 0, req);
2063 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2064 0, 0, kvm_size, "LU",
2068 kvm_free(SYSCTL_HANDLER_ARGS)
2070 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2072 return sysctl_handle_long(oidp, &kfree, 0, req);
2074 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2075 0, 0, kvm_free, "LU",
2076 "Amount of KVM free");
2079 * grow the number of kernel page table entries, if needed
2082 pmap_growkernel(vm_offset_t addr)
2086 pd_entry_t *l0, *l1, *l2;
2088 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2090 addr = roundup2(addr, L2_SIZE);
2091 if (addr - 1 >= vm_map_max(kernel_map))
2092 addr = vm_map_max(kernel_map);
2093 while (kernel_vm_end < addr) {
2094 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2095 KASSERT(pmap_load(l0) != 0,
2096 ("pmap_growkernel: No level 0 kernel entry"));
2098 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2099 if (pmap_load(l1) == 0) {
2100 /* We need a new PDP entry */
2101 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
2102 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2103 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2105 panic("pmap_growkernel: no memory to grow kernel");
2106 if ((nkpg->flags & PG_ZERO) == 0)
2107 pmap_zero_page(nkpg);
2108 /* See the dmb() in _pmap_alloc_l3(). */
2110 paddr = VM_PAGE_TO_PHYS(nkpg);
2111 pmap_store(l1, paddr | L1_TABLE);
2112 continue; /* try again */
2114 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2115 if (pmap_load(l2) != 0) {
2116 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2117 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2118 kernel_vm_end = vm_map_max(kernel_map);
2124 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
2125 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2128 panic("pmap_growkernel: no memory to grow kernel");
2129 if ((nkpg->flags & PG_ZERO) == 0)
2130 pmap_zero_page(nkpg);
2131 /* See the dmb() in _pmap_alloc_l3(). */
2133 paddr = VM_PAGE_TO_PHYS(nkpg);
2134 pmap_store(l2, paddr | L2_TABLE);
2136 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2137 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2138 kernel_vm_end = vm_map_max(kernel_map);
2144 /***************************************************
2145 * page management routines.
2146 ***************************************************/
2148 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2149 CTASSERT(_NPCM == 3);
2150 CTASSERT(_NPCPV == 168);
2152 static __inline struct pv_chunk *
2153 pv_to_chunk(pv_entry_t pv)
2156 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2159 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2161 #define PC_FREE0 0xfffffffffffffffful
2162 #define PC_FREE1 0xfffffffffffffffful
2163 #define PC_FREE2 0x000000fffffffffful
2165 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2169 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2171 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2172 "Current number of pv entry chunks");
2173 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2174 "Current number of pv entry chunks allocated");
2175 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2176 "Current number of pv entry chunks frees");
2177 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2178 "Number of times tried to get a chunk page but failed.");
2180 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2181 static int pv_entry_spare;
2183 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2184 "Current number of pv entry frees");
2185 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2186 "Current number of pv entry allocs");
2187 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2188 "Current number of pv entries");
2189 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2190 "Current number of spare pv entries");
2195 * We are in a serious low memory condition. Resort to
2196 * drastic measures to free some pages so we can allocate
2197 * another pv entry chunk.
2199 * Returns NULL if PV entries were reclaimed from the specified pmap.
2201 * We do not, however, unmap 2mpages because subsequent accesses will
2202 * allocate per-page pv entries until repromotion occurs, thereby
2203 * exacerbating the shortage of free pv entries.
2206 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2208 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2209 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2210 struct md_page *pvh;
2212 pmap_t next_pmap, pmap;
2213 pt_entry_t *pte, tpte;
2217 struct spglist free;
2219 int bit, field, freed, lvl;
2220 static int active_reclaims = 0;
2222 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2223 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2228 bzero(&pc_marker_b, sizeof(pc_marker_b));
2229 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2230 pc_marker = (struct pv_chunk *)&pc_marker_b;
2231 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2233 mtx_lock(&pv_chunks_mutex);
2235 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2236 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2237 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2238 SLIST_EMPTY(&free)) {
2239 next_pmap = pc->pc_pmap;
2240 if (next_pmap == NULL) {
2242 * The next chunk is a marker. However, it is
2243 * not our marker, so active_reclaims must be
2244 * > 1. Consequently, the next_chunk code
2245 * will not rotate the pv_chunks list.
2249 mtx_unlock(&pv_chunks_mutex);
2252 * A pv_chunk can only be removed from the pc_lru list
2253 * when both pv_chunks_mutex is owned and the
2254 * corresponding pmap is locked.
2256 if (pmap != next_pmap) {
2257 if (pmap != NULL && pmap != locked_pmap)
2260 /* Avoid deadlock and lock recursion. */
2261 if (pmap > locked_pmap) {
2262 RELEASE_PV_LIST_LOCK(lockp);
2264 mtx_lock(&pv_chunks_mutex);
2266 } else if (pmap != locked_pmap) {
2267 if (PMAP_TRYLOCK(pmap)) {
2268 mtx_lock(&pv_chunks_mutex);
2271 pmap = NULL; /* pmap is not locked */
2272 mtx_lock(&pv_chunks_mutex);
2273 pc = TAILQ_NEXT(pc_marker, pc_lru);
2275 pc->pc_pmap != next_pmap)
2283 * Destroy every non-wired, 4 KB page mapping in the chunk.
2286 for (field = 0; field < _NPCM; field++) {
2287 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2288 inuse != 0; inuse &= ~(1UL << bit)) {
2289 bit = ffsl(inuse) - 1;
2290 pv = &pc->pc_pventry[field * 64 + bit];
2292 pde = pmap_pde(pmap, va, &lvl);
2295 pte = pmap_l2_to_l3(pde, va);
2296 tpte = pmap_load(pte);
2297 if ((tpte & ATTR_SW_WIRED) != 0)
2299 tpte = pmap_load_clear(pte);
2300 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2301 if (pmap_pte_dirty(pmap, tpte))
2303 if ((tpte & ATTR_AF) != 0) {
2304 pmap_invalidate_page(pmap, va);
2305 vm_page_aflag_set(m, PGA_REFERENCED);
2307 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2308 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2310 if (TAILQ_EMPTY(&m->md.pv_list) &&
2311 (m->flags & PG_FICTITIOUS) == 0) {
2312 pvh = page_to_pvh(m);
2313 if (TAILQ_EMPTY(&pvh->pv_list)) {
2314 vm_page_aflag_clear(m,
2318 pc->pc_map[field] |= 1UL << bit;
2319 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2324 mtx_lock(&pv_chunks_mutex);
2327 /* Every freed mapping is for a 4 KB page. */
2328 pmap_resident_count_dec(pmap, freed);
2329 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2330 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2331 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2332 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2333 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2334 pc->pc_map[2] == PC_FREE2) {
2335 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2336 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2337 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2338 /* Entire chunk is free; return it. */
2339 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2340 dump_drop_page(m_pc->phys_addr);
2341 mtx_lock(&pv_chunks_mutex);
2342 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2345 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2346 mtx_lock(&pv_chunks_mutex);
2347 /* One freed pv entry in locked_pmap is sufficient. */
2348 if (pmap == locked_pmap)
2352 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2353 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2354 if (active_reclaims == 1 && pmap != NULL) {
2356 * Rotate the pv chunks list so that we do not
2357 * scan the same pv chunks that could not be
2358 * freed (because they contained a wired
2359 * and/or superpage mapping) on every
2360 * invocation of reclaim_pv_chunk().
2362 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2363 MPASS(pc->pc_pmap != NULL);
2364 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2365 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2369 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2370 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2372 mtx_unlock(&pv_chunks_mutex);
2373 if (pmap != NULL && pmap != locked_pmap)
2375 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2376 m_pc = SLIST_FIRST(&free);
2377 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2378 /* Recycle a freed page table page. */
2379 m_pc->ref_count = 1;
2381 vm_page_free_pages_toq(&free, true);
2386 * free the pv_entry back to the free list
2389 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2391 struct pv_chunk *pc;
2392 int idx, field, bit;
2394 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2395 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2396 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2397 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2398 pc = pv_to_chunk(pv);
2399 idx = pv - &pc->pc_pventry[0];
2402 pc->pc_map[field] |= 1ul << bit;
2403 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2404 pc->pc_map[2] != PC_FREE2) {
2405 /* 98% of the time, pc is already at the head of the list. */
2406 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2407 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2408 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2412 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2417 free_pv_chunk(struct pv_chunk *pc)
2421 mtx_lock(&pv_chunks_mutex);
2422 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2423 mtx_unlock(&pv_chunks_mutex);
2424 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2425 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2426 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2427 /* entire chunk is free, return it */
2428 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2429 dump_drop_page(m->phys_addr);
2430 vm_page_unwire_noq(m);
2435 * Returns a new PV entry, allocating a new PV chunk from the system when
2436 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2437 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2440 * The given PV list lock may be released.
2443 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2447 struct pv_chunk *pc;
2450 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2451 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2453 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2455 for (field = 0; field < _NPCM; field++) {
2456 if (pc->pc_map[field]) {
2457 bit = ffsl(pc->pc_map[field]) - 1;
2461 if (field < _NPCM) {
2462 pv = &pc->pc_pventry[field * 64 + bit];
2463 pc->pc_map[field] &= ~(1ul << bit);
2464 /* If this was the last item, move it to tail */
2465 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2466 pc->pc_map[2] == 0) {
2467 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2468 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2471 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2472 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2476 /* No free items, allocate another chunk */
2477 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2480 if (lockp == NULL) {
2481 PV_STAT(pc_chunk_tryfail++);
2484 m = reclaim_pv_chunk(pmap, lockp);
2488 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2489 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2490 dump_add_page(m->phys_addr);
2491 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2493 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2494 pc->pc_map[1] = PC_FREE1;
2495 pc->pc_map[2] = PC_FREE2;
2496 mtx_lock(&pv_chunks_mutex);
2497 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2498 mtx_unlock(&pv_chunks_mutex);
2499 pv = &pc->pc_pventry[0];
2500 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2501 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2502 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2507 * Ensure that the number of spare PV entries in the specified pmap meets or
2508 * exceeds the given count, "needed".
2510 * The given PV list lock may be released.
2513 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2515 struct pch new_tail;
2516 struct pv_chunk *pc;
2521 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2522 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2525 * Newly allocated PV chunks must be stored in a private list until
2526 * the required number of PV chunks have been allocated. Otherwise,
2527 * reclaim_pv_chunk() could recycle one of these chunks. In
2528 * contrast, these chunks must be added to the pmap upon allocation.
2530 TAILQ_INIT(&new_tail);
2533 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2534 bit_count((bitstr_t *)pc->pc_map, 0,
2535 sizeof(pc->pc_map) * NBBY, &free);
2539 if (avail >= needed)
2542 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2543 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2546 m = reclaim_pv_chunk(pmap, lockp);
2551 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2552 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2553 dump_add_page(m->phys_addr);
2554 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2556 pc->pc_map[0] = PC_FREE0;
2557 pc->pc_map[1] = PC_FREE1;
2558 pc->pc_map[2] = PC_FREE2;
2559 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2560 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2561 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2564 * The reclaim might have freed a chunk from the current pmap.
2565 * If that chunk contained available entries, we need to
2566 * re-count the number of available entries.
2571 if (!TAILQ_EMPTY(&new_tail)) {
2572 mtx_lock(&pv_chunks_mutex);
2573 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2574 mtx_unlock(&pv_chunks_mutex);
2579 * First find and then remove the pv entry for the specified pmap and virtual
2580 * address from the specified pv list. Returns the pv entry if found and NULL
2581 * otherwise. This operation can be performed on pv lists for either 4KB or
2582 * 2MB page mappings.
2584 static __inline pv_entry_t
2585 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2589 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2590 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2591 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2600 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2601 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2602 * entries for each of the 4KB page mappings.
2605 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2606 struct rwlock **lockp)
2608 struct md_page *pvh;
2609 struct pv_chunk *pc;
2611 vm_offset_t va_last;
2615 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2616 KASSERT((va & L2_OFFSET) == 0,
2617 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2618 KASSERT((pa & L2_OFFSET) == 0,
2619 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2620 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2623 * Transfer the 2mpage's pv entry for this mapping to the first
2624 * page's pv list. Once this transfer begins, the pv list lock
2625 * must not be released until the last pv entry is reinstantiated.
2627 pvh = pa_to_pvh(pa);
2628 pv = pmap_pvh_remove(pvh, pmap, va);
2629 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2630 m = PHYS_TO_VM_PAGE(pa);
2631 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2633 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2634 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2635 va_last = va + L2_SIZE - PAGE_SIZE;
2637 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2638 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2639 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2640 for (field = 0; field < _NPCM; field++) {
2641 while (pc->pc_map[field]) {
2642 bit = ffsl(pc->pc_map[field]) - 1;
2643 pc->pc_map[field] &= ~(1ul << bit);
2644 pv = &pc->pc_pventry[field * 64 + bit];
2648 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2649 ("pmap_pv_demote_l2: page %p is not managed", m));
2650 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2656 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2657 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2660 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2661 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2662 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2664 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2665 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2669 * First find and then destroy the pv entry for the specified pmap and virtual
2670 * address. This operation can be performed on pv lists for either 4KB or 2MB
2674 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2678 pv = pmap_pvh_remove(pvh, pmap, va);
2679 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2680 free_pv_entry(pmap, pv);
2684 * Conditionally create the PV entry for a 4KB page mapping if the required
2685 * memory can be allocated without resorting to reclamation.
2688 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2689 struct rwlock **lockp)
2693 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2694 /* Pass NULL instead of the lock pointer to disable reclamation. */
2695 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2697 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2698 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2706 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2707 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2708 * false if the PV entry cannot be allocated without resorting to reclamation.
2711 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2712 struct rwlock **lockp)
2714 struct md_page *pvh;
2718 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2719 /* Pass NULL instead of the lock pointer to disable reclamation. */
2720 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2721 NULL : lockp)) == NULL)
2724 pa = l2e & ~ATTR_MASK;
2725 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2726 pvh = pa_to_pvh(pa);
2727 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2733 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2735 pt_entry_t newl2, oldl2;
2739 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2740 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2741 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2743 ml3 = pmap_remove_pt_page(pmap, va);
2745 panic("pmap_remove_kernel_l2: Missing pt page");
2747 ml3pa = VM_PAGE_TO_PHYS(ml3);
2748 newl2 = ml3pa | L2_TABLE;
2751 * If this page table page was unmapped by a promotion, then it
2752 * contains valid mappings. Zero it to invalidate those mappings.
2754 if (ml3->valid != 0)
2755 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2758 * Demote the mapping. The caller must have already invalidated the
2759 * mapping (i.e., the "break" in break-before-make).
2761 oldl2 = pmap_load_store(l2, newl2);
2762 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2763 __func__, l2, oldl2));
2767 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2770 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2771 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2773 struct md_page *pvh;
2775 vm_offset_t eva, va;
2778 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2779 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2780 old_l2 = pmap_load_clear(l2);
2781 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2782 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2785 * Since a promotion must break the 4KB page mappings before making
2786 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2788 pmap_invalidate_page(pmap, sva);
2790 if (old_l2 & ATTR_SW_WIRED)
2791 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2792 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2793 if (old_l2 & ATTR_SW_MANAGED) {
2794 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2795 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2796 pmap_pvh_free(pvh, pmap, sva);
2797 eva = sva + L2_SIZE;
2798 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2799 va < eva; va += PAGE_SIZE, m++) {
2800 if (pmap_pte_dirty(pmap, old_l2))
2802 if (old_l2 & ATTR_AF)
2803 vm_page_aflag_set(m, PGA_REFERENCED);
2804 if (TAILQ_EMPTY(&m->md.pv_list) &&
2805 TAILQ_EMPTY(&pvh->pv_list))
2806 vm_page_aflag_clear(m, PGA_WRITEABLE);
2809 if (pmap == kernel_pmap) {
2810 pmap_remove_kernel_l2(pmap, l2, sva);
2812 ml3 = pmap_remove_pt_page(pmap, sva);
2814 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2815 ("pmap_remove_l2: l3 page not promoted"));
2816 pmap_resident_count_dec(pmap, 1);
2817 KASSERT(ml3->ref_count == NL3PG,
2818 ("pmap_remove_l2: l3 page ref count error"));
2820 pmap_add_delayed_free_list(ml3, free, FALSE);
2823 return (pmap_unuse_pt(pmap, sva, l1e, free));
2827 * pmap_remove_l3: do the things to unmap a page in a process
2830 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2831 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2833 struct md_page *pvh;
2837 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2838 old_l3 = pmap_load_clear(l3);
2839 pmap_invalidate_page(pmap, va);
2840 if (old_l3 & ATTR_SW_WIRED)
2841 pmap->pm_stats.wired_count -= 1;
2842 pmap_resident_count_dec(pmap, 1);
2843 if (old_l3 & ATTR_SW_MANAGED) {
2844 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2845 if (pmap_pte_dirty(pmap, old_l3))
2847 if (old_l3 & ATTR_AF)
2848 vm_page_aflag_set(m, PGA_REFERENCED);
2849 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2850 pmap_pvh_free(&m->md, pmap, va);
2851 if (TAILQ_EMPTY(&m->md.pv_list) &&
2852 (m->flags & PG_FICTITIOUS) == 0) {
2853 pvh = page_to_pvh(m);
2854 if (TAILQ_EMPTY(&pvh->pv_list))
2855 vm_page_aflag_clear(m, PGA_WRITEABLE);
2858 return (pmap_unuse_pt(pmap, va, l2e, free));
2862 * Remove the specified range of addresses from the L3 page table that is
2863 * identified by the given L2 entry.
2866 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2867 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2869 struct md_page *pvh;
2870 struct rwlock *new_lock;
2871 pt_entry_t *l3, old_l3;
2875 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2876 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2877 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2878 l3pg = sva < VM_MAXUSER_ADDRESS ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) :
2881 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2882 if (!pmap_l3_valid(pmap_load(l3))) {
2884 pmap_invalidate_range(pmap, va, sva);
2889 old_l3 = pmap_load_clear(l3);
2890 if ((old_l3 & ATTR_SW_WIRED) != 0)
2891 pmap->pm_stats.wired_count--;
2892 pmap_resident_count_dec(pmap, 1);
2893 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2894 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2895 if (pmap_pte_dirty(pmap, old_l3))
2897 if ((old_l3 & ATTR_AF) != 0)
2898 vm_page_aflag_set(m, PGA_REFERENCED);
2899 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2900 if (new_lock != *lockp) {
2901 if (*lockp != NULL) {
2903 * Pending TLB invalidations must be
2904 * performed before the PV list lock is
2905 * released. Otherwise, a concurrent
2906 * pmap_remove_all() on a physical page
2907 * could return while a stale TLB entry
2908 * still provides access to that page.
2911 pmap_invalidate_range(pmap, va,
2920 pmap_pvh_free(&m->md, pmap, sva);
2921 if (TAILQ_EMPTY(&m->md.pv_list) &&
2922 (m->flags & PG_FICTITIOUS) == 0) {
2923 pvh = page_to_pvh(m);
2924 if (TAILQ_EMPTY(&pvh->pv_list))
2925 vm_page_aflag_clear(m, PGA_WRITEABLE);
2930 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
2936 pmap_invalidate_range(pmap, va, sva);
2940 * Remove the given range of addresses from the specified map.
2942 * It is assumed that the start and end are properly
2943 * rounded to the page size.
2946 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2948 struct rwlock *lock;
2949 vm_offset_t va_next;
2950 pd_entry_t *l0, *l1, *l2;
2951 pt_entry_t l3_paddr;
2952 struct spglist free;
2955 * Perform an unsynchronized read. This is, however, safe.
2957 if (pmap->pm_stats.resident_count == 0)
2965 for (; sva < eva; sva = va_next) {
2966 if (pmap->pm_stats.resident_count == 0)
2969 l0 = pmap_l0(pmap, sva);
2970 if (pmap_load(l0) == 0) {
2971 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2977 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2980 l1 = pmap_l0_to_l1(l0, sva);
2981 if (pmap_load(l1) == 0)
2983 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
2984 KASSERT(va_next <= eva,
2985 ("partial update of non-transparent 1G page "
2986 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
2987 pmap_load(l1), sva, eva, va_next));
2988 MPASS(pmap != kernel_pmap);
2989 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
2991 pmap_invalidate_page(pmap, sva);
2992 pmap_resident_count_dec(pmap, L1_SIZE / PAGE_SIZE);
2993 pmap_unuse_pt(pmap, sva, pmap_load(l0), &free);
2998 * Calculate index for next page table.
3000 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3004 l2 = pmap_l1_to_l2(l1, sva);
3008 l3_paddr = pmap_load(l2);
3010 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3011 if (sva + L2_SIZE == va_next && eva >= va_next) {
3012 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
3015 } else if (pmap_demote_l2_locked(pmap, l2, sva,
3018 l3_paddr = pmap_load(l2);
3022 * Weed out invalid mappings.
3024 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
3028 * Limit our scan to either the end of the va represented
3029 * by the current page table page, or to the end of the
3030 * range being removed.
3035 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
3041 vm_page_free_pages_toq(&free, true);
3045 * Routine: pmap_remove_all
3047 * Removes this physical page from
3048 * all physical maps in which it resides.
3049 * Reflects back modify bits to the pager.
3052 * Original versions of this routine were very
3053 * inefficient because they iteratively called
3054 * pmap_remove (slow...)
3058 pmap_remove_all(vm_page_t m)
3060 struct md_page *pvh;
3063 struct rwlock *lock;
3064 pd_entry_t *pde, tpde;
3065 pt_entry_t *pte, tpte;
3067 struct spglist free;
3068 int lvl, pvh_gen, md_gen;
3070 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3071 ("pmap_remove_all: page %p is not managed", m));
3073 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3074 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
3077 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3079 if (!PMAP_TRYLOCK(pmap)) {
3080 pvh_gen = pvh->pv_gen;
3084 if (pvh_gen != pvh->pv_gen) {
3091 pte = pmap_pte(pmap, va, &lvl);
3092 KASSERT(pte != NULL,
3093 ("pmap_remove_all: no page table entry found"));
3095 ("pmap_remove_all: invalid pte level %d", lvl));
3097 pmap_demote_l2_locked(pmap, pte, va, &lock);
3100 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3102 PMAP_ASSERT_STAGE1(pmap);
3103 if (!PMAP_TRYLOCK(pmap)) {
3104 pvh_gen = pvh->pv_gen;
3105 md_gen = m->md.pv_gen;
3109 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3115 pmap_resident_count_dec(pmap, 1);
3117 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3118 KASSERT(pde != NULL,
3119 ("pmap_remove_all: no page directory entry found"));
3121 ("pmap_remove_all: invalid pde level %d", lvl));
3122 tpde = pmap_load(pde);
3124 pte = pmap_l2_to_l3(pde, pv->pv_va);
3125 tpte = pmap_load_clear(pte);
3126 if (tpte & ATTR_SW_WIRED)
3127 pmap->pm_stats.wired_count--;
3128 if ((tpte & ATTR_AF) != 0) {
3129 pmap_invalidate_page(pmap, pv->pv_va);
3130 vm_page_aflag_set(m, PGA_REFERENCED);
3134 * Update the vm_page_t clean and reference bits.
3136 if (pmap_pte_dirty(pmap, tpte))
3138 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3139 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3141 free_pv_entry(pmap, pv);
3144 vm_page_aflag_clear(m, PGA_WRITEABLE);
3146 vm_page_free_pages_toq(&free, true);
3150 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
3153 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3159 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3160 PMAP_ASSERT_STAGE1(pmap);
3161 KASSERT((sva & L2_OFFSET) == 0,
3162 ("pmap_protect_l2: sva is not 2mpage aligned"));
3163 old_l2 = pmap_load(l2);
3164 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3165 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3168 * Return if the L2 entry already has the desired access restrictions
3172 if ((old_l2 & mask) == nbits)
3176 * When a dirty read/write superpage mapping is write protected,
3177 * update the dirty field of each of the superpage's constituent 4KB
3180 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3181 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3182 pmap_pte_dirty(pmap, old_l2)) {
3183 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3184 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3188 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3192 * Since a promotion must break the 4KB page mappings before making
3193 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3195 pmap_invalidate_page(pmap, sva);
3199 * Set the physical protection on the
3200 * specified range of this map as requested.
3203 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3205 vm_offset_t va, va_next;
3206 pd_entry_t *l0, *l1, *l2;
3207 pt_entry_t *l3p, l3, mask, nbits;
3209 PMAP_ASSERT_STAGE1(pmap);
3210 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3211 if (prot == VM_PROT_NONE) {
3212 pmap_remove(pmap, sva, eva);
3217 if ((prot & VM_PROT_WRITE) == 0) {
3218 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3219 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3221 if ((prot & VM_PROT_EXECUTE) == 0) {
3223 nbits |= ATTR_S1_XN;
3229 for (; sva < eva; sva = va_next) {
3230 l0 = pmap_l0(pmap, sva);
3231 if (pmap_load(l0) == 0) {
3232 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3238 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3241 l1 = pmap_l0_to_l1(l0, sva);
3242 if (pmap_load(l1) == 0)
3244 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3245 KASSERT(va_next <= eva,
3246 ("partial update of non-transparent 1G page "
3247 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3248 pmap_load(l1), sva, eva, va_next));
3249 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3250 if ((pmap_load(l1) & mask) != nbits) {
3251 pmap_store(l1, (pmap_load(l1) & ~mask) | nbits);
3252 pmap_invalidate_page(pmap, sva);
3257 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3261 l2 = pmap_l1_to_l2(l1, sva);
3262 if (pmap_load(l2) == 0)
3265 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3266 if (sva + L2_SIZE == va_next && eva >= va_next) {
3267 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3269 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3272 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3273 ("pmap_protect: Invalid L2 entry after demotion"));
3279 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3281 l3 = pmap_load(l3p);
3284 * Go to the next L3 entry if the current one is
3285 * invalid or already has the desired access
3286 * restrictions in place. (The latter case occurs
3287 * frequently. For example, in a "buildworld"
3288 * workload, almost 1 out of 4 L3 entries already
3289 * have the desired restrictions.)
3291 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3292 if (va != va_next) {
3293 pmap_invalidate_range(pmap, va, sva);
3300 * When a dirty read/write mapping is write protected,
3301 * update the page's dirty field.
3303 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3304 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3305 pmap_pte_dirty(pmap, l3))
3306 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3308 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3314 pmap_invalidate_range(pmap, va, sva);
3320 * Inserts the specified page table page into the specified pmap's collection
3321 * of idle page table pages. Each of a pmap's page table pages is responsible
3322 * for mapping a distinct range of virtual addresses. The pmap's collection is
3323 * ordered by this virtual address range.
3325 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3328 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3331 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3332 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3333 return (vm_radix_insert(&pmap->pm_root, mpte));
3337 * Removes the page table page mapping the specified virtual address from the
3338 * specified pmap's collection of idle page table pages, and returns it.
3339 * Otherwise, returns NULL if there is no page table page corresponding to the
3340 * specified virtual address.
3342 static __inline vm_page_t
3343 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3346 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3347 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3351 * Performs a break-before-make update of a pmap entry. This is needed when
3352 * either promoting or demoting pages to ensure the TLB doesn't get into an
3353 * inconsistent state.
3356 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3357 vm_offset_t va, vm_size_t size)
3361 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3364 * Ensure we don't get switched out with the page table in an
3365 * inconsistent state. We also need to ensure no interrupts fire
3366 * as they may make use of an address we are about to invalidate.
3368 intr = intr_disable();
3371 * Clear the old mapping's valid bit, but leave the rest of the entry
3372 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3373 * lookup the physical address.
3375 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3376 pmap_invalidate_range(pmap, va, va + size);
3378 /* Create the new mapping */
3379 pmap_store(pte, newpte);
3385 #if VM_NRESERVLEVEL > 0
3387 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3388 * replace the many pv entries for the 4KB page mappings by a single pv entry
3389 * for the 2MB page mapping.
3392 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3393 struct rwlock **lockp)
3395 struct md_page *pvh;
3397 vm_offset_t va_last;
3400 KASSERT((pa & L2_OFFSET) == 0,
3401 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3402 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3405 * Transfer the first page's pv entry for this mapping to the 2mpage's
3406 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3407 * a transfer avoids the possibility that get_pv_entry() calls
3408 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3409 * mappings that is being promoted.
3411 m = PHYS_TO_VM_PAGE(pa);
3412 va = va & ~L2_OFFSET;
3413 pv = pmap_pvh_remove(&m->md, pmap, va);
3414 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3415 pvh = pa_to_pvh(pa);
3416 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3418 /* Free the remaining NPTEPG - 1 pv entries. */
3419 va_last = va + L2_SIZE - PAGE_SIZE;
3423 pmap_pvh_free(&m->md, pmap, va);
3424 } while (va < va_last);
3428 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3429 * single level 2 table entry to a single 2MB page mapping. For promotion
3430 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3431 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3432 * identical characteristics.
3435 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3436 struct rwlock **lockp)
3438 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3442 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3443 PMAP_ASSERT_STAGE1(pmap);
3445 sva = va & ~L2_OFFSET;
3446 firstl3 = pmap_l2_to_l3(l2, sva);
3447 newl2 = pmap_load(firstl3);
3450 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3451 atomic_add_long(&pmap_l2_p_failures, 1);
3452 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3453 " in pmap %p", va, pmap);
3457 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3458 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3459 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3461 newl2 &= ~ATTR_SW_DBM;
3464 pa = newl2 + L2_SIZE - PAGE_SIZE;
3465 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3466 oldl3 = pmap_load(l3);
3468 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3469 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3470 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3473 oldl3 &= ~ATTR_SW_DBM;
3476 atomic_add_long(&pmap_l2_p_failures, 1);
3477 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3478 " in pmap %p", va, pmap);
3485 * Save the page table page in its current state until the L2
3486 * mapping the superpage is demoted by pmap_demote_l2() or
3487 * destroyed by pmap_remove_l3().
3489 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3490 KASSERT(mpte >= vm_page_array &&
3491 mpte < &vm_page_array[vm_page_array_size],
3492 ("pmap_promote_l2: page table page is out of range"));
3493 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3494 ("pmap_promote_l2: page table page's pindex is wrong"));
3495 if (pmap_insert_pt_page(pmap, mpte, true)) {
3496 atomic_add_long(&pmap_l2_p_failures, 1);
3498 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3503 if ((newl2 & ATTR_SW_MANAGED) != 0)
3504 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3506 newl2 &= ~ATTR_DESCR_MASK;
3509 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3511 atomic_add_long(&pmap_l2_promotions, 1);
3512 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3515 #endif /* VM_NRESERVLEVEL > 0 */
3518 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
3521 pd_entry_t *l0p, *l1p, *l2p, origpte;
3524 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3525 KASSERT(psind > 0 && psind < MAXPAGESIZES,
3526 ("psind %d unexpected", psind));
3527 KASSERT(((newpte & ~ATTR_MASK) & (pagesizes[psind] - 1)) == 0,
3528 ("unaligned phys address %#lx newpte %#lx psind %d",
3529 (newpte & ~ATTR_MASK), newpte, psind));
3533 l0p = pmap_l0(pmap, va);
3534 if ((pmap_load(l0p) & ATTR_DESCR_VALID) == 0) {
3535 mp = _pmap_alloc_l3(pmap, pmap_l0_pindex(va), NULL);
3537 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3538 return (KERN_RESOURCE_SHORTAGE);
3544 l1p = pmap_l0_to_l1(l0p, va);
3545 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3546 origpte = pmap_load(l1p);
3548 l1p = pmap_l0_to_l1(l0p, va);
3549 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3550 origpte = pmap_load(l1p);
3551 if ((origpte & ATTR_DESCR_VALID) == 0) {
3552 mp = PHYS_TO_VM_PAGE(pmap_load(l0p) &
3557 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3558 ((origpte & ATTR_DESCR_MASK) == L1_BLOCK &&
3559 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3560 ("va %#lx changing 1G phys page l1 %#lx newpte %#lx",
3561 va, origpte, newpte));
3562 pmap_store(l1p, newpte);
3563 } else /* (psind == 1) */ {
3564 l2p = pmap_l2(pmap, va);
3566 mp = _pmap_alloc_l3(pmap, pmap_l1_pindex(va), NULL);
3568 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3569 return (KERN_RESOURCE_SHORTAGE);
3575 l2p = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
3576 l2p = &l2p[pmap_l2_index(va)];
3577 origpte = pmap_load(l2p);
3579 l1p = pmap_l1(pmap, va);
3580 origpte = pmap_load(l2p);
3581 if ((origpte & ATTR_DESCR_VALID) == 0) {
3582 mp = PHYS_TO_VM_PAGE(pmap_load(l1p) &
3587 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3588 ((origpte & ATTR_DESCR_MASK) == L2_BLOCK &&
3589 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3590 ("va %#lx changing 2M phys page l2 %#lx newpte %#lx",
3591 va, origpte, newpte));
3592 pmap_store(l2p, newpte);
3596 if ((origpte & ATTR_DESCR_VALID) == 0)
3597 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
3598 if ((newpte & ATTR_SW_WIRED) != 0 && (origpte & ATTR_SW_WIRED) == 0)
3599 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
3600 else if ((newpte & ATTR_SW_WIRED) == 0 &&
3601 (origpte & ATTR_SW_WIRED) != 0)
3602 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
3604 return (KERN_SUCCESS);
3608 * Add a single SMMU entry. This function does not sleep.
3611 pmap_senter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3612 vm_prot_t prot, u_int flags)
3615 pt_entry_t new_l3, orig_l3;
3621 PMAP_ASSERT_STAGE1(pmap);
3622 KASSERT(va < VM_MAXUSER_ADDRESS, ("wrong address space"));
3624 va = trunc_page(va);
3625 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT |
3626 ATTR_S1_IDX(VM_MEMATTR_DEVICE) | L3_PAGE);
3627 if ((prot & VM_PROT_WRITE) == 0)
3628 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3629 new_l3 |= ATTR_S1_XN; /* Execute never. */
3630 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER);
3631 new_l3 |= ATTR_S1_nG; /* Non global. */
3633 CTR2(KTR_PMAP, "pmap_senter: %.16lx -> %.16lx", va, pa);
3638 * In the case that a page table page is not
3639 * resident, we are creating it here.
3642 pde = pmap_pde(pmap, va, &lvl);
3643 if (pde != NULL && lvl == 2) {
3644 l3 = pmap_l2_to_l3(pde, va);
3646 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va), NULL);
3648 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3649 rv = KERN_RESOURCE_SHORTAGE;
3655 orig_l3 = pmap_load(l3);
3656 KASSERT(!pmap_l3_valid(orig_l3), ("l3 is valid"));
3659 pmap_store(l3, new_l3);
3660 pmap_resident_count_inc(pmap, 1);
3671 * Remove a single SMMU entry.
3674 pmap_sremove(pmap_t pmap, vm_offset_t va)
3682 pte = pmap_pte(pmap, va, &lvl);
3684 ("Invalid SMMU pagetable level: %d != 3", lvl));
3687 pmap_resident_count_dec(pmap, 1);
3699 * Remove all the allocated L1, L2 pages from SMMU pmap.
3700 * All the L3 entires must be cleared in advance, otherwise
3701 * this function panics.
3704 pmap_sremove_pages(pmap_t pmap)
3706 pd_entry_t l0e, *l1, l1e, *l2, l2e;
3707 pt_entry_t *l3, l3e;
3708 vm_page_t m, m0, m1;
3717 for (sva = VM_MINUSER_ADDRESS, i = pmap_l0_index(sva);
3718 (i < Ln_ENTRIES && sva < VM_MAXUSER_ADDRESS); i++) {
3719 l0e = pmap->pm_l0[i];
3720 if ((l0e & ATTR_DESCR_VALID) == 0) {
3724 pa0 = l0e & ~ATTR_MASK;
3725 m0 = PHYS_TO_VM_PAGE(pa0);
3726 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa0);
3728 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
3730 if ((l1e & ATTR_DESCR_VALID) == 0) {
3734 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
3738 pa1 = l1e & ~ATTR_MASK;
3739 m1 = PHYS_TO_VM_PAGE(pa1);
3740 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa1);
3742 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
3744 if ((l2e & ATTR_DESCR_VALID) == 0) {
3748 pa = l2e & ~ATTR_MASK;
3749 m = PHYS_TO_VM_PAGE(pa);
3750 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
3752 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
3753 l++, sva += L3_SIZE) {
3755 if ((l3e & ATTR_DESCR_VALID) == 0)
3757 panic("%s: l3e found for va %jx\n",
3761 vm_page_unwire_noq(m1);
3762 vm_page_unwire_noq(m);
3763 pmap_resident_count_dec(pmap, 1);
3768 vm_page_unwire_noq(m0);
3769 pmap_resident_count_dec(pmap, 1);
3774 pmap_resident_count_dec(pmap, 1);
3776 pmap_clear(&pmap->pm_l0[i]);
3779 KASSERT(pmap->pm_stats.resident_count == 0,
3780 ("Invalid resident count %jd", pmap->pm_stats.resident_count));
3786 * Insert the given physical page (p) at
3787 * the specified virtual address (v) in the
3788 * target physical map with the protection requested.
3790 * If specified, the page will be wired down, meaning
3791 * that the related pte can not be reclaimed.
3793 * NB: This is the only routine which MAY NOT lazy-evaluate
3794 * or lose information. That is, this routine must actually
3795 * insert this page into the given map NOW.
3798 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3799 u_int flags, int8_t psind)
3801 struct rwlock *lock;
3803 pt_entry_t new_l3, orig_l3;
3804 pt_entry_t *l2, *l3;
3811 va = trunc_page(va);
3812 if ((m->oflags & VPO_UNMANAGED) == 0)
3813 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3814 pa = VM_PAGE_TO_PHYS(m);
3815 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE);
3816 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
3817 new_l3 |= pmap_pte_prot(pmap, prot);
3819 if ((flags & PMAP_ENTER_WIRED) != 0)
3820 new_l3 |= ATTR_SW_WIRED;
3821 if (pmap->pm_stage == PM_STAGE1) {
3822 if (va < VM_MAXUSER_ADDRESS)
3823 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3825 new_l3 |= ATTR_S1_UXN;
3826 if (pmap != kernel_pmap)
3827 new_l3 |= ATTR_S1_nG;
3830 * Clear the access flag on executable mappings, this will be
3831 * set later when the page is accessed. The fault handler is
3832 * required to invalidate the I-cache.
3834 * TODO: Switch to the valid flag to allow hardware management
3835 * of the access flag. Much of the pmap code assumes the
3836 * valid flag is set and fails to destroy the old page tables
3837 * correctly if it is clear.
3839 if (prot & VM_PROT_EXECUTE)
3842 if ((m->oflags & VPO_UNMANAGED) == 0) {
3843 new_l3 |= ATTR_SW_MANAGED;
3844 if ((prot & VM_PROT_WRITE) != 0) {
3845 new_l3 |= ATTR_SW_DBM;
3846 if ((flags & VM_PROT_WRITE) == 0) {
3847 if (pmap->pm_stage == PM_STAGE1)
3848 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3851 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
3856 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3860 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
3861 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
3862 ("managed largepage va %#lx flags %#x", va, flags));
3866 else /* (psind == 1) */
3868 rv = pmap_enter_largepage(pmap, va, new_l3, flags, psind);
3872 /* Assert the required virtual and physical alignment. */
3873 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3874 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3875 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3882 * In the case that a page table page is not
3883 * resident, we are creating it here.
3886 pde = pmap_pde(pmap, va, &lvl);
3887 if (pde != NULL && lvl == 2) {
3888 l3 = pmap_l2_to_l3(pde, va);
3889 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3890 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3894 } else if (pde != NULL && lvl == 1) {
3895 l2 = pmap_l1_to_l2(pde, va);
3896 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3897 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3898 l3 = &l3[pmap_l3_index(va)];
3899 if (va < VM_MAXUSER_ADDRESS) {
3900 mpte = PHYS_TO_VM_PAGE(
3901 pmap_load(l2) & ~ATTR_MASK);
3906 /* We need to allocate an L3 table. */
3908 if (va < VM_MAXUSER_ADDRESS) {
3909 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3912 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3913 * to handle the possibility that a superpage mapping for "va"
3914 * was created while we slept.
3916 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3917 nosleep ? NULL : &lock);
3918 if (mpte == NULL && nosleep) {
3919 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3920 rv = KERN_RESOURCE_SHORTAGE;
3925 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3928 orig_l3 = pmap_load(l3);
3929 opa = orig_l3 & ~ATTR_MASK;
3933 * Is the specified virtual address already mapped?
3935 if (pmap_l3_valid(orig_l3)) {
3937 * Only allow adding new entries on stage 2 tables for now.
3938 * This simplifies cache invalidation as we may need to call
3939 * into EL2 to perform such actions.
3941 PMAP_ASSERT_STAGE1(pmap);
3943 * Wiring change, just update stats. We don't worry about
3944 * wiring PT pages as they remain resident as long as there
3945 * are valid mappings in them. Hence, if a user page is wired,
3946 * the PT page will be also.
3948 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3949 (orig_l3 & ATTR_SW_WIRED) == 0)
3950 pmap->pm_stats.wired_count++;
3951 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3952 (orig_l3 & ATTR_SW_WIRED) != 0)
3953 pmap->pm_stats.wired_count--;
3956 * Remove the extra PT page reference.
3960 KASSERT(mpte->ref_count > 0,
3961 ("pmap_enter: missing reference to page table page,"
3966 * Has the physical page changed?
3970 * No, might be a protection or wiring change.
3972 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3973 (new_l3 & ATTR_SW_DBM) != 0)
3974 vm_page_aflag_set(m, PGA_WRITEABLE);
3979 * The physical page has changed. Temporarily invalidate
3982 orig_l3 = pmap_load_clear(l3);
3983 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3984 ("pmap_enter: unexpected pa update for %#lx", va));
3985 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3986 om = PHYS_TO_VM_PAGE(opa);
3989 * The pmap lock is sufficient to synchronize with
3990 * concurrent calls to pmap_page_test_mappings() and
3991 * pmap_ts_referenced().
3993 if (pmap_pte_dirty(pmap, orig_l3))
3995 if ((orig_l3 & ATTR_AF) != 0) {
3996 pmap_invalidate_page(pmap, va);
3997 vm_page_aflag_set(om, PGA_REFERENCED);
3999 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4000 pv = pmap_pvh_remove(&om->md, pmap, va);
4001 if ((m->oflags & VPO_UNMANAGED) != 0)
4002 free_pv_entry(pmap, pv);
4003 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
4004 TAILQ_EMPTY(&om->md.pv_list) &&
4005 ((om->flags & PG_FICTITIOUS) != 0 ||
4006 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4007 vm_page_aflag_clear(om, PGA_WRITEABLE);
4009 KASSERT((orig_l3 & ATTR_AF) != 0,
4010 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
4011 pmap_invalidate_page(pmap, va);
4016 * Increment the counters.
4018 if ((new_l3 & ATTR_SW_WIRED) != 0)
4019 pmap->pm_stats.wired_count++;
4020 pmap_resident_count_inc(pmap, 1);
4023 * Enter on the PV list if part of our managed memory.
4025 if ((m->oflags & VPO_UNMANAGED) == 0) {
4027 pv = get_pv_entry(pmap, &lock);
4030 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4031 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4033 if ((new_l3 & ATTR_SW_DBM) != 0)
4034 vm_page_aflag_set(m, PGA_WRITEABLE);
4038 if (pmap->pm_stage == PM_STAGE1) {
4040 * Sync icache if exec permission and attribute
4041 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
4042 * is stored and made valid for hardware table walk. If done
4043 * later, then other can access this page before caches are
4044 * properly synced. Don't do it for kernel memory which is
4045 * mapped with exec permission even if the memory isn't going
4046 * to hold executable code. The only time when icache sync is
4047 * needed is after kernel module is loaded and the relocation
4048 * info is processed. And it's done in elf_cpu_load_file().
4050 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4051 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
4052 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
4053 PMAP_ASSERT_STAGE1(pmap);
4054 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4057 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4061 * Update the L3 entry
4063 if (pmap_l3_valid(orig_l3)) {
4064 PMAP_ASSERT_STAGE1(pmap);
4065 KASSERT(opa == pa, ("pmap_enter: invalid update"));
4066 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
4067 /* same PA, different attributes */
4068 orig_l3 = pmap_load_store(l3, new_l3);
4069 pmap_invalidate_page(pmap, va);
4070 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4071 pmap_pte_dirty(pmap, orig_l3))
4076 * This can happens if multiple threads simultaneously
4077 * access not yet mapped page. This bad for performance
4078 * since this can cause full demotion-NOP-promotion
4080 * Another possible reasons are:
4081 * - VM and pmap memory layout are diverged
4082 * - tlb flush is missing somewhere and CPU doesn't see
4085 CTR4(KTR_PMAP, "%s: already mapped page - "
4086 "pmap %p va 0x%#lx pte 0x%lx",
4087 __func__, pmap, va, new_l3);
4091 pmap_store(l3, new_l3);
4095 #if VM_NRESERVLEVEL > 0
4097 * Try to promote from level 3 pages to a level 2 superpage. This
4098 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at
4099 * stage 1 specific fields and performs a break-before-make sequence
4100 * that is incorrect a stage 2 pmap.
4102 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
4103 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 &&
4104 (m->flags & PG_FICTITIOUS) == 0 &&
4105 vm_reserv_level_iffullpop(m) == 0) {
4106 pmap_promote_l2(pmap, pde, va, &lock);
4119 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
4120 * if successful. Returns false if (1) a page table page cannot be allocated
4121 * without sleeping, (2) a mapping already exists at the specified virtual
4122 * address, or (3) a PV entry cannot be allocated without reclaiming another
4126 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4127 struct rwlock **lockp)
4131 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4132 PMAP_ASSERT_STAGE1(pmap);
4134 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
4135 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
4137 if ((m->oflags & VPO_UNMANAGED) == 0) {
4138 new_l2 |= ATTR_SW_MANAGED;
4141 if ((prot & VM_PROT_EXECUTE) == 0 ||
4142 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4143 new_l2 |= ATTR_S1_XN;
4144 if (va < VM_MAXUSER_ADDRESS)
4145 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4147 new_l2 |= ATTR_S1_UXN;
4148 if (pmap != kernel_pmap)
4149 new_l2 |= ATTR_S1_nG;
4150 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
4151 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
4156 * Returns true if every page table entry in the specified page table is
4160 pmap_every_pte_zero(vm_paddr_t pa)
4162 pt_entry_t *pt_end, *pte;
4164 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
4165 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
4166 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
4174 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
4175 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
4176 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
4177 * a mapping already exists at the specified virtual address. Returns
4178 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
4179 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
4180 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
4182 * The parameter "m" is only used when creating a managed, writeable mapping.
4185 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
4186 vm_page_t m, struct rwlock **lockp)
4188 struct spglist free;
4189 pd_entry_t *l2, old_l2;
4192 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4194 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
4195 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
4196 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
4198 return (KERN_RESOURCE_SHORTAGE);
4202 * If there are existing mappings, either abort or remove them.
4204 if ((old_l2 = pmap_load(l2)) != 0) {
4205 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
4206 ("pmap_enter_l2: l2pg's ref count is too low"));
4207 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
4208 VM_MAXUSER_ADDRESS || (old_l2 & ATTR_DESCR_MASK) ==
4209 L2_BLOCK || !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
4212 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
4213 " in pmap %p", va, pmap);
4214 return (KERN_FAILURE);
4217 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
4218 (void)pmap_remove_l2(pmap, l2, va,
4219 pmap_load(pmap_l1(pmap, va)), &free, lockp);
4221 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
4223 if (va < VM_MAXUSER_ADDRESS) {
4224 vm_page_free_pages_toq(&free, true);
4225 KASSERT(pmap_load(l2) == 0,
4226 ("pmap_enter_l2: non-zero L2 entry %p", l2));
4228 KASSERT(SLIST_EMPTY(&free),
4229 ("pmap_enter_l2: freed kernel page table page"));
4232 * Both pmap_remove_l2() and pmap_remove_l3_range()
4233 * will leave the kernel page table page zero filled.
4234 * Nonetheless, the TLB could have an intermediate
4235 * entry for the kernel page table page.
4237 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
4238 if (pmap_insert_pt_page(pmap, mt, false))
4239 panic("pmap_enter_l2: trie insert failed");
4241 pmap_invalidate_page(pmap, va);
4245 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
4247 * Abort this mapping if its PV entry could not be created.
4249 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
4251 pmap_abort_ptp(pmap, va, l2pg);
4253 "pmap_enter_l2: failure for va %#lx in pmap %p",
4255 return (KERN_RESOURCE_SHORTAGE);
4257 if ((new_l2 & ATTR_SW_DBM) != 0)
4258 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4259 vm_page_aflag_set(mt, PGA_WRITEABLE);
4263 * Increment counters.
4265 if ((new_l2 & ATTR_SW_WIRED) != 0)
4266 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
4267 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
4270 * Map the superpage.
4272 pmap_store(l2, new_l2);
4275 atomic_add_long(&pmap_l2_mappings, 1);
4276 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
4279 return (KERN_SUCCESS);
4283 * Maps a sequence of resident pages belonging to the same object.
4284 * The sequence begins with the given page m_start. This page is
4285 * mapped at the given virtual address start. Each subsequent page is
4286 * mapped at a virtual address that is offset from start by the same
4287 * amount as the page is offset from m_start within the object. The
4288 * last page in the sequence is the page with the largest offset from
4289 * m_start that can be mapped at a virtual address less than the given
4290 * virtual address end. Not every virtual page between start and end
4291 * is mapped; only those for which a resident page exists with the
4292 * corresponding offset from m_start are mapped.
4295 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4296 vm_page_t m_start, vm_prot_t prot)
4298 struct rwlock *lock;
4301 vm_pindex_t diff, psize;
4303 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4305 psize = atop(end - start);
4310 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4311 va = start + ptoa(diff);
4312 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
4313 m->psind == 1 && pmap_ps_enabled(pmap) &&
4314 pmap_enter_2mpage(pmap, va, m, prot, &lock))
4315 m = &m[L2_SIZE / PAGE_SIZE - 1];
4317 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
4319 m = TAILQ_NEXT(m, listq);
4327 * this code makes some *MAJOR* assumptions:
4328 * 1. Current pmap & pmap exists.
4331 * 4. No page table pages.
4332 * but is *MUCH* faster than pmap_enter...
4336 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4338 struct rwlock *lock;
4342 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4349 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4350 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4353 pt_entry_t *l2, *l3, l3_val;
4357 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4358 (m->oflags & VPO_UNMANAGED) != 0,
4359 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4360 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4361 PMAP_ASSERT_STAGE1(pmap);
4363 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
4365 * In the case that a page table page is not
4366 * resident, we are creating it here.
4368 if (va < VM_MAXUSER_ADDRESS) {
4369 vm_pindex_t l2pindex;
4372 * Calculate pagetable page index
4374 l2pindex = pmap_l2_pindex(va);
4375 if (mpte && (mpte->pindex == l2pindex)) {
4381 pde = pmap_pde(pmap, va, &lvl);
4384 * If the page table page is mapped, we just increment
4385 * the hold count, and activate it. Otherwise, we
4386 * attempt to allocate a page table page. If this
4387 * attempt fails, we don't retry. Instead, we give up.
4390 l2 = pmap_l1_to_l2(pde, va);
4391 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
4395 if (lvl == 2 && pmap_load(pde) != 0) {
4397 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4401 * Pass NULL instead of the PV list lock
4402 * pointer, because we don't intend to sleep.
4404 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
4409 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4410 l3 = &l3[pmap_l3_index(va)];
4413 pde = pmap_pde(kernel_pmap, va, &lvl);
4414 KASSERT(pde != NULL,
4415 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
4418 ("pmap_enter_quick_locked: Invalid level %d", lvl));
4419 l3 = pmap_l2_to_l3(pde, va);
4423 * Abort if a mapping already exists.
4425 if (pmap_load(l3) != 0) {
4432 * Enter on the PV list if part of our managed memory.
4434 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4435 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4437 pmap_abort_ptp(pmap, va, mpte);
4442 * Increment counters
4444 pmap_resident_count_inc(pmap, 1);
4446 pa = VM_PAGE_TO_PHYS(m);
4447 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
4448 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
4449 if ((prot & VM_PROT_EXECUTE) == 0 ||
4450 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4451 l3_val |= ATTR_S1_XN;
4452 if (va < VM_MAXUSER_ADDRESS)
4453 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4455 l3_val |= ATTR_S1_UXN;
4456 if (pmap != kernel_pmap)
4457 l3_val |= ATTR_S1_nG;
4460 * Now validate mapping with RO protection
4462 if ((m->oflags & VPO_UNMANAGED) == 0) {
4463 l3_val |= ATTR_SW_MANAGED;
4467 /* Sync icache before the mapping is stored to PTE */
4468 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4469 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
4470 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4472 pmap_store(l3, l3_val);
4479 * This code maps large physical mmap regions into the
4480 * processor address space. Note that some shortcuts
4481 * are taken, but the code works.
4484 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4485 vm_pindex_t pindex, vm_size_t size)
4488 VM_OBJECT_ASSERT_WLOCKED(object);
4489 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4490 ("pmap_object_init_pt: non-device object"));
4494 * Clear the wired attribute from the mappings for the specified range of
4495 * addresses in the given pmap. Every valid mapping within that range
4496 * must have the wired attribute set. In contrast, invalid mappings
4497 * cannot have the wired attribute set, so they are ignored.
4499 * The wired attribute of the page table entry is not a hardware feature,
4500 * so there is no need to invalidate any TLB entries.
4503 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4505 vm_offset_t va_next;
4506 pd_entry_t *l0, *l1, *l2;
4510 for (; sva < eva; sva = va_next) {
4511 l0 = pmap_l0(pmap, sva);
4512 if (pmap_load(l0) == 0) {
4513 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4519 l1 = pmap_l0_to_l1(l0, sva);
4520 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4523 if (pmap_load(l1) == 0)
4526 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4527 KASSERT(va_next <= eva,
4528 ("partial update of non-transparent 1G page "
4529 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
4530 pmap_load(l1), sva, eva, va_next));
4531 MPASS(pmap != kernel_pmap);
4532 MPASS((pmap_load(l1) & (ATTR_SW_MANAGED |
4533 ATTR_SW_WIRED)) == ATTR_SW_WIRED);
4534 pmap_clear_bits(l1, ATTR_SW_WIRED);
4535 pmap->pm_stats.wired_count -= L1_SIZE / PAGE_SIZE;
4539 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4543 l2 = pmap_l1_to_l2(l1, sva);
4544 if (pmap_load(l2) == 0)
4547 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4548 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4549 panic("pmap_unwire: l2 %#jx is missing "
4550 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4553 * Are we unwiring the entire large page? If not,
4554 * demote the mapping and fall through.
4556 if (sva + L2_SIZE == va_next && eva >= va_next) {
4557 pmap_clear_bits(l2, ATTR_SW_WIRED);
4558 pmap->pm_stats.wired_count -= L2_SIZE /
4561 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4562 panic("pmap_unwire: demotion failed");
4564 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4565 ("pmap_unwire: Invalid l2 entry after demotion"));
4569 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4571 if (pmap_load(l3) == 0)
4573 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4574 panic("pmap_unwire: l3 %#jx is missing "
4575 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4578 * ATTR_SW_WIRED must be cleared atomically. Although
4579 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4580 * the System MMU may write to the entry concurrently.
4582 pmap_clear_bits(l3, ATTR_SW_WIRED);
4583 pmap->pm_stats.wired_count--;
4590 * Copy the range specified by src_addr/len
4591 * from the source map to the range dst_addr/len
4592 * in the destination map.
4594 * This routine is only advisory and need not do anything.
4596 * Because the executable mappings created by this routine are copied,
4597 * it should not have to flush the instruction cache.
4600 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4601 vm_offset_t src_addr)
4603 struct rwlock *lock;
4604 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4605 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4606 vm_offset_t addr, end_addr, va_next;
4607 vm_page_t dst_m, dstmpte, srcmpte;
4609 PMAP_ASSERT_STAGE1(dst_pmap);
4610 PMAP_ASSERT_STAGE1(src_pmap);
4612 if (dst_addr != src_addr)
4614 end_addr = src_addr + len;
4616 if (dst_pmap < src_pmap) {
4617 PMAP_LOCK(dst_pmap);
4618 PMAP_LOCK(src_pmap);
4620 PMAP_LOCK(src_pmap);
4621 PMAP_LOCK(dst_pmap);
4623 for (addr = src_addr; addr < end_addr; addr = va_next) {
4624 l0 = pmap_l0(src_pmap, addr);
4625 if (pmap_load(l0) == 0) {
4626 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4632 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4635 l1 = pmap_l0_to_l1(l0, addr);
4636 if (pmap_load(l1) == 0)
4638 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4639 KASSERT(va_next <= end_addr,
4640 ("partial update of non-transparent 1G page "
4641 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4642 pmap_load(l1), addr, end_addr, va_next));
4643 srcptepaddr = pmap_load(l1);
4644 l1 = pmap_l1(dst_pmap, addr);
4646 if (_pmap_alloc_l3(dst_pmap,
4647 pmap_l0_pindex(addr), NULL) == NULL)
4649 l1 = pmap_l1(dst_pmap, addr);
4651 l0 = pmap_l0(dst_pmap, addr);
4652 dst_m = PHYS_TO_VM_PAGE(pmap_load(l0) &
4656 KASSERT(pmap_load(l1) == 0,
4657 ("1G mapping present in dst pmap "
4658 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4659 pmap_load(l1), addr, end_addr, va_next));
4660 pmap_store(l1, srcptepaddr & ~ATTR_SW_WIRED);
4661 pmap_resident_count_inc(dst_pmap, L1_SIZE / PAGE_SIZE);
4665 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4668 l2 = pmap_l1_to_l2(l1, addr);
4669 srcptepaddr = pmap_load(l2);
4670 if (srcptepaddr == 0)
4672 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4673 if ((addr & L2_OFFSET) != 0 ||
4674 addr + L2_SIZE > end_addr)
4676 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_m, NULL);
4679 if (pmap_load(l2) == 0 &&
4680 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4681 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4682 PMAP_ENTER_NORECLAIM, &lock))) {
4683 mask = ATTR_AF | ATTR_SW_WIRED;
4685 if ((srcptepaddr & ATTR_SW_DBM) != 0)
4686 nbits |= ATTR_S1_AP_RW_BIT;
4687 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
4688 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4690 atomic_add_long(&pmap_l2_mappings, 1);
4692 pmap_abort_ptp(dst_pmap, addr, dst_m);
4695 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4696 ("pmap_copy: invalid L2 entry"));
4697 srcptepaddr &= ~ATTR_MASK;
4698 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4699 KASSERT(srcmpte->ref_count > 0,
4700 ("pmap_copy: source page table page is unused"));
4701 if (va_next > end_addr)
4703 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4704 src_pte = &src_pte[pmap_l3_index(addr)];
4706 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4707 ptetemp = pmap_load(src_pte);
4710 * We only virtual copy managed pages.
4712 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4715 if (dstmpte != NULL) {
4716 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4717 ("dstmpte pindex/addr mismatch"));
4718 dstmpte->ref_count++;
4719 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4722 dst_pte = (pt_entry_t *)
4723 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4724 dst_pte = &dst_pte[pmap_l3_index(addr)];
4725 if (pmap_load(dst_pte) == 0 &&
4726 pmap_try_insert_pv_entry(dst_pmap, addr,
4727 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4729 * Clear the wired, modified, and accessed
4730 * (referenced) bits during the copy.
4732 mask = ATTR_AF | ATTR_SW_WIRED;
4734 if ((ptetemp & ATTR_SW_DBM) != 0)
4735 nbits |= ATTR_S1_AP_RW_BIT;
4736 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4737 pmap_resident_count_inc(dst_pmap, 1);
4739 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4742 /* Have we copied all of the valid mappings? */
4743 if (dstmpte->ref_count >= srcmpte->ref_count)
4749 * XXX This barrier may not be needed because the destination pmap is
4756 PMAP_UNLOCK(src_pmap);
4757 PMAP_UNLOCK(dst_pmap);
4761 * pmap_zero_page zeros the specified hardware page by mapping
4762 * the page into KVM and using bzero to clear its contents.
4765 pmap_zero_page(vm_page_t m)
4767 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4769 pagezero((void *)va);
4773 * pmap_zero_page_area zeros the specified hardware page by mapping
4774 * the page into KVM and using bzero to clear its contents.
4776 * off and size may not cover an area beyond a single hardware page.
4779 pmap_zero_page_area(vm_page_t m, int off, int size)
4781 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4783 if (off == 0 && size == PAGE_SIZE)
4784 pagezero((void *)va);
4786 bzero((char *)va + off, size);
4790 * pmap_copy_page copies the specified (machine independent)
4791 * page by mapping the page into virtual memory and using
4792 * bcopy to copy the page, one machine dependent page at a
4796 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4798 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4799 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4801 pagecopy((void *)src, (void *)dst);
4804 int unmapped_buf_allowed = 1;
4807 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4808 vm_offset_t b_offset, int xfersize)
4812 vm_paddr_t p_a, p_b;
4813 vm_offset_t a_pg_offset, b_pg_offset;
4816 while (xfersize > 0) {
4817 a_pg_offset = a_offset & PAGE_MASK;
4818 m_a = ma[a_offset >> PAGE_SHIFT];
4819 p_a = m_a->phys_addr;
4820 b_pg_offset = b_offset & PAGE_MASK;
4821 m_b = mb[b_offset >> PAGE_SHIFT];
4822 p_b = m_b->phys_addr;
4823 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4824 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4825 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4826 panic("!DMAP a %lx", p_a);
4828 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4830 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4831 panic("!DMAP b %lx", p_b);
4833 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4835 bcopy(a_cp, b_cp, cnt);
4843 pmap_quick_enter_page(vm_page_t m)
4846 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4850 pmap_quick_remove_page(vm_offset_t addr)
4855 * Returns true if the pmap's pv is one of the first
4856 * 16 pvs linked to from this page. This count may
4857 * be changed upwards or downwards in the future; it
4858 * is only necessary that true be returned for a small
4859 * subset of pmaps for proper page aging.
4862 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4864 struct md_page *pvh;
4865 struct rwlock *lock;
4870 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4871 ("pmap_page_exists_quick: page %p is not managed", m));
4873 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4875 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4876 if (PV_PMAP(pv) == pmap) {
4884 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4885 pvh = page_to_pvh(m);
4886 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4887 if (PV_PMAP(pv) == pmap) {
4901 * pmap_page_wired_mappings:
4903 * Return the number of managed mappings to the given physical page
4907 pmap_page_wired_mappings(vm_page_t m)
4909 struct rwlock *lock;
4910 struct md_page *pvh;
4914 int count, lvl, md_gen, pvh_gen;
4916 if ((m->oflags & VPO_UNMANAGED) != 0)
4918 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4922 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4924 if (!PMAP_TRYLOCK(pmap)) {
4925 md_gen = m->md.pv_gen;
4929 if (md_gen != m->md.pv_gen) {
4934 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4935 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4939 if ((m->flags & PG_FICTITIOUS) == 0) {
4940 pvh = page_to_pvh(m);
4941 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4943 if (!PMAP_TRYLOCK(pmap)) {
4944 md_gen = m->md.pv_gen;
4945 pvh_gen = pvh->pv_gen;
4949 if (md_gen != m->md.pv_gen ||
4950 pvh_gen != pvh->pv_gen) {
4955 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4957 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4967 * Returns true if the given page is mapped individually or as part of
4968 * a 2mpage. Otherwise, returns false.
4971 pmap_page_is_mapped(vm_page_t m)
4973 struct rwlock *lock;
4976 if ((m->oflags & VPO_UNMANAGED) != 0)
4978 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4980 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4981 ((m->flags & PG_FICTITIOUS) == 0 &&
4982 !TAILQ_EMPTY(&page_to_pvh(m)->pv_list));
4988 * Destroy all managed, non-wired mappings in the given user-space
4989 * pmap. This pmap cannot be active on any processor besides the
4992 * This function cannot be applied to the kernel pmap. Moreover, it
4993 * is not intended for general use. It is only to be used during
4994 * process termination. Consequently, it can be implemented in ways
4995 * that make it faster than pmap_remove(). First, it can more quickly
4996 * destroy mappings by iterating over the pmap's collection of PV
4997 * entries, rather than searching the page table. Second, it doesn't
4998 * have to test and clear the page table entries atomically, because
4999 * no processor is currently accessing the user address space. In
5000 * particular, a page table entry's dirty bit won't change state once
5001 * this function starts.
5004 pmap_remove_pages(pmap_t pmap)
5007 pt_entry_t *pte, tpte;
5008 struct spglist free;
5009 vm_page_t m, ml3, mt;
5011 struct md_page *pvh;
5012 struct pv_chunk *pc, *npc;
5013 struct rwlock *lock;
5015 uint64_t inuse, bitmask;
5016 int allfree, field, freed, idx, lvl;
5023 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5026 for (field = 0; field < _NPCM; field++) {
5027 inuse = ~pc->pc_map[field] & pc_freemask[field];
5028 while (inuse != 0) {
5029 bit = ffsl(inuse) - 1;
5030 bitmask = 1UL << bit;
5031 idx = field * 64 + bit;
5032 pv = &pc->pc_pventry[idx];
5035 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5036 KASSERT(pde != NULL,
5037 ("Attempting to remove an unmapped page"));
5041 pte = pmap_l1_to_l2(pde, pv->pv_va);
5042 tpte = pmap_load(pte);
5043 KASSERT((tpte & ATTR_DESCR_MASK) ==
5045 ("Attempting to remove an invalid "
5046 "block: %lx", tpte));
5049 pte = pmap_l2_to_l3(pde, pv->pv_va);
5050 tpte = pmap_load(pte);
5051 KASSERT((tpte & ATTR_DESCR_MASK) ==
5053 ("Attempting to remove an invalid "
5054 "page: %lx", tpte));
5058 "Invalid page directory level: %d",
5063 * We cannot remove wired pages from a process' mapping at this time
5065 if (tpte & ATTR_SW_WIRED) {
5070 pa = tpte & ~ATTR_MASK;
5072 m = PHYS_TO_VM_PAGE(pa);
5073 KASSERT(m->phys_addr == pa,
5074 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5075 m, (uintmax_t)m->phys_addr,
5078 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5079 m < &vm_page_array[vm_page_array_size],
5080 ("pmap_remove_pages: bad pte %#jx",
5084 * Because this pmap is not active on other
5085 * processors, the dirty bit cannot have
5086 * changed state since we last loaded pte.
5091 * Update the vm_page_t clean/reference bits.
5093 if (pmap_pte_dirty(pmap, tpte)) {
5096 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5105 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5108 pc->pc_map[field] |= bitmask;
5111 pmap_resident_count_dec(pmap,
5112 L2_SIZE / PAGE_SIZE);
5113 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
5114 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
5116 if (TAILQ_EMPTY(&pvh->pv_list)) {
5117 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5118 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
5119 TAILQ_EMPTY(&mt->md.pv_list))
5120 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5122 ml3 = pmap_remove_pt_page(pmap,
5125 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
5126 ("pmap_remove_pages: l3 page not promoted"));
5127 pmap_resident_count_dec(pmap,1);
5128 KASSERT(ml3->ref_count == NL3PG,
5129 ("pmap_remove_pages: l3 page ref count error"));
5131 pmap_add_delayed_free_list(ml3,
5136 pmap_resident_count_dec(pmap, 1);
5137 TAILQ_REMOVE(&m->md.pv_list, pv,
5140 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
5141 TAILQ_EMPTY(&m->md.pv_list) &&
5142 (m->flags & PG_FICTITIOUS) == 0) {
5143 pvh = page_to_pvh(m);
5144 if (TAILQ_EMPTY(&pvh->pv_list))
5145 vm_page_aflag_clear(m,
5150 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
5155 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5156 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5157 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5159 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5165 pmap_invalidate_all(pmap);
5167 vm_page_free_pages_toq(&free, true);
5171 * This is used to check if a page has been accessed or modified.
5174 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5176 struct rwlock *lock;
5178 struct md_page *pvh;
5179 pt_entry_t *pte, mask, value;
5181 int lvl, md_gen, pvh_gen;
5185 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5188 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5190 PMAP_ASSERT_STAGE1(pmap);
5191 if (!PMAP_TRYLOCK(pmap)) {
5192 md_gen = m->md.pv_gen;
5196 if (md_gen != m->md.pv_gen) {
5201 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5203 ("pmap_page_test_mappings: Invalid level %d", lvl));
5207 mask |= ATTR_S1_AP_RW_BIT;
5208 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5211 mask |= ATTR_AF | ATTR_DESCR_MASK;
5212 value |= ATTR_AF | L3_PAGE;
5214 rv = (pmap_load(pte) & mask) == value;
5219 if ((m->flags & PG_FICTITIOUS) == 0) {
5220 pvh = page_to_pvh(m);
5221 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5223 PMAP_ASSERT_STAGE1(pmap);
5224 if (!PMAP_TRYLOCK(pmap)) {
5225 md_gen = m->md.pv_gen;
5226 pvh_gen = pvh->pv_gen;
5230 if (md_gen != m->md.pv_gen ||
5231 pvh_gen != pvh->pv_gen) {
5236 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5238 ("pmap_page_test_mappings: Invalid level %d", lvl));
5242 mask |= ATTR_S1_AP_RW_BIT;
5243 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5246 mask |= ATTR_AF | ATTR_DESCR_MASK;
5247 value |= ATTR_AF | L2_BLOCK;
5249 rv = (pmap_load(pte) & mask) == value;
5263 * Return whether or not the specified physical page was modified
5264 * in any physical maps.
5267 pmap_is_modified(vm_page_t m)
5270 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5271 ("pmap_is_modified: page %p is not managed", m));
5274 * If the page is not busied then this check is racy.
5276 if (!pmap_page_is_write_mapped(m))
5278 return (pmap_page_test_mappings(m, FALSE, TRUE));
5282 * pmap_is_prefaultable:
5284 * Return whether or not the specified virtual address is eligible
5288 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5296 pte = pmap_pte(pmap, addr, &lvl);
5297 if (pte != NULL && pmap_load(pte) != 0) {
5305 * pmap_is_referenced:
5307 * Return whether or not the specified physical page was referenced
5308 * in any physical maps.
5311 pmap_is_referenced(vm_page_t m)
5314 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5315 ("pmap_is_referenced: page %p is not managed", m));
5316 return (pmap_page_test_mappings(m, TRUE, FALSE));
5320 * Clear the write and modified bits in each of the given page's mappings.
5323 pmap_remove_write(vm_page_t m)
5325 struct md_page *pvh;
5327 struct rwlock *lock;
5328 pv_entry_t next_pv, pv;
5329 pt_entry_t oldpte, *pte;
5331 int lvl, md_gen, pvh_gen;
5333 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5334 ("pmap_remove_write: page %p is not managed", m));
5335 vm_page_assert_busied(m);
5337 if (!pmap_page_is_write_mapped(m))
5339 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5340 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5343 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5345 PMAP_ASSERT_STAGE1(pmap);
5346 if (!PMAP_TRYLOCK(pmap)) {
5347 pvh_gen = pvh->pv_gen;
5351 if (pvh_gen != pvh->pv_gen) {
5358 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5359 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
5360 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
5361 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5362 ("inconsistent pv lock %p %p for page %p",
5363 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5366 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5368 PMAP_ASSERT_STAGE1(pmap);
5369 if (!PMAP_TRYLOCK(pmap)) {
5370 pvh_gen = pvh->pv_gen;
5371 md_gen = m->md.pv_gen;
5375 if (pvh_gen != pvh->pv_gen ||
5376 md_gen != m->md.pv_gen) {
5382 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5383 oldpte = pmap_load(pte);
5385 if ((oldpte & ATTR_SW_DBM) != 0) {
5386 if (!atomic_fcmpset_long(pte, &oldpte,
5387 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
5389 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
5390 ATTR_S1_AP(ATTR_S1_AP_RW))
5392 pmap_invalidate_page(pmap, pv->pv_va);
5397 vm_page_aflag_clear(m, PGA_WRITEABLE);
5401 * pmap_ts_referenced:
5403 * Return a count of reference bits for a page, clearing those bits.
5404 * It is not necessary for every reference bit to be cleared, but it
5405 * is necessary that 0 only be returned when there are truly no
5406 * reference bits set.
5408 * As an optimization, update the page's dirty field if a modified bit is
5409 * found while counting reference bits. This opportunistic update can be
5410 * performed at low cost and can eliminate the need for some future calls
5411 * to pmap_is_modified(). However, since this function stops after
5412 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5413 * dirty pages. Those dirty pages will only be detected by a future call
5414 * to pmap_is_modified().
5417 pmap_ts_referenced(vm_page_t m)
5419 struct md_page *pvh;
5422 struct rwlock *lock;
5423 pd_entry_t *pde, tpde;
5424 pt_entry_t *pte, tpte;
5427 int cleared, lvl, md_gen, not_cleared, pvh_gen;
5428 struct spglist free;
5430 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5431 ("pmap_ts_referenced: page %p is not managed", m));
5434 pa = VM_PAGE_TO_PHYS(m);
5435 lock = PHYS_TO_PV_LIST_LOCK(pa);
5436 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5440 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5441 goto small_mappings;
5447 if (!PMAP_TRYLOCK(pmap)) {
5448 pvh_gen = pvh->pv_gen;
5452 if (pvh_gen != pvh->pv_gen) {
5458 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5459 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
5461 ("pmap_ts_referenced: invalid pde level %d", lvl));
5462 tpde = pmap_load(pde);
5463 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
5464 ("pmap_ts_referenced: found an invalid l1 table"));
5465 pte = pmap_l1_to_l2(pde, pv->pv_va);
5466 tpte = pmap_load(pte);
5467 if (pmap_pte_dirty(pmap, tpte)) {
5469 * Although "tpte" is mapping a 2MB page, because
5470 * this function is called at a 4KB page granularity,
5471 * we only update the 4KB page under test.
5476 if ((tpte & ATTR_AF) != 0) {
5478 * Since this reference bit is shared by 512 4KB pages,
5479 * it should not be cleared every time it is tested.
5480 * Apply a simple "hash" function on the physical page
5481 * number, the virtual superpage number, and the pmap
5482 * address to select one 4KB page out of the 512 on
5483 * which testing the reference bit will result in
5484 * clearing that reference bit. This function is
5485 * designed to avoid the selection of the same 4KB page
5486 * for every 2MB page mapping.
5488 * On demotion, a mapping that hasn't been referenced
5489 * is simply destroyed. To avoid the possibility of a
5490 * subsequent page fault on a demoted wired mapping,
5491 * always leave its reference bit set. Moreover,
5492 * since the superpage is wired, the current state of
5493 * its reference bit won't affect page replacement.
5495 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
5496 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
5497 (tpte & ATTR_SW_WIRED) == 0) {
5498 pmap_clear_bits(pte, ATTR_AF);
5499 pmap_invalidate_page(pmap, pv->pv_va);
5505 /* Rotate the PV list if it has more than one entry. */
5506 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5507 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5508 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5511 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5513 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5515 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5522 if (!PMAP_TRYLOCK(pmap)) {
5523 pvh_gen = pvh->pv_gen;
5524 md_gen = m->md.pv_gen;
5528 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5533 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5534 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
5536 ("pmap_ts_referenced: invalid pde level %d", lvl));
5537 tpde = pmap_load(pde);
5538 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
5539 ("pmap_ts_referenced: found an invalid l2 table"));
5540 pte = pmap_l2_to_l3(pde, pv->pv_va);
5541 tpte = pmap_load(pte);
5542 if (pmap_pte_dirty(pmap, tpte))
5544 if ((tpte & ATTR_AF) != 0) {
5545 if ((tpte & ATTR_SW_WIRED) == 0) {
5546 pmap_clear_bits(pte, ATTR_AF);
5547 pmap_invalidate_page(pmap, pv->pv_va);
5553 /* Rotate the PV list if it has more than one entry. */
5554 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5555 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5556 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5559 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5560 not_cleared < PMAP_TS_REFERENCED_MAX);
5563 vm_page_free_pages_toq(&free, true);
5564 return (cleared + not_cleared);
5568 * Apply the given advice to the specified range of addresses within the
5569 * given pmap. Depending on the advice, clear the referenced and/or
5570 * modified flags in each mapping and set the mapped page's dirty field.
5573 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5575 struct rwlock *lock;
5576 vm_offset_t va, va_next;
5578 pd_entry_t *l0, *l1, *l2, oldl2;
5579 pt_entry_t *l3, oldl3;
5581 PMAP_ASSERT_STAGE1(pmap);
5583 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5587 for (; sva < eva; sva = va_next) {
5588 l0 = pmap_l0(pmap, sva);
5589 if (pmap_load(l0) == 0) {
5590 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5596 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5599 l1 = pmap_l0_to_l1(l0, sva);
5600 if (pmap_load(l1) == 0)
5602 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
5603 KASSERT(va_next <= eva,
5604 ("partial update of non-transparent 1G page "
5605 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
5606 pmap_load(l1), sva, eva, va_next));
5610 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5613 l2 = pmap_l1_to_l2(l1, sva);
5614 oldl2 = pmap_load(l2);
5617 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5618 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5621 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5626 * The 2MB page mapping was destroyed.
5632 * Unless the page mappings are wired, remove the
5633 * mapping to a single page so that a subsequent
5634 * access may repromote. Choosing the last page
5635 * within the address range [sva, min(va_next, eva))
5636 * generally results in more repromotions. Since the
5637 * underlying page table page is fully populated, this
5638 * removal never frees a page table page.
5640 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5646 ("pmap_advise: no address gap"));
5647 l3 = pmap_l2_to_l3(l2, va);
5648 KASSERT(pmap_load(l3) != 0,
5649 ("pmap_advise: invalid PTE"));
5650 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5656 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5657 ("pmap_advise: invalid L2 entry after demotion"));
5661 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5663 oldl3 = pmap_load(l3);
5664 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5665 (ATTR_SW_MANAGED | L3_PAGE))
5667 else if (pmap_pte_dirty(pmap, oldl3)) {
5668 if (advice == MADV_DONTNEED) {
5670 * Future calls to pmap_is_modified()
5671 * can be avoided by making the page
5674 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5677 while (!atomic_fcmpset_long(l3, &oldl3,
5678 (oldl3 & ~ATTR_AF) |
5679 ATTR_S1_AP(ATTR_S1_AP_RO)))
5681 } else if ((oldl3 & ATTR_AF) != 0)
5682 pmap_clear_bits(l3, ATTR_AF);
5689 if (va != va_next) {
5690 pmap_invalidate_range(pmap, va, sva);
5695 pmap_invalidate_range(pmap, va, sva);
5701 * Clear the modify bits on the specified physical page.
5704 pmap_clear_modify(vm_page_t m)
5706 struct md_page *pvh;
5707 struct rwlock *lock;
5709 pv_entry_t next_pv, pv;
5710 pd_entry_t *l2, oldl2;
5711 pt_entry_t *l3, oldl3;
5713 int md_gen, pvh_gen;
5715 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5716 ("pmap_clear_modify: page %p is not managed", m));
5717 vm_page_assert_busied(m);
5719 if (!pmap_page_is_write_mapped(m))
5721 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5722 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5725 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5727 PMAP_ASSERT_STAGE1(pmap);
5728 if (!PMAP_TRYLOCK(pmap)) {
5729 pvh_gen = pvh->pv_gen;
5733 if (pvh_gen != pvh->pv_gen) {
5739 l2 = pmap_l2(pmap, va);
5740 oldl2 = pmap_load(l2);
5741 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5742 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5743 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5744 (oldl2 & ATTR_SW_WIRED) == 0) {
5746 * Write protect the mapping to a single page so that
5747 * a subsequent write access may repromote.
5749 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5750 l3 = pmap_l2_to_l3(l2, va);
5751 oldl3 = pmap_load(l3);
5752 while (!atomic_fcmpset_long(l3, &oldl3,
5753 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
5756 pmap_invalidate_page(pmap, va);
5760 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5762 PMAP_ASSERT_STAGE1(pmap);
5763 if (!PMAP_TRYLOCK(pmap)) {
5764 md_gen = m->md.pv_gen;
5765 pvh_gen = pvh->pv_gen;
5769 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5774 l2 = pmap_l2(pmap, pv->pv_va);
5775 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5776 oldl3 = pmap_load(l3);
5777 if (pmap_l3_valid(oldl3) &&
5778 (oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
5779 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
5780 pmap_invalidate_page(pmap, pv->pv_va);
5788 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5790 struct pmap_preinit_mapping *ppim;
5791 vm_offset_t va, offset;
5794 int i, lvl, l2_blocks, free_l2_count, start_idx;
5796 if (!vm_initialized) {
5798 * No L3 ptables so map entire L2 blocks where start VA is:
5799 * preinit_map_va + start_idx * L2_SIZE
5800 * There may be duplicate mappings (multiple VA -> same PA) but
5801 * ARM64 dcache is always PIPT so that's acceptable.
5806 /* Calculate how many L2 blocks are needed for the mapping */
5807 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5808 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5810 offset = pa & L2_OFFSET;
5812 if (preinit_map_va == 0)
5815 /* Map 2MiB L2 blocks from reserved VA space */
5819 /* Find enough free contiguous VA space */
5820 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5821 ppim = pmap_preinit_mapping + i;
5822 if (free_l2_count > 0 && ppim->pa != 0) {
5823 /* Not enough space here */
5829 if (ppim->pa == 0) {
5831 if (start_idx == -1)
5834 if (free_l2_count == l2_blocks)
5838 if (free_l2_count != l2_blocks)
5839 panic("%s: too many preinit mappings", __func__);
5841 va = preinit_map_va + (start_idx * L2_SIZE);
5842 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5843 /* Mark entries as allocated */
5844 ppim = pmap_preinit_mapping + i;
5846 ppim->va = va + offset;
5851 pa = rounddown2(pa, L2_SIZE);
5852 for (i = 0; i < l2_blocks; i++) {
5853 pde = pmap_pde(kernel_pmap, va, &lvl);
5854 KASSERT(pde != NULL,
5855 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5858 ("pmap_mapbios: Invalid level %d", lvl));
5860 /* Insert L2_BLOCK */
5861 l2 = pmap_l1_to_l2(pde, va);
5863 pa | ATTR_DEFAULT | ATTR_S1_XN |
5864 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5869 pmap_invalidate_all(kernel_pmap);
5871 va = preinit_map_va + (start_idx * L2_SIZE);
5874 /* kva_alloc may be used to map the pages */
5875 offset = pa & PAGE_MASK;
5876 size = round_page(offset + size);
5878 va = kva_alloc(size);
5880 panic("%s: Couldn't allocate KVA", __func__);
5882 pde = pmap_pde(kernel_pmap, va, &lvl);
5883 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5885 /* L3 table is linked */
5886 va = trunc_page(va);
5887 pa = trunc_page(pa);
5888 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
5891 return ((void *)(va + offset));
5895 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5897 struct pmap_preinit_mapping *ppim;
5898 vm_offset_t offset, tmpsize, va_trunc;
5901 int i, lvl, l2_blocks, block;
5905 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5906 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5908 /* Remove preinit mapping */
5909 preinit_map = false;
5911 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5912 ppim = pmap_preinit_mapping + i;
5913 if (ppim->va == va) {
5914 KASSERT(ppim->size == size,
5915 ("pmap_unmapbios: size mismatch"));
5920 offset = block * L2_SIZE;
5921 va_trunc = rounddown2(va, L2_SIZE) + offset;
5923 /* Remove L2_BLOCK */
5924 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5925 KASSERT(pde != NULL,
5926 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5928 l2 = pmap_l1_to_l2(pde, va_trunc);
5931 if (block == (l2_blocks - 1))
5937 pmap_invalidate_all(kernel_pmap);
5941 /* Unmap the pages reserved with kva_alloc. */
5942 if (vm_initialized) {
5943 offset = va & PAGE_MASK;
5944 size = round_page(offset + size);
5945 va = trunc_page(va);
5947 pde = pmap_pde(kernel_pmap, va, &lvl);
5948 KASSERT(pde != NULL,
5949 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5950 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5952 /* Unmap and invalidate the pages */
5953 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5954 pmap_kremove(va + tmpsize);
5961 * Sets the memory attribute for the specified page.
5964 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5967 m->md.pv_memattr = ma;
5970 * If "m" is a normal page, update its direct mapping. This update
5971 * can be relied upon to perform any cache operations that are
5972 * required for data coherence.
5974 if ((m->flags & PG_FICTITIOUS) == 0 &&
5975 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5976 m->md.pv_memattr) != 0)
5977 panic("memory attribute change on the direct map failed");
5981 * Changes the specified virtual address range's memory type to that given by
5982 * the parameter "mode". The specified virtual address range must be
5983 * completely contained within either the direct map or the kernel map. If
5984 * the virtual address range is contained within the kernel map, then the
5985 * memory type for each of the corresponding ranges of the direct map is also
5986 * changed. (The corresponding ranges of the direct map are those ranges that
5987 * map the same physical pages as the specified virtual address range.) These
5988 * changes to the direct map are necessary because Intel describes the
5989 * behavior of their processors as "undefined" if two or more mappings to the
5990 * same physical page have different memory types.
5992 * Returns zero if the change completed successfully, and either EINVAL or
5993 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5994 * of the virtual address range was not mapped, and ENOMEM is returned if
5995 * there was insufficient memory available to complete the change. In the
5996 * latter case, the memory type may have been changed on some part of the
5997 * virtual address range or the direct map.
6000 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6004 PMAP_LOCK(kernel_pmap);
6005 error = pmap_change_attr_locked(va, size, mode);
6006 PMAP_UNLOCK(kernel_pmap);
6011 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6013 vm_offset_t base, offset, tmpva;
6014 pt_entry_t l3, *pte, *newpte;
6017 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6018 base = trunc_page(va);
6019 offset = va & PAGE_MASK;
6020 size = round_page(offset + size);
6022 if (!VIRT_IN_DMAP(base) &&
6023 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
6026 for (tmpva = base; tmpva < base + size; ) {
6027 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
6031 if ((pmap_load(pte) & ATTR_S1_IDX_MASK) == ATTR_S1_IDX(mode)) {
6033 * We already have the correct attribute,
6034 * ignore this entry.
6038 panic("Invalid DMAP table level: %d\n", lvl);
6040 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
6043 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
6051 * Split the entry to an level 3 table, then
6052 * set the new attribute.
6056 panic("Invalid DMAP table level: %d\n", lvl);
6058 newpte = pmap_demote_l1(kernel_pmap, pte,
6059 tmpva & ~L1_OFFSET);
6062 pte = pmap_l1_to_l2(pte, tmpva);
6064 newpte = pmap_demote_l2(kernel_pmap, pte,
6068 pte = pmap_l2_to_l3(pte, tmpva);
6070 /* Update the entry */
6071 l3 = pmap_load(pte);
6072 l3 &= ~ATTR_S1_IDX_MASK;
6073 l3 |= ATTR_S1_IDX(mode);
6074 if (mode == VM_MEMATTR_DEVICE)
6077 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
6081 * If moving to a non-cacheable entry flush
6084 if (mode == VM_MEMATTR_UNCACHEABLE)
6085 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
6097 * Create an L2 table to map all addresses within an L1 mapping.
6100 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
6102 pt_entry_t *l2, newl2, oldl1;
6104 vm_paddr_t l2phys, phys;
6108 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6109 oldl1 = pmap_load(l1);
6110 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
6111 ("pmap_demote_l1: Demoting a non-block entry"));
6112 KASSERT((va & L1_OFFSET) == 0,
6113 ("pmap_demote_l1: Invalid virtual address %#lx", va));
6114 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
6115 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
6118 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
6119 tmpl1 = kva_alloc(PAGE_SIZE);
6124 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
6125 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6126 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
6127 " in pmap %p", va, pmap);
6131 l2phys = VM_PAGE_TO_PHYS(ml2);
6132 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
6134 /* Address the range points at */
6135 phys = oldl1 & ~ATTR_MASK;
6136 /* The attributed from the old l1 table to be copied */
6137 newl2 = oldl1 & ATTR_MASK;
6139 /* Create the new entries */
6140 for (i = 0; i < Ln_ENTRIES; i++) {
6141 l2[i] = newl2 | phys;
6144 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
6145 ("Invalid l2 page (%lx != %lx)", l2[0],
6146 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
6149 pmap_kenter(tmpl1, PAGE_SIZE,
6150 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
6151 VM_MEMATTR_WRITE_BACK);
6152 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
6155 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
6158 pmap_kremove(tmpl1);
6159 kva_free(tmpl1, PAGE_SIZE);
6166 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
6170 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
6177 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
6178 struct rwlock **lockp)
6180 struct spglist free;
6183 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
6185 vm_page_free_pages_toq(&free, true);
6189 * Create an L3 table to map all addresses within an L2 mapping.
6192 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
6193 struct rwlock **lockp)
6195 pt_entry_t *l3, newl3, oldl2;
6200 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6201 PMAP_ASSERT_STAGE1(pmap);
6203 oldl2 = pmap_load(l2);
6204 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
6205 ("pmap_demote_l2: Demoting a non-block entry"));
6209 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
6210 tmpl2 = kva_alloc(PAGE_SIZE);
6216 * Invalidate the 2MB page mapping and return "failure" if the
6217 * mapping was never accessed.
6219 if ((oldl2 & ATTR_AF) == 0) {
6220 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6221 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
6222 pmap_demote_l2_abort(pmap, va, l2, lockp);
6223 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
6228 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
6229 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6230 ("pmap_demote_l2: page table page for a wired mapping"
6234 * If the page table page is missing and the mapping
6235 * is for a kernel address, the mapping must belong to
6236 * the direct map. Page table pages are preallocated
6237 * for every other part of the kernel address space,
6238 * so the direct map region is the only part of the
6239 * kernel address space that must be handled here.
6241 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
6242 ("pmap_demote_l2: No saved mpte for va %#lx", va));
6245 * If the 2MB page mapping belongs to the direct map
6246 * region of the kernel's address space, then the page
6247 * allocation request specifies the highest possible
6248 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
6249 * priority is normal.
6251 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
6252 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
6253 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
6256 * If the allocation of the new page table page fails,
6257 * invalidate the 2MB page mapping and return "failure".
6260 pmap_demote_l2_abort(pmap, va, l2, lockp);
6261 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
6262 " in pmap %p", va, pmap);
6266 if (va < VM_MAXUSER_ADDRESS) {
6267 ml3->ref_count = NL3PG;
6268 pmap_resident_count_inc(pmap, 1);
6271 l3phys = VM_PAGE_TO_PHYS(ml3);
6272 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
6273 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
6274 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
6275 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
6276 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
6279 * If the page table page is not leftover from an earlier promotion,
6280 * or the mapping attributes have changed, (re)initialize the L3 table.
6282 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
6283 * performs a dsb(). That dsb() ensures that the stores for filling
6284 * "l3" are visible before "l3" is added to the page table.
6286 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
6287 pmap_fill_l3(l3, newl3);
6290 * Map the temporary page so we don't lose access to the l2 table.
6293 pmap_kenter(tmpl2, PAGE_SIZE,
6294 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
6295 VM_MEMATTR_WRITE_BACK);
6296 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
6300 * The spare PV entries must be reserved prior to demoting the
6301 * mapping, that is, prior to changing the PDE. Otherwise, the state
6302 * of the L2 and the PV lists will be inconsistent, which can result
6303 * in reclaim_pv_chunk() attempting to remove a PV entry from the
6304 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
6305 * PV entry for the 2MB page mapping that is being demoted.
6307 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6308 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
6311 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
6312 * the 2MB page mapping.
6314 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
6317 * Demote the PV entry.
6319 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6320 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
6322 atomic_add_long(&pmap_l2_demotions, 1);
6323 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
6324 " in pmap %p %lx", va, pmap, l3[0]);
6328 pmap_kremove(tmpl2);
6329 kva_free(tmpl2, PAGE_SIZE);
6337 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
6339 struct rwlock *lock;
6343 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
6350 * Perform the pmap work for mincore(2). If the page is not both referenced and
6351 * modified by this pmap, returns its physical address so that the caller can
6352 * find other mappings.
6355 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
6357 pt_entry_t *pte, tpte;
6358 vm_paddr_t mask, pa;
6362 PMAP_ASSERT_STAGE1(pmap);
6364 pte = pmap_pte(pmap, addr, &lvl);
6366 tpte = pmap_load(pte);
6379 panic("pmap_mincore: invalid level %d", lvl);
6382 managed = (tpte & ATTR_SW_MANAGED) != 0;
6383 val = MINCORE_INCORE;
6385 val |= MINCORE_PSIND(3 - lvl);
6386 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
6387 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
6388 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6389 if ((tpte & ATTR_AF) == ATTR_AF)
6390 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6392 pa = (tpte & ~ATTR_MASK) | (addr & mask);
6398 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6399 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6407 * Garbage collect every ASID that is neither active on a processor nor
6411 pmap_reset_asid_set(pmap_t pmap)
6414 int asid, cpuid, epoch;
6415 struct asid_set *set;
6416 enum pmap_stage stage;
6418 set = pmap->pm_asid_set;
6419 stage = pmap->pm_stage;
6421 set = pmap->pm_asid_set;
6422 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6423 mtx_assert(&set->asid_set_mutex, MA_OWNED);
6426 * Ensure that the store to asid_epoch is globally visible before the
6427 * loads from pc_curpmap are performed.
6429 epoch = set->asid_epoch + 1;
6430 if (epoch == INT_MAX)
6432 set->asid_epoch = epoch;
6434 if (stage == PM_STAGE1) {
6435 __asm __volatile("tlbi vmalle1is");
6437 KASSERT(pmap_clean_stage2_tlbi != NULL,
6438 ("%s: Unset stage 2 tlb invalidation callback\n",
6440 pmap_clean_stage2_tlbi();
6443 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
6444 set->asid_set_size - 1);
6445 CPU_FOREACH(cpuid) {
6446 if (cpuid == curcpu)
6448 if (stage == PM_STAGE1) {
6449 curpmap = pcpu_find(cpuid)->pc_curpmap;
6450 PMAP_ASSERT_STAGE1(pmap);
6452 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
6453 if (curpmap == NULL)
6455 PMAP_ASSERT_STAGE2(pmap);
6457 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
6458 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
6461 bit_set(set->asid_set, asid);
6462 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
6467 * Allocate a new ASID for the specified pmap.
6470 pmap_alloc_asid(pmap_t pmap)
6472 struct asid_set *set;
6475 set = pmap->pm_asid_set;
6476 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6478 mtx_lock_spin(&set->asid_set_mutex);
6481 * While this processor was waiting to acquire the asid set mutex,
6482 * pmap_reset_asid_set() running on another processor might have
6483 * updated this pmap's cookie to the current epoch. In which case, we
6484 * don't need to allocate a new ASID.
6486 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
6489 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
6491 if (new_asid == -1) {
6492 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6493 set->asid_next, &new_asid);
6494 if (new_asid == -1) {
6495 pmap_reset_asid_set(pmap);
6496 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6497 set->asid_set_size, &new_asid);
6498 KASSERT(new_asid != -1, ("ASID allocation failure"));
6501 bit_set(set->asid_set, new_asid);
6502 set->asid_next = new_asid + 1;
6503 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
6505 mtx_unlock_spin(&set->asid_set_mutex);
6509 * Compute the value that should be stored in ttbr0 to activate the specified
6510 * pmap. This value may change from time to time.
6513 pmap_to_ttbr0(pmap_t pmap)
6516 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
6521 pmap_activate_int(pmap_t pmap)
6523 struct asid_set *set;
6526 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
6527 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
6529 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
6530 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
6532 * Handle the possibility that the old thread was preempted
6533 * after an "ic" or "tlbi" instruction but before it performed
6534 * a "dsb" instruction. If the old thread migrates to a new
6535 * processor, its completion of a "dsb" instruction on that
6536 * new processor does not guarantee that the "ic" or "tlbi"
6537 * instructions performed on the old processor have completed.
6543 set = pmap->pm_asid_set;
6544 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6547 * Ensure that the store to curpmap is globally visible before the
6548 * load from asid_epoch is performed.
6550 if (pmap->pm_stage == PM_STAGE1)
6551 PCPU_SET(curpmap, pmap);
6553 PCPU_SET(curvmpmap, pmap);
6555 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
6556 if (epoch >= 0 && epoch != set->asid_epoch)
6557 pmap_alloc_asid(pmap);
6559 if (pmap->pm_stage == PM_STAGE1) {
6560 set_ttbr0(pmap_to_ttbr0(pmap));
6561 if (PCPU_GET(bcast_tlbi_workaround) != 0)
6562 invalidate_local_icache();
6568 pmap_activate_vm(pmap_t pmap)
6571 PMAP_ASSERT_STAGE2(pmap);
6573 (void)pmap_activate_int(pmap);
6577 pmap_activate(struct thread *td)
6581 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6582 PMAP_ASSERT_STAGE1(pmap);
6584 (void)pmap_activate_int(pmap);
6589 * To eliminate the unused parameter "old", we would have to add an instruction
6593 pmap_switch(struct thread *old __unused, struct thread *new)
6595 pcpu_bp_harden bp_harden;
6598 /* Store the new curthread */
6599 PCPU_SET(curthread, new);
6601 /* And the new pcb */
6603 PCPU_SET(curpcb, pcb);
6606 * TODO: We may need to flush the cache here if switching
6607 * to a user process.
6610 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
6612 * Stop userspace from training the branch predictor against
6613 * other processes. This will call into a CPU specific
6614 * function that clears the branch predictor state.
6616 bp_harden = PCPU_GET(bp_harden);
6617 if (bp_harden != NULL)
6625 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
6628 PMAP_ASSERT_STAGE1(pmap);
6629 if (va >= VM_MIN_KERNEL_ADDRESS) {
6630 cpu_icache_sync_range(va, sz);
6635 /* Find the length of data in this page to flush */
6636 offset = va & PAGE_MASK;
6637 len = imin(PAGE_SIZE - offset, sz);
6640 /* Extract the physical address & find it in the DMAP */
6641 pa = pmap_extract(pmap, va);
6643 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
6645 /* Move to the next page */
6648 /* Set the length for the next iteration */
6649 len = imin(PAGE_SIZE, sz);
6655 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6658 pt_entry_t *ptep, pte;
6661 PMAP_ASSERT_STAGE2(pmap);
6664 /* Data and insn aborts use same encoding for FSC field. */
6665 dfsc = esr & ISS_DATA_DFSC_MASK;
6667 case ISS_DATA_DFSC_TF_L0:
6668 case ISS_DATA_DFSC_TF_L1:
6669 case ISS_DATA_DFSC_TF_L2:
6670 case ISS_DATA_DFSC_TF_L3:
6672 pdep = pmap_pde(pmap, far, &lvl);
6673 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
6680 ptep = pmap_l0_to_l1(pdep, far);
6683 ptep = pmap_l1_to_l2(pdep, far);
6686 ptep = pmap_l2_to_l3(pdep, far);
6689 panic("%s: Invalid pde level %d", __func__,lvl);
6693 case ISS_DATA_DFSC_AFF_L1:
6694 case ISS_DATA_DFSC_AFF_L2:
6695 case ISS_DATA_DFSC_AFF_L3:
6697 ptep = pmap_pte(pmap, far, &lvl);
6699 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
6701 pmap_invalidate_vpipt_icache();
6704 * If accessing an executable page invalidate
6705 * the I-cache so it will be valid when we
6706 * continue execution in the guest. The D-cache
6707 * is assumed to already be clean to the Point
6710 if ((pte & ATTR_S2_XN_MASK) !=
6711 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
6712 invalidate_icache();
6715 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
6726 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6728 pt_entry_t pte, *ptep;
6735 ec = ESR_ELx_EXCEPTION(esr);
6737 case EXCP_INSN_ABORT_L:
6738 case EXCP_INSN_ABORT:
6739 case EXCP_DATA_ABORT_L:
6740 case EXCP_DATA_ABORT:
6746 if (pmap->pm_stage == PM_STAGE2)
6747 return (pmap_stage2_fault(pmap, esr, far));
6749 /* Data and insn aborts use same encoding for FSC field. */
6750 switch (esr & ISS_DATA_DFSC_MASK) {
6751 case ISS_DATA_DFSC_AFF_L1:
6752 case ISS_DATA_DFSC_AFF_L2:
6753 case ISS_DATA_DFSC_AFF_L3:
6755 ptep = pmap_pte(pmap, far, &lvl);
6757 pmap_set_bits(ptep, ATTR_AF);
6760 * XXXMJ as an optimization we could mark the entry
6761 * dirty if this is a write fault.
6766 case ISS_DATA_DFSC_PF_L1:
6767 case ISS_DATA_DFSC_PF_L2:
6768 case ISS_DATA_DFSC_PF_L3:
6769 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6770 (esr & ISS_DATA_WnR) == 0)
6773 ptep = pmap_pte(pmap, far, &lvl);
6775 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6776 if ((pte & ATTR_S1_AP_RW_BIT) ==
6777 ATTR_S1_AP(ATTR_S1_AP_RO)) {
6778 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
6779 pmap_invalidate_page(pmap, far);
6785 case ISS_DATA_DFSC_TF_L0:
6786 case ISS_DATA_DFSC_TF_L1:
6787 case ISS_DATA_DFSC_TF_L2:
6788 case ISS_DATA_DFSC_TF_L3:
6790 * Retry the translation. A break-before-make sequence can
6791 * produce a transient fault.
6793 if (pmap == kernel_pmap) {
6795 * The translation fault may have occurred within a
6796 * critical section. Therefore, we must check the
6797 * address without acquiring the kernel pmap's lock.
6799 if (pmap_kextract(far) != 0)
6803 /* Ask the MMU to check the address. */
6804 intr = intr_disable();
6805 par = arm64_address_translate_s1e0r(far);
6810 * If the translation was successful, then we can
6811 * return success to the trap handler.
6813 if (PAR_SUCCESS(par))
6823 * Increase the starting virtual address of the given mapping if a
6824 * different alignment might result in more superpage mappings.
6827 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6828 vm_offset_t *addr, vm_size_t size)
6830 vm_offset_t superpage_offset;
6834 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6835 offset += ptoa(object->pg_color);
6836 superpage_offset = offset & L2_OFFSET;
6837 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6838 (*addr & L2_OFFSET) == superpage_offset)
6840 if ((*addr & L2_OFFSET) < superpage_offset)
6841 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6843 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6847 * Get the kernel virtual address of a set of physical pages. If there are
6848 * physical addresses not covered by the DMAP perform a transient mapping
6849 * that will be removed when calling pmap_unmap_io_transient.
6851 * \param page The pages the caller wishes to obtain the virtual
6852 * address on the kernel memory map.
6853 * \param vaddr On return contains the kernel virtual memory address
6854 * of the pages passed in the page parameter.
6855 * \param count Number of pages passed in.
6856 * \param can_fault TRUE if the thread using the mapped pages can take
6857 * page faults, FALSE otherwise.
6859 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6860 * finished or FALSE otherwise.
6864 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6865 boolean_t can_fault)
6868 boolean_t needs_mapping;
6872 * Allocate any KVA space that we need, this is done in a separate
6873 * loop to prevent calling vmem_alloc while pinned.
6875 needs_mapping = FALSE;
6876 for (i = 0; i < count; i++) {
6877 paddr = VM_PAGE_TO_PHYS(page[i]);
6878 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6879 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6880 M_BESTFIT | M_WAITOK, &vaddr[i]);
6881 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6882 needs_mapping = TRUE;
6884 vaddr[i] = PHYS_TO_DMAP(paddr);
6888 /* Exit early if everything is covered by the DMAP */
6894 for (i = 0; i < count; i++) {
6895 paddr = VM_PAGE_TO_PHYS(page[i]);
6896 if (!PHYS_IN_DMAP(paddr)) {
6898 "pmap_map_io_transient: TODO: Map out of DMAP data");
6902 return (needs_mapping);
6906 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6907 boolean_t can_fault)
6914 for (i = 0; i < count; i++) {
6915 paddr = VM_PAGE_TO_PHYS(page[i]);
6916 if (!PHYS_IN_DMAP(paddr)) {
6917 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
6923 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
6926 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
6930 * Track a range of the kernel's virtual address space that is contiguous
6931 * in various mapping attributes.
6933 struct pmap_kernel_map_range {
6943 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6949 if (eva <= range->sva)
6952 index = range->attrs & ATTR_S1_IDX_MASK;
6954 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
6957 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
6960 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
6963 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
6968 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
6969 __func__, index, range->sva, eva);
6974 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
6976 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
6977 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
6978 (range->attrs & ATTR_S1_AP_USER) != 0 ? 'u' : 's',
6979 mode, range->l1blocks, range->l2blocks, range->l3contig,
6982 /* Reset to sentinel value. */
6983 range->sva = 0xfffffffffffffffful;
6987 * Determine whether the attributes specified by a page table entry match those
6988 * being tracked by the current range.
6991 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6994 return (range->attrs == attrs);
6998 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
7002 memset(range, 0, sizeof(*range));
7004 range->attrs = attrs;
7008 * Given a leaf PTE, derive the mapping's attributes. If they do not match
7009 * those of the current run, dump the address range and its attributes, and
7013 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
7014 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
7019 attrs = l0e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
7020 attrs |= l1e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
7021 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
7022 attrs |= l1e & ATTR_S1_IDX_MASK;
7023 attrs |= l2e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
7024 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
7025 attrs |= l2e & ATTR_S1_IDX_MASK;
7026 attrs |= l3e & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK);
7028 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
7029 sysctl_kmaps_dump(sb, range, va);
7030 sysctl_kmaps_reinit(range, va, attrs);
7035 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
7037 struct pmap_kernel_map_range range;
7038 struct sbuf sbuf, *sb;
7039 pd_entry_t l0e, *l1, l1e, *l2, l2e;
7040 pt_entry_t *l3, l3e;
7043 int error, i, j, k, l;
7045 error = sysctl_wire_old_buffer(req, 0);
7049 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
7051 /* Sentinel value. */
7052 range.sva = 0xfffffffffffffffful;
7055 * Iterate over the kernel page tables without holding the kernel pmap
7056 * lock. Kernel page table pages are never freed, so at worst we will
7057 * observe inconsistencies in the output.
7059 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
7061 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
7062 sbuf_printf(sb, "\nDirect map:\n");
7063 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
7064 sbuf_printf(sb, "\nKernel map:\n");
7066 l0e = kernel_pmap->pm_l0[i];
7067 if ((l0e & ATTR_DESCR_VALID) == 0) {
7068 sysctl_kmaps_dump(sb, &range, sva);
7072 pa = l0e & ~ATTR_MASK;
7073 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
7075 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
7077 if ((l1e & ATTR_DESCR_VALID) == 0) {
7078 sysctl_kmaps_dump(sb, &range, sva);
7082 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
7083 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
7089 pa = l1e & ~ATTR_MASK;
7090 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
7092 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
7094 if ((l2e & ATTR_DESCR_VALID) == 0) {
7095 sysctl_kmaps_dump(sb, &range, sva);
7099 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
7100 sysctl_kmaps_check(sb, &range, sva,
7106 pa = l2e & ~ATTR_MASK;
7107 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
7109 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
7110 l++, sva += L3_SIZE) {
7112 if ((l3e & ATTR_DESCR_VALID) == 0) {
7113 sysctl_kmaps_dump(sb, &range,
7117 sysctl_kmaps_check(sb, &range, sva,
7118 l0e, l1e, l2e, l3e);
7119 if ((l3e & ATTR_CONTIGUOUS) != 0)
7120 range.l3contig += l % 16 == 0 ?
7129 error = sbuf_finish(sb);
7133 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
7134 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7135 NULL, 0, sysctl_kmaps, "A",
7136 "Dump kernel address layout");