2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
5 * Copyright (c) 2018 Greg V <greg@unrelenting.technology>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <machine/bus.h>
42 #include <dev/fdt/simplebus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
47 #include <dev/extres/clk/clk_div.h>
48 #include <dev/extres/clk/clk_fixed.h>
49 #include <dev/extres/clk/clk_mux.h>
51 #include <arm64/rockchip/clk/rk_cru.h>
53 #include <arm64/rockchip/clk/rk3399_cru_dt.h>
55 #define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4)
56 #define CRU_CLKGATE_CON(x) (0x300 + (x) * 0x4)
61 static struct rk_cru_gate rk3399_gates[] = {
62 /* CRU_CLKGATE_CON0 */
64 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7),
65 GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6),
66 GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5),
67 GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4),
68 GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3),
69 GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2),
70 GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1),
71 GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0),
73 /* CRU_CLKGATE_CON1 */
75 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7),
76 GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c", 1, 6),
77 GATE(0, "atclk_core_b", "atclk_core_b_c", 1, 5),
78 GATE(0, "aclkm_core_b", "aclkm_core_b_c", 1, 4),
79 GATE(0, "clk_core_b_gpll_src", "gpll", 1, 3),
80 GATE(0, "clk_core_b_dpll_src", "dpll", 1, 2),
81 GATE(0, "clk_core_b_bpll_src", "bpll", 1, 1),
82 GATE(0, "clk_core_b_lpll_src", "lpll", 1, 0),
84 /* CRU_CLKGATE_CON2 */
86 GATE(0, "npll_cs", "npll", 2, 10),
87 GATE(0, "gpll_cs", "gpll", 2, 9),
88 GATE(0, "cpll_cs", "cpll", 2, 8),
89 GATE(SCLK_CCI_TRACE, "clk_cci_trace", "clk_cci_trace_c", 2, 7),
90 GATE(0, "gpll_cci_trace", "gpll", 2, 6),
91 GATE(0, "cpll_cci_trace", "cpll", 2, 5),
92 GATE(0, "aclk_cci_pre", "aclk_cci_pre_c", 2, 4),
93 GATE(0, "vpll_aclk_cci_src", "vpll", 2, 3),
94 GATE(0, "npll_aclk_cci_src", "npll", 2, 2),
95 GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1),
96 GATE(0, "cpll_aclk_cci_src", "cpll", 2, 0),
98 /* CRU_CLKGATE_CON3 */
100 GATE(0, "aclk_center", "aclk_center_c", 3, 7),
103 GATE(PCLK_DDR, "pclk_ddr", "pclk_ddr_c", 3, 4),
104 GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3),
105 GATE(0, "clk_ddrc_dpll_src", "dpll", 3, 2),
106 GATE(0, "clk_ddrc_bpll_src", "bpll", 3, 1),
107 GATE(0, "clk_ddrc_lpll_src", "lpll", 3, 0),
110 /* CRU_CLKGATE_CON4 */
112 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11),
113 GATE(0, "clk_rga_core", "clk_rga_core_c", 4, 10),
114 GATE(0, "hclk_rga_pre", "hclk_rga_pre_c", 4, 9),
115 GATE(0, "aclk_rga_pre", "aclk_rga_pre_c", 4, 8),
116 GATE(0, "hclk_iep_pre", "hclk_iep_pre_c", 4, 7),
117 GATE(0, "aclk_iep_pre", "aclk_iep_pre_c", 4, 6),
118 GATE(SCLK_VDU_CA, "clk_vdu_ca", "clk_vdu_ca_c", 4, 5),
119 GATE(SCLK_VDU_CORE, "clk_vdu_core", "clk_vdu_core_c", 4, 4),
120 GATE(0, "hclk_vdu_pre", "hclk_vdu_pre_c", 4, 3),
121 GATE(0, "aclk_vdu_pre", "aclk_vdu_pre_c", 4, 2),
122 GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_c", 4, 1),
123 GATE(0, "aclk_vcodec_pre", "aclk_vcodec_pre_c", 4, 0),
125 /* CRU_CLKGATE_CON5 */
127 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 5, 9),
128 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 5, 8),
129 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 5, 7),
130 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 5, 6),
131 GATE(SCLK_MAC, "clk_gmac", "clk_gmac_c", 5, 5),
132 GATE(PCLK_PERIHP, "pclk_perihp", "pclk_perihp_c", 5, 4),
133 GATE(HCLK_PERIHP, "hclk_perihp", "hclk_perihp_c", 5, 3),
134 GATE(ACLK_PERIHP, "aclk_perihp", "aclk_perihp_c", 5, 2),
135 GATE(0, "cpll_aclk_perihp_src", "cpll", 5, 1),
136 GATE(0, "gpll_aclk_perihp_src", "gpll", 5, 0),
138 /* CRU_CLKGATE_CON6 */
140 GATE(SCLK_EMMC, "clk_emmc", "clk_emmc_c", 6, 14),
141 GATE(0, "cpll_aclk_emmc_src", "cpll", 6, 13),
142 GATE(0, "gpll_aclk_emmc_src", "gpll", 6, 12),
143 GATE(0, "pclk_gmac_pre", "pclk_gmac_pre_c", 6, 11),
144 GATE(0, "aclk_gmac_pre", "aclk_gmac_pre_c", 6, 10),
145 GATE(0, "cpll_aclk_gmac_src", "cpll", 6, 9),
146 GATE(0, "gpll_aclk_gmac_src", "gpll", 6, 8),
148 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 6, 6),
149 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 6, 5),
150 GATE(SCLK_HSICPHY, "clk_hsicphy", "clk_hsicphy_c", 6, 4),
151 GATE(0, "clk_pcie_core_cru", "clk_pcie_core_cru_c", 6, 3),
152 GATE(SCLK_PCIE_PM, "clk_pcie_pm", "clk_pcie_pm_c", 6, 2),
153 GATE(SCLK_SDMMC, "clk_sdmmc", "clk_sdmmc_c", 6, 1),
154 GATE(SCLK_SDIO, "clk_sdio", "clk_sdio_c", 6, 0),
156 /* CRU_CLKGATE_CON7 */
158 GATE(FCLK_CM0S, "fclk_cm0s", "fclk_cm0s_c", 7, 9),
159 GATE(SCLK_CRYPTO1, "clk_crypto1", "clk_crypto1_c", 7, 8),
160 GATE(SCLK_CRYPTO0, "clk_crypto0", "clk_crypto0_c", 7, 7),
161 GATE(0, "cpll_fclk_cm0s_src", "cpll", 7, 6),
162 GATE(0, "gpll_fclk_cm0s_src", "gpll", 7, 5),
163 GATE(PCLK_PERILP0, "pclk_perilp0", "pclk_perilp0_c", 7, 4),
164 GATE(HCLK_PERILP0, "hclk_perilp0", "hclk_perilp0_c", 7, 3),
165 GATE(ACLK_PERILP0, "aclk_perilp0", "aclk_perilp0_c", 7, 2),
166 GATE(0, "cpll_aclk_perilp0_src", "cpll", 7, 1),
167 GATE(0, "gpll_aclk_perilp0_src", "gpll", 7, 0),
169 /* CRU_CLKGATE_CON8 */
170 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", 8, 15),
171 GATE(0, "clk_spdif_frac", "clk_spdif_frac_c", 8, 14),
172 GATE(0, "clk_spdif_div", "clk_spdif_div_c", 8, 13),
173 GATE(SCLK_I2S_8CH_OUT, "clk_i2sout", "clk_i2sout_c", 8, 12),
174 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", 8, 11),
175 GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_c", 8, 10),
176 GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 8, 9),
177 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", 8, 8),
178 GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_c", 8, 7),
179 GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 8, 6),
180 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", 8, 5),
181 GATE(0, "clk_i2s0_frac","clk_i2s0_frac_c", 8, 4),
182 GATE(0, "clk_i2s0_div","clk_i2s0_div_c", 8, 3),
183 GATE(PCLK_PERILP1, "pclk_perilp1", "pclk_perilp1_c", 8, 2),
184 GATE(HCLK_PERILP1, "cpll_hclk_perilp1_src", "cpll", 8, 1),
185 GATE(0, "gpll_hclk_perilp1_src", "gpll", 8, 0),
187 /* CRU_CLKGATE_CON9 */
188 GATE(SCLK_SPI4, "clk_spi4", "clk_spi4_c", 9, 15),
189 GATE(SCLK_SPI2, "clk_spi2", "clk_spi2_c", 9, 14),
190 GATE(SCLK_SPI1, "clk_spi1", "clk_spi1_c", 9, 13),
191 GATE(SCLK_SPI0, "clk_spi0", "clk_spi0_c", 9, 12),
192 GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 9, 11),
193 GATE(SCLK_TSADC, "clk_tsadc", "clk_tsadc_c", 9, 10),
195 GATE(0, "clk_uart3_frac", "clk_uart3_frac_c", 9, 7),
196 GATE(0, "clk_uart3_div", "clk_uart3_div_c", 9, 6),
197 GATE(0, "clk_uart2_frac", "clk_uart2_frac_c", 9, 5),
198 GATE(0, "clk_uart2_div", "clk_uart2_div_c", 9, 4),
199 GATE(0, "clk_uart1_frac", "clk_uart1_frac_c", 9, 3),
200 GATE(0, "clk_uart1_div", "clk_uart1_div_c", 9, 2),
201 GATE(0, "clk_uart0_frac", "clk_uart0_frac_c", 9, 1),
202 GATE(0, "clk_uart0_div", "clk_uart0_div_c", 9, 0),
204 /* CRU_CLKGATE_CON10 */
205 GATE(SCLK_VOP1_PWM, "clk_vop1_pwm", "clk_vop1_pwm_c", 10, 15),
206 GATE(SCLK_VOP0_PWM, "clk_vop0_pwm", "clk_vop0_pwm_c", 10, 14),
207 GATE(DCLK_VOP0_DIV, "dclk_vop0_div", "dclk_vop0_div_c", 10, 12),
208 GATE(DCLK_VOP1_DIV, "dclk_vop1_div", "dclk_vop1_div_c", 10, 13),
209 GATE(0, "hclk_vop1_pre", "hclk_vop1_pre_c", 10, 11),
210 GATE(ACLK_VOP1_PRE, "aclk_vop1_pre", "aclk_vop1_pre_c", 10, 10),
211 GATE(0, "hclk_vop0_pre", "hclk_vop0_pre_c", 10, 9),
212 GATE(ACLK_VOP0_PRE, "aclk_vop0_pre", "aclk_vop0_pre_c", 10, 8),
213 GATE(0, "clk_cifout_src", "clk_cifout_src_c", 10, 7),
214 GATE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", "clk_spdif_rec_dptx_c", 10, 6),
215 GATE(SCLK_I2C7, "clk_i2c7", "clk_i2c7_c", 10, 5),
216 GATE(SCLK_I2C3, "clk_i2c3", "clk_i2c3_c", 10, 4),
217 GATE(SCLK_I2C6, "clk_i2c6", "clk_i2c6_c", 10, 3),
218 GATE(SCLK_I2C2, "clk_i2c2", "clk_i2c2_c", 10, 2),
219 GATE(SCLK_I2C5, "clk_i2c5", "clk_i2c5_c", 10, 1),
220 GATE(SCLK_I2C1, "clk_i2c1", "clk_i2c1_c", 10, 0),
223 /* CRU_CLKGATE_CON11 */
224 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15),
225 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14),
227 GATE(PCLK_EDP, "pclk_edp", "pclk_edp_c", 11, 11),
228 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_hdcp_c", 11, 10),
230 GATE(SCLK_DP_CORE, "clk_dp_core", "clk_dp_core_c", 11, 8),
231 GATE(SCLK_HDMI_CEC, "clk_hdmi_cec", "clk_hdmi_cec_c", 11, 7),
232 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 11, 6),
233 GATE(SCLK_ISP1, "clk_isp1", "clk_isp1_c", 11, 5),
234 GATE(SCLK_ISP0, "clk_isp0", "clk_isp0_c", 11, 4),
235 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_hdcp_c", 11, 3),
236 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_c", 11, 2),
237 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_c", 11, 1),
238 GATE(ACLK_VIO, "aclk_vio", "aclk_vio_c", 11, 0),
240 /* CRU_CLKGATE_CON12 */
242 GATE(HCLK_SD, "hclk_sd", "hclk_sd_c", 12, 13),
243 GATE(ACLK_GIC_PRE, "aclk_gic_pre", "aclk_gic_pre_c", 12, 12),
244 GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_c", 12, 11),
245 GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_c", 12, 10),
246 GATE(HCLK_ISP0, "hclk_isp0", "hclk_isp0_c", 12, 9),
247 GATE(ACLK_ISP0, "aclk_isp0", "aclk_isp0_c", 12, 8),
249 GATE(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "clk_pciephy_ref100m_c", 12, 6),
251 GATE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_c", 12, 4),
252 GATE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_c", 12, 3),
253 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 12, 2),
254 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 12, 1),
255 GATE(ACLK_USB3, "aclk_usb3", "aclk_usb3_c", 12, 0),
257 /* CRU_CLKGATE_CON13 */
258 GATE(SCLK_TESTCLKOUT2, "clk_testout2", "clk_testout2_c", 13, 15),
259 GATE(SCLK_TESTCLKOUT1, "clk_testout1", "clk_testout1_c", 13, 14),
260 GATE(SCLK_SPI5, "clk_spi5", "clk_spi5_c", 13, 13),
261 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 13, 12),
262 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 13, 12),
263 GATE(0, "clk_test", "clk_test_c", 13, 11),
265 GATE(0, "clk_test_frac", "clk_test_frac_c", 13, 9),
267 GATE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", "clk_uphy1_tcpdcore_c", 13, 7),
268 GATE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", "clk_uphy1_tcpdphy_ref_c", 13, 6),
269 GATE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", "clk_uphy0_tcpdcore_c", 13, 5),
270 GATE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", "clk_uphy0_tcpdphy_ref_c", 13, 4),
272 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 13, 1),
273 GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 13, 0),
275 /* CRU_CLKGATE_CON14 */
277 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", 14, 13),
278 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", 14, 12),
279 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", 14, 11),
280 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", 14, 10),
281 GATE(0, "clk_dbg_pd_core_l", "armclkl", 14, 9),
283 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", 14, 6),
284 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", 14, 5),
285 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", 14, 4),
286 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", 14, 3),
287 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", 14, 2),
288 GATE(0, "clk_dbg_pd_core_b", "armclkb", 14, 1),
291 /* CRU_CLKGATE_CON15 */
293 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", 15, 7),
294 GATE(0, "clk_dbg_noc", "clk_cs", 15, 6),
295 GATE(0, "clk_dbg_cxcs", "clk_cs", 15, 5),
296 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", 15, 4),
297 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", 15, 3),
298 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", 15, 2),
299 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", 15, 1),
300 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", 15, 0),
302 /* CRU_CLKGATE_CON16 */
304 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", 16, 11),
305 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 16, 10),
306 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", 16, 9),
307 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 16, 8),
309 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", 16, 3),
310 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 16, 2),
311 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", 16, 1),
312 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 16, 0),
315 /* CRU_CLKGATE_CON17 */
317 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", 17, 11),
318 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 17, 10),
319 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", 17, 9),
320 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 17, 8),
321 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", 17, 3),
322 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 17, 2),
323 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", 17, 1),
324 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 17, 0),
326 /* CRU_CLKGATE_CON18 */
327 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", 18, 15),
328 GATE(0, "clk_ddr_mon_timer", "xin24m", 18, 14),
329 GATE(0, "clk_ddr_mon", "clk_ddrc_div2", 18, 13),
330 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 18, 12),
331 GATE(0, "clk_ddr_cic", "clk_ddrc_div2", 18, 11),
332 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", 18, 10),
333 GATE(0, "clk_ddrcfg_msch1", "clk_ddrc_div2", 18, 9),
334 GATE(0, "clk_ddrphy1", "clk_ddrc_div2", 18, 8),
335 GATE(0, "clk_ddrphy_ctrl1", "clk_ddrc_div2", 18, 7),
336 GATE(0, "clk_ddrc1", "clk_ddrc_div2", 18, 6),
337 GATE(0, "clk_ddr1_msch", "clk_ddrc_div2", 18, 5),
338 GATE(0, "clk_ddrcfg_msch0", "clk_ddrc_div2", 18, 4),
339 GATE(0, "clk_ddrphy0", "clk_ddrc_div2", 18, 3),
340 GATE(0, "clk_ddrphy_ctrl0", "clk_ddrc_div2", 18, 2),
341 GATE(0, "clk_ddrc0", "clk_ddrc_div2", 18, 1),
343 /* CRU_CLKGATE_CON19 */
345 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", 19, 2),
346 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", 19, 1),
347 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", 19, 0),
350 /* CRU_CLKGATE_CON20 */
351 GATE(0, "hclk_ahb1tom", "hclk_perihp", 20, 15),
352 GATE(0, "pclk_perihp_noc", "pclk_perihp", 20, 14),
353 GATE(0, "hclk_perihp_noc", "hclk_perihp", 20, 13),
354 GATE(0, "aclk_perihp_noc", "aclk_perihp", 20, 12),
355 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 20, 11),
356 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 20, 10),
357 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 20, 9),
358 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 20, 8),
359 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 20, 7),
360 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 20, 6),
361 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 20, 5),
362 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", 20, 4),
363 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 20, 2),
366 /* CRU_CLKGATE_CON21 */
368 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", 21, 9),
369 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", 21, 8),
371 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", 21, 6),
372 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", 21, 5),
373 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", 21, 4),
374 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 21, 3),
375 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 21, 2),
376 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 21, 1),
377 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 21, 0),
380 /* CRU_CLKGATE_CON22 */
381 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 22, 15),
382 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 22, 14),
383 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 22, 13),
384 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 22, 12),
385 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 22, 11),
386 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_perilp1", 22, 10),
387 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_perilp1", 22, 9),
388 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_perilp1", 22, 8),
389 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_perilp1", 22, 7),
390 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_perilp1", 22, 6),
391 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_perilp1", 22, 5),
392 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 22, 3),
393 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 22, 2),
394 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 22, 1),
395 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 22, 0),
397 /* CRU_CLKGATE_CON23 */
399 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 23, 13),
400 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 23, 12),
401 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 23, 11),
402 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 23, 10),
403 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 23, 9),
404 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 23, 8),
405 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", 23, 7),
406 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", 23, 6),
407 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", 23, 5),
408 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", 23, 4),
409 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", 23, 3),
410 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", 23, 2),
411 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", 23, 1),
412 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", 23, 0),
414 /* CRU_CLKGATE_CON24 */
415 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 24, 15),
416 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 24, 14),
417 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 24, 13),
418 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 24, 11),
419 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 24, 10),
420 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 24, 9),
421 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 24, 8),
423 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 24, 6),
424 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 24, 5),
425 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", 24, 4),
428 /* CRU_CLKGATE_CON25 */
430 GATE(0, "hclk_sdio_noc", "hclk_perilp1", 25, 12),
431 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", 25, 11),
432 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 25, 10),
433 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", 25, 9),
434 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", 25, 8),
435 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 25, 7),
436 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 25, 6),
437 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 25, 5),
440 /* CRU_CLKGATE_CON26 */
442 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 26, 11),
443 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 26, 10),
444 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 26, 9),
445 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 26, 8),
446 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 26, 7),
447 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 26, 6),
448 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 26, 5),
449 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 26, 4),
450 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 26, 3),
451 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 26, 2),
452 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 26, 1),
453 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 26, 0),
455 /* CRU_CLKGATE_CON27 */
457 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 27, 8),
458 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 27, 7),
459 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 27, 6),
460 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 27, 5),
461 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 27, 4),
462 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", 27, 3),
463 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", 27, 2),
464 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", 27, 1),
465 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", 27, 0),
467 /* CRU_CLKGATE_CON28 */
469 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 28, 7),
470 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 28, 6),
471 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", 28, 5),
472 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", 28, 4),
473 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 28, 3),
474 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 28, 2),
475 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", 28, 1),
476 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", 28, 0),
478 /* CRU_CLKGATE_CON29 */
480 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", 29, 12),
481 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 29, 11),
482 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 29, 10),
483 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 29, 9),
484 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 29, 8),
485 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 29, 7),
486 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 29, 6),
487 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", 29, 5),
488 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", 29, 4),
489 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", 29, 3),
490 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 29, 2),
491 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 29, 1),
492 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", 29, 0),
494 /* CRU_CLKGATE_CON30 */
496 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 30, 11),
497 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 30, 10),
499 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 30, 8),
501 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 30, 4),
502 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 30, 3),
503 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 30, 2),
504 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 30, 1),
505 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 30, 0),
507 /* CRU_CLKGATE_CON31 */
509 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", 31, 10),
510 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", 31, 9),
511 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 31, 8),
512 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 31, 7),
513 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 31, 6),
514 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 31, 5),
515 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 31, 4),
516 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 31, 3),
517 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", 31, 2),
518 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", 31, 1),
521 /* CRU_CLKGATE_CON32 */
523 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 32, 13),
524 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", 32, 12),
526 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 32, 10),
527 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 32, 9),
528 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 32, 8),
530 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 32, 4),
531 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", 32, 3),
532 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 32, 2),
533 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", 32, 1),
534 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 32, 0),
536 /* CRU_CLKGATE_CON33 */
538 GATE(0, "hclk_sdmmc_noc", "hclk_sd", 33, 9),
539 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 33, 8),
540 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", 33, 5),
541 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", 33, 4),
542 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", 33, 3),
543 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", 33, 2),
544 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", 33, 1),
545 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", 33, 0),
547 /* CRU_CLKGATE_CON34 */
549 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", 34, 6),
550 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 34, 5),
551 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 34, 4),
552 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 34, 3),
553 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 34, 2),
554 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 34, 1),
555 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 34, 0),
558 #define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd) \
563 .postdiv1 = _post1, \
564 .postdiv2 = _post2, \
568 static struct rk_clk_pll_rate rk3399_pll_rates[] = {
569 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
570 PLL_RATE(2208000000, 1, 92, 1, 1, 1),
571 PLL_RATE(2184000000, 1, 91, 1, 1, 1),
572 PLL_RATE(2160000000, 1, 90, 1, 1, 1),
573 PLL_RATE(2136000000, 1, 89, 1, 1, 1),
574 PLL_RATE(2112000000, 1, 88, 1, 1, 1),
575 PLL_RATE(2088000000, 1, 87, 1, 1, 1),
576 PLL_RATE(2064000000, 1, 86, 1, 1, 1),
577 PLL_RATE(2040000000, 1, 85, 1, 1, 1),
578 PLL_RATE(2016000000, 1, 84, 1, 1, 1),
579 PLL_RATE(1992000000, 1, 83, 1, 1, 1),
580 PLL_RATE(1968000000, 1, 82, 1, 1, 1),
581 PLL_RATE(1944000000, 1, 81, 1, 1, 1),
582 PLL_RATE(1920000000, 1, 80, 1, 1, 1),
583 PLL_RATE(1896000000, 1, 79, 1, 1, 1),
584 PLL_RATE(1872000000, 1, 78, 1, 1, 1),
585 PLL_RATE(1848000000, 1, 77, 1, 1, 1),
586 PLL_RATE(1824000000, 1, 76, 1, 1, 1),
587 PLL_RATE(1800000000, 1, 75, 1, 1, 1),
588 PLL_RATE(1776000000, 1, 74, 1, 1, 1),
589 PLL_RATE(1752000000, 1, 73, 1, 1, 1),
590 PLL_RATE(1728000000, 1, 72, 1, 1, 1),
591 PLL_RATE(1704000000, 1, 71, 1, 1, 1),
592 PLL_RATE(1680000000, 1, 70, 1, 1, 1),
593 PLL_RATE(1656000000, 1, 69, 1, 1, 1),
594 PLL_RATE(1632000000, 1, 68, 1, 1, 1),
595 PLL_RATE(1608000000, 1, 67, 1, 1, 1),
596 PLL_RATE(1600000000, 3, 200, 1, 1, 1),
597 PLL_RATE(1584000000, 1, 66, 1, 1, 1),
598 PLL_RATE(1560000000, 1, 65, 1, 1, 1),
599 PLL_RATE(1536000000, 1, 64, 1, 1, 1),
600 PLL_RATE(1512000000, 1, 63, 1, 1, 1),
601 PLL_RATE(1488000000, 1, 62, 1, 1, 1),
602 PLL_RATE(1464000000, 1, 61, 1, 1, 1),
603 PLL_RATE(1440000000, 1, 60, 1, 1, 1),
604 PLL_RATE(1416000000, 1, 59, 1, 1, 1),
605 PLL_RATE(1392000000, 1, 58, 1, 1, 1),
606 PLL_RATE(1368000000, 1, 57, 1, 1, 1),
607 PLL_RATE(1344000000, 1, 56, 1, 1, 1),
608 PLL_RATE(1320000000, 1, 55, 1, 1, 1),
609 PLL_RATE(1296000000, 1, 54, 1, 1, 1),
610 PLL_RATE(1272000000, 1, 53, 1, 1, 1),
611 PLL_RATE(1248000000, 1, 52, 1, 1, 1),
612 PLL_RATE(1200000000, 1, 50, 1, 1, 1),
613 PLL_RATE(1188000000, 2, 99, 1, 1, 1),
614 PLL_RATE(1104000000, 1, 46, 1, 1, 1),
615 PLL_RATE(1100000000, 12, 550, 1, 1, 1),
616 PLL_RATE(1008000000, 1, 84, 2, 1, 1),
617 PLL_RATE(1000000000, 1, 125, 3, 1, 1),
618 PLL_RATE( 984000000, 1, 82, 2, 1, 1),
619 PLL_RATE( 960000000, 1, 80, 2, 1, 1),
620 PLL_RATE( 936000000, 1, 78, 2, 1, 1),
621 PLL_RATE( 912000000, 1, 76, 2, 1, 1),
622 PLL_RATE( 900000000, 4, 300, 2, 1, 1),
623 PLL_RATE( 888000000, 1, 74, 2, 1, 1),
624 PLL_RATE( 864000000, 1, 72, 2, 1, 1),
625 PLL_RATE( 840000000, 1, 70, 2, 1, 1),
626 PLL_RATE( 816000000, 1, 68, 2, 1, 1),
627 PLL_RATE( 800000000, 1, 100, 3, 1, 1),
628 PLL_RATE( 700000000, 6, 350, 2, 1, 1),
629 PLL_RATE( 696000000, 1, 58, 2, 1, 1),
630 PLL_RATE( 676000000, 3, 169, 2, 1, 1),
631 PLL_RATE( 600000000, 1, 75, 3, 1, 1),
632 PLL_RATE( 594000000, 1, 99, 4, 1, 1),
633 PLL_RATE( 533250000, 8, 711, 4, 1, 1),
634 PLL_RATE( 504000000, 1, 63, 3, 1, 1),
635 PLL_RATE( 500000000, 6, 250, 2, 1, 1),
636 PLL_RATE( 408000000, 1, 68, 2, 2, 1),
637 PLL_RATE( 312000000, 1, 52, 2, 2, 1),
638 PLL_RATE( 297000000, 1, 99, 4, 2, 1),
639 PLL_RATE( 216000000, 1, 72, 4, 2, 1),
640 PLL_RATE( 148500000, 1, 99, 4, 4, 1),
641 PLL_RATE( 106500000, 1, 71, 4, 4, 1),
642 PLL_RATE( 96000000, 1, 64, 4, 4, 1),
643 PLL_RATE( 74250000, 2, 99, 4, 4, 1),
644 PLL_RATE( 65000000, 1, 65, 6, 4, 1),
645 PLL_RATE( 54000000, 1, 54, 6, 4, 1),
646 PLL_RATE( 27000000, 1, 27, 6, 4, 1),
650 static struct rk_clk_armclk_rates rk3399_cpu_l_rates[] = {
668 static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] = {
695 #define PLL(_id, _name, _base) \
697 .type = RK3399_CLK_PLL, \
698 .clk.pll = &(struct rk_clk_pll_def) { \
700 .clkdef.name = _name, \
701 .clkdef.parent_names = pll_src_p, \
702 .clkdef.parent_cnt = nitems(pll_src_p), \
703 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
704 .base_offset = _base, \
705 .rates = rk3399_pll_rates, \
709 #define PLIST(_name) static const char *_name[]
710 PLIST(pll_src_p) = {"xin24m", "xin32k"};
712 PLIST(armclkl_p) = {"clk_core_l_lpll_src", "clk_core_l_bpll_src",
713 "clk_core_l_dpll_src", "clk_core_l_gpll_src"};
714 PLIST(armclkb_p) = {"clk_core_b_lpll_src", "clk_core_b_bpll_src",
715 "clk_core_b_dpll_src", "clk_core_b_gpll_src"};
716 PLIST(ddrclk_p) = {"clk_ddrc_lpll_src", "clk_ddrc_bpll_src",
717 "clk_ddrc_dpll_src", "clk_ddrc_gpll_src"};
718 PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};
719 PLIST(pll_src_cpll_gpll_ppll_p) = {"cpll", "gpll", "ppll"};
720 PLIST(pll_src_cpll_gpll_upll_p) = {"cpll", "gpll", "upll"};
721 PLIST(pll_src_npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};
722 PLIST(pll_src_cpll_gpll_npll_npll_p) = {"cpll", "gpll", "npll", "npll"};
723 PLIST(pll_src_cpll_gpll_npll_ppll_p) = {"cpll", "gpll", "npll", "ppll" };
724 PLIST(pll_src_cpll_gpll_npll_24m_p) = {"cpll", "gpll", "npll", "xin24m" };
725 PLIST(pll_src_cpll_gpll_npll_usbphy480m_p)= {"cpll", "gpll", "npll", "clk_usbphy_480m" };
726 PLIST(pll_src_ppll_cpll_gpll_npll_upll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };
727 PLIST(pll_src_cpll_gpll_npll_upll_24m_p)= { "cpll", "gpll", "npll", "upll", "xin24m" };
728 PLIST(pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
729 PLIST(pll_src_vpll_cpll_gpll_gpll_p) = {"vpll", "cpll", "gpll", "gpll"};
730 PLIST(pll_src_vpll_cpll_gpll_npll_p) = {"vpll", "cpll", "gpll", "npll"};
732 PLIST(aclk_cci_p) = {"cpll_aclk_cci_src", "gpll_aclk_cci_src",
733 "npll_aclk_cci_src", "vpll_aclk_cci_src"};
734 PLIST(cci_trace_p) = {"cpll_cci_trace","gpll_cci_trace"};
735 PLIST(cs_p)= {"cpll_cs", "gpll_cs", "npll_cs","npll_cs"};
736 PLIST(aclk_perihp_p)= {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
737 PLIST(dclk_vop0_p) = {"dclk_vop0_div", "dclk_vop0_frac"};
738 PLIST(dclk_vop1_p)= {"dclk_vop1_div", "dclk_vop1_frac"};
740 PLIST(clk_cif_p) = {"clk_cifout_src", "xin24m"};
743 PLIST(pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m"};
744 PLIST(pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m"};
745 PLIST(pll_src_24m_32k_cpll_gpll_p)= {"xin24m", "xin32k", "cpll", "gpll"};
746 PLIST(pciecore_cru_phy_p) = {"clk_pcie_core_cru", "clk_pcie_core_phy"};
748 PLIST(aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src"};
750 PLIST(aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
751 "gpll_aclk_perilp0_src" };
753 PLIST(fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
754 "gpll_fclk_cm0s_src" };
756 PLIST(hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
757 "gpll_hclk_perilp1_src" };
759 PLIST(clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
760 PLIST(clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
762 PLIST(usbphy_480m_p) = { "clk_usbphy0_480m_src",
763 "clk_usbphy1_480m_src" };
764 PLIST(aclk_gmac_p) = { "cpll_aclk_gmac_src",
765 "gpll_aclk_gmac_src" };
766 PLIST(rmii_p) = { "clk_gmac", "clkin_gmac" };
767 PLIST(spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
768 "clkin_i2s", "xin12m" };
769 PLIST(i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
770 "clkin_i2s", "xin12m" };
771 PLIST(i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
772 "clkin_i2s", "xin12m" };
773 PLIST(i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
774 "clkin_i2s", "xin12m" };
775 PLIST(i2sch_p) = {"clk_i2s0", "clk_i2s1", "clk_i2s2"};
776 PLIST(i2sout_p) = {"clk_i2sout_src", "xin12m"};
778 PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"};
779 PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"};
780 PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"};
781 PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"};
783 static struct rk_clk rk3399_clks[] = {
785 /* External clocks */
787 FRATE(0, "xin32k", 32768),
788 FFACT(0, "xin12m", "xin24m", 1, 2),
789 FRATE(0, "clkin_i2s", 0),
790 FRATE(0, "pclkin_cif", 0),
791 LINK("clk_usbphy0_480m"),
792 LINK("clk_usbphy1_480m"),
794 FRATE(0, "clk_pcie_core_phy", 0),
795 FFACT(0, "clk_ddrc_div2", "clk_ddrc", 1, 2),
798 PLL(PLL_APLLL, "lpll", 0x00),
799 PLL(PLL_APLLB, "bpll", 0x20),
800 PLL(PLL_DPLL, "dpll", 0x40),
801 PLL(PLL_CPLL, "cpll", 0x60),
802 PLL(PLL_GPLL, "gpll", 0x80),
803 PLL(PLL_NPLL, "npll", 0xA0),
804 PLL(PLL_VPLL, "vpll", 0xC0),
806 /* CRU_CLKSEL_CON0 */
807 CDIV(0, "aclkm_core_l_c", "armclkl", 0,
809 ARMDIV(ARMCLKL, "armclkl", armclkl_p, rk3399_cpu_l_rates,
810 0, 0, 5, 6, 2, 0, 3),
811 /* CRU_CLKSEL_CON1 */
812 CDIV(0, "pclk_dbg_core_l_c", "armclkl", 0,
814 CDIV(0, "atclk_core_l_c", "armclkl", 0,
817 /* CRU_CLKSEL_CON2 */
818 CDIV(0, "aclkm_core_b_c", "armclkb", 0,
820 ARMDIV(ARMCLKB, "armclkb", armclkb_p, rk3399_cpu_b_rates,
821 2, 0, 5, 6, 2, 1, 3),
823 /* CRU_CLKSEL_CON3 */
824 CDIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", 0,
826 CDIV(0, "pclk_dbg_core_b_c", "armclkb", 0,
828 CDIV(0, "atclk_core_b_c", "armclkb", 0,
831 /* CRU_CLKSEL_CON4 */
832 COMP(0, "clk_cs", cs_p, 0,
835 /* CRU_CLKSEL_CON5 */
836 COMP(0, "clk_cci_trace_c", cci_trace_p, 0,
838 COMP(0, "aclk_cci_pre_c", aclk_cci_p, 0,
841 /* CRU_CLKSEL_CON6 */
842 COMP(0, "pclk_ddr_c", pll_src_cpll_gpll_p, 0,
844 COMP(SCLK_DDRC, "clk_ddrc", ddrclk_p, 0,
847 /* CRU_CLKSEL_CON7 */
848 CDIV(0, "hclk_vcodec_pre_c", "aclk_vcodec_pre", 0,
850 COMP(0, "aclk_vcodec_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
853 /* CRU_CLKSEL_CON8 */
854 CDIV(0, "hclk_vdu_pre_c", "aclk_vdu_pre", 0,
856 COMP(0, "aclk_vdu_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
859 /* CRU_CLKSEL_CON9 */
860 COMP(0, "clk_vdu_ca_c", pll_src_cpll_gpll_npll_npll_p, 0,
862 COMP(0, "clk_vdu_core_c", pll_src_cpll_gpll_npll_npll_p, 0,
865 /* CRU_CLKSEL_CON10 */
866 CDIV(0, "hclk_iep_pre_c", "aclk_iep_pre", 0,
868 COMP(0, "aclk_iep_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
871 /* CRU_CLKSEL_CON11 */
872 CDIV(0, "hclk_rga_pre_c", "aclk_rga_pre", 0,
874 COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
877 /* CRU_CLKSEL_CON12 */
878 COMP(0, "aclk_center_c", pll_src_cpll_gpll_npll_npll_p, 0,
880 COMP(SCLK_RGA_CORE, "clk_rga_core_c", pll_src_cpll_gpll_npll_ppll_p, 0,
883 /* CRU_CLKSEL_CON13 */
884 COMP(0, "hclk_sd_c", pll_src_cpll_gpll_p, 0,
886 COMP(0, "aclk_gpu_pre_c", pll_src_ppll_cpll_gpll_npll_upll_p, 0,
889 /* CRU_CLKSEL_CON14 */
890 MUX(0, "upll", pll_src_24m_usbphy480m_p, 0,
892 CDIV(0, "pclk_perihp_c", "aclk_perihp", 0,
894 CDIV(0, "hclk_perihp_c", "aclk_perihp", 0,
896 MUX(0, "clk_usbphy_480m", usbphy_480m_p, 0,
898 COMP(0, "aclk_perihp_c", aclk_perihp_p, 0,
901 /* CRU_CLKSEL_CON15 */
902 COMP(0, "clk_sdio_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
905 /* CRU_CLKSEL_CON16 */
906 COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
909 /* CRU_CLKSEL_CON17 */
910 COMP(0, "clk_pcie_pm_c", pll_src_cpll_gpll_npll_24m_p, 0,
913 /* CRU_CLKSEL_CON18 */
914 CDIV(0, "clk_pciephy_ref100m_c", "npll", 0,
916 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", pll_src_24m_pciephy_p, 0,
918 MUX(SCLK_PCIE_CORE, "clk_pcie_core", pciecore_cru_phy_p, 0,
920 COMP(0, "clk_pcie_core_cru_c", pll_src_cpll_gpll_npll_npll_p, 0,
923 /* CRU_CLKSEL_CON19 */
924 CDIV(0, "pclk_gmac_pre_c", "aclk_gmac_pre", 0,
926 MUX(SCLK_RMII_SRC, "clk_rmii_src",rmii_p, 0,
928 MUX(SCLK_HSICPHY, "clk_hsicphy_c", pll_src_cpll_gpll_npll_usbphy480m_p, 0,
931 /* CRU_CLKSEL_CON20 */
932 COMP(0, "clk_gmac_c", pll_src_cpll_gpll_npll_npll_p, 0,
934 COMP(0, "aclk_gmac_pre_c", aclk_gmac_p, 0,
937 /* CRU_CLKSEL_CON21 */
938 COMP(ACLK_EMMC, "aclk_emmc", aclk_emmc_p, 0,
941 /* CRU_CLKSEL_CON22 */
942 COMP(0, "clk_emmc_c", pll_src_cpll_gpll_npll_upll_24m_p, 0,
945 /* CRU_CLKSEL_CON23 */
946 CDIV(0, "pclk_perilp0_c", "aclk_perilp0", 0,
948 CDIV(0, "hclk_perilp0_c", "aclk_perilp0", 0,
950 COMP(0, "aclk_perilp0_c", aclk_perilp0_p, 0,
953 /* CRU_CLKSEL_CON24 */
954 COMP(0, "fclk_cm0s_c", fclk_cm0s_p, 0,
956 COMP(0, "clk_crypto0_c", pll_src_cpll_gpll_ppll_p, 0,
959 /* CRU_CLKSEL_CON25 */
960 CDIV(0, "pclk_perilp1_c", "hclk_perilp1", 0,
962 COMP(HCLK_PERILP1, "hclk_perilp1", hclk_perilp1_p, 0,
965 /* CRU_CLKSEL_CON26 */
966 CDIV(0, "clk_saradc_c", "xin24m", 0,
968 COMP(0, "clk_crypto1_c", pll_src_cpll_gpll_ppll_p, 0,
971 /* CRU_CLKSEL_CON27 */
972 COMP(0, "clk_tsadc_c", pll_src_p, 0,
975 /* CRU_CLKSEL_CON28 */
976 MUX(0, "clk_i2s0_mux", i2s0_p, 0,
978 COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0,
981 /* CRU_CLKSEL_CON29 */
982 MUX(0, "clk_i2s1_mux", i2s1_p, 0,
984 COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0,
987 /* CRU_CLKSEL_CON30 */
988 MUX(0, "clk_i2s2_mux", i2s2_p, 0,
990 COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0,
993 /* CRU_CLKSEL_CON31 */
994 MUX(0, "clk_i2sout_c", i2sout_p, 0,
996 MUX(0, "clk_i2sout_src", i2sch_p, 0,
999 /* CRU_CLKSEL_CON32 */
1000 COMP(0, "clk_spdif_rec_dptx_c", pll_src_cpll_gpll_p, 0,
1002 MUX(0, "clk_spdif_mux", spdif_p, 0,
1004 COMP(0, "clk_spdif_div_c", pll_src_cpll_gpll_p, 0,
1007 /* CRU_CLKSEL_CON33 */
1008 MUX(0, "clk_uart_src", pll_src_cpll_gpll_p, 0,
1010 MUX(0, "clk_uart0_src", pll_src_cpll_gpll_upll_p, 0,
1012 MUX(SCLK_UART0, "clk_uart0", uart0_p, 0,
1014 CDIV(0, "clk_uart0_div_c", "clk_uart0_src", 0,
1017 /* CRU_CLKSEL_CON34 */
1018 MUX(SCLK_UART1, "clk_uart1", uart1_p, 0,
1020 CDIV(0, "clk_uart1_div_c", "clk_uart_src", 0,
1023 /* CRU_CLKSEL_CON35 */
1024 MUX(SCLK_UART2, "clk_uart2", uart2_p, 0,
1026 CDIV(0, "clk_uart2_div_c", "clk_uart_src", 0,
1029 /* CRU_CLKSEL_CON36 */
1030 MUX(SCLK_UART3, "clk_uart3", uart3_p, 0,
1032 CDIV(0, "clk_uart3_div_c", "clk_uart_src", 0,
1035 /* CRU_CLKSEL_CON37 */
1038 /* CRU_CLKSEL_CON38 */
1039 MUX(0, "clk_testout2_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
1041 COMP(0, "clk_testout2_c", clk_testout2_p, 0,
1043 MUX(0, "clk_testout1_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
1045 COMP(0, "clk_testout1_c", clk_testout1_p, 0,
1048 /* CRU_CLKSEL_CON39 */
1049 COMP(0, "aclk_usb3_c", pll_src_cpll_gpll_npll_npll_p, 0,
1052 /* CRU_CLKSEL_CON40 */
1053 COMP(0, "clk_usb3otg0_suspend_c", pll_src_p, 0,
1056 /* CRU_CLKSEL_CON41 */
1057 COMP(0, "clk_usb3otg1_suspend_c", pll_src_p, 0,
1060 /* CRU_CLKSEL_CON42 */
1061 COMP(0, "aclk_hdcp_c", pll_src_cpll_gpll_ppll_p, 0,
1063 COMP(0, "aclk_vio_c", pll_src_cpll_gpll_ppll_p, 0,
1067 /* CRU_CLKSEL_CON43 */
1068 CDIV(0, "pclk_hdcp_c", "aclk_hdcp", 0,
1070 CDIV(0, "hclk_hdcp_c", "aclk_hdcp", 0,
1072 CDIV(0, "pclk_vio_c", "aclk_vio", 0,
1075 /* CRU_CLKSEL_CON44 */
1076 COMP(0, "pclk_edp_c", pll_src_cpll_gpll_p, 0,
1079 /* CRU_CLKSEL_CON45 - XXX clocks in mux are reversed in TRM !!!*/
1080 COMP(0, "clk_hdmi_cec_c", pll_src_p, 0,
1083 /* CRU_CLKSEL_CON46 */
1084 COMP(0, "clk_dp_core_c", pll_src_npll_cpll_gpll_p, 0,
1087 /* CRU_CLKSEL_CON47 */
1088 CDIV(0, "hclk_vop0_pre_c", "aclk_vop0_pre_c", 0,
1090 COMP(0, "aclk_vop0_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1093 /* CRU_CLKSEL_CON48 */
1094 CDIV(0, "hclk_vop1_pre_c", "aclk_vop1_pre", 0,
1096 COMP(0, "aclk_vop1_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1099 /* CRU_CLKSEL_CON49 */
1100 MUX(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 0,
1102 COMP(0, "dclk_vop0_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1105 /* CRU_CLKSEL_CON50 */
1106 MUX(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 0,
1108 COMP(0, "dclk_vop1_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1111 /* CRU_CLKSEL_CON51 */
1112 COMP(0, "clk_vop0_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1115 /* CRU_CLKSEL_CON52 */
1116 COMP(0, "clk_vop1_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1119 /* CRU_CLKSEL_CON53 */
1120 CDIV(0, "hclk_isp0_c", "aclk_isp0", 0,
1122 COMP(0, "aclk_isp0_c", pll_src_cpll_gpll_ppll_p, 0,
1125 /* CRU_CLKSEL_CON54 */
1126 CDIV(0, "hclk_isp1_c", "aclk_isp1", 0,
1128 COMP(0, "aclk_isp1_c", pll_src_cpll_gpll_ppll_p, 0,
1131 /* CRU_CLKSEL_CON55 */
1132 COMP(0, "clk_isp1_c", pll_src_cpll_gpll_npll_npll_p, 0,
1134 COMP(0, "clk_isp0_c", pll_src_cpll_gpll_npll_npll_p, 0,
1137 /* CRU_CLKSEL_CON56 */
1138 COMP(0, "aclk_gic_pre_c", pll_src_cpll_gpll_p, 0,
1140 MUX(0, "clk_cifout_src_c", pll_src_cpll_gpll_npll_npll_p, 0,
1142 COMP(SCLK_CIF_OUT, "clk_cifout", clk_cif_p, 0,
1145 /* CRU_CLKSEL_CON57 */
1146 CDIV(0, "clk_test_24m", "xin24m", 0,
1148 CDIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1151 /* CRU_CLKSEL_CON58 */
1152 COMP(0, "clk_spi5_c", pll_src_cpll_gpll_p, 0,
1154 MUX(0, "clk_test_pre", pll_src_cpll_gpll_p, 0,
1156 CDIV(0, "clk_test_c", "clk_test_pre", 0,
1159 /* CRU_CLKSEL_CON59 */
1160 COMP(0, "clk_spi1_c", pll_src_cpll_gpll_p, 0,
1162 COMP(0, "clk_spi0_c", pll_src_cpll_gpll_p, 0,
1165 /* CRU_CLKSEL_CON60 */
1166 COMP(0, "clk_spi4_c", pll_src_cpll_gpll_p, 0,
1168 COMP(0, "clk_spi2_c", pll_src_cpll_gpll_p, 0,
1171 /* CRU_CLKSEL_CON61 */
1172 COMP(0, "clk_i2c5_c", pll_src_cpll_gpll_p, 0,
1174 COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0,
1177 /* CRU_CLKSEL_CON62 */
1178 COMP(0, "clk_i2c6_c", pll_src_cpll_gpll_p, 0,
1180 COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0,
1183 /* CRU_CLKSEL_CON63 */
1184 COMP(0, "clk_i2c7_c", pll_src_cpll_gpll_p, 0,
1186 COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0,
1189 /* CRU_CLKSEL_CON64 */
1190 COMP(0, "clk_uphy0_tcpdphy_ref_c", pll_src_p, 0,
1192 COMP(0, "clk_uphy0_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,
1195 /* CRU_CLKSEL_CON65 */
1196 COMP(0, "clk_uphy1_tcpdphy_ref_c", pll_src_p, 0,
1198 COMP(0, "clk_uphy1_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,
1201 /* CRU_CLKSEL_CON99 - 107 */
1202 FRACT(0, "clk_spdif_frac_c", "clk_spdif_div", 0,
1204 FRACT(0, "clk_i2s0_frac_c", "clk_i2s0_div", 0,
1206 FRACT(0, "clk_i2s1_frac_c", "clk_i2s1_div", 0,
1208 FRACT(0, "clk_i2s2_frac_c", "clk_i2s2_div", 0,
1210 FRACT(0, "clk_uart0_frac_c", "clk_uart0_div", 0,
1212 FRACT(0, "clk_uart1_frac_c", "clk_uart1_div", 0,
1214 FRACT(0, "clk_uart2_frac_c", "clk_uart2_div", 0,
1216 FRACT(0, "clk_uart3_frac_c", "clk_uart3_div", 0,
1218 FRACT(0, "clk_test_frac_c", "clk_test_pre", 0,
1220 FRACT(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
1222 FRACT(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
1225 /* Not yet implemented yet
1226 * MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
1227 * MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
1228 * MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
1229 * MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
1237 rk3399_cru_probe(device_t dev)
1240 if (!ofw_bus_status_okay(dev))
1243 if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {
1244 device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");
1245 return (BUS_PROBE_DEFAULT);
1252 rk3399_cru_attach(device_t dev)
1254 struct rk_cru_softc *sc;
1256 sc = device_get_softc(dev);
1259 sc->gates = rk3399_gates;
1260 sc->ngates = nitems(rk3399_gates);
1262 sc->clks = rk3399_clks;
1263 sc->nclks = nitems(rk3399_clks);
1265 sc->reset_offset = 0x400;
1266 sc->reset_num = 335;
1268 return (rk_cru_attach(dev));
1271 static device_method_t rk3399_cru_methods[] = {
1272 /* Device interface */
1273 DEVMETHOD(device_probe, rk3399_cru_probe),
1274 DEVMETHOD(device_attach, rk3399_cru_attach),
1279 static devclass_t rk3399_cru_devclass;
1281 DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,
1282 sizeof(struct rk_cru_softc), rk_cru_driver);
1284 EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver,
1285 rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);