2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #define BXE_DRIVER_VERSION "1.78.91"
34 #include "ecore_init.h"
35 #include "ecore_init_ops.h"
37 #include "57710_int_offsets.h"
38 #include "57711_int_offsets.h"
39 #include "57712_int_offsets.h"
42 * CTLTYPE_U64 and sysctl_handle_64 were added in r217616. Define these
43 * explicitly here for older kernels that don't include this changeset.
46 #define CTLTYPE_U64 CTLTYPE_QUAD
47 #define sysctl_handle_64 sysctl_handle_quad
51 * CSUM_TCP_IPV6 and CSUM_UDP_IPV6 were added in r236170. Define these
52 * here as zero(0) for older kernels that don't include this changeset
53 * thereby masking the functionality.
56 #define CSUM_TCP_IPV6 0
57 #define CSUM_UDP_IPV6 0
61 * pci_find_cap was added in r219865. Re-define this at pci_find_extcap
62 * for older kernels that don't include this changeset.
64 #if __FreeBSD_version < 900035
65 #define pci_find_cap pci_find_extcap
68 #define BXE_DEF_SB_ATT_IDX 0x0001
69 #define BXE_DEF_SB_IDX 0x0002
72 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per
73 * function HW initialization.
75 #define FLR_WAIT_USEC 10000 /* 10 msecs */
76 #define FLR_WAIT_INTERVAL 50 /* usecs */
77 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
79 struct pbf_pN_buf_regs {
86 struct pbf_pN_cmd_regs {
93 * PCI Device ID Table used by bxe_probe().
95 #define BXE_DEVDESC_MAX 64
96 static struct bxe_device_type bxe_devs[] = {
100 PCI_ANY_ID, PCI_ANY_ID,
101 "QLogic NetXtreme II BCM57710 10GbE"
106 PCI_ANY_ID, PCI_ANY_ID,
107 "QLogic NetXtreme II BCM57711 10GbE"
112 PCI_ANY_ID, PCI_ANY_ID,
113 "QLogic NetXtreme II BCM57711E 10GbE"
118 PCI_ANY_ID, PCI_ANY_ID,
119 "QLogic NetXtreme II BCM57712 10GbE"
124 PCI_ANY_ID, PCI_ANY_ID,
125 "QLogic NetXtreme II BCM57712 MF 10GbE"
130 PCI_ANY_ID, PCI_ANY_ID,
131 "QLogic NetXtreme II BCM57800 10GbE"
136 PCI_ANY_ID, PCI_ANY_ID,
137 "QLogic NetXtreme II BCM57800 MF 10GbE"
142 PCI_ANY_ID, PCI_ANY_ID,
143 "QLogic NetXtreme II BCM57810 10GbE"
148 PCI_ANY_ID, PCI_ANY_ID,
149 "QLogic NetXtreme II BCM57810 MF 10GbE"
154 PCI_ANY_ID, PCI_ANY_ID,
155 "QLogic NetXtreme II BCM57811 10GbE"
160 PCI_ANY_ID, PCI_ANY_ID,
161 "QLogic NetXtreme II BCM57811 MF 10GbE"
166 PCI_ANY_ID, PCI_ANY_ID,
167 "QLogic NetXtreme II BCM57840 4x10GbE"
172 PCI_ANY_ID, PCI_ANY_ID,
173 "QLogic NetXtreme II BCM57840 MF 10GbE"
180 MALLOC_DECLARE(M_BXE_ILT);
181 MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer");
184 * FreeBSD device entry points.
186 static int bxe_probe(device_t);
187 static int bxe_attach(device_t);
188 static int bxe_detach(device_t);
189 static int bxe_shutdown(device_t);
192 * FreeBSD KLD module/device interface event handler method.
194 static device_method_t bxe_methods[] = {
195 /* Device interface (device_if.h) */
196 DEVMETHOD(device_probe, bxe_probe),
197 DEVMETHOD(device_attach, bxe_attach),
198 DEVMETHOD(device_detach, bxe_detach),
199 DEVMETHOD(device_shutdown, bxe_shutdown),
200 /* Bus interface (bus_if.h) */
201 DEVMETHOD(bus_print_child, bus_generic_print_child),
202 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
207 * FreeBSD KLD Module data declaration
209 static driver_t bxe_driver = {
210 "bxe", /* module name */
211 bxe_methods, /* event handler */
212 sizeof(struct bxe_softc) /* extra data */
216 * FreeBSD dev class is needed to manage dev instances and
217 * to associate with a bus type
219 static devclass_t bxe_devclass;
221 MODULE_DEPEND(bxe, pci, 1, 1, 1);
222 MODULE_DEPEND(bxe, ether, 1, 1, 1);
223 DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0);
225 /* resources needed for unloading a previously loaded device */
227 #define BXE_PREV_WAIT_NEEDED 1
228 struct mtx bxe_prev_mtx;
229 MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF);
230 struct bxe_prev_list_node {
231 LIST_ENTRY(bxe_prev_list_node) node;
235 uint8_t aer; /* XXX automatic error recovery */
238 static LIST_HEAD(, bxe_prev_list_node) bxe_prev_list = LIST_HEAD_INITIALIZER(bxe_prev_list);
240 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
242 /* Tunable device values... */
244 SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters");
247 unsigned long bxe_debug = 0;
248 TUNABLE_ULONG("hw.bxe.debug", &bxe_debug);
249 SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, (CTLFLAG_RDTUN),
250 &bxe_debug, 0, "Debug logging mode");
252 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
253 static int bxe_interrupt_mode = INTR_MODE_MSIX;
254 TUNABLE_INT("hw.bxe.interrupt_mode", &bxe_interrupt_mode);
255 SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN,
256 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode");
258 /* Number of Queues: 0 (Auto) or 1 to 16 (fixed queue number) */
259 static int bxe_queue_count = 4;
260 TUNABLE_INT("hw.bxe.queue_count", &bxe_queue_count);
261 SYSCTL_INT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN,
262 &bxe_queue_count, 0, "Multi-Queue queue count");
264 /* max number of buffers per queue (default RX_BD_USABLE) */
265 static int bxe_max_rx_bufs = 0;
266 TUNABLE_INT("hw.bxe.max_rx_bufs", &bxe_max_rx_bufs);
267 SYSCTL_INT(_hw_bxe, OID_AUTO, max_rx_bufs, CTLFLAG_RDTUN,
268 &bxe_max_rx_bufs, 0, "Maximum Number of Rx Buffers Per Queue");
270 /* Host interrupt coalescing RX tick timer (usecs) */
271 static int bxe_hc_rx_ticks = 25;
272 TUNABLE_INT("hw.bxe.hc_rx_ticks", &bxe_hc_rx_ticks);
273 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_rx_ticks, CTLFLAG_RDTUN,
274 &bxe_hc_rx_ticks, 0, "Host Coalescing Rx ticks");
276 /* Host interrupt coalescing TX tick timer (usecs) */
277 static int bxe_hc_tx_ticks = 50;
278 TUNABLE_INT("hw.bxe.hc_tx_ticks", &bxe_hc_tx_ticks);
279 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_tx_ticks, CTLFLAG_RDTUN,
280 &bxe_hc_tx_ticks, 0, "Host Coalescing Tx ticks");
282 /* Maximum number of Rx packets to process at a time */
283 static int bxe_rx_budget = 0xffffffff;
284 TUNABLE_INT("hw.bxe.rx_budget", &bxe_rx_budget);
285 SYSCTL_INT(_hw_bxe, OID_AUTO, rx_budget, CTLFLAG_TUN,
286 &bxe_rx_budget, 0, "Rx processing budget");
288 /* Maximum LRO aggregation size */
289 static int bxe_max_aggregation_size = 0;
290 TUNABLE_INT("hw.bxe.max_aggregation_size", &bxe_max_aggregation_size);
291 SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_TUN,
292 &bxe_max_aggregation_size, 0, "max aggregation size");
294 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */
295 static int bxe_mrrs = -1;
296 TUNABLE_INT("hw.bxe.mrrs", &bxe_mrrs);
297 SYSCTL_INT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN,
298 &bxe_mrrs, 0, "PCIe maximum read request size");
300 /* AutoGrEEEn: 0 (hardware default), 1 (force on), 2 (force off) */
301 static int bxe_autogreeen = 0;
302 TUNABLE_INT("hw.bxe.autogreeen", &bxe_autogreeen);
303 SYSCTL_INT(_hw_bxe, OID_AUTO, autogreeen, CTLFLAG_RDTUN,
304 &bxe_autogreeen, 0, "AutoGrEEEn support");
306 /* 4-tuple RSS support for UDP: 0 (disabled), 1 (enabled) */
307 static int bxe_udp_rss = 0;
308 TUNABLE_INT("hw.bxe.udp_rss", &bxe_udp_rss);
309 SYSCTL_INT(_hw_bxe, OID_AUTO, udp_rss, CTLFLAG_RDTUN,
310 &bxe_udp_rss, 0, "UDP RSS support");
313 #define STAT_NAME_LEN 32 /* no stat names below can be longer than this */
315 #define STATS_OFFSET32(stat_name) \
316 (offsetof(struct bxe_eth_stats, stat_name) / 4)
318 #define Q_STATS_OFFSET32(stat_name) \
319 (offsetof(struct bxe_eth_q_stats, stat_name) / 4)
321 static const struct {
325 #define STATS_FLAGS_PORT 1
326 #define STATS_FLAGS_FUNC 2 /* MF only cares about function stats */
327 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
328 char string[STAT_NAME_LEN];
329 } bxe_eth_stats_arr[] = {
330 { STATS_OFFSET32(total_bytes_received_hi),
331 8, STATS_FLAGS_BOTH, "rx_bytes" },
332 { STATS_OFFSET32(error_bytes_received_hi),
333 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
334 { STATS_OFFSET32(total_unicast_packets_received_hi),
335 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
336 { STATS_OFFSET32(total_multicast_packets_received_hi),
337 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
338 { STATS_OFFSET32(total_broadcast_packets_received_hi),
339 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
340 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
341 8, STATS_FLAGS_PORT, "rx_crc_errors" },
342 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
343 8, STATS_FLAGS_PORT, "rx_align_errors" },
344 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
345 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
346 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
347 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
348 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
349 8, STATS_FLAGS_PORT, "rx_fragments" },
350 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
351 8, STATS_FLAGS_PORT, "rx_jabbers" },
352 { STATS_OFFSET32(no_buff_discard_hi),
353 8, STATS_FLAGS_BOTH, "rx_discards" },
354 { STATS_OFFSET32(mac_filter_discard),
355 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
356 { STATS_OFFSET32(mf_tag_discard),
357 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
358 { STATS_OFFSET32(pfc_frames_received_hi),
359 8, STATS_FLAGS_PORT, "pfc_frames_received" },
360 { STATS_OFFSET32(pfc_frames_sent_hi),
361 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
362 { STATS_OFFSET32(brb_drop_hi),
363 8, STATS_FLAGS_PORT, "rx_brb_discard" },
364 { STATS_OFFSET32(brb_truncate_hi),
365 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
366 { STATS_OFFSET32(pause_frames_received_hi),
367 8, STATS_FLAGS_PORT, "rx_pause_frames" },
368 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
369 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
370 { STATS_OFFSET32(nig_timer_max),
371 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
372 { STATS_OFFSET32(total_bytes_transmitted_hi),
373 8, STATS_FLAGS_BOTH, "tx_bytes" },
374 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
375 8, STATS_FLAGS_PORT, "tx_error_bytes" },
376 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
377 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
378 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
379 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
380 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
381 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
382 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
383 8, STATS_FLAGS_PORT, "tx_mac_errors" },
384 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
385 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
386 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
387 8, STATS_FLAGS_PORT, "tx_single_collisions" },
388 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
389 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
390 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
391 8, STATS_FLAGS_PORT, "tx_deferred" },
392 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
393 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
394 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
395 8, STATS_FLAGS_PORT, "tx_late_collisions" },
396 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
397 8, STATS_FLAGS_PORT, "tx_total_collisions" },
398 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
399 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
400 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
401 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
402 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
403 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
404 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
405 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
406 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
407 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
408 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
409 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
410 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
411 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
412 { STATS_OFFSET32(pause_frames_sent_hi),
413 8, STATS_FLAGS_PORT, "tx_pause_frames" },
414 { STATS_OFFSET32(total_tpa_aggregations_hi),
415 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
416 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
417 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
418 { STATS_OFFSET32(total_tpa_bytes_hi),
419 8, STATS_FLAGS_FUNC, "tpa_bytes"},
420 { STATS_OFFSET32(eee_tx_lpi),
421 4, STATS_FLAGS_PORT, "eee_tx_lpi"},
422 { STATS_OFFSET32(rx_calls),
423 4, STATS_FLAGS_FUNC, "rx_calls"},
424 { STATS_OFFSET32(rx_pkts),
425 4, STATS_FLAGS_FUNC, "rx_pkts"},
426 { STATS_OFFSET32(rx_tpa_pkts),
427 4, STATS_FLAGS_FUNC, "rx_tpa_pkts"},
428 { STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts),
429 4, STATS_FLAGS_FUNC, "rx_erroneous_jumbo_sge_pkts"},
430 { STATS_OFFSET32(rx_bxe_service_rxsgl),
431 4, STATS_FLAGS_FUNC, "rx_bxe_service_rxsgl"},
432 { STATS_OFFSET32(rx_jumbo_sge_pkts),
433 4, STATS_FLAGS_FUNC, "rx_jumbo_sge_pkts"},
434 { STATS_OFFSET32(rx_soft_errors),
435 4, STATS_FLAGS_FUNC, "rx_soft_errors"},
436 { STATS_OFFSET32(rx_hw_csum_errors),
437 4, STATS_FLAGS_FUNC, "rx_hw_csum_errors"},
438 { STATS_OFFSET32(rx_ofld_frames_csum_ip),
439 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_ip"},
440 { STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
441 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_tcp_udp"},
442 { STATS_OFFSET32(rx_budget_reached),
443 4, STATS_FLAGS_FUNC, "rx_budget_reached"},
444 { STATS_OFFSET32(tx_pkts),
445 4, STATS_FLAGS_FUNC, "tx_pkts"},
446 { STATS_OFFSET32(tx_soft_errors),
447 4, STATS_FLAGS_FUNC, "tx_soft_errors"},
448 { STATS_OFFSET32(tx_ofld_frames_csum_ip),
449 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_ip"},
450 { STATS_OFFSET32(tx_ofld_frames_csum_tcp),
451 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_tcp"},
452 { STATS_OFFSET32(tx_ofld_frames_csum_udp),
453 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_udp"},
454 { STATS_OFFSET32(tx_ofld_frames_lso),
455 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso"},
456 { STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
457 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso_hdr_splits"},
458 { STATS_OFFSET32(tx_encap_failures),
459 4, STATS_FLAGS_FUNC, "tx_encap_failures"},
460 { STATS_OFFSET32(tx_hw_queue_full),
461 4, STATS_FLAGS_FUNC, "tx_hw_queue_full"},
462 { STATS_OFFSET32(tx_hw_max_queue_depth),
463 4, STATS_FLAGS_FUNC, "tx_hw_max_queue_depth"},
464 { STATS_OFFSET32(tx_dma_mapping_failure),
465 4, STATS_FLAGS_FUNC, "tx_dma_mapping_failure"},
466 { STATS_OFFSET32(tx_max_drbr_queue_depth),
467 4, STATS_FLAGS_FUNC, "tx_max_drbr_queue_depth"},
468 { STATS_OFFSET32(tx_window_violation_std),
469 4, STATS_FLAGS_FUNC, "tx_window_violation_std"},
470 { STATS_OFFSET32(tx_window_violation_tso),
471 4, STATS_FLAGS_FUNC, "tx_window_violation_tso"},
472 { STATS_OFFSET32(tx_chain_lost_mbuf),
473 4, STATS_FLAGS_FUNC, "tx_chain_lost_mbuf"},
474 { STATS_OFFSET32(tx_frames_deferred),
475 4, STATS_FLAGS_FUNC, "tx_frames_deferred"},
476 { STATS_OFFSET32(tx_queue_xoff),
477 4, STATS_FLAGS_FUNC, "tx_queue_xoff"},
478 { STATS_OFFSET32(mbuf_defrag_attempts),
479 4, STATS_FLAGS_FUNC, "mbuf_defrag_attempts"},
480 { STATS_OFFSET32(mbuf_defrag_failures),
481 4, STATS_FLAGS_FUNC, "mbuf_defrag_failures"},
482 { STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
483 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_alloc_failed"},
484 { STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
485 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_mapping_failed"},
486 { STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
487 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_alloc_failed"},
488 { STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
489 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_mapping_failed"},
490 { STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
491 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_alloc_failed"},
492 { STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
493 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_mapping_failed"},
494 { STATS_OFFSET32(mbuf_alloc_tx),
495 4, STATS_FLAGS_FUNC, "mbuf_alloc_tx"},
496 { STATS_OFFSET32(mbuf_alloc_rx),
497 4, STATS_FLAGS_FUNC, "mbuf_alloc_rx"},
498 { STATS_OFFSET32(mbuf_alloc_sge),
499 4, STATS_FLAGS_FUNC, "mbuf_alloc_sge"},
500 { STATS_OFFSET32(mbuf_alloc_tpa),
501 4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"},
502 { STATS_OFFSET32(tx_queue_full_return),
503 4, STATS_FLAGS_FUNC, "tx_queue_full_return"},
504 { STATS_OFFSET32(bxe_tx_mq_sc_state_failures),
505 4, STATS_FLAGS_FUNC, "bxe_tx_mq_sc_state_failures"},
506 { STATS_OFFSET32(tx_request_link_down_failures),
507 4, STATS_FLAGS_FUNC, "tx_request_link_down_failures"},
508 { STATS_OFFSET32(bd_avail_too_less_failures),
509 4, STATS_FLAGS_FUNC, "bd_avail_too_less_failures"},
510 { STATS_OFFSET32(tx_mq_not_empty),
511 4, STATS_FLAGS_FUNC, "tx_mq_not_empty"},
512 { STATS_OFFSET32(nsegs_path1_errors),
513 4, STATS_FLAGS_FUNC, "nsegs_path1_errors"},
514 { STATS_OFFSET32(nsegs_path2_errors),
515 4, STATS_FLAGS_FUNC, "nsegs_path2_errors"}
520 static const struct {
523 char string[STAT_NAME_LEN];
524 } bxe_eth_q_stats_arr[] = {
525 { Q_STATS_OFFSET32(total_bytes_received_hi),
527 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
528 8, "rx_ucast_packets" },
529 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
530 8, "rx_mcast_packets" },
531 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
532 8, "rx_bcast_packets" },
533 { Q_STATS_OFFSET32(no_buff_discard_hi),
535 { Q_STATS_OFFSET32(total_bytes_transmitted_hi),
537 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
538 8, "tx_ucast_packets" },
539 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
540 8, "tx_mcast_packets" },
541 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
542 8, "tx_bcast_packets" },
543 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
544 8, "tpa_aggregations" },
545 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
546 8, "tpa_aggregated_frames"},
547 { Q_STATS_OFFSET32(total_tpa_bytes_hi),
549 { Q_STATS_OFFSET32(rx_calls),
551 { Q_STATS_OFFSET32(rx_pkts),
553 { Q_STATS_OFFSET32(rx_tpa_pkts),
555 { Q_STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts),
556 4, "rx_erroneous_jumbo_sge_pkts"},
557 { Q_STATS_OFFSET32(rx_bxe_service_rxsgl),
558 4, "rx_bxe_service_rxsgl"},
559 { Q_STATS_OFFSET32(rx_jumbo_sge_pkts),
560 4, "rx_jumbo_sge_pkts"},
561 { Q_STATS_OFFSET32(rx_soft_errors),
562 4, "rx_soft_errors"},
563 { Q_STATS_OFFSET32(rx_hw_csum_errors),
564 4, "rx_hw_csum_errors"},
565 { Q_STATS_OFFSET32(rx_ofld_frames_csum_ip),
566 4, "rx_ofld_frames_csum_ip"},
567 { Q_STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
568 4, "rx_ofld_frames_csum_tcp_udp"},
569 { Q_STATS_OFFSET32(rx_budget_reached),
570 4, "rx_budget_reached"},
571 { Q_STATS_OFFSET32(tx_pkts),
573 { Q_STATS_OFFSET32(tx_soft_errors),
574 4, "tx_soft_errors"},
575 { Q_STATS_OFFSET32(tx_ofld_frames_csum_ip),
576 4, "tx_ofld_frames_csum_ip"},
577 { Q_STATS_OFFSET32(tx_ofld_frames_csum_tcp),
578 4, "tx_ofld_frames_csum_tcp"},
579 { Q_STATS_OFFSET32(tx_ofld_frames_csum_udp),
580 4, "tx_ofld_frames_csum_udp"},
581 { Q_STATS_OFFSET32(tx_ofld_frames_lso),
582 4, "tx_ofld_frames_lso"},
583 { Q_STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
584 4, "tx_ofld_frames_lso_hdr_splits"},
585 { Q_STATS_OFFSET32(tx_encap_failures),
586 4, "tx_encap_failures"},
587 { Q_STATS_OFFSET32(tx_hw_queue_full),
588 4, "tx_hw_queue_full"},
589 { Q_STATS_OFFSET32(tx_hw_max_queue_depth),
590 4, "tx_hw_max_queue_depth"},
591 { Q_STATS_OFFSET32(tx_dma_mapping_failure),
592 4, "tx_dma_mapping_failure"},
593 { Q_STATS_OFFSET32(tx_max_drbr_queue_depth),
594 4, "tx_max_drbr_queue_depth"},
595 { Q_STATS_OFFSET32(tx_window_violation_std),
596 4, "tx_window_violation_std"},
597 { Q_STATS_OFFSET32(tx_window_violation_tso),
598 4, "tx_window_violation_tso"},
599 { Q_STATS_OFFSET32(tx_chain_lost_mbuf),
600 4, "tx_chain_lost_mbuf"},
601 { Q_STATS_OFFSET32(tx_frames_deferred),
602 4, "tx_frames_deferred"},
603 { Q_STATS_OFFSET32(tx_queue_xoff),
605 { Q_STATS_OFFSET32(mbuf_defrag_attempts),
606 4, "mbuf_defrag_attempts"},
607 { Q_STATS_OFFSET32(mbuf_defrag_failures),
608 4, "mbuf_defrag_failures"},
609 { Q_STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
610 4, "mbuf_rx_bd_alloc_failed"},
611 { Q_STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
612 4, "mbuf_rx_bd_mapping_failed"},
613 { Q_STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
614 4, "mbuf_rx_tpa_alloc_failed"},
615 { Q_STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
616 4, "mbuf_rx_tpa_mapping_failed"},
617 { Q_STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
618 4, "mbuf_rx_sge_alloc_failed"},
619 { Q_STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
620 4, "mbuf_rx_sge_mapping_failed"},
621 { Q_STATS_OFFSET32(mbuf_alloc_tx),
623 { Q_STATS_OFFSET32(mbuf_alloc_rx),
625 { Q_STATS_OFFSET32(mbuf_alloc_sge),
626 4, "mbuf_alloc_sge"},
627 { Q_STATS_OFFSET32(mbuf_alloc_tpa),
628 4, "mbuf_alloc_tpa"},
629 { Q_STATS_OFFSET32(tx_queue_full_return),
630 4, "tx_queue_full_return"},
631 { Q_STATS_OFFSET32(bxe_tx_mq_sc_state_failures),
632 4, "bxe_tx_mq_sc_state_failures"},
633 { Q_STATS_OFFSET32(tx_request_link_down_failures),
634 4, "tx_request_link_down_failures"},
635 { Q_STATS_OFFSET32(bd_avail_too_less_failures),
636 4, "bd_avail_too_less_failures"},
637 { Q_STATS_OFFSET32(tx_mq_not_empty),
638 4, "tx_mq_not_empty"},
639 { Q_STATS_OFFSET32(nsegs_path1_errors),
640 4, "nsegs_path1_errors"},
641 { Q_STATS_OFFSET32(nsegs_path2_errors),
642 4, "nsegs_path2_errors"}
647 #define BXE_NUM_ETH_STATS ARRAY_SIZE(bxe_eth_stats_arr)
648 #define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr)
651 static void bxe_cmng_fns_init(struct bxe_softc *sc,
654 static int bxe_get_cmng_fns_mode(struct bxe_softc *sc);
655 static void storm_memset_cmng(struct bxe_softc *sc,
656 struct cmng_init *cmng,
658 static void bxe_set_reset_global(struct bxe_softc *sc);
659 static void bxe_set_reset_in_progress(struct bxe_softc *sc);
660 static uint8_t bxe_reset_is_done(struct bxe_softc *sc,
662 static uint8_t bxe_clear_pf_load(struct bxe_softc *sc);
663 static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc,
666 static void bxe_int_disable(struct bxe_softc *sc);
667 static int bxe_release_leader_lock(struct bxe_softc *sc);
668 static void bxe_pf_disable(struct bxe_softc *sc);
669 static void bxe_free_fp_buffers(struct bxe_softc *sc);
670 static inline void bxe_update_rx_prod(struct bxe_softc *sc,
671 struct bxe_fastpath *fp,
674 uint16_t rx_sge_prod);
675 static void bxe_link_report_locked(struct bxe_softc *sc);
676 static void bxe_link_report(struct bxe_softc *sc);
677 static void bxe_link_status_update(struct bxe_softc *sc);
678 static void bxe_periodic_callout_func(void *xsc);
679 static void bxe_periodic_start(struct bxe_softc *sc);
680 static void bxe_periodic_stop(struct bxe_softc *sc);
681 static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
684 static int bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
686 static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
688 static uint8_t bxe_txeof(struct bxe_softc *sc,
689 struct bxe_fastpath *fp);
690 static void bxe_task_fp(struct bxe_fastpath *fp);
691 static __noinline void bxe_dump_mbuf(struct bxe_softc *sc,
694 static int bxe_alloc_mem(struct bxe_softc *sc);
695 static void bxe_free_mem(struct bxe_softc *sc);
696 static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc);
697 static void bxe_free_fw_stats_mem(struct bxe_softc *sc);
698 static int bxe_interrupt_attach(struct bxe_softc *sc);
699 static void bxe_interrupt_detach(struct bxe_softc *sc);
700 static void bxe_set_rx_mode(struct bxe_softc *sc);
701 static int bxe_init_locked(struct bxe_softc *sc);
702 static int bxe_stop_locked(struct bxe_softc *sc);
703 static __noinline int bxe_nic_load(struct bxe_softc *sc,
705 static __noinline int bxe_nic_unload(struct bxe_softc *sc,
706 uint32_t unload_mode,
709 static void bxe_handle_sp_tq(void *context, int pending);
710 static void bxe_handle_fp_tq(void *context, int pending);
712 static int bxe_add_cdev(struct bxe_softc *sc);
713 static void bxe_del_cdev(struct bxe_softc *sc);
714 int bxe_grc_dump(struct bxe_softc *sc);
715 static int bxe_alloc_buf_rings(struct bxe_softc *sc);
716 static void bxe_free_buf_rings(struct bxe_softc *sc);
718 /* calculate crc32 on a buffer (NOTE: crc32_length MUST be aligned to 8) */
720 calc_crc32(uint8_t *crc32_packet,
721 uint32_t crc32_length,
730 uint8_t current_byte = 0;
731 uint32_t crc32_result = crc32_seed;
732 const uint32_t CRC32_POLY = 0x1edc6f41;
734 if ((crc32_packet == NULL) ||
735 (crc32_length == 0) ||
736 ((crc32_length % 8) != 0))
738 return (crc32_result);
741 for (byte = 0; byte < crc32_length; byte = byte + 1)
743 current_byte = crc32_packet[byte];
744 for (bit = 0; bit < 8; bit = bit + 1)
746 /* msb = crc32_result[31]; */
747 msb = (uint8_t)(crc32_result >> 31);
749 crc32_result = crc32_result << 1;
751 /* it (msb != current_byte[bit]) */
752 if (msb != (0x1 & (current_byte >> bit)))
754 crc32_result = crc32_result ^ CRC32_POLY;
755 /* crc32_result[0] = 1 */
762 * 1. "mirror" every bit
763 * 2. swap the 4 bytes
764 * 3. complement each bit
769 shft = sizeof(crc32_result) * 8 - 1;
771 for (crc32_result >>= 1; crc32_result; crc32_result >>= 1)
774 temp |= crc32_result & 1;
778 /* temp[31-bit] = crc32_result[bit] */
782 /* crc32_result = {temp[7:0], temp[15:8], temp[23:16], temp[31:24]} */
784 uint32_t t0, t1, t2, t3;
785 t0 = (0x000000ff & (temp >> 24));
786 t1 = (0x0000ff00 & (temp >> 8));
787 t2 = (0x00ff0000 & (temp << 8));
788 t3 = (0xff000000 & (temp << 24));
789 crc32_result = t0 | t1 | t2 | t3;
795 crc32_result = ~crc32_result;
798 return (crc32_result);
803 volatile unsigned long *addr)
805 return ((atomic_load_acq_long(addr) & (1 << nr)) != 0);
809 bxe_set_bit(unsigned int nr,
810 volatile unsigned long *addr)
812 atomic_set_acq_long(addr, (1 << nr));
816 bxe_clear_bit(int nr,
817 volatile unsigned long *addr)
819 atomic_clear_acq_long(addr, (1 << nr));
823 bxe_test_and_set_bit(int nr,
824 volatile unsigned long *addr)
830 } while (atomic_cmpset_acq_long(addr, x, x | nr) == 0);
831 // if (x & nr) bit_was_set; else bit_was_not_set;
836 bxe_test_and_clear_bit(int nr,
837 volatile unsigned long *addr)
843 } while (atomic_cmpset_acq_long(addr, x, x & ~nr) == 0);
844 // if (x & nr) bit_was_set; else bit_was_not_set;
849 bxe_cmpxchg(volatile int *addr,
856 } while (atomic_cmpset_acq_int(addr, old, new) == 0);
861 * Get DMA memory from the OS.
863 * Validates that the OS has provided DMA buffers in response to a
864 * bus_dmamap_load call and saves the physical address of those buffers.
865 * When the callback is used the OS will return 0 for the mapping function
866 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any
867 * failures back to the caller.
873 bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
875 struct bxe_dma *dma = arg;
880 BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error);
882 dma->paddr = segs->ds_addr;
888 * Allocate a block of memory and map it for DMA. No partial completions
889 * allowed and release any resources acquired if we can't acquire all
893 * 0 = Success, !0 = Failure
896 bxe_dma_alloc(struct bxe_softc *sc,
904 BLOGE(sc, "dma block '%s' already has size %lu\n", msg,
905 (unsigned long)dma->size);
909 memset(dma, 0, sizeof(*dma)); /* sanity */
912 snprintf(dma->msg, sizeof(dma->msg), "%s", msg);
914 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
915 BCM_PAGE_SIZE, /* alignment */
916 0, /* boundary limit */
917 BUS_SPACE_MAXADDR, /* restricted low */
918 BUS_SPACE_MAXADDR, /* restricted hi */
919 NULL, /* addr filter() */
920 NULL, /* addr filter() arg */
921 size, /* max map size */
922 1, /* num discontinuous */
923 size, /* max seg size */
924 BUS_DMA_ALLOCNOW, /* flags */
926 NULL, /* lock() arg */
927 &dma->tag); /* returned dma tag */
929 BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc);
930 memset(dma, 0, sizeof(*dma));
934 rc = bus_dmamem_alloc(dma->tag,
935 (void **)&dma->vaddr,
936 (BUS_DMA_NOWAIT | BUS_DMA_ZERO),
939 BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc);
940 bus_dma_tag_destroy(dma->tag);
941 memset(dma, 0, sizeof(*dma));
945 rc = bus_dmamap_load(dma->tag,
949 bxe_dma_map_addr, /* BLOGD in here */
953 BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc);
954 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
955 bus_dma_tag_destroy(dma->tag);
956 memset(dma, 0, sizeof(*dma));
964 bxe_dma_free(struct bxe_softc *sc,
968 DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL"));
970 bus_dmamap_sync(dma->tag, dma->map,
971 (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE));
972 bus_dmamap_unload(dma->tag, dma->map);
973 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
974 bus_dma_tag_destroy(dma->tag);
977 memset(dma, 0, sizeof(*dma));
981 * These indirect read and write routines are only during init.
982 * The locking is handled by the MCP.
986 bxe_reg_wr_ind(struct bxe_softc *sc,
990 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
991 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4);
992 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
996 bxe_reg_rd_ind(struct bxe_softc *sc,
1001 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
1002 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4);
1003 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
1009 bxe_acquire_hw_lock(struct bxe_softc *sc,
1012 uint32_t lock_status;
1013 uint32_t resource_bit = (1 << resource);
1014 int func = SC_FUNC(sc);
1015 uint32_t hw_lock_control_reg;
1018 /* validate the resource is within range */
1019 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1020 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
1021 " resource_bit 0x%x\n", resource, resource_bit);
1026 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1028 hw_lock_control_reg =
1029 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1032 /* validate the resource is not already taken */
1033 lock_status = REG_RD(sc, hw_lock_control_reg);
1034 if (lock_status & resource_bit) {
1035 BLOGE(sc, "resource (0x%x) in use (status 0x%x bit 0x%x)\n",
1036 resource, lock_status, resource_bit);
1040 /* try every 5ms for 5 seconds */
1041 for (cnt = 0; cnt < 1000; cnt++) {
1042 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
1043 lock_status = REG_RD(sc, hw_lock_control_reg);
1044 if (lock_status & resource_bit) {
1050 BLOGE(sc, "Resource 0x%x resource_bit 0x%x lock timeout!\n",
1051 resource, resource_bit);
1056 bxe_release_hw_lock(struct bxe_softc *sc,
1059 uint32_t lock_status;
1060 uint32_t resource_bit = (1 << resource);
1061 int func = SC_FUNC(sc);
1062 uint32_t hw_lock_control_reg;
1064 /* validate the resource is within range */
1065 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1066 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
1067 " resource_bit 0x%x\n", resource, resource_bit);
1072 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1074 hw_lock_control_reg =
1075 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1078 /* validate the resource is currently taken */
1079 lock_status = REG_RD(sc, hw_lock_control_reg);
1080 if (!(lock_status & resource_bit)) {
1081 BLOGE(sc, "resource (0x%x) not in use (status 0x%x bit 0x%x)\n",
1082 resource, lock_status, resource_bit);
1086 REG_WR(sc, hw_lock_control_reg, resource_bit);
1089 static void bxe_acquire_phy_lock(struct bxe_softc *sc)
1092 bxe_acquire_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1095 static void bxe_release_phy_lock(struct bxe_softc *sc)
1097 bxe_release_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1101 * Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1102 * had we done things the other way around, if two pfs from the same port
1103 * would attempt to access nvram at the same time, we could run into a
1105 * pf A takes the port lock.
1106 * pf B succeeds in taking the same lock since they are from the same port.
1107 * pf A takes the per pf misc lock. Performs eeprom access.
1108 * pf A finishes. Unlocks the per pf misc lock.
1109 * Pf B takes the lock and proceeds to perform it's own access.
1110 * pf A unlocks the per port lock, while pf B is still working (!).
1111 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1112 * access corrupted by pf B).*
1115 bxe_acquire_nvram_lock(struct bxe_softc *sc)
1117 int port = SC_PORT(sc);
1121 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1122 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1124 /* adjust timeout for emulation/FPGA */
1125 count = NVRAM_TIMEOUT_COUNT;
1126 if (CHIP_REV_IS_SLOW(sc)) {
1130 /* request access to nvram interface */
1131 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1132 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1134 for (i = 0; i < count*10; i++) {
1135 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1136 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1143 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1144 BLOGE(sc, "Cannot get access to nvram interface "
1145 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1154 bxe_release_nvram_lock(struct bxe_softc *sc)
1156 int port = SC_PORT(sc);
1160 /* adjust timeout for emulation/FPGA */
1161 count = NVRAM_TIMEOUT_COUNT;
1162 if (CHIP_REV_IS_SLOW(sc)) {
1166 /* relinquish nvram interface */
1167 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1168 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1170 for (i = 0; i < count*10; i++) {
1171 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1172 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1179 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1180 BLOGE(sc, "Cannot free access to nvram interface "
1181 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1186 /* release HW lock: protect against other PFs in PF Direct Assignment */
1187 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1193 bxe_enable_nvram_access(struct bxe_softc *sc)
1197 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1199 /* enable both bits, even on read */
1200 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1201 (val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN));
1205 bxe_disable_nvram_access(struct bxe_softc *sc)
1209 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1211 /* disable both bits, even after read */
1212 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1213 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1214 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1218 bxe_nvram_read_dword(struct bxe_softc *sc,
1226 /* build the command word */
1227 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1229 /* need to clear DONE bit separately */
1230 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1232 /* address of the NVRAM to read from */
1233 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1234 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1236 /* issue a read command */
1237 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1239 /* adjust timeout for emulation/FPGA */
1240 count = NVRAM_TIMEOUT_COUNT;
1241 if (CHIP_REV_IS_SLOW(sc)) {
1245 /* wait for completion */
1248 for (i = 0; i < count; i++) {
1250 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1252 if (val & MCPR_NVM_COMMAND_DONE) {
1253 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
1254 /* we read nvram data in cpu order
1255 * but ethtool sees it as an array of bytes
1256 * converting to big-endian will do the work
1258 *ret_val = htobe32(val);
1265 BLOGE(sc, "nvram read timeout expired "
1266 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1267 offset, cmd_flags, val);
1274 bxe_nvram_read(struct bxe_softc *sc,
1283 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1284 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1289 if ((offset + buf_size) > sc->devinfo.flash_size) {
1290 BLOGE(sc, "Invalid parameter, "
1291 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1292 offset, buf_size, sc->devinfo.flash_size);
1296 /* request access to nvram interface */
1297 rc = bxe_acquire_nvram_lock(sc);
1302 /* enable access to nvram interface */
1303 bxe_enable_nvram_access(sc);
1305 /* read the first word(s) */
1306 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1307 while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
1308 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1309 memcpy(ret_buf, &val, 4);
1311 /* advance to the next dword */
1312 offset += sizeof(uint32_t);
1313 ret_buf += sizeof(uint32_t);
1314 buf_size -= sizeof(uint32_t);
1319 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1320 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1321 memcpy(ret_buf, &val, 4);
1324 /* disable access to nvram interface */
1325 bxe_disable_nvram_access(sc);
1326 bxe_release_nvram_lock(sc);
1332 bxe_nvram_write_dword(struct bxe_softc *sc,
1339 /* build the command word */
1340 cmd_flags |= (MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR);
1342 /* need to clear DONE bit separately */
1343 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1345 /* write the data */
1346 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val);
1348 /* address of the NVRAM to write to */
1349 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1350 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1352 /* issue the write command */
1353 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1355 /* adjust timeout for emulation/FPGA */
1356 count = NVRAM_TIMEOUT_COUNT;
1357 if (CHIP_REV_IS_SLOW(sc)) {
1361 /* wait for completion */
1363 for (i = 0; i < count; i++) {
1365 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1366 if (val & MCPR_NVM_COMMAND_DONE) {
1373 BLOGE(sc, "nvram write timeout expired "
1374 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1375 offset, cmd_flags, val);
1381 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1384 bxe_nvram_write1(struct bxe_softc *sc,
1390 uint32_t align_offset;
1394 if ((offset + buf_size) > sc->devinfo.flash_size) {
1395 BLOGE(sc, "Invalid parameter, "
1396 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1397 offset, buf_size, sc->devinfo.flash_size);
1401 /* request access to nvram interface */
1402 rc = bxe_acquire_nvram_lock(sc);
1407 /* enable access to nvram interface */
1408 bxe_enable_nvram_access(sc);
1410 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1411 align_offset = (offset & ~0x03);
1412 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags);
1415 val &= ~(0xff << BYTE_OFFSET(offset));
1416 val |= (*data_buf << BYTE_OFFSET(offset));
1418 /* nvram data is returned as an array of bytes
1419 * convert it back to cpu order
1423 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags);
1426 /* disable access to nvram interface */
1427 bxe_disable_nvram_access(sc);
1428 bxe_release_nvram_lock(sc);
1434 bxe_nvram_write(struct bxe_softc *sc,
1441 uint32_t written_so_far;
1444 if (buf_size == 1) {
1445 return (bxe_nvram_write1(sc, offset, data_buf, buf_size));
1448 if ((offset & 0x03) || (buf_size & 0x03) /* || (buf_size == 0) */) {
1449 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1454 if (buf_size == 0) {
1455 return (0); /* nothing to do */
1458 if ((offset + buf_size) > sc->devinfo.flash_size) {
1459 BLOGE(sc, "Invalid parameter, "
1460 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1461 offset, buf_size, sc->devinfo.flash_size);
1465 /* request access to nvram interface */
1466 rc = bxe_acquire_nvram_lock(sc);
1471 /* enable access to nvram interface */
1472 bxe_enable_nvram_access(sc);
1475 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1476 while ((written_so_far < buf_size) && (rc == 0)) {
1477 if (written_so_far == (buf_size - sizeof(uint32_t))) {
1478 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1479 } else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) {
1480 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1481 } else if ((offset % NVRAM_PAGE_SIZE) == 0) {
1482 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1485 memcpy(&val, data_buf, 4);
1487 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags);
1489 /* advance to the next dword */
1490 offset += sizeof(uint32_t);
1491 data_buf += sizeof(uint32_t);
1492 written_so_far += sizeof(uint32_t);
1496 /* disable access to nvram interface */
1497 bxe_disable_nvram_access(sc);
1498 bxe_release_nvram_lock(sc);
1503 /* copy command into DMAE command memory and set DMAE command Go */
1505 bxe_post_dmae(struct bxe_softc *sc,
1506 struct dmae_cmd *dmae,
1509 uint32_t cmd_offset;
1512 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_cmd) * idx));
1513 for (i = 0; i < ((sizeof(struct dmae_cmd) / 4)); i++) {
1514 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1517 REG_WR(sc, dmae_reg_go_c[idx], 1);
1521 bxe_dmae_opcode_add_comp(uint32_t opcode,
1524 return (opcode | ((comp_type << DMAE_CMD_C_DST_SHIFT) |
1525 DMAE_CMD_C_TYPE_ENABLE));
1529 bxe_dmae_opcode_clr_src_reset(uint32_t opcode)
1531 return (opcode & ~DMAE_CMD_SRC_RESET);
1535 bxe_dmae_opcode(struct bxe_softc *sc,
1541 uint32_t opcode = 0;
1543 opcode |= ((src_type << DMAE_CMD_SRC_SHIFT) |
1544 (dst_type << DMAE_CMD_DST_SHIFT));
1546 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
1548 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
1550 opcode |= ((SC_VN(sc) << DMAE_CMD_E1HVN_SHIFT) |
1551 (SC_VN(sc) << DMAE_CMD_DST_VN_SHIFT));
1553 opcode |= (DMAE_COM_SET_ERR << DMAE_CMD_ERR_POLICY_SHIFT);
1556 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
1558 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
1562 opcode = bxe_dmae_opcode_add_comp(opcode, comp_type);
1569 bxe_prep_dmae_with_comp(struct bxe_softc *sc,
1570 struct dmae_cmd *dmae,
1574 memset(dmae, 0, sizeof(struct dmae_cmd));
1576 /* set the opcode */
1577 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type,
1578 TRUE, DMAE_COMP_PCI);
1580 /* fill in the completion parameters */
1581 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
1582 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
1583 dmae->comp_val = DMAE_COMP_VAL;
1586 /* issue a DMAE command over the init channel and wait for completion */
1588 bxe_issue_dmae_with_comp(struct bxe_softc *sc,
1589 struct dmae_cmd *dmae)
1591 uint32_t *wb_comp = BXE_SP(sc, wb_comp);
1592 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
1596 /* reset completion */
1599 /* post the command on the channel used for initializations */
1600 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
1602 /* wait for completion */
1605 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
1607 (sc->recovery_state != BXE_RECOVERY_DONE &&
1608 sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) {
1609 BLOGE(sc, "DMAE timeout! *wb_comp 0x%x recovery_state 0x%x\n",
1610 *wb_comp, sc->recovery_state);
1611 BXE_DMAE_UNLOCK(sc);
1612 return (DMAE_TIMEOUT);
1619 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
1620 BLOGE(sc, "DMAE PCI error! *wb_comp 0x%x recovery_state 0x%x\n",
1621 *wb_comp, sc->recovery_state);
1622 BXE_DMAE_UNLOCK(sc);
1623 return (DMAE_PCI_ERROR);
1626 BXE_DMAE_UNLOCK(sc);
1631 bxe_read_dmae(struct bxe_softc *sc,
1635 struct dmae_cmd dmae;
1639 DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32));
1641 if (!sc->dmae_ready) {
1642 data = BXE_SP(sc, wb_data[0]);
1644 for (i = 0; i < len32; i++) {
1645 data[i] = (CHIP_IS_E1(sc)) ?
1646 bxe_reg_rd_ind(sc, (src_addr + (i * 4))) :
1647 REG_RD(sc, (src_addr + (i * 4)));
1653 /* set opcode and fixed command fields */
1654 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
1656 /* fill in addresses and len */
1657 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
1658 dmae.src_addr_hi = 0;
1659 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
1660 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
1663 /* issue the command and wait for completion */
1664 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1665 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1670 bxe_write_dmae(struct bxe_softc *sc,
1671 bus_addr_t dma_addr,
1675 struct dmae_cmd dmae;
1678 if (!sc->dmae_ready) {
1679 DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32));
1681 if (CHIP_IS_E1(sc)) {
1682 ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1684 ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1690 /* set opcode and fixed command fields */
1691 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
1693 /* fill in addresses and len */
1694 dmae.src_addr_lo = U64_LO(dma_addr);
1695 dmae.src_addr_hi = U64_HI(dma_addr);
1696 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
1697 dmae.dst_addr_hi = 0;
1700 /* issue the command and wait for completion */
1701 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1702 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1707 bxe_write_dmae_phys_len(struct bxe_softc *sc,
1708 bus_addr_t phys_addr,
1712 int dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
1715 while (len > dmae_wr_max) {
1717 (phys_addr + offset), /* src DMA address */
1718 (addr + offset), /* dst GRC address */
1720 offset += (dmae_wr_max * 4);
1725 (phys_addr + offset), /* src DMA address */
1726 (addr + offset), /* dst GRC address */
1731 bxe_set_ctx_validation(struct bxe_softc *sc,
1732 struct eth_context *cxt,
1735 /* ustorm cxt validation */
1736 cxt->ustorm_ag_context.cdu_usage =
1737 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1738 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
1739 /* xcontext validation */
1740 cxt->xstorm_ag_context.cdu_reserved =
1741 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1742 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
1746 bxe_storm_memset_hc_timeout(struct bxe_softc *sc,
1753 (BAR_CSTRORM_INTMEM +
1754 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
1756 REG_WR8(sc, addr, ticks);
1759 "port %d fw_sb_id %d sb_index %d ticks %d\n",
1760 port, fw_sb_id, sb_index, ticks);
1764 bxe_storm_memset_hc_disable(struct bxe_softc *sc,
1770 uint32_t enable_flag =
1771 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
1773 (BAR_CSTRORM_INTMEM +
1774 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
1778 flags = REG_RD8(sc, addr);
1779 flags &= ~HC_INDEX_DATA_HC_ENABLED;
1780 flags |= enable_flag;
1781 REG_WR8(sc, addr, flags);
1784 "port %d fw_sb_id %d sb_index %d disable %d\n",
1785 port, fw_sb_id, sb_index, disable);
1789 bxe_update_coalesce_sb_index(struct bxe_softc *sc,
1795 int port = SC_PORT(sc);
1796 uint8_t ticks = (usec / 4); /* XXX ??? */
1798 bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks);
1800 disable = (disable) ? 1 : ((usec) ? 0 : 1);
1801 bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable);
1805 elink_cb_udelay(struct bxe_softc *sc,
1812 elink_cb_reg_read(struct bxe_softc *sc,
1815 return (REG_RD(sc, reg_addr));
1819 elink_cb_reg_write(struct bxe_softc *sc,
1823 REG_WR(sc, reg_addr, val);
1827 elink_cb_reg_wb_write(struct bxe_softc *sc,
1832 REG_WR_DMAE(sc, offset, wb_write, len);
1836 elink_cb_reg_wb_read(struct bxe_softc *sc,
1841 REG_RD_DMAE(sc, offset, wb_write, len);
1845 elink_cb_path_id(struct bxe_softc *sc)
1847 return (SC_PATH(sc));
1851 elink_cb_event_log(struct bxe_softc *sc,
1852 const elink_log_id_t elink_log_id,
1856 BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id);
1860 bxe_set_spio(struct bxe_softc *sc,
1866 /* Only 2 SPIOs are configurable */
1867 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
1868 BLOGE(sc, "Invalid SPIO 0x%x mode 0x%x\n", spio, mode);
1872 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1874 /* read SPIO and mask except the float bits */
1875 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
1878 case MISC_SPIO_OUTPUT_LOW:
1879 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio);
1880 /* clear FLOAT and set CLR */
1881 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1882 spio_reg |= (spio << MISC_SPIO_CLR_POS);
1885 case MISC_SPIO_OUTPUT_HIGH:
1886 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio);
1887 /* clear FLOAT and set SET */
1888 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1889 spio_reg |= (spio << MISC_SPIO_SET_POS);
1892 case MISC_SPIO_INPUT_HI_Z:
1893 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio);
1895 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
1902 REG_WR(sc, MISC_REG_SPIO, spio_reg);
1903 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1909 bxe_gpio_read(struct bxe_softc *sc,
1913 /* The GPIO should be swapped if swap register is set and active */
1914 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1915 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1916 int gpio_shift = (gpio_num +
1917 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
1918 uint32_t gpio_mask = (1 << gpio_shift);
1921 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1922 BLOGE(sc, "Invalid GPIO %d port 0x%x gpio_port %d gpio_shift %d"
1923 " gpio_mask 0x%x\n", gpio_num, port, gpio_port, gpio_shift,
1928 /* read GPIO value */
1929 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
1931 /* get the requested pin value */
1932 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
1936 bxe_gpio_write(struct bxe_softc *sc,
1941 /* The GPIO should be swapped if swap register is set and active */
1942 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1943 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1944 int gpio_shift = (gpio_num +
1945 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
1946 uint32_t gpio_mask = (1 << gpio_shift);
1949 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1950 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
1951 " gpio_shift %d gpio_mask 0x%x\n",
1952 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
1956 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
1958 /* read GPIO and mask except the float bits */
1959 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1962 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1964 "Set GPIO %d (shift %d) -> output low\n",
1965 gpio_num, gpio_shift);
1966 /* clear FLOAT and set CLR */
1967 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1968 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1971 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1973 "Set GPIO %d (shift %d) -> output high\n",
1974 gpio_num, gpio_shift);
1975 /* clear FLOAT and set SET */
1976 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1977 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1980 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1982 "Set GPIO %d (shift %d) -> input\n",
1983 gpio_num, gpio_shift);
1985 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1992 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
1993 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
1999 bxe_gpio_mult_write(struct bxe_softc *sc,
2005 /* any port swapping should be handled by caller */
2007 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2009 /* read GPIO and mask except the float bits */
2010 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
2011 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2012 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2013 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2016 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2017 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins);
2019 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2022 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2023 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins);
2025 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2028 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2029 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins);
2031 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2035 BLOGE(sc, "Invalid GPIO mode assignment pins 0x%x mode 0x%x"
2036 " gpio_reg 0x%x\n", pins, mode, gpio_reg);
2037 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2041 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
2042 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2048 bxe_gpio_int_write(struct bxe_softc *sc,
2053 /* The GPIO should be swapped if swap register is set and active */
2054 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
2055 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
2056 int gpio_shift = (gpio_num +
2057 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
2058 uint32_t gpio_mask = (1 << gpio_shift);
2061 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2062 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
2063 " gpio_shift %d gpio_mask 0x%x\n",
2064 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
2068 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2071 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
2074 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2076 "Clear GPIO INT %d (shift %d) -> output low\n",
2077 gpio_num, gpio_shift);
2078 /* clear SET and set CLR */
2079 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2080 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2083 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2085 "Set GPIO INT %d (shift %d) -> output high\n",
2086 gpio_num, gpio_shift);
2087 /* clear CLR and set SET */
2088 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2089 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2096 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
2097 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2103 elink_cb_gpio_read(struct bxe_softc *sc,
2107 return (bxe_gpio_read(sc, gpio_num, port));
2111 elink_cb_gpio_write(struct bxe_softc *sc,
2113 uint8_t mode, /* 0=low 1=high */
2116 return (bxe_gpio_write(sc, gpio_num, mode, port));
2120 elink_cb_gpio_mult_write(struct bxe_softc *sc,
2122 uint8_t mode) /* 0=low 1=high */
2124 return (bxe_gpio_mult_write(sc, pins, mode));
2128 elink_cb_gpio_int_write(struct bxe_softc *sc,
2130 uint8_t mode, /* 0=low 1=high */
2133 return (bxe_gpio_int_write(sc, gpio_num, mode, port));
2137 elink_cb_notify_link_changed(struct bxe_softc *sc)
2139 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
2140 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
2143 /* send the MCP a request, block until there is a reply */
2145 elink_cb_fw_command(struct bxe_softc *sc,
2149 int mb_idx = SC_FW_MB_IDX(sc);
2153 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
2158 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
2159 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
2162 "wrote command 0x%08x to FW MB param 0x%08x\n",
2163 (command | seq), param);
2165 /* Let the FW do it's magic. GIve it up to 5 seconds... */
2167 DELAY(delay * 1000);
2168 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
2169 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2172 "[after %d ms] read 0x%x seq 0x%x from FW MB\n",
2173 cnt*delay, rc, seq);
2175 /* is this a reply to our command? */
2176 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
2177 rc &= FW_MSG_CODE_MASK;
2180 BLOGE(sc, "FW failed to respond!\n");
2181 // XXX bxe_fw_dump(sc);
2185 BXE_FWMB_UNLOCK(sc);
2190 bxe_fw_command(struct bxe_softc *sc,
2194 return (elink_cb_fw_command(sc, command, param));
2198 __storm_memset_dma_mapping(struct bxe_softc *sc,
2202 REG_WR(sc, addr, U64_LO(mapping));
2203 REG_WR(sc, (addr + 4), U64_HI(mapping));
2207 storm_memset_spq_addr(struct bxe_softc *sc,
2211 uint32_t addr = (XSEM_REG_FAST_MEMORY +
2212 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
2213 __storm_memset_dma_mapping(sc, addr, mapping);
2217 storm_memset_vf_to_pf(struct bxe_softc *sc,
2221 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2222 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2223 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2224 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2228 storm_memset_func_en(struct bxe_softc *sc,
2232 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2233 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2234 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2235 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2239 storm_memset_eq_data(struct bxe_softc *sc,
2240 struct event_ring_data *eq_data,
2246 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
2247 size = sizeof(struct event_ring_data);
2248 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data);
2252 storm_memset_eq_prod(struct bxe_softc *sc,
2256 uint32_t addr = (BAR_CSTRORM_INTMEM +
2257 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
2258 REG_WR16(sc, addr, eq_prod);
2262 * Post a slowpath command.
2264 * A slowpath command is used to propogate a configuration change through
2265 * the controller in a controlled manner, allowing each STORM processor and
2266 * other H/W blocks to phase in the change. The commands sent on the
2267 * slowpath are referred to as ramrods. Depending on the ramrod used the
2268 * completion of the ramrod will occur in different ways. Here's a
2269 * breakdown of ramrods and how they complete:
2271 * RAMROD_CMD_ID_ETH_PORT_SETUP
2272 * Used to setup the leading connection on a port. Completes on the
2273 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
2275 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
2276 * Used to setup an additional connection on a port. Completes on the
2277 * RCQ of the multi-queue/RSS connection being initialized.
2279 * RAMROD_CMD_ID_ETH_STAT_QUERY
2280 * Used to force the storm processors to update the statistics database
2281 * in host memory. This ramrod is send on the leading connection CID and
2282 * completes as an index increment of the CSTORM on the default status
2285 * RAMROD_CMD_ID_ETH_UPDATE
2286 * Used to update the state of the leading connection, usually to udpate
2287 * the RSS indirection table. Completes on the RCQ of the leading
2288 * connection. (Not currently used under FreeBSD until OS support becomes
2291 * RAMROD_CMD_ID_ETH_HALT
2292 * Used when tearing down a connection prior to driver unload. Completes
2293 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
2294 * use this on the leading connection.
2296 * RAMROD_CMD_ID_ETH_SET_MAC
2297 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
2298 * the RCQ of the leading connection.
2300 * RAMROD_CMD_ID_ETH_CFC_DEL
2301 * Used when tearing down a conneciton prior to driver unload. Completes
2302 * on the RCQ of the leading connection (since the current connection
2303 * has been completely removed from controller memory).
2305 * RAMROD_CMD_ID_ETH_PORT_DEL
2306 * Used to tear down the leading connection prior to driver unload,
2307 * typically fp[0]. Completes as an index increment of the CSTORM on the
2308 * default status block.
2310 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
2311 * Used for connection offload. Completes on the RCQ of the multi-queue
2312 * RSS connection that is being offloaded. (Not currently used under
2315 * There can only be one command pending per function.
2318 * 0 = Success, !0 = Failure.
2321 /* must be called under the spq lock */
2323 struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc)
2325 struct eth_spe *next_spe = sc->spq_prod_bd;
2327 if (sc->spq_prod_bd == sc->spq_last_bd) {
2328 /* wrap back to the first eth_spq */
2329 sc->spq_prod_bd = sc->spq;
2330 sc->spq_prod_idx = 0;
2339 /* must be called under the spq lock */
2341 void bxe_sp_prod_update(struct bxe_softc *sc)
2343 int func = SC_FUNC(sc);
2346 * Make sure that BD data is updated before writing the producer.
2347 * BD data is written to the memory, the producer is read from the
2348 * memory, thus we need a full memory barrier to ensure the ordering.
2352 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
2355 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
2356 BUS_SPACE_BARRIER_WRITE);
2360 * bxe_is_contextless_ramrod - check if the current command ends on EQ
2362 * @cmd: command to check
2363 * @cmd_type: command type
2366 int bxe_is_contextless_ramrod(int cmd,
2369 if ((cmd_type == NONE_CONNECTION_TYPE) ||
2370 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
2371 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
2372 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
2373 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
2374 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
2375 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
2383 * bxe_sp_post - place a single command on an SP ring
2385 * @sc: driver handle
2386 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
2387 * @cid: SW CID the command is related to
2388 * @data_hi: command private data address (high 32 bits)
2389 * @data_lo: command private data address (low 32 bits)
2390 * @cmd_type: command type (e.g. NONE, ETH)
2392 * SP data is handled as if it's always an address pair, thus data fields are
2393 * not swapped to little endian in upper functions. Instead this function swaps
2394 * data as if it's two uint32 fields.
2397 bxe_sp_post(struct bxe_softc *sc,
2404 struct eth_spe *spe;
2408 common = bxe_is_contextless_ramrod(command, cmd_type);
2413 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
2414 BLOGE(sc, "EQ ring is full!\n");
2419 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
2420 BLOGE(sc, "SPQ ring is full!\n");
2426 spe = bxe_sp_get_next(sc);
2428 /* CID needs port number to be encoded int it */
2429 spe->hdr.conn_and_cmd_data =
2430 htole32((command << SPE_HDR_T_CMD_ID_SHIFT) | HW_CID(sc, cid));
2432 type = (cmd_type << SPE_HDR_T_CONN_TYPE_SHIFT) & SPE_HDR_T_CONN_TYPE;
2434 /* TBD: Check if it works for VFs */
2435 type |= ((SC_FUNC(sc) << SPE_HDR_T_FUNCTION_ID_SHIFT) &
2436 SPE_HDR_T_FUNCTION_ID);
2438 spe->hdr.type = htole16(type);
2440 spe->data.update_data_addr.hi = htole32(data_hi);
2441 spe->data.update_data_addr.lo = htole32(data_lo);
2444 * It's ok if the actual decrement is issued towards the memory
2445 * somewhere between the lock and unlock. Thus no more explict
2446 * memory barrier is needed.
2449 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
2451 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
2454 BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr);
2455 BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n",
2456 BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata));
2458 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n",
2460 (uint32_t)U64_HI(sc->spq_dma.paddr),
2461 (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq),
2468 atomic_load_acq_long(&sc->cq_spq_left),
2469 atomic_load_acq_long(&sc->eq_spq_left));
2471 bxe_sp_prod_update(sc);
2478 * bxe_debug_print_ind_table - prints the indirection table configuration.
2480 * @sc: driver hanlde
2481 * @p: pointer to rss configuration
2485 * FreeBSD Device probe function.
2487 * Compares the device found to the driver's list of supported devices and
2488 * reports back to the bsd loader whether this is the right driver for the device.
2489 * This is the driver entry function called from the "kldload" command.
2492 * BUS_PROBE_DEFAULT on success, positive value on failure.
2495 bxe_probe(device_t dev)
2497 struct bxe_softc *sc;
2498 struct bxe_device_type *t;
2500 uint16_t did, sdid, svid, vid;
2502 /* Find our device structure */
2503 sc = device_get_softc(dev);
2507 /* Get the data for the device to be probed. */
2508 vid = pci_get_vendor(dev);
2509 did = pci_get_device(dev);
2510 svid = pci_get_subvendor(dev);
2511 sdid = pci_get_subdevice(dev);
2514 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
2515 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
2517 /* Look through the list of known devices for a match. */
2518 while (t->bxe_name != NULL) {
2519 if ((vid == t->bxe_vid) && (did == t->bxe_did) &&
2520 ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) &&
2521 ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) {
2522 descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
2523 if (descbuf == NULL)
2526 /* Print out the device identity. */
2527 snprintf(descbuf, BXE_DEVDESC_MAX,
2528 "%s (%c%d) BXE v:%s\n", t->bxe_name,
2529 (((pci_read_config(dev, PCIR_REVID, 4) &
2531 (pci_read_config(dev, PCIR_REVID, 4) & 0xf),
2532 BXE_DRIVER_VERSION);
2534 device_set_desc_copy(dev, descbuf);
2535 free(descbuf, M_TEMP);
2536 return (BUS_PROBE_DEFAULT);
2545 bxe_init_mutexes(struct bxe_softc *sc)
2547 #ifdef BXE_CORE_LOCK_SX
2548 snprintf(sc->core_sx_name, sizeof(sc->core_sx_name),
2549 "bxe%d_core_lock", sc->unit);
2550 sx_init(&sc->core_sx, sc->core_sx_name);
2552 snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name),
2553 "bxe%d_core_lock", sc->unit);
2554 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF);
2557 snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name),
2558 "bxe%d_sp_lock", sc->unit);
2559 mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF);
2561 snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name),
2562 "bxe%d_dmae_lock", sc->unit);
2563 mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF);
2565 snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name),
2566 "bxe%d_phy_lock", sc->unit);
2567 mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF);
2569 snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name),
2570 "bxe%d_fwmb_lock", sc->unit);
2571 mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF);
2573 snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name),
2574 "bxe%d_print_lock", sc->unit);
2575 mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF);
2577 snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name),
2578 "bxe%d_stats_lock", sc->unit);
2579 mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF);
2581 snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name),
2582 "bxe%d_mcast_lock", sc->unit);
2583 mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF);
2587 bxe_release_mutexes(struct bxe_softc *sc)
2589 #ifdef BXE_CORE_LOCK_SX
2590 sx_destroy(&sc->core_sx);
2592 if (mtx_initialized(&sc->core_mtx)) {
2593 mtx_destroy(&sc->core_mtx);
2597 if (mtx_initialized(&sc->sp_mtx)) {
2598 mtx_destroy(&sc->sp_mtx);
2601 if (mtx_initialized(&sc->dmae_mtx)) {
2602 mtx_destroy(&sc->dmae_mtx);
2605 if (mtx_initialized(&sc->port.phy_mtx)) {
2606 mtx_destroy(&sc->port.phy_mtx);
2609 if (mtx_initialized(&sc->fwmb_mtx)) {
2610 mtx_destroy(&sc->fwmb_mtx);
2613 if (mtx_initialized(&sc->print_mtx)) {
2614 mtx_destroy(&sc->print_mtx);
2617 if (mtx_initialized(&sc->stats_mtx)) {
2618 mtx_destroy(&sc->stats_mtx);
2621 if (mtx_initialized(&sc->mcast_mtx)) {
2622 mtx_destroy(&sc->mcast_mtx);
2627 bxe_tx_disable(struct bxe_softc* sc)
2629 struct ifnet *ifp = sc->ifnet;
2631 /* tell the stack the driver is stopped and TX queue is full */
2633 ifp->if_drv_flags = 0;
2638 bxe_drv_pulse(struct bxe_softc *sc)
2640 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
2641 sc->fw_drv_pulse_wr_seq);
2644 static inline uint16_t
2645 bxe_tx_avail(struct bxe_softc *sc,
2646 struct bxe_fastpath *fp)
2652 prod = fp->tx_bd_prod;
2653 cons = fp->tx_bd_cons;
2655 used = SUB_S16(prod, cons);
2657 return (int16_t)(sc->tx_ring_size) - used;
2661 bxe_tx_queue_has_work(struct bxe_fastpath *fp)
2665 mb(); /* status block fields can change */
2666 hw_cons = le16toh(*fp->tx_cons_sb);
2667 return (hw_cons != fp->tx_pkt_cons);
2670 static inline uint8_t
2671 bxe_has_tx_work(struct bxe_fastpath *fp)
2673 /* expand this for multi-cos if ever supported */
2674 return (bxe_tx_queue_has_work(fp)) ? TRUE : FALSE;
2678 bxe_has_rx_work(struct bxe_fastpath *fp)
2680 uint16_t rx_cq_cons_sb;
2682 mb(); /* status block fields can change */
2683 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
2684 if ((rx_cq_cons_sb & RCQ_MAX) == RCQ_MAX)
2686 return (fp->rx_cq_cons != rx_cq_cons_sb);
2690 bxe_sp_event(struct bxe_softc *sc,
2691 struct bxe_fastpath *fp,
2692 union eth_rx_cqe *rr_cqe)
2694 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2695 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2696 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
2697 struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
2699 BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n",
2700 fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type);
2703 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
2704 BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid);
2705 drv_cmd = ECORE_Q_CMD_UPDATE;
2708 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
2709 BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid);
2710 drv_cmd = ECORE_Q_CMD_SETUP;
2713 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
2714 BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
2715 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
2718 case (RAMROD_CMD_ID_ETH_HALT):
2719 BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid);
2720 drv_cmd = ECORE_Q_CMD_HALT;
2723 case (RAMROD_CMD_ID_ETH_TERMINATE):
2724 BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid);
2725 drv_cmd = ECORE_Q_CMD_TERMINATE;
2728 case (RAMROD_CMD_ID_ETH_EMPTY):
2729 BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid);
2730 drv_cmd = ECORE_Q_CMD_EMPTY;
2734 BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n",
2735 command, fp->index);
2739 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
2740 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
2742 * q_obj->complete_cmd() failure means that this was
2743 * an unexpected completion.
2745 * In this case we don't want to increase the sc->spq_left
2746 * because apparently we haven't sent this command the first
2749 // bxe_panic(sc, ("Unexpected SP completion\n"));
2753 atomic_add_acq_long(&sc->cq_spq_left, 1);
2755 BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n",
2756 atomic_load_acq_long(&sc->cq_spq_left));
2760 * The current mbuf is part of an aggregation. Move the mbuf into the TPA
2761 * aggregation queue, put an empty mbuf back onto the receive chain, and mark
2762 * the current aggregation queue as in-progress.
2765 bxe_tpa_start(struct bxe_softc *sc,
2766 struct bxe_fastpath *fp,
2770 struct eth_fast_path_rx_cqe *cqe)
2772 struct bxe_sw_rx_bd tmp_bd;
2773 struct bxe_sw_rx_bd *rx_buf;
2774 struct eth_rx_bd *rx_bd;
2776 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
2779 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START "
2780 "cons=%d prod=%d\n",
2781 fp->index, queue, cons, prod);
2783 max_agg_queues = MAX_AGG_QS(sc);
2785 KASSERT((queue < max_agg_queues),
2786 ("fp[%02d] invalid aggr queue (%d >= %d)!",
2787 fp->index, queue, max_agg_queues));
2789 KASSERT((tpa_info->state == BXE_TPA_STATE_STOP),
2790 ("fp[%02d].tpa[%02d] starting aggr on queue not stopped!",
2793 /* copy the existing mbuf and mapping from the TPA pool */
2794 tmp_bd = tpa_info->bd;
2796 if (tmp_bd.m == NULL) {
2799 tmp = (uint32_t *)cqe;
2801 BLOGE(sc, "fp[%02d].tpa[%02d] cons[%d] prod[%d]mbuf not allocated!\n",
2802 fp->index, queue, cons, prod);
2803 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2804 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2806 /* XXX Error handling? */
2810 /* change the TPA queue to the start state */
2811 tpa_info->state = BXE_TPA_STATE_START;
2812 tpa_info->placement_offset = cqe->placement_offset;
2813 tpa_info->parsing_flags = le16toh(cqe->pars_flags.flags);
2814 tpa_info->vlan_tag = le16toh(cqe->vlan_tag);
2815 tpa_info->len_on_bd = le16toh(cqe->len_on_bd);
2817 fp->rx_tpa_queue_used |= (1 << queue);
2820 * If all the buffer descriptors are filled with mbufs then fill in
2821 * the current consumer index with a new BD. Else if a maximum Rx
2822 * buffer limit is imposed then fill in the next producer index.
2824 index = (sc->max_rx_bufs != RX_BD_USABLE) ?
2827 /* move the received mbuf and mapping to TPA pool */
2828 tpa_info->bd = fp->rx_mbuf_chain[cons];
2830 /* release any existing RX BD mbuf mappings */
2831 if (cons != index) {
2832 rx_buf = &fp->rx_mbuf_chain[cons];
2834 if (rx_buf->m_map != NULL) {
2835 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
2836 BUS_DMASYNC_POSTREAD);
2837 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
2841 * We get here when the maximum number of rx buffers is less than
2842 * RX_BD_USABLE. The mbuf is already saved above so it's OK to NULL
2843 * it out here without concern of a memory leak.
2845 fp->rx_mbuf_chain[cons].m = NULL;
2848 /* update the Rx SW BD with the mbuf info from the TPA pool */
2849 fp->rx_mbuf_chain[index] = tmp_bd;
2851 /* update the Rx BD with the empty mbuf phys address from the TPA pool */
2852 rx_bd = &fp->rx_chain[index];
2853 rx_bd->addr_hi = htole32(U64_HI(tpa_info->seg.ds_addr));
2854 rx_bd->addr_lo = htole32(U64_LO(tpa_info->seg.ds_addr));
2858 * When a TPA aggregation is completed, loop through the individual mbufs
2859 * of the aggregation, combining them into a single mbuf which will be sent
2860 * up the stack. Refill all freed SGEs with mbufs as we go along.
2863 bxe_fill_frag_mbuf(struct bxe_softc *sc,
2864 struct bxe_fastpath *fp,
2865 struct bxe_sw_tpa_info *tpa_info,
2869 struct eth_end_agg_rx_cqe *cqe,
2872 struct mbuf *m_frag;
2873 uint32_t frag_len, frag_size, i;
2878 frag_size = le16toh(cqe->pkt_len) - tpa_info->len_on_bd;
2881 "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n",
2882 fp->index, queue, tpa_info->len_on_bd, frag_size, pages);
2884 /* make sure the aggregated frame is not too big to handle */
2885 if (pages > 8 * PAGES_PER_SGE) {
2887 uint32_t *tmp = (uint32_t *)cqe;
2889 BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! "
2890 "pkt_len=%d len_on_bd=%d frag_size=%d\n",
2891 fp->index, cqe_idx, pages, le16toh(cqe->pkt_len),
2892 tpa_info->len_on_bd, frag_size);
2894 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2895 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2897 bxe_panic(sc, ("sge page count error\n"));
2902 * Scan through the scatter gather list pulling individual mbufs into a
2903 * single mbuf for the host stack.
2905 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
2906 sge_idx = RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[j]));
2909 * Firmware gives the indices of the SGE as if the ring is an array
2910 * (meaning that the "next" element will consume 2 indices).
2912 frag_len = min(frag_size, (uint32_t)(SGE_PAGES));
2914 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d "
2915 "sge_idx=%d frag_size=%d frag_len=%d\n",
2916 fp->index, queue, i, j, sge_idx, frag_size, frag_len);
2918 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
2920 /* allocate a new mbuf for the SGE */
2921 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
2923 /* Leave all remaining SGEs in the ring! */
2927 /* update the fragment length */
2928 m_frag->m_len = frag_len;
2930 /* concatenate the fragment to the head mbuf */
2932 fp->eth_q_stats.mbuf_alloc_sge--;
2934 /* update the TPA mbuf size and remaining fragment size */
2935 m->m_pkthdr.len += frag_len;
2936 frag_size -= frag_len;
2940 "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n",
2941 fp->index, queue, frag_size);
2947 bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp)
2951 for (i = 1; i <= RX_SGE_NUM_PAGES; i++) {
2952 int idx = RX_SGE_TOTAL_PER_PAGE * i - 1;
2954 for (j = 0; j < 2; j++) {
2955 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
2962 bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp)
2964 /* set the mask to all 1's, it's faster to compare to 0 than to 0xf's */
2965 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
2968 * Clear the two last indices in the page to 1. These are the indices that
2969 * correspond to the "next" element, hence will never be indicated and
2970 * should be removed from the calculations.
2972 bxe_clear_sge_mask_next_elems(fp);
2976 bxe_update_last_max_sge(struct bxe_fastpath *fp,
2979 uint16_t last_max = fp->last_max_sge;
2981 if (SUB_S16(idx, last_max) > 0) {
2982 fp->last_max_sge = idx;
2987 bxe_update_sge_prod(struct bxe_softc *sc,
2988 struct bxe_fastpath *fp,
2990 union eth_sgl_or_raw_data *cqe)
2992 uint16_t last_max, last_elem, first_elem;
3000 /* first mark all used pages */
3001 for (i = 0; i < sge_len; i++) {
3002 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
3003 RX_SGE(le16toh(cqe->sgl[i])));
3007 "fp[%02d] fp_cqe->sgl[%d] = %d\n",
3008 fp->index, sge_len - 1,
3009 le16toh(cqe->sgl[sge_len - 1]));
3011 /* assume that the last SGE index is the biggest */
3012 bxe_update_last_max_sge(fp,
3013 le16toh(cqe->sgl[sge_len - 1]));
3015 last_max = RX_SGE(fp->last_max_sge);
3016 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
3017 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
3019 /* if ring is not full */
3020 if (last_elem + 1 != first_elem) {
3024 /* now update the prod */
3025 for (i = first_elem; i != last_elem; i = RX_SGE_NEXT_MASK_ELEM(i)) {
3026 if (__predict_true(fp->sge_mask[i])) {
3030 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
3031 delta += BIT_VEC64_ELEM_SZ;
3035 fp->rx_sge_prod += delta;
3036 /* clear page-end entries */
3037 bxe_clear_sge_mask_next_elems(fp);
3041 "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n",
3042 fp->index, fp->last_max_sge, fp->rx_sge_prod);
3046 * The aggregation on the current TPA queue has completed. Pull the individual
3047 * mbuf fragments together into a single mbuf, perform all necessary checksum
3048 * calculations, and send the resuting mbuf to the stack.
3051 bxe_tpa_stop(struct bxe_softc *sc,
3052 struct bxe_fastpath *fp,
3053 struct bxe_sw_tpa_info *tpa_info,
3056 struct eth_end_agg_rx_cqe *cqe,
3059 struct ifnet *ifp = sc->ifnet;
3064 "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n",
3065 fp->index, queue, tpa_info->placement_offset,
3066 le16toh(cqe->pkt_len), pages, tpa_info->vlan_tag);
3070 /* allocate a replacement before modifying existing mbuf */
3071 rc = bxe_alloc_rx_tpa_mbuf(fp, queue);
3073 /* drop the frame and log an error */
3074 fp->eth_q_stats.rx_soft_errors++;
3075 goto bxe_tpa_stop_exit;
3078 /* we have a replacement, fixup the current mbuf */
3079 m_adj(m, tpa_info->placement_offset);
3080 m->m_pkthdr.len = m->m_len = tpa_info->len_on_bd;
3082 /* mark the checksums valid (taken care of by the firmware) */
3083 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3084 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3085 m->m_pkthdr.csum_data = 0xffff;
3086 m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED |
3091 /* aggregate all of the SGEs into a single mbuf */
3092 rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx);
3094 /* drop the packet and log an error */
3095 fp->eth_q_stats.rx_soft_errors++;
3098 if (tpa_info->parsing_flags & PARSING_FLAGS_INNER_VLAN_EXIST) {
3099 m->m_pkthdr.ether_vtag = tpa_info->vlan_tag;
3100 m->m_flags |= M_VLANTAG;
3103 /* assign packet to this interface interface */
3104 m->m_pkthdr.rcvif = ifp;
3106 #if __FreeBSD_version >= 800000
3107 /* specify what RSS queue was used for this flow */
3108 m->m_pkthdr.flowid = fp->index;
3113 fp->eth_q_stats.rx_tpa_pkts++;
3115 /* pass the frame to the stack */
3116 (*ifp->if_input)(ifp, m);
3119 /* we passed an mbuf up the stack or dropped the frame */
3120 fp->eth_q_stats.mbuf_alloc_tpa--;
3124 fp->rx_tpa_info[queue].state = BXE_TPA_STATE_STOP;
3125 fp->rx_tpa_queue_used &= ~(1 << queue);
3130 struct bxe_fastpath *fp,
3134 struct eth_fast_path_rx_cqe *cqe_fp)
3136 struct mbuf *m_frag;
3137 uint16_t frags, frag_len;
3138 uint16_t sge_idx = 0;
3143 /* adjust the mbuf */
3146 frag_size = len - lenonbd;
3147 frags = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3149 for (i = 0, j = 0; i < frags; i += PAGES_PER_SGE, j++) {
3150 sge_idx = RX_SGE(le16toh(cqe_fp->sgl_or_raw_data.sgl[j]));
3152 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
3153 frag_len = min(frag_size, (uint32_t)(SGE_PAGE_SIZE));
3154 m_frag->m_len = frag_len;
3156 /* allocate a new mbuf for the SGE */
3157 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
3159 /* Leave all remaining SGEs in the ring! */
3162 fp->eth_q_stats.mbuf_alloc_sge--;
3164 /* concatenate the fragment to the head mbuf */
3167 frag_size -= frag_len;
3170 bxe_update_sge_prod(fp->sc, fp, frags, &cqe_fp->sgl_or_raw_data);
3176 bxe_rxeof(struct bxe_softc *sc,
3177 struct bxe_fastpath *fp)
3179 struct ifnet *ifp = sc->ifnet;
3180 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
3181 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
3187 /* CQ "next element" is of the size of the regular element */
3188 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
3189 if ((hw_cq_cons & RCQ_USABLE_PER_PAGE) == RCQ_USABLE_PER_PAGE) {
3193 bd_cons = fp->rx_bd_cons;
3194 bd_prod = fp->rx_bd_prod;
3195 bd_prod_fw = bd_prod;
3196 sw_cq_cons = fp->rx_cq_cons;
3197 sw_cq_prod = fp->rx_cq_prod;
3200 * Memory barrier necessary as speculative reads of the rx
3201 * buffer can be ahead of the index in the status block
3206 "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n",
3207 fp->index, hw_cq_cons, sw_cq_cons);
3209 while (sw_cq_cons != hw_cq_cons) {
3210 struct bxe_sw_rx_bd *rx_buf = NULL;
3211 union eth_rx_cqe *cqe;
3212 struct eth_fast_path_rx_cqe *cqe_fp;
3213 uint8_t cqe_fp_flags;
3214 enum eth_rx_cqe_type cqe_fp_type;
3215 uint16_t len, lenonbd, pad;
3216 struct mbuf *m = NULL;
3218 comp_ring_cons = RCQ(sw_cq_cons);
3219 bd_prod = RX_BD(bd_prod);
3220 bd_cons = RX_BD(bd_cons);
3222 cqe = &fp->rcq_chain[comp_ring_cons];
3223 cqe_fp = &cqe->fast_path_cqe;
3224 cqe_fp_flags = cqe_fp->type_error_flags;
3225 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
3228 "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d "
3229 "BD prod=%d cons=%d CQE type=0x%x err=0x%x "
3230 "status=0x%x rss_hash=0x%x vlan=0x%x len=%u lenonbd=%u\n",
3236 CQE_TYPE(cqe_fp_flags),
3238 cqe_fp->status_flags,
3239 le32toh(cqe_fp->rss_hash_result),
3240 le16toh(cqe_fp->vlan_tag),
3241 le16toh(cqe_fp->pkt_len_or_gro_seg_len),
3242 le16toh(cqe_fp->len_on_bd));
3244 /* is this a slowpath msg? */
3245 if (__predict_false(CQE_TYPE_SLOW(cqe_fp_type))) {
3246 bxe_sp_event(sc, fp, cqe);
3250 rx_buf = &fp->rx_mbuf_chain[bd_cons];
3252 if (!CQE_TYPE_FAST(cqe_fp_type)) {
3253 struct bxe_sw_tpa_info *tpa_info;
3254 uint16_t frag_size, pages;
3257 if (CQE_TYPE_START(cqe_fp_type)) {
3258 bxe_tpa_start(sc, fp, cqe_fp->queue_index,
3259 bd_cons, bd_prod, cqe_fp);
3260 m = NULL; /* packet not ready yet */
3264 KASSERT(CQE_TYPE_STOP(cqe_fp_type),
3265 ("CQE type is not STOP! (0x%x)\n", cqe_fp_type));
3267 queue = cqe->end_agg_cqe.queue_index;
3268 tpa_info = &fp->rx_tpa_info[queue];
3270 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n",
3273 frag_size = (le16toh(cqe->end_agg_cqe.pkt_len) -
3274 tpa_info->len_on_bd);
3275 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3277 bxe_tpa_stop(sc, fp, tpa_info, queue, pages,
3278 &cqe->end_agg_cqe, comp_ring_cons);
3280 bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe.sgl_or_raw_data);
3287 /* is this an error packet? */
3288 if (__predict_false(cqe_fp_flags &
3289 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
3290 BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons);
3291 fp->eth_q_stats.rx_soft_errors++;
3295 len = le16toh(cqe_fp->pkt_len_or_gro_seg_len);
3296 lenonbd = le16toh(cqe_fp->len_on_bd);
3297 pad = cqe_fp->placement_offset;
3301 if (__predict_false(m == NULL)) {
3302 BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n",
3303 bd_cons, fp->index);
3307 /* XXX double copy if packet length under a threshold */
3310 * If all the buffer descriptors are filled with mbufs then fill in
3311 * the current consumer index with a new BD. Else if a maximum Rx
3312 * buffer limit is imposed then fill in the next producer index.
3314 rc = bxe_alloc_rx_bd_mbuf(fp, bd_cons,
3315 (sc->max_rx_bufs != RX_BD_USABLE) ?
3319 /* we simply reuse the received mbuf and don't post it to the stack */
3322 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
3324 fp->eth_q_stats.rx_soft_errors++;
3326 if (sc->max_rx_bufs != RX_BD_USABLE) {
3327 /* copy this consumer index to the producer index */
3328 memcpy(&fp->rx_mbuf_chain[bd_prod], rx_buf,
3329 sizeof(struct bxe_sw_rx_bd));
3330 memset(rx_buf, 0, sizeof(struct bxe_sw_rx_bd));
3336 /* current mbuf was detached from the bd */
3337 fp->eth_q_stats.mbuf_alloc_rx--;
3339 /* we allocated a replacement mbuf, fixup the current one */
3341 m->m_pkthdr.len = m->m_len = len;
3343 if ((len > 60) && (len > lenonbd)) {
3344 fp->eth_q_stats.rx_bxe_service_rxsgl++;
3345 rc = bxe_service_rxsgl(fp, len, lenonbd, m, cqe_fp);
3348 fp->eth_q_stats.rx_jumbo_sge_pkts++;
3349 } else if (lenonbd < len) {
3350 fp->eth_q_stats.rx_erroneous_jumbo_sge_pkts++;
3353 /* assign packet to this interface interface */
3354 m->m_pkthdr.rcvif = ifp;
3356 /* assume no hardware checksum has complated */
3357 m->m_pkthdr.csum_flags = 0;
3359 /* validate checksum if offload enabled */
3360 if (ifp->if_capenable & IFCAP_RXCSUM) {
3361 /* check for a valid IP frame */
3362 if (!(cqe->fast_path_cqe.status_flags &
3363 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) {
3364 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3365 if (__predict_false(cqe_fp_flags &
3366 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) {
3367 fp->eth_q_stats.rx_hw_csum_errors++;
3369 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3370 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3374 /* check for a valid TCP/UDP frame */
3375 if (!(cqe->fast_path_cqe.status_flags &
3376 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) {
3377 if (__predict_false(cqe_fp_flags &
3378 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) {
3379 fp->eth_q_stats.rx_hw_csum_errors++;
3381 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3382 m->m_pkthdr.csum_data = 0xFFFF;
3383 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID |
3389 /* if there is a VLAN tag then flag that info */
3390 if (cqe->fast_path_cqe.pars_flags.flags & PARSING_FLAGS_INNER_VLAN_EXIST) {
3391 m->m_pkthdr.ether_vtag = cqe->fast_path_cqe.vlan_tag;
3392 m->m_flags |= M_VLANTAG;
3395 #if __FreeBSD_version >= 800000
3396 /* specify what RSS queue was used for this flow */
3397 m->m_pkthdr.flowid = fp->index;
3403 bd_cons = RX_BD_NEXT(bd_cons);
3404 bd_prod = RX_BD_NEXT(bd_prod);
3405 bd_prod_fw = RX_BD_NEXT(bd_prod_fw);
3407 /* pass the frame to the stack */
3408 if (__predict_true(m != NULL)) {
3411 (*ifp->if_input)(ifp, m);
3416 sw_cq_prod = RCQ_NEXT(sw_cq_prod);
3417 sw_cq_cons = RCQ_NEXT(sw_cq_cons);
3419 /* limit spinning on the queue */
3423 if (rx_pkts == sc->rx_budget) {
3424 fp->eth_q_stats.rx_budget_reached++;
3427 } /* while work to do */
3429 fp->rx_bd_cons = bd_cons;
3430 fp->rx_bd_prod = bd_prod_fw;
3431 fp->rx_cq_cons = sw_cq_cons;
3432 fp->rx_cq_prod = sw_cq_prod;
3434 /* Update producers */
3435 bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod);
3437 fp->eth_q_stats.rx_pkts += rx_pkts;
3438 fp->eth_q_stats.rx_calls++;
3440 BXE_FP_RX_UNLOCK(fp);
3442 return (sw_cq_cons != hw_cq_cons);
3446 bxe_free_tx_pkt(struct bxe_softc *sc,
3447 struct bxe_fastpath *fp,
3450 struct bxe_sw_tx_bd *tx_buf = &fp->tx_mbuf_chain[idx];
3451 struct eth_tx_start_bd *tx_start_bd;
3452 uint16_t bd_idx = TX_BD(tx_buf->first_bd);
3456 /* unmap the mbuf from non-paged memory */
3457 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
3459 tx_start_bd = &fp->tx_chain[bd_idx].start_bd;
3460 nbd = le16toh(tx_start_bd->nbd) - 1;
3462 new_cons = (tx_buf->first_bd + nbd);
3465 if (__predict_true(tx_buf->m != NULL)) {
3467 fp->eth_q_stats.mbuf_alloc_tx--;
3469 fp->eth_q_stats.tx_chain_lost_mbuf++;
3473 tx_buf->first_bd = 0;
3478 /* transmit timeout watchdog */
3480 bxe_watchdog(struct bxe_softc *sc,
3481 struct bxe_fastpath *fp)
3485 if ((fp->watchdog_timer == 0) || (--fp->watchdog_timer)) {
3486 BXE_FP_TX_UNLOCK(fp);
3490 BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index);
3491 if(sc->trigger_grcdump) {
3492 /* taking grcdump */
3496 BXE_FP_TX_UNLOCK(fp);
3498 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT);
3499 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task);
3504 /* processes transmit completions */
3506 bxe_txeof(struct bxe_softc *sc,
3507 struct bxe_fastpath *fp)
3509 struct ifnet *ifp = sc->ifnet;
3510 uint16_t bd_cons, hw_cons, sw_cons, pkt_cons;
3511 uint16_t tx_bd_avail;
3513 BXE_FP_TX_LOCK_ASSERT(fp);
3515 bd_cons = fp->tx_bd_cons;
3516 hw_cons = le16toh(*fp->tx_cons_sb);
3517 sw_cons = fp->tx_pkt_cons;
3519 while (sw_cons != hw_cons) {
3520 pkt_cons = TX_BD(sw_cons);
3523 "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n",
3524 fp->index, hw_cons, sw_cons, pkt_cons);
3526 bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons);
3531 fp->tx_pkt_cons = sw_cons;
3532 fp->tx_bd_cons = bd_cons;
3535 "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n",
3536 fp->index, hw_cons, fp->tx_pkt_cons, fp->tx_pkt_prod);
3540 tx_bd_avail = bxe_tx_avail(sc, fp);
3542 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
3543 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3545 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3548 if (fp->tx_pkt_prod != fp->tx_pkt_cons) {
3549 /* reset the watchdog timer if there are pending transmits */
3550 fp->watchdog_timer = BXE_TX_TIMEOUT;
3553 /* clear watchdog when there are no pending transmits */
3554 fp->watchdog_timer = 0;
3560 bxe_drain_tx_queues(struct bxe_softc *sc)
3562 struct bxe_fastpath *fp;
3565 /* wait until all TX fastpath tasks have completed */
3566 for (i = 0; i < sc->num_queues; i++) {
3571 while (bxe_has_tx_work(fp)) {
3575 BXE_FP_TX_UNLOCK(fp);
3578 BLOGE(sc, "Timeout waiting for fp[%d] "
3579 "transmits to complete!\n", i);
3580 bxe_panic(sc, ("tx drain failure\n"));
3594 bxe_del_all_macs(struct bxe_softc *sc,
3595 struct ecore_vlan_mac_obj *mac_obj,
3597 uint8_t wait_for_comp)
3599 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
3602 /* wait for completion of requested */
3603 if (wait_for_comp) {
3604 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
3607 /* Set the mac type of addresses we want to clear */
3608 bxe_set_bit(mac_type, &vlan_mac_flags);
3610 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
3612 BLOGE(sc, "Failed to delete MACs (%d) mac_type %d wait_for_comp 0x%x\n",
3613 rc, mac_type, wait_for_comp);
3620 bxe_fill_accept_flags(struct bxe_softc *sc,
3622 unsigned long *rx_accept_flags,
3623 unsigned long *tx_accept_flags)
3625 /* Clear the flags first */
3626 *rx_accept_flags = 0;
3627 *tx_accept_flags = 0;
3630 case BXE_RX_MODE_NONE:
3632 * 'drop all' supersedes any accept flags that may have been
3633 * passed to the function.
3637 case BXE_RX_MODE_NORMAL:
3638 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3639 bxe_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
3640 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3642 /* internal switching mode */
3643 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3644 bxe_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
3645 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3649 case BXE_RX_MODE_ALLMULTI:
3650 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3651 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3652 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3654 /* internal switching mode */
3655 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3656 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3657 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3661 case BXE_RX_MODE_PROMISC:
3663 * According to deffinition of SI mode, iface in promisc mode
3664 * should receive matched and unmatched (in resolution of port)
3667 bxe_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
3668 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3669 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3670 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3672 /* internal switching mode */
3673 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3674 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3677 bxe_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
3679 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3685 BLOGE(sc, "Unknown rx_mode (0x%x)\n", rx_mode);
3689 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
3690 if (rx_mode != BXE_RX_MODE_NONE) {
3691 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
3692 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
3699 bxe_set_q_rx_mode(struct bxe_softc *sc,
3701 unsigned long rx_mode_flags,
3702 unsigned long rx_accept_flags,
3703 unsigned long tx_accept_flags,
3704 unsigned long ramrod_flags)
3706 struct ecore_rx_mode_ramrod_params ramrod_param;
3709 memset(&ramrod_param, 0, sizeof(ramrod_param));
3711 /* Prepare ramrod parameters */
3712 ramrod_param.cid = 0;
3713 ramrod_param.cl_id = cl_id;
3714 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
3715 ramrod_param.func_id = SC_FUNC(sc);
3717 ramrod_param.pstate = &sc->sp_state;
3718 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
3720 ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata);
3721 ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata);
3723 bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
3725 ramrod_param.ramrod_flags = ramrod_flags;
3726 ramrod_param.rx_mode_flags = rx_mode_flags;
3728 ramrod_param.rx_accept_flags = rx_accept_flags;
3729 ramrod_param.tx_accept_flags = tx_accept_flags;
3731 rc = ecore_config_rx_mode(sc, &ramrod_param);
3733 BLOGE(sc, "Set rx_mode %d cli_id 0x%x rx_mode_flags 0x%x "
3734 "rx_accept_flags 0x%x tx_accept_flags 0x%x "
3735 "ramrod_flags 0x%x rc %d failed\n", sc->rx_mode, cl_id,
3736 (uint32_t)rx_mode_flags, (uint32_t)rx_accept_flags,
3737 (uint32_t)tx_accept_flags, (uint32_t)ramrod_flags, rc);
3745 bxe_set_storm_rx_mode(struct bxe_softc *sc)
3747 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
3748 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
3751 rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
3757 bxe_set_bit(RAMROD_RX, &ramrod_flags);
3758 bxe_set_bit(RAMROD_TX, &ramrod_flags);
3760 /* XXX ensure all fastpath have same cl_id and/or move it to bxe_softc */
3761 return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
3762 rx_accept_flags, tx_accept_flags,
3766 /* returns the "mcp load_code" according to global load_count array */
3768 bxe_nic_load_no_mcp(struct bxe_softc *sc)
3770 int path = SC_PATH(sc);
3771 int port = SC_PORT(sc);
3773 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3774 path, load_count[path][0], load_count[path][1],
3775 load_count[path][2]);
3776 load_count[path][0]++;
3777 load_count[path][1 + port]++;
3778 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3779 path, load_count[path][0], load_count[path][1],
3780 load_count[path][2]);
3781 if (load_count[path][0] == 1) {
3782 return (FW_MSG_CODE_DRV_LOAD_COMMON);
3783 } else if (load_count[path][1 + port] == 1) {
3784 return (FW_MSG_CODE_DRV_LOAD_PORT);
3786 return (FW_MSG_CODE_DRV_LOAD_FUNCTION);
3790 /* returns the "mcp load_code" according to global load_count array */
3792 bxe_nic_unload_no_mcp(struct bxe_softc *sc)
3794 int port = SC_PORT(sc);
3795 int path = SC_PATH(sc);
3797 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3798 path, load_count[path][0], load_count[path][1],
3799 load_count[path][2]);
3800 load_count[path][0]--;
3801 load_count[path][1 + port]--;
3802 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3803 path, load_count[path][0], load_count[path][1],
3804 load_count[path][2]);
3805 if (load_count[path][0] == 0) {
3806 return (FW_MSG_CODE_DRV_UNLOAD_COMMON);
3807 } else if (load_count[path][1 + port] == 0) {
3808 return (FW_MSG_CODE_DRV_UNLOAD_PORT);
3810 return (FW_MSG_CODE_DRV_UNLOAD_FUNCTION);
3814 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
3816 bxe_send_unload_req(struct bxe_softc *sc,
3819 uint32_t reset_code = 0;
3821 /* Select the UNLOAD request mode */
3822 if (unload_mode == UNLOAD_NORMAL) {
3823 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3825 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3828 /* Send the request to the MCP */
3829 if (!BXE_NOMCP(sc)) {
3830 reset_code = bxe_fw_command(sc, reset_code, 0);
3832 reset_code = bxe_nic_unload_no_mcp(sc);
3835 return (reset_code);
3838 /* send UNLOAD_DONE command to the MCP */
3840 bxe_send_unload_done(struct bxe_softc *sc,
3843 uint32_t reset_param =
3844 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
3846 /* Report UNLOAD_DONE to MCP */
3847 if (!BXE_NOMCP(sc)) {
3848 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
3853 bxe_func_wait_started(struct bxe_softc *sc)
3857 if (!sc->port.pmf) {
3862 * (assumption: No Attention from MCP at this stage)
3863 * PMF probably in the middle of TX disable/enable transaction
3864 * 1. Sync IRS for default SB
3865 * 2. Sync SP queue - this guarantees us that attention handling started
3866 * 3. Wait, that TX disable/enable transaction completes
3868 * 1+2 guarantee that if DCBX attention was scheduled it already changed
3869 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
3870 * received completion for the transaction the state is TX_STOPPED.
3871 * State will return to STARTED after completion of TX_STOPPED-->STARTED
3875 /* XXX make sure default SB ISR is done */
3876 /* need a way to synchronize an irq (intr_mtx?) */
3878 /* XXX flush any work queues */
3880 while (ecore_func_get_state(sc, &sc->func_obj) !=
3881 ECORE_F_STATE_STARTED && tout--) {
3885 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
3887 * Failed to complete the transaction in a "good way"
3888 * Force both transactions with CLR bit.
3890 struct ecore_func_state_params func_params = { NULL };
3892 BLOGE(sc, "Unexpected function state! "
3893 "Forcing STARTED-->TX_STOPPED-->STARTED\n");
3895 func_params.f_obj = &sc->func_obj;
3896 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
3898 /* STARTED-->TX_STOPPED */
3899 func_params.cmd = ECORE_F_CMD_TX_STOP;
3900 ecore_func_state_change(sc, &func_params);
3902 /* TX_STOPPED-->STARTED */
3903 func_params.cmd = ECORE_F_CMD_TX_START;
3904 return (ecore_func_state_change(sc, &func_params));
3911 bxe_stop_queue(struct bxe_softc *sc,
3914 struct bxe_fastpath *fp = &sc->fp[index];
3915 struct ecore_queue_state_params q_params = { NULL };
3918 BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index);
3920 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
3921 /* We want to wait for completion in this context */
3922 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
3924 /* Stop the primary connection: */
3926 /* ...halt the connection */
3927 q_params.cmd = ECORE_Q_CMD_HALT;
3928 rc = ecore_queue_state_change(sc, &q_params);
3933 /* ...terminate the connection */
3934 q_params.cmd = ECORE_Q_CMD_TERMINATE;
3935 memset(&q_params.params.terminate, 0, sizeof(q_params.params.terminate));
3936 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
3937 rc = ecore_queue_state_change(sc, &q_params);
3942 /* ...delete cfc entry */
3943 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
3944 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
3945 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
3946 return (ecore_queue_state_change(sc, &q_params));
3949 /* wait for the outstanding SP commands */
3950 static inline uint8_t
3951 bxe_wait_sp_comp(struct bxe_softc *sc,
3955 int tout = 5000; /* wait for 5 secs tops */
3959 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
3968 tmp = atomic_load_acq_long(&sc->sp_state);
3970 BLOGE(sc, "Filtering completion timed out: "
3971 "sp_state 0x%lx, mask 0x%lx\n",
3980 bxe_func_stop(struct bxe_softc *sc)
3982 struct ecore_func_state_params func_params = { NULL };
3985 /* prepare parameters for function state transitions */
3986 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
3987 func_params.f_obj = &sc->func_obj;
3988 func_params.cmd = ECORE_F_CMD_STOP;
3991 * Try to stop the function the 'good way'. If it fails (in case
3992 * of a parity error during bxe_chip_cleanup()) and we are
3993 * not in a debug mode, perform a state transaction in order to
3994 * enable further HW_RESET transaction.
3996 rc = ecore_func_state_change(sc, &func_params);
3998 BLOGE(sc, "FUNC_STOP ramrod failed. "
3999 "Running a dry transaction (%d)\n", rc);
4000 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
4001 return (ecore_func_state_change(sc, &func_params));
4008 bxe_reset_hw(struct bxe_softc *sc,
4011 struct ecore_func_state_params func_params = { NULL };
4013 /* Prepare parameters for function state transitions */
4014 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4016 func_params.f_obj = &sc->func_obj;
4017 func_params.cmd = ECORE_F_CMD_HW_RESET;
4019 func_params.params.hw_init.load_phase = load_code;
4021 return (ecore_func_state_change(sc, &func_params));
4025 bxe_int_disable_sync(struct bxe_softc *sc,
4029 /* prevent the HW from sending interrupts */
4030 bxe_int_disable(sc);
4033 /* XXX need a way to synchronize ALL irqs (intr_mtx?) */
4034 /* make sure all ISRs are done */
4036 /* XXX make sure sp_task is not running */
4037 /* cancel and flush work queues */
4041 bxe_chip_cleanup(struct bxe_softc *sc,
4042 uint32_t unload_mode,
4045 int port = SC_PORT(sc);
4046 struct ecore_mcast_ramrod_params rparam = { NULL };
4047 uint32_t reset_code;
4050 bxe_drain_tx_queues(sc);
4052 /* give HW time to discard old tx messages */
4055 /* Clean all ETH MACs */
4056 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE);
4058 BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc);
4061 /* Clean up UC list */
4062 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE);
4064 BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc);
4068 if (!CHIP_IS_E1(sc)) {
4069 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
4072 /* Set "drop all" to stop Rx */
4075 * We need to take the BXE_MCAST_LOCK() here in order to prevent
4076 * a race between the completion code and this code.
4080 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
4081 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
4083 bxe_set_storm_rx_mode(sc);
4086 /* Clean up multicast configuration */
4087 rparam.mcast_obj = &sc->mcast_obj;
4088 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4090 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4093 BXE_MCAST_UNLOCK(sc);
4095 // XXX bxe_iov_chip_cleanup(sc);
4098 * Send the UNLOAD_REQUEST to the MCP. This will return if
4099 * this function should perform FUNCTION, PORT, or COMMON HW
4102 reset_code = bxe_send_unload_req(sc, unload_mode);
4105 * (assumption: No Attention from MCP at this stage)
4106 * PMF probably in the middle of TX disable/enable transaction
4108 rc = bxe_func_wait_started(sc);
4110 BLOGE(sc, "bxe_func_wait_started failed (%d)\n", rc);
4114 * Close multi and leading connections
4115 * Completions for ramrods are collected in a synchronous way
4117 for (i = 0; i < sc->num_queues; i++) {
4118 if (bxe_stop_queue(sc, i)) {
4124 * If SP settings didn't get completed so far - something
4125 * very wrong has happen.
4127 if (!bxe_wait_sp_comp(sc, ~0x0UL)) {
4128 BLOGE(sc, "Common slow path ramrods got stuck!(%d)\n", rc);
4133 rc = bxe_func_stop(sc);
4135 BLOGE(sc, "Function stop failed!(%d)\n", rc);
4138 /* disable HW interrupts */
4139 bxe_int_disable_sync(sc, TRUE);
4141 /* detach interrupts */
4142 bxe_interrupt_detach(sc);
4144 /* Reset the chip */
4145 rc = bxe_reset_hw(sc, reset_code);
4147 BLOGE(sc, "Hardware reset failed(%d)\n", rc);
4150 /* Report UNLOAD_DONE to MCP */
4151 bxe_send_unload_done(sc, keep_link);
4155 bxe_disable_close_the_gate(struct bxe_softc *sc)
4158 int port = SC_PORT(sc);
4161 "Disabling 'close the gates'\n");
4163 if (CHIP_IS_E1(sc)) {
4164 uint32_t addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4165 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4166 val = REG_RD(sc, addr);
4168 REG_WR(sc, addr, val);
4170 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
4171 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
4172 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
4173 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
4178 * Cleans the object that have internal lists without sending
4179 * ramrods. Should be run when interrutps are disabled.
4182 bxe_squeeze_objects(struct bxe_softc *sc)
4184 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
4185 struct ecore_mcast_ramrod_params rparam = { NULL };
4186 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
4189 /* Cleanup MACs' object first... */
4191 /* Wait for completion of requested */
4192 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
4193 /* Perform a dry cleanup */
4194 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
4196 /* Clean ETH primary MAC */
4197 bxe_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
4198 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
4201 BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc);
4204 /* Cleanup UC list */
4206 bxe_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
4207 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags,
4210 BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc);
4213 /* Now clean mcast object... */
4215 rparam.mcast_obj = &sc->mcast_obj;
4216 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
4218 /* Add a DEL command... */
4219 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4221 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4224 /* now wait until all pending commands are cleared */
4226 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4229 BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc);
4233 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4237 /* stop the controller */
4238 static __noinline int
4239 bxe_nic_unload(struct bxe_softc *sc,
4240 uint32_t unload_mode,
4243 uint8_t global = FALSE;
4247 BXE_CORE_LOCK_ASSERT(sc);
4249 sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING;
4251 for (i = 0; i < sc->num_queues; i++) {
4252 struct bxe_fastpath *fp;
4256 BXE_FP_TX_UNLOCK(fp);
4259 BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n");
4261 /* mark driver as unloaded in shmem2 */
4262 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
4263 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
4264 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
4265 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
4268 if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE &&
4269 (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) {
4271 * We can get here if the driver has been unloaded
4272 * during parity error recovery and is either waiting for a
4273 * leader to complete or for other functions to unload and
4274 * then ifconfig down has been issued. In this case we want to
4275 * unload and let other functions to complete a recovery
4278 sc->recovery_state = BXE_RECOVERY_DONE;
4280 bxe_release_leader_lock(sc);
4283 BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n");
4284 BLOGE(sc, "Can't unload in closed or error state recover_state 0x%x"
4285 " state = 0x%x\n", sc->recovery_state, sc->state);
4290 * Nothing to do during unload if previous bxe_nic_load()
4291 * did not completed succesfully - all resourses are released.
4293 if ((sc->state == BXE_STATE_CLOSED) ||
4294 (sc->state == BXE_STATE_ERROR)) {
4298 sc->state = BXE_STATE_CLOSING_WAITING_HALT;
4304 sc->rx_mode = BXE_RX_MODE_NONE;
4305 /* XXX set rx mode ??? */
4307 if (IS_PF(sc) && !sc->grcdump_done) {
4308 /* set ALWAYS_ALIVE bit in shmem */
4309 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
4313 bxe_stats_handle(sc, STATS_EVENT_STOP);
4314 bxe_save_statistics(sc);
4317 /* wait till consumers catch up with producers in all queues */
4318 bxe_drain_tx_queues(sc);
4320 /* if VF indicate to PF this function is going down (PF will delete sp
4321 * elements and clear initializations
4324 ; /* bxe_vfpf_close_vf(sc); */
4325 } else if (unload_mode != UNLOAD_RECOVERY) {
4326 /* if this is a normal/close unload need to clean up chip */
4327 if (!sc->grcdump_done)
4328 bxe_chip_cleanup(sc, unload_mode, keep_link);
4330 /* Send the UNLOAD_REQUEST to the MCP */
4331 bxe_send_unload_req(sc, unload_mode);
4334 * Prevent transactions to host from the functions on the
4335 * engine that doesn't reset global blocks in case of global
4336 * attention once gloabl blocks are reset and gates are opened
4337 * (the engine which leader will perform the recovery
4340 if (!CHIP_IS_E1x(sc)) {
4344 /* disable HW interrupts */
4345 bxe_int_disable_sync(sc, TRUE);
4347 /* detach interrupts */
4348 bxe_interrupt_detach(sc);
4350 /* Report UNLOAD_DONE to MCP */
4351 bxe_send_unload_done(sc, FALSE);
4355 * At this stage no more interrupts will arrive so we may safely clean
4356 * the queue'able objects here in case they failed to get cleaned so far.
4359 bxe_squeeze_objects(sc);
4362 /* There should be no more pending SP commands at this stage */
4367 bxe_free_fp_buffers(sc);
4373 bxe_free_fw_stats_mem(sc);
4375 sc->state = BXE_STATE_CLOSED;
4378 * Check if there are pending parity attentions. If there are - set
4379 * RECOVERY_IN_PROGRESS.
4381 if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) {
4382 bxe_set_reset_in_progress(sc);
4384 /* Set RESET_IS_GLOBAL if needed */
4386 bxe_set_reset_global(sc);
4391 * The last driver must disable a "close the gate" if there is no
4392 * parity attention or "process kill" pending.
4394 if (IS_PF(sc) && !bxe_clear_pf_load(sc) &&
4395 bxe_reset_is_done(sc, SC_PATH(sc))) {
4396 bxe_disable_close_the_gate(sc);
4399 BLOGD(sc, DBG_LOAD, "Ended NIC unload\n");
4401 bxe_link_report(sc);
4407 * Called by the OS to set various media options (i.e. link, speed, etc.) when
4408 * the user runs "ifconfig bxe media ..." or "ifconfig bxe mediaopt ...".
4411 bxe_ifmedia_update(struct ifnet *ifp)
4413 struct bxe_softc *sc = (struct bxe_softc *)ifp->if_softc;
4414 struct ifmedia *ifm;
4418 /* We only support Ethernet media type. */
4419 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
4423 switch (IFM_SUBTYPE(ifm->ifm_media)) {
4429 case IFM_10G_TWINAX:
4431 /* We don't support changing the media type. */
4432 BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n",
4433 IFM_SUBTYPE(ifm->ifm_media));
4441 * Called by the OS to get the current media status (i.e. link, speed, etc.).
4444 bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
4446 struct bxe_softc *sc = ifp->if_softc;
4448 /* Bug 165447: the 'ifconfig' tool skips printing of the "status: ..."
4449 line if the IFM_AVALID flag is *NOT* set. So we need to set this
4450 flag unconditionally (irrespective of the admininistrative
4451 'up/down' state of the interface) to ensure that that line is always
4454 ifmr->ifm_status = IFM_AVALID;
4456 /* Setup the default interface info. */
4457 ifmr->ifm_active = IFM_ETHER;
4459 /* Report link down if the driver isn't running. */
4460 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4461 ifmr->ifm_active |= IFM_NONE;
4462 BLOGD(sc, DBG_PHY, "in %s : nic still not loaded fully\n", __func__);
4463 BLOGD(sc, DBG_PHY, "in %s : link_up (1) : %d\n",
4464 __func__, sc->link_vars.link_up);
4469 if (sc->link_vars.link_up) {
4470 ifmr->ifm_status |= IFM_ACTIVE;
4471 ifmr->ifm_active |= IFM_FDX;
4473 ifmr->ifm_active |= IFM_NONE;
4474 BLOGD(sc, DBG_PHY, "in %s : setting IFM_NONE\n",
4479 ifmr->ifm_active |= sc->media;
4484 bxe_handle_chip_tq(void *context,
4487 struct bxe_softc *sc = (struct bxe_softc *)context;
4488 long work = atomic_load_acq_long(&sc->chip_tq_flags);
4492 case CHIP_TQ_REINIT:
4493 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
4494 /* restart the interface */
4495 BLOGD(sc, DBG_LOAD, "Restarting the interface...\n");
4496 bxe_periodic_stop(sc);
4498 bxe_stop_locked(sc);
4499 bxe_init_locked(sc);
4500 BXE_CORE_UNLOCK(sc);
4510 * Handles any IOCTL calls from the operating system.
4513 * 0 = Success, >0 Failure
4516 bxe_ioctl(struct ifnet *ifp,
4520 struct bxe_softc *sc = ifp->if_softc;
4521 struct ifreq *ifr = (struct ifreq *)data;
4526 int mtu_min = (ETH_MIN_PACKET_SIZE - ETH_HLEN);
4527 int mtu_max = (MJUM9BYTES - ETH_OVERHEAD - IP_HEADER_ALIGNMENT_PADDING);
4532 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n",
4535 if (sc->mtu == ifr->ifr_mtu) {
4536 /* nothing to change */
4540 if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) {
4541 BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n",
4542 ifr->ifr_mtu, mtu_min, mtu_max);
4547 atomic_store_rel_int((volatile unsigned int *)&sc->mtu,
4548 (unsigned long)ifr->ifr_mtu);
4549 atomic_store_rel_long((volatile unsigned long *)&ifp->if_mtu,
4550 (unsigned long)ifr->ifr_mtu);
4556 /* toggle the interface state up or down */
4557 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n");
4560 /* check if the interface is up */
4561 if (ifp->if_flags & IFF_UP) {
4562 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4563 /* set the receive mode flags */
4564 bxe_set_rx_mode(sc);
4565 } else if(sc->state != BXE_STATE_DISABLED) {
4566 bxe_init_locked(sc);
4569 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4570 bxe_periodic_stop(sc);
4571 bxe_stop_locked(sc);
4574 BXE_CORE_UNLOCK(sc);
4580 /* add/delete multicast addresses */
4581 BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n");
4583 /* check if the interface is up */
4584 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4585 /* set the receive mode flags */
4587 bxe_set_rx_mode(sc);
4588 BXE_CORE_UNLOCK(sc);
4594 /* find out which capabilities have changed */
4595 mask = (ifr->ifr_reqcap ^ ifp->if_capenable);
4597 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n",
4600 /* toggle the LRO capabilites enable flag */
4601 if (mask & IFCAP_LRO) {
4602 ifp->if_capenable ^= IFCAP_LRO;
4603 BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n",
4604 (ifp->if_capenable & IFCAP_LRO) ? "ON" : "OFF");
4608 /* toggle the TXCSUM checksum capabilites enable flag */
4609 if (mask & IFCAP_TXCSUM) {
4610 ifp->if_capenable ^= IFCAP_TXCSUM;
4611 BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n",
4612 (ifp->if_capenable & IFCAP_TXCSUM) ? "ON" : "OFF");
4613 if (ifp->if_capenable & IFCAP_TXCSUM) {
4614 ifp->if_hwassist = (CSUM_IP |
4621 ifp->if_hwassist = 0;
4625 /* toggle the RXCSUM checksum capabilities enable flag */
4626 if (mask & IFCAP_RXCSUM) {
4627 ifp->if_capenable ^= IFCAP_RXCSUM;
4628 BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n",
4629 (ifp->if_capenable & IFCAP_RXCSUM) ? "ON" : "OFF");
4630 if (ifp->if_capenable & IFCAP_RXCSUM) {
4631 ifp->if_hwassist = (CSUM_IP |
4638 ifp->if_hwassist = 0;
4642 /* toggle TSO4 capabilities enabled flag */
4643 if (mask & IFCAP_TSO4) {
4644 ifp->if_capenable ^= IFCAP_TSO4;
4645 BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n",
4646 (ifp->if_capenable & IFCAP_TSO4) ? "ON" : "OFF");
4649 /* toggle TSO6 capabilities enabled flag */
4650 if (mask & IFCAP_TSO6) {
4651 ifp->if_capenable ^= IFCAP_TSO6;
4652 BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n",
4653 (ifp->if_capenable & IFCAP_TSO6) ? "ON" : "OFF");
4656 /* toggle VLAN_HWTSO capabilities enabled flag */
4657 if (mask & IFCAP_VLAN_HWTSO) {
4658 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4659 BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n",
4660 (ifp->if_capenable & IFCAP_VLAN_HWTSO) ? "ON" : "OFF");
4663 /* toggle VLAN_HWCSUM capabilities enabled flag */
4664 if (mask & IFCAP_VLAN_HWCSUM) {
4665 /* XXX investigate this... */
4666 BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n");
4670 /* toggle VLAN_MTU capabilities enable flag */
4671 if (mask & IFCAP_VLAN_MTU) {
4672 /* XXX investigate this... */
4673 BLOGE(sc, "Changing VLAN_MTU is not supported!\n");
4677 /* toggle VLAN_HWTAGGING capabilities enabled flag */
4678 if (mask & IFCAP_VLAN_HWTAGGING) {
4679 /* XXX investigate this... */
4680 BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n");
4684 /* toggle VLAN_HWFILTER capabilities enabled flag */
4685 if (mask & IFCAP_VLAN_HWFILTER) {
4686 /* XXX investigate this... */
4687 BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n");
4699 /* set/get interface media */
4700 BLOGD(sc, DBG_IOCTL,
4701 "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n",
4703 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
4707 BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n",
4709 error = ether_ioctl(ifp, command, data);
4713 if (reinit && (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
4714 BLOGD(sc, DBG_LOAD | DBG_IOCTL,
4715 "Re-initializing hardware from IOCTL change\n");
4716 bxe_periodic_stop(sc);
4718 bxe_stop_locked(sc);
4719 bxe_init_locked(sc);
4720 BXE_CORE_UNLOCK(sc);
4726 static __noinline void
4727 bxe_dump_mbuf(struct bxe_softc *sc,
4734 if (!(sc->debug & DBG_MBUF)) {
4739 BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n");
4745 #if __FreeBSD_version >= 1000000
4747 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
4748 i, m, m->m_len, m->m_flags,
4749 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", m->m_data);
4751 if (m->m_flags & M_PKTHDR) {
4753 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
4754 i, m->m_pkthdr.len, m->m_flags,
4755 "\20\12M_BCAST\13M_MCAST\14M_FRAG"
4756 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
4757 "\22M_PROMISC\23M_NOFREE",
4758 (int)m->m_pkthdr.csum_flags,
4759 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
4760 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
4761 "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
4762 "\14CSUM_PSEUDO_HDR");
4766 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
4767 i, m, m->m_len, m->m_flags,
4768 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", m->m_data);
4770 if (m->m_flags & M_PKTHDR) {
4772 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
4773 i, m->m_pkthdr.len, m->m_flags,
4774 "\20\12M_BCAST\13M_MCAST\14M_FRAG"
4775 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
4776 "\22M_PROMISC\23M_NOFREE",
4777 (int)m->m_pkthdr.csum_flags,
4778 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
4779 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
4780 "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
4781 "\14CSUM_PSEUDO_HDR");
4783 #endif /* #if __FreeBSD_version >= 1000000 */
4785 if (m->m_flags & M_EXT) {
4786 switch (m->m_ext.ext_type) {
4787 case EXT_CLUSTER: type = "EXT_CLUSTER"; break;
4788 case EXT_SFBUF: type = "EXT_SFBUF"; break;
4789 case EXT_JUMBOP: type = "EXT_JUMBOP"; break;
4790 case EXT_JUMBO9: type = "EXT_JUMBO9"; break;
4791 case EXT_JUMBO16: type = "EXT_JUMBO16"; break;
4792 case EXT_PACKET: type = "EXT_PACKET"; break;
4793 case EXT_MBUF: type = "EXT_MBUF"; break;
4794 case EXT_NET_DRV: type = "EXT_NET_DRV"; break;
4795 case EXT_MOD_TYPE: type = "EXT_MOD_TYPE"; break;
4796 case EXT_DISPOSABLE: type = "EXT_DISPOSABLE"; break;
4797 case EXT_EXTREF: type = "EXT_EXTREF"; break;
4798 default: type = "UNKNOWN"; break;
4802 "%02d: - m_ext: %p ext_size=%d type=%s\n",
4803 i, m->m_ext.ext_buf, m->m_ext.ext_size, type);
4807 bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE);
4816 * Checks to ensure the 13 bd sliding window is >= MSS for TSO.
4817 * Check that (13 total bds - 3 bds) = 10 bd window >= MSS.
4818 * The window: 3 bds are = 1 for headers BD + 2 for parse BD and last BD
4819 * The headers comes in a seperate bd in FreeBSD so 13-3=10.
4820 * Returns: 0 if OK to send, 1 if packet needs further defragmentation
4823 bxe_chktso_window(struct bxe_softc *sc,
4825 bus_dma_segment_t *segs,
4828 uint32_t num_wnds, wnd_size, wnd_sum;
4829 int32_t frag_idx, wnd_idx;
4830 unsigned short lso_mss;
4836 num_wnds = nsegs - wnd_size;
4837 lso_mss = htole16(m->m_pkthdr.tso_segsz);
4840 * Total header lengths Eth+IP+TCP in first FreeBSD mbuf so calculate the
4841 * first window sum of data while skipping the first assuming it is the
4842 * header in FreeBSD.
4844 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) {
4845 wnd_sum += htole16(segs[frag_idx].ds_len);
4848 /* check the first 10 bd window size */
4849 if (wnd_sum < lso_mss) {
4853 /* run through the windows */
4854 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) {
4855 /* subtract the first mbuf->m_len of the last wndw(-header) */
4856 wnd_sum -= htole16(segs[wnd_idx+1].ds_len);
4857 /* add the next mbuf len to the len of our new window */
4858 wnd_sum += htole16(segs[frag_idx].ds_len);
4859 if (wnd_sum < lso_mss) {
4868 bxe_set_pbd_csum_e2(struct bxe_fastpath *fp,
4870 uint32_t *parsing_data)
4872 struct ether_vlan_header *eh = NULL;
4873 struct ip *ip4 = NULL;
4874 struct ip6_hdr *ip6 = NULL;
4876 struct tcphdr *th = NULL;
4877 int e_hlen, ip_hlen, l4_off;
4880 if (m->m_pkthdr.csum_flags == CSUM_IP) {
4881 /* no L4 checksum offload needed */
4885 /* get the Ethernet header */
4886 eh = mtod(m, struct ether_vlan_header *);
4888 /* handle VLAN encapsulation if present */
4889 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4890 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4891 proto = ntohs(eh->evl_proto);
4893 e_hlen = ETHER_HDR_LEN;
4894 proto = ntohs(eh->evl_encap_proto);
4899 /* get the IP header, if mbuf len < 20 then header in next mbuf */
4900 ip4 = (m->m_len < sizeof(struct ip)) ?
4901 (struct ip *)m->m_next->m_data :
4902 (struct ip *)(m->m_data + e_hlen);
4903 /* ip_hl is number of 32-bit words */
4904 ip_hlen = (ip4->ip_hl << 2);
4907 case ETHERTYPE_IPV6:
4908 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
4909 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
4910 (struct ip6_hdr *)m->m_next->m_data :
4911 (struct ip6_hdr *)(m->m_data + e_hlen);
4912 /* XXX cannot support offload with IPv6 extensions */
4913 ip_hlen = sizeof(struct ip6_hdr);
4917 /* We can't offload in this case... */
4918 /* XXX error stat ??? */
4922 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
4923 l4_off = (e_hlen + ip_hlen);
4926 (((l4_off >> 1) << ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
4927 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W);
4929 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
4932 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
4933 th = (struct tcphdr *)(ip + ip_hlen);
4934 /* th_off is number of 32-bit words */
4935 *parsing_data |= ((th->th_off <<
4936 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
4937 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW);
4938 return (l4_off + (th->th_off << 2)); /* entire header length */
4939 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
4941 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
4942 return (l4_off + sizeof(struct udphdr)); /* entire header length */
4944 /* XXX error stat ??? */
4950 bxe_set_pbd_csum(struct bxe_fastpath *fp,
4952 struct eth_tx_parse_bd_e1x *pbd)
4954 struct ether_vlan_header *eh = NULL;
4955 struct ip *ip4 = NULL;
4956 struct ip6_hdr *ip6 = NULL;
4958 struct tcphdr *th = NULL;
4959 struct udphdr *uh = NULL;
4960 int e_hlen, ip_hlen;
4966 /* get the Ethernet header */
4967 eh = mtod(m, struct ether_vlan_header *);
4969 /* handle VLAN encapsulation if present */
4970 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4971 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4972 proto = ntohs(eh->evl_proto);
4974 e_hlen = ETHER_HDR_LEN;
4975 proto = ntohs(eh->evl_encap_proto);
4980 /* get the IP header, if mbuf len < 20 then header in next mbuf */
4981 ip4 = (m->m_len < sizeof(struct ip)) ?
4982 (struct ip *)m->m_next->m_data :
4983 (struct ip *)(m->m_data + e_hlen);
4984 /* ip_hl is number of 32-bit words */
4985 ip_hlen = (ip4->ip_hl << 1);
4988 case ETHERTYPE_IPV6:
4989 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
4990 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
4991 (struct ip6_hdr *)m->m_next->m_data :
4992 (struct ip6_hdr *)(m->m_data + e_hlen);
4993 /* XXX cannot support offload with IPv6 extensions */
4994 ip_hlen = (sizeof(struct ip6_hdr) >> 1);
4998 /* We can't offload in this case... */
4999 /* XXX error stat ??? */
5003 hlen = (e_hlen >> 1);
5005 /* note that rest of global_data is indirectly zeroed here */
5006 if (m->m_flags & M_VLANTAG) {
5008 htole16(hlen | (1 << ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
5010 pbd->global_data = htole16(hlen);
5013 pbd->ip_hlen_w = ip_hlen;
5015 hlen += pbd->ip_hlen_w;
5017 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
5019 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5022 th = (struct tcphdr *)(ip + (ip_hlen << 1));
5023 /* th_off is number of 32-bit words */
5024 hlen += (uint16_t)(th->th_off << 1);
5025 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5027 uh = (struct udphdr *)(ip + (ip_hlen << 1));
5028 hlen += (sizeof(struct udphdr) / 2);
5030 /* valid case as only CSUM_IP was set */
5034 pbd->total_hlen_w = htole16(hlen);
5036 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5039 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
5040 pbd->tcp_pseudo_csum = ntohs(th->th_sum);
5041 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5043 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
5046 * Everest1 (i.e. 57710, 57711, 57711E) does not natively support UDP
5047 * checksums and does not know anything about the UDP header and where
5048 * the checksum field is located. It only knows about TCP. Therefore
5049 * we "lie" to the hardware for outgoing UDP packets w/ checksum
5050 * offload. Since the checksum field offset for TCP is 16 bytes and
5051 * for UDP it is 6 bytes we pass a pointer to the hardware that is 10
5052 * bytes less than the start of the UDP header. This allows the
5053 * hardware to write the checksum in the correct spot. But the
5054 * hardware will compute a checksum which includes the last 10 bytes
5055 * of the IP header. To correct this we tweak the stack computed
5056 * pseudo checksum by folding in the calculation of the inverse
5057 * checksum for those final 10 bytes of the IP header. This allows
5058 * the correct checksum to be computed by the hardware.
5061 /* set pointer 10 bytes before UDP header */
5062 tmp_uh = (uint32_t *)((uint8_t *)uh - 10);
5064 /* calculate a pseudo header checksum over the first 10 bytes */
5065 tmp_csum = in_pseudo(*tmp_uh,
5067 *(uint16_t *)(tmp_uh + 2));
5069 pbd->tcp_pseudo_csum = ntohs(in_addword(uh->uh_sum, ~tmp_csum));
5072 return (hlen * 2); /* entire header length, number of bytes */
5076 bxe_set_pbd_lso_e2(struct mbuf *m,
5077 uint32_t *parsing_data)
5079 *parsing_data |= ((m->m_pkthdr.tso_segsz <<
5080 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
5081 ETH_TX_PARSE_BD_E2_LSO_MSS);
5083 /* XXX test for IPv6 with extension header... */
5087 bxe_set_pbd_lso(struct mbuf *m,
5088 struct eth_tx_parse_bd_e1x *pbd)
5090 struct ether_vlan_header *eh = NULL;
5091 struct ip *ip = NULL;
5092 struct tcphdr *th = NULL;
5095 /* get the Ethernet header */
5096 eh = mtod(m, struct ether_vlan_header *);
5098 /* handle VLAN encapsulation if present */
5099 e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ?
5100 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN;
5102 /* get the IP and TCP header, with LSO entire header in first mbuf */
5103 /* XXX assuming IPv4 */
5104 ip = (struct ip *)(m->m_data + e_hlen);
5105 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
5107 pbd->lso_mss = htole16(m->m_pkthdr.tso_segsz);
5108 pbd->tcp_send_seq = ntohl(th->th_seq);
5109 pbd->tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff);
5113 pbd->ip_id = ntohs(ip->ip_id);
5114 pbd->tcp_pseudo_csum =
5115 ntohs(in_pseudo(ip->ip_src.s_addr,
5117 htons(IPPROTO_TCP)));
5120 pbd->tcp_pseudo_csum =
5121 ntohs(in_pseudo(&ip6->ip6_src,
5123 htons(IPPROTO_TCP)));
5127 htole16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
5131 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
5132 * visible to the controller.
5134 * If an mbuf is submitted to this routine and cannot be given to the
5135 * controller (e.g. it has too many fragments) then the function may free
5136 * the mbuf and return to the caller.
5139 * 0 = Success, !0 = Failure
5140 * Note the side effect that an mbuf may be freed if it causes a problem.
5143 bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head)
5145 bus_dma_segment_t segs[32];
5147 struct bxe_sw_tx_bd *tx_buf;
5148 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
5149 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
5150 /* struct eth_tx_parse_2nd_bd *pbd2 = NULL; */
5151 struct eth_tx_bd *tx_data_bd;
5152 struct eth_tx_bd *tx_total_pkt_size_bd;
5153 struct eth_tx_start_bd *tx_start_bd;
5154 uint16_t bd_prod, pkt_prod, total_pkt_size;
5156 int defragged, error, nsegs, rc, nbds, vlan_off, ovlan;
5157 struct bxe_softc *sc;
5158 uint16_t tx_bd_avail;
5159 struct ether_vlan_header *eh;
5160 uint32_t pbd_e2_parsing_data = 0;
5167 #if __FreeBSD_version >= 800000
5168 M_ASSERTPKTHDR(*m_head);
5169 #endif /* #if __FreeBSD_version >= 800000 */
5172 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0;
5175 tx_total_pkt_size_bd = NULL;
5177 /* get the H/W pointer for packets and BDs */
5178 pkt_prod = fp->tx_pkt_prod;
5179 bd_prod = fp->tx_bd_prod;
5181 mac_type = UNICAST_ADDRESS;
5183 /* map the mbuf into the next open DMAable memory */
5184 tx_buf = &fp->tx_mbuf_chain[TX_BD(pkt_prod)];
5185 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5187 segs, &nsegs, BUS_DMA_NOWAIT);
5189 /* mapping errors */
5190 if(__predict_false(error != 0)) {
5191 fp->eth_q_stats.tx_dma_mapping_failure++;
5192 if (error == ENOMEM) {
5193 /* resource issue, try again later */
5195 } else if (error == EFBIG) {
5196 /* possibly recoverable with defragmentation */
5197 fp->eth_q_stats.mbuf_defrag_attempts++;
5198 m0 = m_defrag(*m_head, M_DONTWAIT);
5200 fp->eth_q_stats.mbuf_defrag_failures++;
5203 /* defrag successful, try mapping again */
5205 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5207 segs, &nsegs, BUS_DMA_NOWAIT);
5209 fp->eth_q_stats.tx_dma_mapping_failure++;
5214 /* unknown, unrecoverable mapping error */
5215 BLOGE(sc, "Unknown TX mapping error rc=%d\n", error);
5216 bxe_dump_mbuf(sc, m0, FALSE);
5220 goto bxe_tx_encap_continue;
5223 tx_bd_avail = bxe_tx_avail(sc, fp);
5225 /* make sure there is enough room in the send queue */
5226 if (__predict_false(tx_bd_avail < (nsegs + 2))) {
5227 /* Recoverable, try again later. */
5228 fp->eth_q_stats.tx_hw_queue_full++;
5229 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5231 goto bxe_tx_encap_continue;
5234 /* capture the current H/W TX chain high watermark */
5235 if (__predict_false(fp->eth_q_stats.tx_hw_max_queue_depth <
5236 (TX_BD_USABLE - tx_bd_avail))) {
5237 fp->eth_q_stats.tx_hw_max_queue_depth = (TX_BD_USABLE - tx_bd_avail);
5240 /* make sure it fits in the packet window */
5241 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5243 * The mbuf may be to big for the controller to handle. If the frame
5244 * is a TSO frame we'll need to do an additional check.
5246 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5247 if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) {
5248 goto bxe_tx_encap_continue; /* OK to send */
5250 fp->eth_q_stats.tx_window_violation_tso++;
5253 fp->eth_q_stats.tx_window_violation_std++;
5256 /* lets try to defragment this mbuf and remap it */
5257 fp->eth_q_stats.mbuf_defrag_attempts++;
5258 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5260 m0 = m_defrag(*m_head, M_DONTWAIT);
5262 fp->eth_q_stats.mbuf_defrag_failures++;
5263 /* Ugh, just drop the frame... :( */
5266 /* defrag successful, try mapping again */
5268 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5270 segs, &nsegs, BUS_DMA_NOWAIT);
5272 fp->eth_q_stats.tx_dma_mapping_failure++;
5273 /* No sense in trying to defrag/copy chain, drop it. :( */
5276 /* if the chain is still too long then drop it */
5277 if(m0->m_pkthdr.csum_flags & CSUM_TSO) {
5279 * in case TSO is enabled nsegs should be checked against
5280 * BXE_TSO_MAX_SEGMENTS
5282 if (__predict_false(nsegs > BXE_TSO_MAX_SEGMENTS)) {
5283 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5284 fp->eth_q_stats.nsegs_path1_errors++;
5288 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5289 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5290 fp->eth_q_stats.nsegs_path2_errors++;
5298 bxe_tx_encap_continue:
5300 /* Check for errors */
5303 /* recoverable try again later */
5305 fp->eth_q_stats.tx_soft_errors++;
5306 fp->eth_q_stats.mbuf_alloc_tx--;
5314 /* set flag according to packet type (UNICAST_ADDRESS is default) */
5315 if (m0->m_flags & M_BCAST) {
5316 mac_type = BROADCAST_ADDRESS;
5317 } else if (m0->m_flags & M_MCAST) {
5318 mac_type = MULTICAST_ADDRESS;
5321 /* store the mbuf into the mbuf ring */
5323 tx_buf->first_bd = fp->tx_bd_prod;
5326 /* prepare the first transmit (start) BD for the mbuf */
5327 tx_start_bd = &fp->tx_chain[TX_BD(bd_prod)].start_bd;
5330 "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n",
5331 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
5333 tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
5334 tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
5335 tx_start_bd->nbytes = htole16(segs[0].ds_len);
5336 total_pkt_size += tx_start_bd->nbytes;
5337 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
5339 tx_start_bd->general_data = (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
5341 /* all frames have at least Start BD + Parsing BD */
5343 tx_start_bd->nbd = htole16(nbds);
5345 if (m0->m_flags & M_VLANTAG) {
5346 tx_start_bd->vlan_or_ethertype = htole16(m0->m_pkthdr.ether_vtag);
5347 tx_start_bd->bd_flags.as_bitfield |=
5348 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
5350 /* vf tx, start bd must hold the ethertype for fw to enforce it */
5352 /* map ethernet header to find type and header length */
5353 eh = mtod(m0, struct ether_vlan_header *);
5354 tx_start_bd->vlan_or_ethertype = eh->evl_encap_proto;
5356 /* used by FW for packet accounting */
5357 tx_start_bd->vlan_or_ethertype = htole16(fp->tx_pkt_prod);
5362 * add a parsing BD from the chain. The parsing BD is always added
5363 * though it is only used for TSO and chksum
5365 bd_prod = TX_BD_NEXT(bd_prod);
5367 if (m0->m_pkthdr.csum_flags) {
5368 if (m0->m_pkthdr.csum_flags & CSUM_IP) {
5369 fp->eth_q_stats.tx_ofld_frames_csum_ip++;
5370 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
5373 if (m0->m_pkthdr.csum_flags & CSUM_TCP_IPV6) {
5374 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5375 ETH_TX_BD_FLAGS_L4_CSUM);
5376 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP_IPV6) {
5377 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5378 ETH_TX_BD_FLAGS_IS_UDP |
5379 ETH_TX_BD_FLAGS_L4_CSUM);
5380 } else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) ||
5381 (m0->m_pkthdr.csum_flags & CSUM_TSO)) {
5382 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
5383 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) {
5384 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_L4_CSUM |
5385 ETH_TX_BD_FLAGS_IS_UDP);
5389 if (!CHIP_IS_E1x(sc)) {
5390 pbd_e2 = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e2;
5391 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
5393 if (m0->m_pkthdr.csum_flags) {
5394 hlen = bxe_set_pbd_csum_e2(fp, m0, &pbd_e2_parsing_data);
5397 SET_FLAG(pbd_e2_parsing_data, ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE,
5400 uint16_t global_data = 0;
5402 pbd_e1x = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e1x;
5403 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
5405 if (m0->m_pkthdr.csum_flags) {
5406 hlen = bxe_set_pbd_csum(fp, m0, pbd_e1x);
5409 SET_FLAG(global_data,
5410 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
5411 pbd_e1x->global_data |= htole16(global_data);
5414 /* setup the parsing BD with TSO specific info */
5415 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5416 fp->eth_q_stats.tx_ofld_frames_lso++;
5417 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
5419 if (__predict_false(tx_start_bd->nbytes > hlen)) {
5420 fp->eth_q_stats.tx_ofld_frames_lso_hdr_splits++;
5422 /* split the first BD into header/data making the fw job easy */
5424 tx_start_bd->nbd = htole16(nbds);
5425 tx_start_bd->nbytes = htole16(hlen);
5427 bd_prod = TX_BD_NEXT(bd_prod);
5429 /* new transmit BD after the tx_parse_bd */
5430 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5431 tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hlen));
5432 tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hlen));
5433 tx_data_bd->nbytes = htole16(segs[0].ds_len - hlen);
5434 if (tx_total_pkt_size_bd == NULL) {
5435 tx_total_pkt_size_bd = tx_data_bd;
5439 "TSO split header size is %d (%x:%x) nbds %d\n",
5440 le16toh(tx_start_bd->nbytes),
5441 le32toh(tx_start_bd->addr_hi),
5442 le32toh(tx_start_bd->addr_lo),
5446 if (!CHIP_IS_E1x(sc)) {
5447 bxe_set_pbd_lso_e2(m0, &pbd_e2_parsing_data);
5449 bxe_set_pbd_lso(m0, pbd_e1x);
5453 if (pbd_e2_parsing_data) {
5454 pbd_e2->parsing_data = htole32(pbd_e2_parsing_data);
5457 /* prepare remaining BDs, start tx bd contains first seg/frag */
5458 for (i = 1; i < nsegs ; i++) {
5459 bd_prod = TX_BD_NEXT(bd_prod);
5460 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5461 tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr));
5462 tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr));
5463 tx_data_bd->nbytes = htole16(segs[i].ds_len);
5464 if (tx_total_pkt_size_bd == NULL) {
5465 tx_total_pkt_size_bd = tx_data_bd;
5467 total_pkt_size += tx_data_bd->nbytes;
5470 BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd);
5472 if (tx_total_pkt_size_bd != NULL) {
5473 tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size;
5476 if (__predict_false(sc->debug & DBG_TX)) {
5477 tmp_bd = tx_buf->first_bd;
5478 for (i = 0; i < nbds; i++)
5482 "TX Strt: %p bd=%d nbd=%d vlan=0x%x "
5483 "bd_flags=0x%x hdr_nbds=%d\n",
5486 le16toh(tx_start_bd->nbd),
5487 le16toh(tx_start_bd->vlan_or_ethertype),
5488 tx_start_bd->bd_flags.as_bitfield,
5489 (tx_start_bd->general_data & ETH_TX_START_BD_HDR_NBDS));
5490 } else if (i == 1) {
5493 "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u "
5494 "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x "
5495 "tcp_seq=%u total_hlen_w=%u\n",
5498 pbd_e1x->global_data,
5503 pbd_e1x->tcp_pseudo_csum,
5504 pbd_e1x->tcp_send_seq,
5505 le16toh(pbd_e1x->total_hlen_w));
5506 } else { /* if (pbd_e2) */
5508 "-> Parse: %p bd=%d dst=%02x:%02x:%02x "
5509 "src=%02x:%02x:%02x parsing_data=0x%x\n",
5512 pbd_e2->data.mac_addr.dst_hi,
5513 pbd_e2->data.mac_addr.dst_mid,
5514 pbd_e2->data.mac_addr.dst_lo,
5515 pbd_e2->data.mac_addr.src_hi,
5516 pbd_e2->data.mac_addr.src_mid,
5517 pbd_e2->data.mac_addr.src_lo,
5518 pbd_e2->parsing_data);
5522 if (i != 1) { /* skip parse db as it doesn't hold data */
5523 tx_data_bd = &fp->tx_chain[TX_BD(tmp_bd)].reg_bd;
5525 "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n",
5528 le16toh(tx_data_bd->nbytes),
5529 le32toh(tx_data_bd->addr_hi),
5530 le32toh(tx_data_bd->addr_lo));
5533 tmp_bd = TX_BD_NEXT(tmp_bd);
5537 BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod);
5539 /* update TX BD producer index value for next TX */
5540 bd_prod = TX_BD_NEXT(bd_prod);
5543 * If the chain of tx_bd's describing this frame is adjacent to or spans
5544 * an eth_tx_next_bd element then we need to increment the nbds value.
5546 if (TX_BD_IDX(bd_prod) < nbds) {
5550 /* don't allow reordering of writes for nbd and packets */
5553 fp->tx_db.data.prod += nbds;
5555 /* producer points to the next free tx_bd at this point */
5557 fp->tx_bd_prod = bd_prod;
5559 DOORBELL(sc, fp->index, fp->tx_db.raw);
5561 fp->eth_q_stats.tx_pkts++;
5563 /* Prevent speculative reads from getting ahead of the status block. */
5564 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle,
5565 0, 0, BUS_SPACE_BARRIER_READ);
5567 /* Prevent speculative reads from getting ahead of the doorbell. */
5568 bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle,
5569 0, 0, BUS_SPACE_BARRIER_READ);
5575 bxe_tx_start_locked(struct bxe_softc *sc,
5577 struct bxe_fastpath *fp)
5579 struct mbuf *m = NULL;
5581 uint16_t tx_bd_avail;
5583 BXE_FP_TX_LOCK_ASSERT(fp);
5585 /* keep adding entries while there are frames to send */
5586 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
5589 * check for any frames to send
5590 * dequeue can still be NULL even if queue is not empty
5592 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
5593 if (__predict_false(m == NULL)) {
5597 /* the mbuf now belongs to us */
5598 fp->eth_q_stats.mbuf_alloc_tx++;
5601 * Put the frame into the transmit ring. If we don't have room,
5602 * place the mbuf back at the head of the TX queue, set the
5603 * OACTIVE flag, and wait for the NIC to drain the chain.
5605 if (__predict_false(bxe_tx_encap(fp, &m))) {
5606 fp->eth_q_stats.tx_encap_failures++;
5608 /* mark the TX queue as full and return the frame */
5609 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5610 IFQ_DRV_PREPEND(&ifp->if_snd, m);
5611 fp->eth_q_stats.mbuf_alloc_tx--;
5612 fp->eth_q_stats.tx_queue_xoff++;
5615 /* stop looking for more work */
5619 /* the frame was enqueued successfully */
5622 /* send a copy of the frame to any BPF listeners. */
5625 tx_bd_avail = bxe_tx_avail(sc, fp);
5627 /* handle any completions if we're running low */
5628 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5629 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5631 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
5637 /* all TX packets were dequeued and/or the tx ring is full */
5639 /* reset the TX watchdog timeout timer */
5640 fp->watchdog_timer = BXE_TX_TIMEOUT;
5644 /* Legacy (non-RSS) dispatch routine */
5646 bxe_tx_start(struct ifnet *ifp)
5648 struct bxe_softc *sc;
5649 struct bxe_fastpath *fp;
5653 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5654 BLOGW(sc, "Interface not running, ignoring transmit request\n");
5658 if (!sc->link_vars.link_up) {
5659 BLOGW(sc, "Interface link is down, ignoring transmit request\n");
5665 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
5666 fp->eth_q_stats.tx_queue_full_return++;
5671 bxe_tx_start_locked(sc, ifp, fp);
5672 BXE_FP_TX_UNLOCK(fp);
5675 #if __FreeBSD_version >= 901504
5678 bxe_tx_mq_start_locked(struct bxe_softc *sc,
5680 struct bxe_fastpath *fp,
5683 struct buf_ring *tx_br = fp->tx_br;
5685 int depth, rc, tx_count;
5686 uint16_t tx_bd_avail;
5690 BXE_FP_TX_LOCK_ASSERT(fp);
5692 if (sc->state != BXE_STATE_OPEN) {
5693 fp->eth_q_stats.bxe_tx_mq_sc_state_failures++;
5698 BLOGE(sc, "Multiqueue TX and no buf_ring!\n");
5703 rc = drbr_enqueue(ifp, tx_br, m);
5705 fp->eth_q_stats.tx_soft_errors++;
5706 goto bxe_tx_mq_start_locked_exit;
5710 if (!sc->link_vars.link_up || !(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5711 fp->eth_q_stats.tx_request_link_down_failures++;
5712 goto bxe_tx_mq_start_locked_exit;
5715 /* fetch the depth of the driver queue */
5716 depth = drbr_inuse(ifp, tx_br);
5717 if (depth > fp->eth_q_stats.tx_max_drbr_queue_depth) {
5718 fp->eth_q_stats.tx_max_drbr_queue_depth = depth;
5721 /* keep adding entries while there are frames to send */
5722 while ((next = drbr_peek(ifp, tx_br)) != NULL) {
5723 /* handle any completions if we're running low */
5724 tx_bd_avail = bxe_tx_avail(sc, fp);
5725 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5726 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5728 tx_bd_avail = bxe_tx_avail(sc, fp);
5729 if (tx_bd_avail < (BXE_TSO_MAX_SEGMENTS + 1)) {
5730 fp->eth_q_stats.bd_avail_too_less_failures++;
5732 drbr_advance(ifp, tx_br);
5738 /* the mbuf now belongs to us */
5739 fp->eth_q_stats.mbuf_alloc_tx++;
5742 * Put the frame into the transmit ring. If we don't have room,
5743 * place the mbuf back at the head of the TX queue, set the
5744 * OACTIVE flag, and wait for the NIC to drain the chain.
5746 rc = bxe_tx_encap(fp, &next);
5747 if (__predict_false(rc != 0)) {
5748 fp->eth_q_stats.tx_encap_failures++;
5750 /* mark the TX queue as full and save the frame */
5751 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5752 drbr_putback(ifp, tx_br, next);
5753 fp->eth_q_stats.mbuf_alloc_tx--;
5754 fp->eth_q_stats.tx_frames_deferred++;
5756 drbr_advance(ifp, tx_br);
5758 /* stop looking for more work */
5762 /* the transmit frame was enqueued successfully */
5765 /* send a copy of the frame to any BPF listeners */
5766 BPF_MTAP(ifp, next);
5768 drbr_advance(ifp, tx_br);
5771 /* all TX packets were dequeued and/or the tx ring is full */
5773 /* reset the TX watchdog timeout timer */
5774 fp->watchdog_timer = BXE_TX_TIMEOUT;
5777 bxe_tx_mq_start_locked_exit:
5778 /* If we didn't drain the drbr, enqueue a task in the future to do it. */
5779 if (!drbr_empty(ifp, tx_br)) {
5780 fp->eth_q_stats.tx_mq_not_empty++;
5781 taskqueue_enqueue_timeout(fp->tq, &fp->tx_timeout_task, 1);
5788 bxe_tx_mq_start_deferred(void *arg,
5791 struct bxe_fastpath *fp = (struct bxe_fastpath *)arg;
5792 struct bxe_softc *sc = fp->sc;
5793 struct ifnet *ifp = sc->ifnet;
5796 bxe_tx_mq_start_locked(sc, ifp, fp, NULL);
5797 BXE_FP_TX_UNLOCK(fp);
5800 /* Multiqueue (TSS) dispatch routine. */
5802 bxe_tx_mq_start(struct ifnet *ifp,
5805 struct bxe_softc *sc = ifp->if_softc;
5806 struct bxe_fastpath *fp;
5809 fp_index = 0; /* default is the first queue */
5811 /* check if flowid is set */
5813 if (BXE_VALID_FLOWID(m))
5814 fp_index = (m->m_pkthdr.flowid % sc->num_queues);
5816 fp = &sc->fp[fp_index];
5818 if (sc->state != BXE_STATE_OPEN) {
5819 fp->eth_q_stats.bxe_tx_mq_sc_state_failures++;
5823 if (BXE_FP_TX_TRYLOCK(fp)) {
5824 rc = bxe_tx_mq_start_locked(sc, ifp, fp, m);
5825 BXE_FP_TX_UNLOCK(fp);
5827 rc = drbr_enqueue(ifp, fp->tx_br, m);
5828 taskqueue_enqueue(fp->tq, &fp->tx_task);
5835 bxe_mq_flush(struct ifnet *ifp)
5837 struct bxe_softc *sc = ifp->if_softc;
5838 struct bxe_fastpath *fp;
5842 for (i = 0; i < sc->num_queues; i++) {
5845 if (fp->state != BXE_FP_STATE_IRQ) {
5846 BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n",
5847 fp->index, fp->state);
5851 if (fp->tx_br != NULL) {
5852 BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index);
5854 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) {
5857 BXE_FP_TX_UNLOCK(fp);
5864 #endif /* FreeBSD_version >= 901504 */
5867 bxe_cid_ilt_lines(struct bxe_softc *sc)
5870 return ((BXE_FIRST_VF_CID + BXE_VF_CIDS) / ILT_PAGE_CIDS);
5872 return (L2_ILT_LINES(sc));
5876 bxe_ilt_set_info(struct bxe_softc *sc)
5878 struct ilt_client_info *ilt_client;
5879 struct ecore_ilt *ilt = sc->ilt;
5882 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
5883 BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line);
5886 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
5887 ilt_client->client_num = ILT_CLIENT_CDU;
5888 ilt_client->page_size = CDU_ILT_PAGE_SZ;
5889 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
5890 ilt_client->start = line;
5891 line += bxe_cid_ilt_lines(sc);
5893 if (CNIC_SUPPORT(sc)) {
5894 line += CNIC_ILT_LINES;
5897 ilt_client->end = (line - 1);
5900 "ilt client[CDU]: start %d, end %d, "
5901 "psz 0x%x, flags 0x%x, hw psz %d\n",
5902 ilt_client->start, ilt_client->end,
5903 ilt_client->page_size,
5905 ilog2(ilt_client->page_size >> 12));
5908 if (QM_INIT(sc->qm_cid_count)) {
5909 ilt_client = &ilt->clients[ILT_CLIENT_QM];
5910 ilt_client->client_num = ILT_CLIENT_QM;
5911 ilt_client->page_size = QM_ILT_PAGE_SZ;
5912 ilt_client->flags = 0;
5913 ilt_client->start = line;
5915 /* 4 bytes for each cid */
5916 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
5919 ilt_client->end = (line - 1);
5922 "ilt client[QM]: start %d, end %d, "
5923 "psz 0x%x, flags 0x%x, hw psz %d\n",
5924 ilt_client->start, ilt_client->end,
5925 ilt_client->page_size, ilt_client->flags,
5926 ilog2(ilt_client->page_size >> 12));
5929 if (CNIC_SUPPORT(sc)) {
5931 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
5932 ilt_client->client_num = ILT_CLIENT_SRC;
5933 ilt_client->page_size = SRC_ILT_PAGE_SZ;
5934 ilt_client->flags = 0;
5935 ilt_client->start = line;
5936 line += SRC_ILT_LINES;
5937 ilt_client->end = (line - 1);
5940 "ilt client[SRC]: start %d, end %d, "
5941 "psz 0x%x, flags 0x%x, hw psz %d\n",
5942 ilt_client->start, ilt_client->end,
5943 ilt_client->page_size, ilt_client->flags,
5944 ilog2(ilt_client->page_size >> 12));
5947 ilt_client = &ilt->clients[ILT_CLIENT_TM];
5948 ilt_client->client_num = ILT_CLIENT_TM;
5949 ilt_client->page_size = TM_ILT_PAGE_SZ;
5950 ilt_client->flags = 0;
5951 ilt_client->start = line;
5952 line += TM_ILT_LINES;
5953 ilt_client->end = (line - 1);
5956 "ilt client[TM]: start %d, end %d, "
5957 "psz 0x%x, flags 0x%x, hw psz %d\n",
5958 ilt_client->start, ilt_client->end,
5959 ilt_client->page_size, ilt_client->flags,
5960 ilog2(ilt_client->page_size >> 12));
5963 KASSERT((line <= ILT_MAX_LINES), ("Invalid number of ILT lines!"));
5967 bxe_set_fp_rx_buf_size(struct bxe_softc *sc)
5970 uint32_t rx_buf_size;
5972 rx_buf_size = (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
5974 for (i = 0; i < sc->num_queues; i++) {
5975 if(rx_buf_size <= MCLBYTES){
5976 sc->fp[i].rx_buf_size = rx_buf_size;
5977 sc->fp[i].mbuf_alloc_size = MCLBYTES;
5978 }else if (rx_buf_size <= MJUMPAGESIZE){
5979 sc->fp[i].rx_buf_size = rx_buf_size;
5980 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
5981 }else if (rx_buf_size <= (MJUMPAGESIZE + MCLBYTES)){
5982 sc->fp[i].rx_buf_size = MCLBYTES;
5983 sc->fp[i].mbuf_alloc_size = MCLBYTES;
5984 }else if (rx_buf_size <= (2 * MJUMPAGESIZE)){
5985 sc->fp[i].rx_buf_size = MJUMPAGESIZE;
5986 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
5988 sc->fp[i].rx_buf_size = MCLBYTES;
5989 sc->fp[i].mbuf_alloc_size = MCLBYTES;
5995 bxe_alloc_ilt_mem(struct bxe_softc *sc)
6000 (struct ecore_ilt *)malloc(sizeof(struct ecore_ilt),
6002 (M_NOWAIT | M_ZERO))) == NULL) {
6010 bxe_alloc_ilt_lines_mem(struct bxe_softc *sc)
6014 if ((sc->ilt->lines =
6015 (struct ilt_line *)malloc((sizeof(struct ilt_line) * ILT_MAX_LINES),
6017 (M_NOWAIT | M_ZERO))) == NULL) {
6025 bxe_free_ilt_mem(struct bxe_softc *sc)
6027 if (sc->ilt != NULL) {
6028 free(sc->ilt, M_BXE_ILT);
6034 bxe_free_ilt_lines_mem(struct bxe_softc *sc)
6036 if (sc->ilt->lines != NULL) {
6037 free(sc->ilt->lines, M_BXE_ILT);
6038 sc->ilt->lines = NULL;
6043 bxe_free_mem(struct bxe_softc *sc)
6047 for (i = 0; i < L2_ILT_LINES(sc); i++) {
6048 bxe_dma_free(sc, &sc->context[i].vcxt_dma);
6049 sc->context[i].vcxt = NULL;
6050 sc->context[i].size = 0;
6053 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
6055 bxe_free_ilt_lines_mem(sc);
6060 bxe_alloc_mem(struct bxe_softc *sc)
6068 * Allocate memory for CDU context:
6069 * This memory is allocated separately and not in the generic ILT
6070 * functions because CDU differs in few aspects:
6071 * 1. There can be multiple entities allocating memory for context -
6072 * regular L2, CNIC, and SRIOV drivers. Each separately controls
6073 * its own ILT lines.
6074 * 2. Since CDU page-size is not a single 4KB page (which is the case
6075 * for the other ILT clients), to be efficient we want to support
6076 * allocation of sub-page-size in the last entry.
6077 * 3. Context pointers are used by the driver to pass to FW / update
6078 * the context (for the other ILT clients the pointers are used just to
6079 * free the memory during unload).
6081 context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc));
6082 for (i = 0, allocated = 0; allocated < context_size; i++) {
6083 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
6084 (context_size - allocated));
6086 if (bxe_dma_alloc(sc, sc->context[i].size,
6087 &sc->context[i].vcxt_dma,
6088 "cdu context") != 0) {
6093 sc->context[i].vcxt =
6094 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
6096 allocated += sc->context[i].size;
6099 bxe_alloc_ilt_lines_mem(sc);
6101 BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n",
6102 sc->ilt, sc->ilt->start_line, sc->ilt->lines);
6104 for (i = 0; i < 4; i++) {
6106 "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n",
6108 sc->ilt->clients[i].page_size,
6109 sc->ilt->clients[i].start,
6110 sc->ilt->clients[i].end,
6111 sc->ilt->clients[i].client_num,
6112 sc->ilt->clients[i].flags);
6115 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
6116 BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n");
6125 bxe_free_rx_bd_chain(struct bxe_fastpath *fp)
6127 struct bxe_softc *sc;
6132 if (fp->rx_mbuf_tag == NULL) {
6136 /* free all mbufs and unload all maps */
6137 for (i = 0; i < RX_BD_TOTAL; i++) {
6138 if (fp->rx_mbuf_chain[i].m_map != NULL) {
6139 bus_dmamap_sync(fp->rx_mbuf_tag,
6140 fp->rx_mbuf_chain[i].m_map,
6141 BUS_DMASYNC_POSTREAD);
6142 bus_dmamap_unload(fp->rx_mbuf_tag,
6143 fp->rx_mbuf_chain[i].m_map);
6146 if (fp->rx_mbuf_chain[i].m != NULL) {
6147 m_freem(fp->rx_mbuf_chain[i].m);
6148 fp->rx_mbuf_chain[i].m = NULL;
6149 fp->eth_q_stats.mbuf_alloc_rx--;
6155 bxe_free_tpa_pool(struct bxe_fastpath *fp)
6157 struct bxe_softc *sc;
6158 int i, max_agg_queues;
6162 if (fp->rx_mbuf_tag == NULL) {
6166 max_agg_queues = MAX_AGG_QS(sc);
6168 /* release all mbufs and unload all DMA maps in the TPA pool */
6169 for (i = 0; i < max_agg_queues; i++) {
6170 if (fp->rx_tpa_info[i].bd.m_map != NULL) {
6171 bus_dmamap_sync(fp->rx_mbuf_tag,
6172 fp->rx_tpa_info[i].bd.m_map,
6173 BUS_DMASYNC_POSTREAD);
6174 bus_dmamap_unload(fp->rx_mbuf_tag,
6175 fp->rx_tpa_info[i].bd.m_map);
6178 if (fp->rx_tpa_info[i].bd.m != NULL) {
6179 m_freem(fp->rx_tpa_info[i].bd.m);
6180 fp->rx_tpa_info[i].bd.m = NULL;
6181 fp->eth_q_stats.mbuf_alloc_tpa--;
6187 bxe_free_sge_chain(struct bxe_fastpath *fp)
6189 struct bxe_softc *sc;
6194 if (fp->rx_sge_mbuf_tag == NULL) {
6198 /* rree all mbufs and unload all maps */
6199 for (i = 0; i < RX_SGE_TOTAL; i++) {
6200 if (fp->rx_sge_mbuf_chain[i].m_map != NULL) {
6201 bus_dmamap_sync(fp->rx_sge_mbuf_tag,
6202 fp->rx_sge_mbuf_chain[i].m_map,
6203 BUS_DMASYNC_POSTREAD);
6204 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
6205 fp->rx_sge_mbuf_chain[i].m_map);
6208 if (fp->rx_sge_mbuf_chain[i].m != NULL) {
6209 m_freem(fp->rx_sge_mbuf_chain[i].m);
6210 fp->rx_sge_mbuf_chain[i].m = NULL;
6211 fp->eth_q_stats.mbuf_alloc_sge--;
6217 bxe_free_fp_buffers(struct bxe_softc *sc)
6219 struct bxe_fastpath *fp;
6222 for (i = 0; i < sc->num_queues; i++) {
6225 #if __FreeBSD_version >= 901504
6226 if (fp->tx_br != NULL) {
6227 /* just in case bxe_mq_flush() wasn't called */
6228 if (mtx_initialized(&fp->tx_mtx)) {
6232 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL)
6234 BXE_FP_TX_UNLOCK(fp);
6239 /* free all RX buffers */
6240 bxe_free_rx_bd_chain(fp);
6241 bxe_free_tpa_pool(fp);
6242 bxe_free_sge_chain(fp);
6244 if (fp->eth_q_stats.mbuf_alloc_rx != 0) {
6245 BLOGE(sc, "failed to claim all rx mbufs (%d left)\n",
6246 fp->eth_q_stats.mbuf_alloc_rx);
6249 if (fp->eth_q_stats.mbuf_alloc_sge != 0) {
6250 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6251 fp->eth_q_stats.mbuf_alloc_sge);
6254 if (fp->eth_q_stats.mbuf_alloc_tpa != 0) {
6255 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6256 fp->eth_q_stats.mbuf_alloc_tpa);
6259 if (fp->eth_q_stats.mbuf_alloc_tx != 0) {
6260 BLOGE(sc, "failed to release tx mbufs (%d left)\n",
6261 fp->eth_q_stats.mbuf_alloc_tx);
6264 /* XXX verify all mbufs were reclaimed */
6269 bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
6270 uint16_t prev_index,
6273 struct bxe_sw_rx_bd *rx_buf;
6274 struct eth_rx_bd *rx_bd;
6275 bus_dma_segment_t segs[1];
6282 /* allocate the new RX BD mbuf */
6283 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6284 if (__predict_false(m == NULL)) {
6285 fp->eth_q_stats.mbuf_rx_bd_alloc_failed++;
6289 fp->eth_q_stats.mbuf_alloc_rx++;
6291 /* initialize the mbuf buffer length */
6292 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6294 /* map the mbuf into non-paged pool */
6295 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6296 fp->rx_mbuf_spare_map,
6297 m, segs, &nsegs, BUS_DMA_NOWAIT);
6298 if (__predict_false(rc != 0)) {
6299 fp->eth_q_stats.mbuf_rx_bd_mapping_failed++;
6301 fp->eth_q_stats.mbuf_alloc_rx--;
6305 /* all mbufs must map to a single segment */
6306 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6308 /* release any existing RX BD mbuf mappings */
6310 if (prev_index != index) {
6311 rx_buf = &fp->rx_mbuf_chain[prev_index];
6313 if (rx_buf->m_map != NULL) {
6314 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6315 BUS_DMASYNC_POSTREAD);
6316 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6320 * We only get here from bxe_rxeof() when the maximum number
6321 * of rx buffers is less than RX_BD_USABLE. bxe_rxeof() already
6322 * holds the mbuf in the prev_index so it's OK to NULL it out
6323 * here without concern of a memory leak.
6325 fp->rx_mbuf_chain[prev_index].m = NULL;
6328 rx_buf = &fp->rx_mbuf_chain[index];
6330 if (rx_buf->m_map != NULL) {
6331 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6332 BUS_DMASYNC_POSTREAD);
6333 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6336 /* save the mbuf and mapping info for a future packet */
6337 map = (prev_index != index) ?
6338 fp->rx_mbuf_chain[prev_index].m_map : rx_buf->m_map;
6339 rx_buf->m_map = fp->rx_mbuf_spare_map;
6340 fp->rx_mbuf_spare_map = map;
6341 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6342 BUS_DMASYNC_PREREAD);
6345 rx_bd = &fp->rx_chain[index];
6346 rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6347 rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6353 bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
6356 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
6357 bus_dma_segment_t segs[1];
6363 /* allocate the new TPA mbuf */
6364 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6365 if (__predict_false(m == NULL)) {
6366 fp->eth_q_stats.mbuf_rx_tpa_alloc_failed++;
6370 fp->eth_q_stats.mbuf_alloc_tpa++;
6372 /* initialize the mbuf buffer length */
6373 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6375 /* map the mbuf into non-paged pool */
6376 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6377 fp->rx_tpa_info_mbuf_spare_map,
6378 m, segs, &nsegs, BUS_DMA_NOWAIT);
6379 if (__predict_false(rc != 0)) {
6380 fp->eth_q_stats.mbuf_rx_tpa_mapping_failed++;
6382 fp->eth_q_stats.mbuf_alloc_tpa--;
6386 /* all mbufs must map to a single segment */
6387 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6389 /* release any existing TPA mbuf mapping */
6390 if (tpa_info->bd.m_map != NULL) {
6391 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6392 BUS_DMASYNC_POSTREAD);
6393 bus_dmamap_unload(fp->rx_mbuf_tag, tpa_info->bd.m_map);
6396 /* save the mbuf and mapping info for the TPA mbuf */
6397 map = tpa_info->bd.m_map;
6398 tpa_info->bd.m_map = fp->rx_tpa_info_mbuf_spare_map;
6399 fp->rx_tpa_info_mbuf_spare_map = map;
6400 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6401 BUS_DMASYNC_PREREAD);
6403 tpa_info->seg = segs[0];
6409 * Allocate an mbuf and assign it to the receive scatter gather chain. The
6410 * caller must take care to save a copy of the existing mbuf in the SG mbuf
6414 bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
6417 struct bxe_sw_rx_bd *sge_buf;
6418 struct eth_rx_sge *sge;
6419 bus_dma_segment_t segs[1];
6425 /* allocate a new SGE mbuf */
6426 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE);
6427 if (__predict_false(m == NULL)) {
6428 fp->eth_q_stats.mbuf_rx_sge_alloc_failed++;
6432 fp->eth_q_stats.mbuf_alloc_sge++;
6434 /* initialize the mbuf buffer length */
6435 m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE;
6437 /* map the SGE mbuf into non-paged pool */
6438 rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_mbuf_tag,
6439 fp->rx_sge_mbuf_spare_map,
6440 m, segs, &nsegs, BUS_DMA_NOWAIT);
6441 if (__predict_false(rc != 0)) {
6442 fp->eth_q_stats.mbuf_rx_sge_mapping_failed++;
6444 fp->eth_q_stats.mbuf_alloc_sge--;
6448 /* all mbufs must map to a single segment */
6449 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6451 sge_buf = &fp->rx_sge_mbuf_chain[index];
6453 /* release any existing SGE mbuf mapping */
6454 if (sge_buf->m_map != NULL) {
6455 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6456 BUS_DMASYNC_POSTREAD);
6457 bus_dmamap_unload(fp->rx_sge_mbuf_tag, sge_buf->m_map);
6460 /* save the mbuf and mapping info for a future packet */
6461 map = sge_buf->m_map;
6462 sge_buf->m_map = fp->rx_sge_mbuf_spare_map;
6463 fp->rx_sge_mbuf_spare_map = map;
6464 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6465 BUS_DMASYNC_PREREAD);
6468 sge = &fp->rx_sge_chain[index];
6469 sge->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6470 sge->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6475 static __noinline int
6476 bxe_alloc_fp_buffers(struct bxe_softc *sc)
6478 struct bxe_fastpath *fp;
6480 int ring_prod, cqe_ring_prod;
6483 for (i = 0; i < sc->num_queues; i++) {
6486 ring_prod = cqe_ring_prod = 0;
6490 /* allocate buffers for the RX BDs in RX BD chain */
6491 for (j = 0; j < sc->max_rx_bufs; j++) {
6492 rc = bxe_alloc_rx_bd_mbuf(fp, ring_prod, ring_prod);
6494 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
6496 goto bxe_alloc_fp_buffers_error;
6499 ring_prod = RX_BD_NEXT(ring_prod);
6500 cqe_ring_prod = RCQ_NEXT(cqe_ring_prod);
6503 fp->rx_bd_prod = ring_prod;
6504 fp->rx_cq_prod = cqe_ring_prod;
6505 fp->eth_q_stats.rx_calls = fp->eth_q_stats.rx_pkts = 0;
6507 max_agg_queues = MAX_AGG_QS(sc);
6509 fp->tpa_enable = TRUE;
6511 /* fill the TPA pool */
6512 for (j = 0; j < max_agg_queues; j++) {
6513 rc = bxe_alloc_rx_tpa_mbuf(fp, j);
6515 BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n",
6517 fp->tpa_enable = FALSE;
6518 goto bxe_alloc_fp_buffers_error;
6521 fp->rx_tpa_info[j].state = BXE_TPA_STATE_STOP;
6524 if (fp->tpa_enable) {
6525 /* fill the RX SGE chain */
6527 for (j = 0; j < RX_SGE_USABLE; j++) {
6528 rc = bxe_alloc_rx_sge_mbuf(fp, ring_prod);
6530 BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n",
6532 fp->tpa_enable = FALSE;
6534 goto bxe_alloc_fp_buffers_error;
6537 ring_prod = RX_SGE_NEXT(ring_prod);
6540 fp->rx_sge_prod = ring_prod;
6546 bxe_alloc_fp_buffers_error:
6548 /* unwind what was already allocated */
6549 bxe_free_rx_bd_chain(fp);
6550 bxe_free_tpa_pool(fp);
6551 bxe_free_sge_chain(fp);
6557 bxe_free_fw_stats_mem(struct bxe_softc *sc)
6559 bxe_dma_free(sc, &sc->fw_stats_dma);
6561 sc->fw_stats_num = 0;
6563 sc->fw_stats_req_size = 0;
6564 sc->fw_stats_req = NULL;
6565 sc->fw_stats_req_mapping = 0;
6567 sc->fw_stats_data_size = 0;
6568 sc->fw_stats_data = NULL;
6569 sc->fw_stats_data_mapping = 0;
6573 bxe_alloc_fw_stats_mem(struct bxe_softc *sc)
6575 uint8_t num_queue_stats;
6578 /* number of queues for statistics is number of eth queues */
6579 num_queue_stats = BXE_NUM_ETH_QUEUES(sc);
6582 * Total number of FW statistics requests =
6583 * 1 for port stats + 1 for PF stats + num of queues
6585 sc->fw_stats_num = (2 + num_queue_stats);
6588 * Request is built from stats_query_header and an array of
6589 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
6590 * rules. The real number or requests is configured in the
6591 * stats_query_header.
6594 ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) +
6595 ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0));
6597 BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n",
6598 sc->fw_stats_num, num_groups);
6600 sc->fw_stats_req_size =
6601 (sizeof(struct stats_query_header) +
6602 (num_groups * sizeof(struct stats_query_cmd_group)));
6605 * Data for statistics requests + stats_counter.
6606 * stats_counter holds per-STORM counters that are incremented when
6607 * STORM has finished with the current request. Memory for FCoE
6608 * offloaded statistics are counted anyway, even if they will not be sent.
6609 * VF stats are not accounted for here as the data of VF stats is stored
6610 * in memory allocated by the VF, not here.
6612 sc->fw_stats_data_size =
6613 (sizeof(struct stats_counter) +
6614 sizeof(struct per_port_stats) +
6615 sizeof(struct per_pf_stats) +
6616 /* sizeof(struct fcoe_statistics_params) + */
6617 (sizeof(struct per_queue_stats) * num_queue_stats));
6619 if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
6620 &sc->fw_stats_dma, "fw stats") != 0) {
6621 bxe_free_fw_stats_mem(sc);
6625 /* set up the shortcuts */
6628 (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr;
6629 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
6632 (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr +
6633 sc->fw_stats_req_size);
6634 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
6635 sc->fw_stats_req_size);
6637 BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n",
6638 (uintmax_t)sc->fw_stats_req_mapping);
6640 BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n",
6641 (uintmax_t)sc->fw_stats_data_mapping);
6648 * 0-7 - Engine0 load counter.
6649 * 8-15 - Engine1 load counter.
6650 * 16 - Engine0 RESET_IN_PROGRESS bit.
6651 * 17 - Engine1 RESET_IN_PROGRESS bit.
6652 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
6653 * function on the engine
6654 * 19 - Engine1 ONE_IS_LOADED.
6655 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
6656 * leader to complete (check for both RESET_IN_PROGRESS bits and not
6657 * for just the one belonging to its engine).
6659 #define BXE_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
6660 #define BXE_PATH0_LOAD_CNT_MASK 0x000000ff
6661 #define BXE_PATH0_LOAD_CNT_SHIFT 0
6662 #define BXE_PATH1_LOAD_CNT_MASK 0x0000ff00
6663 #define BXE_PATH1_LOAD_CNT_SHIFT 8
6664 #define BXE_PATH0_RST_IN_PROG_BIT 0x00010000
6665 #define BXE_PATH1_RST_IN_PROG_BIT 0x00020000
6666 #define BXE_GLOBAL_RESET_BIT 0x00040000
6668 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
6670 bxe_set_reset_global(struct bxe_softc *sc)
6673 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6674 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6675 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT);
6676 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6679 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
6681 bxe_clear_reset_global(struct bxe_softc *sc)
6684 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6685 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6686 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT));
6687 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6690 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
6692 bxe_reset_is_global(struct bxe_softc *sc)
6694 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6695 BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val);
6696 return (val & BXE_GLOBAL_RESET_BIT) ? TRUE : FALSE;
6699 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
6701 bxe_set_reset_done(struct bxe_softc *sc)
6704 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
6705 BXE_PATH0_RST_IN_PROG_BIT;
6707 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6709 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6712 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6714 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6717 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
6719 bxe_set_reset_in_progress(struct bxe_softc *sc)
6722 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
6723 BXE_PATH0_RST_IN_PROG_BIT;
6725 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6727 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6730 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6732 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6735 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
6737 bxe_reset_is_done(struct bxe_softc *sc,
6740 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6741 uint32_t bit = engine ? BXE_PATH1_RST_IN_PROG_BIT :
6742 BXE_PATH0_RST_IN_PROG_BIT;
6744 /* return false if bit is set */
6745 return (val & bit) ? FALSE : TRUE;
6748 /* get the load status for an engine, should be run under rtnl lock */
6750 bxe_get_load_status(struct bxe_softc *sc,
6753 uint32_t mask = engine ? BXE_PATH1_LOAD_CNT_MASK :
6754 BXE_PATH0_LOAD_CNT_MASK;
6755 uint32_t shift = engine ? BXE_PATH1_LOAD_CNT_SHIFT :
6756 BXE_PATH0_LOAD_CNT_SHIFT;
6757 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6759 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
6761 val = ((val & mask) >> shift);
6763 BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val);
6768 /* set pf load mark */
6769 /* XXX needs to be under rtnl lock */
6771 bxe_set_pf_load(struct bxe_softc *sc)
6775 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
6776 BXE_PATH0_LOAD_CNT_MASK;
6777 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
6778 BXE_PATH0_LOAD_CNT_SHIFT;
6780 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6782 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6783 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
6785 /* get the current counter value */
6786 val1 = ((val & mask) >> shift);
6788 /* set bit of this PF */
6789 val1 |= (1 << SC_ABS_FUNC(sc));
6791 /* clear the old value */
6794 /* set the new one */
6795 val |= ((val1 << shift) & mask);
6797 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6799 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6802 /* clear pf load mark */
6803 /* XXX needs to be under rtnl lock */
6805 bxe_clear_pf_load(struct bxe_softc *sc)
6808 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
6809 BXE_PATH0_LOAD_CNT_MASK;
6810 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
6811 BXE_PATH0_LOAD_CNT_SHIFT;
6813 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6814 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6815 BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val);
6817 /* get the current counter value */
6818 val1 = (val & mask) >> shift;
6820 /* clear bit of that PF */
6821 val1 &= ~(1 << SC_ABS_FUNC(sc));
6823 /* clear the old value */
6826 /* set the new one */
6827 val |= ((val1 << shift) & mask);
6829 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6830 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6834 /* send load requrest to mcp and analyze response */
6836 bxe_nic_load_request(struct bxe_softc *sc,
6837 uint32_t *load_code)
6841 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
6842 DRV_MSG_SEQ_NUMBER_MASK);
6844 BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq);
6846 /* get the current FW pulse sequence */
6847 sc->fw_drv_pulse_wr_seq =
6848 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
6849 DRV_PULSE_SEQ_MASK);
6851 BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n",
6852 sc->fw_drv_pulse_wr_seq);
6855 (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6856 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6858 /* if the MCP fails to respond we must abort */
6859 if (!(*load_code)) {
6860 BLOGE(sc, "MCP response failure!\n");
6864 /* if MCP refused then must abort */
6865 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
6866 BLOGE(sc, "MCP refused load request\n");
6874 * Check whether another PF has already loaded FW to chip. In virtualized
6875 * environments a pf from anoth VM may have already initialized the device
6876 * including loading FW.
6879 bxe_nic_load_analyze_req(struct bxe_softc *sc,
6882 uint32_t my_fw, loaded_fw;
6884 /* is another pf loaded on this engine? */
6885 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6886 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6887 /* build my FW version dword */
6888 my_fw = (BCM_5710_FW_MAJOR_VERSION +
6889 (BCM_5710_FW_MINOR_VERSION << 8 ) +
6890 (BCM_5710_FW_REVISION_VERSION << 16) +
6891 (BCM_5710_FW_ENGINEERING_VERSION << 24));
6893 /* read loaded FW from chip */
6894 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
6895 BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n",
6898 /* abort nic load if version mismatch */
6899 if (my_fw != loaded_fw) {
6900 BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)",
6909 /* mark PMF if applicable */
6911 bxe_nic_load_pmf(struct bxe_softc *sc,
6914 uint32_t ncsi_oem_data_addr;
6916 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
6917 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
6918 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
6920 * Barrier here for ordering between the writing to sc->port.pmf here
6921 * and reading it from the periodic task.
6929 BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf);
6932 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
6933 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
6934 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
6935 if (ncsi_oem_data_addr) {
6937 (ncsi_oem_data_addr +
6938 offsetof(struct glob_ncsi_oem_data, driver_version)),
6946 bxe_read_mf_cfg(struct bxe_softc *sc)
6948 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
6952 if (BXE_NOMCP(sc)) {
6953 return; /* what should be the default bvalue in this case */
6957 * The formula for computing the absolute function number is...
6958 * For 2 port configuration (4 functions per port):
6959 * abs_func = 2 * vn + SC_PORT + SC_PATH
6960 * For 4 port configuration (2 functions per port):
6961 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
6963 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
6964 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
6965 if (abs_func >= E1H_FUNC_MAX) {
6968 sc->devinfo.mf_info.mf_config[vn] =
6969 MFCFG_RD(sc, func_mf_config[abs_func].config);
6972 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
6973 FUNC_MF_CFG_FUNC_DISABLED) {
6974 BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n");
6975 sc->flags |= BXE_MF_FUNC_DIS;
6977 BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n");
6978 sc->flags &= ~BXE_MF_FUNC_DIS;
6982 /* acquire split MCP access lock register */
6983 static int bxe_acquire_alr(struct bxe_softc *sc)
6987 for (j = 0; j < 1000; j++) {
6989 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
6990 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
6991 if (val & (1L << 31))
6997 if (!(val & (1L << 31))) {
6998 BLOGE(sc, "Cannot acquire MCP access lock register\n");
7005 /* release split MCP access lock register */
7006 static void bxe_release_alr(struct bxe_softc *sc)
7008 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
7012 bxe_fan_failure(struct bxe_softc *sc)
7014 int port = SC_PORT(sc);
7015 uint32_t ext_phy_config;
7017 /* mark the failure */
7019 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
7021 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
7022 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
7023 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
7026 /* log the failure */
7027 BLOGW(sc, "Fan Failure has caused the driver to shutdown "
7028 "the card to prevent permanent damage. "
7029 "Please contact OEM Support for assistance\n");
7033 bxe_panic(sc, ("Schedule task to handle fan failure\n"));
7036 * Schedule device reset (unload)
7037 * This is due to some boards consuming sufficient power when driver is
7038 * up to overheat if fan fails.
7040 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state);
7041 schedule_delayed_work(&sc->sp_rtnl_task, 0);
7045 /* this function is called upon a link interrupt */
7047 bxe_link_attn(struct bxe_softc *sc)
7049 uint32_t pause_enabled = 0;
7050 struct host_port_stats *pstats;
7052 struct bxe_fastpath *fp;
7055 /* Make sure that we are synced with the current statistics */
7056 bxe_stats_handle(sc, STATS_EVENT_STOP);
7057 BLOGD(sc, DBG_LOAD, "link_vars phy_flags : %x\n", sc->link_vars.phy_flags);
7058 elink_link_update(&sc->link_params, &sc->link_vars);
7060 if (sc->link_vars.link_up) {
7062 /* dropless flow control */
7063 if (!CHIP_IS_E1(sc) && sc->dropless_fc) {
7066 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
7071 (BAR_USTRORM_INTMEM +
7072 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
7076 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
7077 pstats = BXE_SP(sc, port_stats);
7078 /* reset old mac stats */
7079 memset(&(pstats->mac_stx[0]), 0, sizeof(struct mac_stx));
7082 if (sc->state == BXE_STATE_OPEN) {
7083 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
7086 /* Restart tx when the link comes back. */
7087 FOR_EACH_ETH_QUEUE(sc, i) {
7089 taskqueue_enqueue(fp->tq, &fp->tx_task);
7093 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
7094 cmng_fns = bxe_get_cmng_fns_mode(sc);
7096 if (cmng_fns != CMNG_FNS_NONE) {
7097 bxe_cmng_fns_init(sc, FALSE, cmng_fns);
7098 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7100 /* rate shaping and fairness are disabled */
7101 BLOGD(sc, DBG_LOAD, "single function mode without fairness\n");
7105 bxe_link_report_locked(sc);
7108 ; // XXX bxe_link_sync_notify(sc);
7113 bxe_attn_int_asserted(struct bxe_softc *sc,
7116 int port = SC_PORT(sc);
7117 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7118 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7119 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
7120 NIG_REG_MASK_INTERRUPT_PORT0;
7122 uint32_t nig_mask = 0;
7127 if (sc->attn_state & asserted) {
7128 BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted);
7131 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7133 aeu_mask = REG_RD(sc, aeu_addr);
7135 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n",
7136 aeu_mask, asserted);
7138 aeu_mask &= ~(asserted & 0x3ff);
7140 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
7142 REG_WR(sc, aeu_addr, aeu_mask);
7144 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7146 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
7147 sc->attn_state |= asserted;
7148 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
7150 if (asserted & ATTN_HARD_WIRED_MASK) {
7151 if (asserted & ATTN_NIG_FOR_FUNC) {
7153 bxe_acquire_phy_lock(sc);
7154 /* save nig interrupt mask */
7155 nig_mask = REG_RD(sc, nig_int_mask_addr);
7157 /* If nig_mask is not set, no need to call the update function */
7159 REG_WR(sc, nig_int_mask_addr, 0);
7164 /* handle unicore attn? */
7167 if (asserted & ATTN_SW_TIMER_4_FUNC) {
7168 BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n");
7171 if (asserted & GPIO_2_FUNC) {
7172 BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n");
7175 if (asserted & GPIO_3_FUNC) {
7176 BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n");
7179 if (asserted & GPIO_4_FUNC) {
7180 BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n");
7184 if (asserted & ATTN_GENERAL_ATTN_1) {
7185 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n");
7186 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
7188 if (asserted & ATTN_GENERAL_ATTN_2) {
7189 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n");
7190 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
7192 if (asserted & ATTN_GENERAL_ATTN_3) {
7193 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n");
7194 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
7197 if (asserted & ATTN_GENERAL_ATTN_4) {
7198 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n");
7199 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
7201 if (asserted & ATTN_GENERAL_ATTN_5) {
7202 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n");
7203 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
7205 if (asserted & ATTN_GENERAL_ATTN_6) {
7206 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n");
7207 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
7212 if (sc->devinfo.int_block == INT_BLOCK_HC) {
7213 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET);
7215 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
7218 BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n",
7220 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
7221 REG_WR(sc, reg_addr, asserted);
7223 /* now set back the mask */
7224 if (asserted & ATTN_NIG_FOR_FUNC) {
7226 * Verify that IGU ack through BAR was written before restoring
7227 * NIG mask. This loop should exit after 2-3 iterations max.
7229 if (sc->devinfo.int_block != INT_BLOCK_HC) {
7233 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
7234 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
7235 (++cnt < MAX_IGU_ATTN_ACK_TO));
7238 BLOGE(sc, "Failed to verify IGU ack on time\n");
7244 REG_WR(sc, nig_int_mask_addr, nig_mask);
7246 bxe_release_phy_lock(sc);
7251 bxe_print_next_block(struct bxe_softc *sc,
7255 BLOGI(sc, "%s%s", idx ? ", " : "", blk);
7259 bxe_check_blocks_with_parity0(struct bxe_softc *sc,
7264 uint32_t cur_bit = 0;
7267 for (i = 0; sig; i++) {
7268 cur_bit = ((uint32_t)0x1 << i);
7269 if (sig & cur_bit) {
7271 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
7273 bxe_print_next_block(sc, par_num++, "BRB");
7275 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
7277 bxe_print_next_block(sc, par_num++, "PARSER");
7279 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
7281 bxe_print_next_block(sc, par_num++, "TSDM");
7283 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
7285 bxe_print_next_block(sc, par_num++, "SEARCHER");
7287 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
7289 bxe_print_next_block(sc, par_num++, "TCM");
7291 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
7293 bxe_print_next_block(sc, par_num++, "TSEMI");
7295 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
7297 bxe_print_next_block(sc, par_num++, "XPB");
7310 bxe_check_blocks_with_parity1(struct bxe_softc *sc,
7317 uint32_t cur_bit = 0;
7318 for (i = 0; sig; i++) {
7319 cur_bit = ((uint32_t)0x1 << i);
7320 if (sig & cur_bit) {
7322 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
7324 bxe_print_next_block(sc, par_num++, "PBF");
7326 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
7328 bxe_print_next_block(sc, par_num++, "QM");
7330 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
7332 bxe_print_next_block(sc, par_num++, "TM");
7334 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
7336 bxe_print_next_block(sc, par_num++, "XSDM");
7338 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
7340 bxe_print_next_block(sc, par_num++, "XCM");
7342 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
7344 bxe_print_next_block(sc, par_num++, "XSEMI");
7346 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
7348 bxe_print_next_block(sc, par_num++, "DOORBELLQ");
7350 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
7352 bxe_print_next_block(sc, par_num++, "NIG");
7354 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
7356 bxe_print_next_block(sc, par_num++, "VAUX PCI CORE");
7359 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
7361 bxe_print_next_block(sc, par_num++, "DEBUG");
7363 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
7365 bxe_print_next_block(sc, par_num++, "USDM");
7367 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
7369 bxe_print_next_block(sc, par_num++, "UCM");
7371 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
7373 bxe_print_next_block(sc, par_num++, "USEMI");
7375 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
7377 bxe_print_next_block(sc, par_num++, "UPB");
7379 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
7381 bxe_print_next_block(sc, par_num++, "CSDM");
7383 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
7385 bxe_print_next_block(sc, par_num++, "CCM");
7398 bxe_check_blocks_with_parity2(struct bxe_softc *sc,
7403 uint32_t cur_bit = 0;
7406 for (i = 0; sig; i++) {
7407 cur_bit = ((uint32_t)0x1 << i);
7408 if (sig & cur_bit) {
7410 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
7412 bxe_print_next_block(sc, par_num++, "CSEMI");
7414 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
7416 bxe_print_next_block(sc, par_num++, "PXP");
7418 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
7420 bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT");
7422 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
7424 bxe_print_next_block(sc, par_num++, "CFC");
7426 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
7428 bxe_print_next_block(sc, par_num++, "CDU");
7430 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
7432 bxe_print_next_block(sc, par_num++, "DMAE");
7434 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
7436 bxe_print_next_block(sc, par_num++, "IGU");
7438 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
7440 bxe_print_next_block(sc, par_num++, "MISC");
7453 bxe_check_blocks_with_parity3(struct bxe_softc *sc,
7459 uint32_t cur_bit = 0;
7462 for (i = 0; sig; i++) {
7463 cur_bit = ((uint32_t)0x1 << i);
7464 if (sig & cur_bit) {
7466 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
7468 bxe_print_next_block(sc, par_num++, "MCP ROM");
7471 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
7473 bxe_print_next_block(sc, par_num++,
7477 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
7479 bxe_print_next_block(sc, par_num++,
7483 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
7485 bxe_print_next_block(sc, par_num++,
7500 bxe_check_blocks_with_parity4(struct bxe_softc *sc,
7505 uint32_t cur_bit = 0;
7508 for (i = 0; sig; i++) {
7509 cur_bit = ((uint32_t)0x1 << i);
7510 if (sig & cur_bit) {
7512 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
7514 bxe_print_next_block(sc, par_num++, "PGLUE_B");
7516 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
7518 bxe_print_next_block(sc, par_num++, "ATC");
7531 bxe_parity_attn(struct bxe_softc *sc,
7538 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
7539 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
7540 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
7541 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
7542 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
7543 BLOGE(sc, "Parity error: HW block parity attention:\n"
7544 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
7545 (uint32_t)(sig[0] & HW_PRTY_ASSERT_SET_0),
7546 (uint32_t)(sig[1] & HW_PRTY_ASSERT_SET_1),
7547 (uint32_t)(sig[2] & HW_PRTY_ASSERT_SET_2),
7548 (uint32_t)(sig[3] & HW_PRTY_ASSERT_SET_3),
7549 (uint32_t)(sig[4] & HW_PRTY_ASSERT_SET_4));
7552 BLOGI(sc, "Parity errors detected in blocks: ");
7555 bxe_check_blocks_with_parity0(sc, sig[0] &
7556 HW_PRTY_ASSERT_SET_0,
7559 bxe_check_blocks_with_parity1(sc, sig[1] &
7560 HW_PRTY_ASSERT_SET_1,
7561 par_num, global, print);
7563 bxe_check_blocks_with_parity2(sc, sig[2] &
7564 HW_PRTY_ASSERT_SET_2,
7567 bxe_check_blocks_with_parity3(sc, sig[3] &
7568 HW_PRTY_ASSERT_SET_3,
7569 par_num, global, print);
7571 bxe_check_blocks_with_parity4(sc, sig[4] &
7572 HW_PRTY_ASSERT_SET_4,
7585 bxe_chk_parity_attn(struct bxe_softc *sc,
7589 struct attn_route attn = { {0} };
7590 int port = SC_PORT(sc);
7592 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
7593 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
7594 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
7595 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
7598 * Since MCP attentions can't be disabled inside the block, we need to
7599 * read AEU registers to see whether they're currently disabled
7601 attn.sig[3] &= ((REG_RD(sc, (!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
7602 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0)) &
7603 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
7604 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
7607 if (!CHIP_IS_E1x(sc))
7608 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
7610 return (bxe_parity_attn(sc, global, print, attn.sig));
7614 bxe_attn_int_deasserted4(struct bxe_softc *sc,
7619 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
7620 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
7621 BLOGE(sc, "PGLUE hw attention 0x%08x\n", val);
7622 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
7623 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
7624 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
7625 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
7626 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
7627 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
7628 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
7629 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
7630 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
7631 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
7632 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
7633 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
7634 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
7635 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
7636 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
7637 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
7638 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
7639 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
7642 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
7643 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
7644 BLOGE(sc, "ATC hw attention 0x%08x\n", val);
7645 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
7646 BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
7647 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
7648 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
7649 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
7650 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
7651 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
7652 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
7653 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
7654 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
7655 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
7656 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
7659 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7660 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
7661 BLOGE(sc, "FATAL parity attention set4 0x%08x\n",
7662 (uint32_t)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7663 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
7668 bxe_e1h_disable(struct bxe_softc *sc)
7670 int port = SC_PORT(sc);
7674 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7678 bxe_e1h_enable(struct bxe_softc *sc)
7680 int port = SC_PORT(sc);
7682 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7684 // XXX bxe_tx_enable(sc);
7688 * called due to MCP event (on pmf):
7689 * reread new bandwidth configuration
7691 * notify others function about the change
7694 bxe_config_mf_bw(struct bxe_softc *sc)
7696 if (sc->link_vars.link_up) {
7697 bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
7698 // XXX bxe_link_sync_notify(sc);
7701 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7705 bxe_set_mf_bw(struct bxe_softc *sc)
7707 bxe_config_mf_bw(sc);
7708 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
7712 bxe_handle_eee_event(struct bxe_softc *sc)
7714 BLOGD(sc, DBG_INTR, "EEE - LLDP event\n");
7715 bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
7718 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
7721 bxe_drv_info_ether_stat(struct bxe_softc *sc)
7723 struct eth_stats_info *ether_stat =
7724 &sc->sp->drv_info_to_mcp.ether_stat;
7726 strlcpy(ether_stat->version, BXE_DRIVER_VERSION,
7727 ETH_STAT_INFO_VERSION_LEN);
7729 /* XXX (+ MAC_PAD) taken from other driver... verify this is right */
7730 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
7731 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
7732 ether_stat->mac_local + MAC_PAD,
7735 ether_stat->mtu_size = sc->mtu;
7737 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
7738 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) {
7739 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
7742 // XXX ether_stat->feature_flags |= ???;
7744 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
7746 ether_stat->txq_size = sc->tx_ring_size;
7747 ether_stat->rxq_size = sc->rx_ring_size;
7751 bxe_handle_drv_info_req(struct bxe_softc *sc)
7753 enum drv_info_opcode op_code;
7754 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
7756 /* if drv_info version supported by MFW doesn't match - send NACK */
7757 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
7758 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
7762 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
7763 DRV_INFO_CONTROL_OP_CODE_SHIFT);
7765 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
7768 case ETH_STATS_OPCODE:
7769 bxe_drv_info_ether_stat(sc);
7771 case FCOE_STATS_OPCODE:
7772 case ISCSI_STATS_OPCODE:
7774 /* if op code isn't supported - send NACK */
7775 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
7780 * If we got drv_info attn from MFW then these fields are defined in
7783 SHMEM2_WR(sc, drv_info_host_addr_lo,
7784 U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
7785 SHMEM2_WR(sc, drv_info_host_addr_hi,
7786 U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
7788 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
7792 bxe_dcc_event(struct bxe_softc *sc,
7795 BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event);
7797 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
7799 * This is the only place besides the function initialization
7800 * where the sc->flags can change so it is done without any
7803 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
7804 BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n");
7805 sc->flags |= BXE_MF_FUNC_DIS;
7806 bxe_e1h_disable(sc);
7808 BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n");
7809 sc->flags &= ~BXE_MF_FUNC_DIS;
7812 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
7815 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
7816 bxe_config_mf_bw(sc);
7817 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
7820 /* Report results to MCP */
7822 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
7824 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
7828 bxe_pmf_update(struct bxe_softc *sc)
7830 int port = SC_PORT(sc);
7834 BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf);
7837 * We need the mb() to ensure the ordering between the writing to
7838 * sc->port.pmf here and reading it from the bxe_periodic_task().
7842 /* queue a periodic task */
7843 // XXX schedule task...
7845 // XXX bxe_dcbx_pmf_update(sc);
7847 /* enable nig attention */
7848 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
7849 if (sc->devinfo.int_block == INT_BLOCK_HC) {
7850 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val);
7851 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val);
7852 } else if (!CHIP_IS_E1x(sc)) {
7853 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
7854 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
7857 bxe_stats_handle(sc, STATS_EVENT_PMF);
7861 bxe_mc_assert(struct bxe_softc *sc)
7865 uint32_t row0, row1, row2, row3;
7868 last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
7870 BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7872 /* print the asserts */
7873 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7875 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
7876 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4);
7877 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8);
7878 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12);
7880 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7881 BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7882 i, row3, row2, row1, row0);
7890 last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
7892 BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7895 /* print the asserts */
7896 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7898 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
7899 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4);
7900 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8);
7901 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12);
7903 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7904 BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7905 i, row3, row2, row1, row0);
7913 last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
7915 BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7918 /* print the asserts */
7919 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7921 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
7922 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4);
7923 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8);
7924 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12);
7926 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7927 BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7928 i, row3, row2, row1, row0);
7936 last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
7938 BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7941 /* print the asserts */
7942 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7944 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
7945 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4);
7946 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8);
7947 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12);
7949 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7950 BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7951 i, row3, row2, row1, row0);
7962 bxe_attn_int_deasserted3(struct bxe_softc *sc,
7965 int func = SC_FUNC(sc);
7968 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
7970 if (attn & BXE_PMF_LINK_ASSERT(sc)) {
7972 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7973 bxe_read_mf_cfg(sc);
7974 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
7975 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7976 val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
7978 if (val & DRV_STATUS_DCC_EVENT_MASK)
7979 bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK));
7981 if (val & DRV_STATUS_SET_MF_BW)
7984 if (val & DRV_STATUS_DRV_INFO_REQ)
7985 bxe_handle_drv_info_req(sc);
7987 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
7990 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
7991 bxe_handle_eee_event(sc);
7993 if (sc->link_vars.periodic_flags &
7994 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
7995 /* sync with link */
7996 bxe_acquire_phy_lock(sc);
7997 sc->link_vars.periodic_flags &=
7998 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
7999 bxe_release_phy_lock(sc);
8001 ; // XXX bxe_link_sync_notify(sc);
8002 bxe_link_report(sc);
8006 * Always call it here: bxe_link_report() will
8007 * prevent the link indication duplication.
8009 bxe_link_status_update(sc);
8011 } else if (attn & BXE_MC_ASSERT_BITS) {
8013 BLOGE(sc, "MC assert!\n");
8015 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
8016 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
8017 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
8018 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
8019 bxe_panic(sc, ("MC assert!\n"));
8021 } else if (attn & BXE_MCP_ASSERT) {
8023 BLOGE(sc, "MCP assert!\n");
8024 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
8025 // XXX bxe_fw_dump(sc);
8028 BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn);
8032 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
8033 BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn);
8034 if (attn & BXE_GRC_TIMEOUT) {
8035 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
8036 BLOGE(sc, "GRC time-out 0x%08x\n", val);
8038 if (attn & BXE_GRC_RSV) {
8039 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
8040 BLOGE(sc, "GRC reserved 0x%08x\n", val);
8042 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
8047 bxe_attn_int_deasserted2(struct bxe_softc *sc,
8050 int port = SC_PORT(sc);
8052 uint32_t val0, mask0, val1, mask1;
8055 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
8056 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
8057 BLOGE(sc, "CFC hw attention 0x%08x\n", val);
8058 /* CFC error attention */
8060 BLOGE(sc, "FATAL error from CFC\n");
8064 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
8065 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
8066 BLOGE(sc, "PXP hw attention-0 0x%08x\n", val);
8067 /* RQ_USDMDP_FIFO_OVERFLOW */
8068 if (val & 0x18000) {
8069 BLOGE(sc, "FATAL error from PXP\n");
8072 if (!CHIP_IS_E1x(sc)) {
8073 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
8074 BLOGE(sc, "PXP hw attention-1 0x%08x\n", val);
8078 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
8079 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
8081 if (attn & AEU_PXP2_HW_INT_BIT) {
8082 /* CQ47854 workaround do not panic on
8083 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8085 if (!CHIP_IS_E1x(sc)) {
8086 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
8087 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
8088 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
8089 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
8091 * If the olny PXP2_EOP_ERROR_BIT is set in
8092 * STS0 and STS1 - clear it
8094 * probably we lose additional attentions between
8095 * STS0 and STS_CLR0, in this case user will not
8096 * be notified about them
8098 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
8100 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
8102 /* print the register, since no one can restore it */
8103 BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0);
8106 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8109 if (val0 & PXP2_EOP_ERROR_BIT) {
8110 BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n");
8113 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
8114 * set then clear attention from PXP2 block without panic
8116 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
8117 ((val1 & mask1) == 0))
8118 attn &= ~AEU_PXP2_HW_INT_BIT;
8123 if (attn & HW_INTERRUT_ASSERT_SET_2) {
8124 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
8125 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
8127 val = REG_RD(sc, reg_offset);
8128 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
8129 REG_WR(sc, reg_offset, val);
8131 BLOGE(sc, "FATAL HW block attention set2 0x%x\n",
8132 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_2));
8133 bxe_panic(sc, ("HW block attention set2\n"));
8138 bxe_attn_int_deasserted1(struct bxe_softc *sc,
8141 int port = SC_PORT(sc);
8145 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
8146 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
8147 BLOGE(sc, "DB hw attention 0x%08x\n", val);
8148 /* DORQ discard attention */
8150 BLOGE(sc, "FATAL error from DORQ\n");
8154 if (attn & HW_INTERRUT_ASSERT_SET_1) {
8155 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
8156 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
8158 val = REG_RD(sc, reg_offset);
8159 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
8160 REG_WR(sc, reg_offset, val);
8162 BLOGE(sc, "FATAL HW block attention set1 0x%08x\n",
8163 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_1));
8164 bxe_panic(sc, ("HW block attention set1\n"));
8169 bxe_attn_int_deasserted0(struct bxe_softc *sc,
8172 int port = SC_PORT(sc);
8176 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
8177 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
8179 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
8180 val = REG_RD(sc, reg_offset);
8181 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
8182 REG_WR(sc, reg_offset, val);
8184 BLOGW(sc, "SPIO5 hw attention\n");
8186 /* Fan failure attention */
8187 elink_hw_reset_phy(&sc->link_params);
8188 bxe_fan_failure(sc);
8191 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
8192 bxe_acquire_phy_lock(sc);
8193 elink_handle_module_detect_int(&sc->link_params);
8194 bxe_release_phy_lock(sc);
8197 if (attn & HW_INTERRUT_ASSERT_SET_0) {
8198 val = REG_RD(sc, reg_offset);
8199 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
8200 REG_WR(sc, reg_offset, val);
8202 bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n",
8203 (attn & HW_INTERRUT_ASSERT_SET_0)));
8208 bxe_attn_int_deasserted(struct bxe_softc *sc,
8209 uint32_t deasserted)
8211 struct attn_route attn;
8212 struct attn_route *group_mask;
8213 int port = SC_PORT(sc);
8218 uint8_t global = FALSE;
8221 * Need to take HW lock because MCP or other port might also
8222 * try to handle this event.
8224 bxe_acquire_alr(sc);
8226 if (bxe_chk_parity_attn(sc, &global, TRUE)) {
8228 * In case of parity errors don't handle attentions so that
8229 * other function would "see" parity errors.
8231 sc->recovery_state = BXE_RECOVERY_INIT;
8232 // XXX schedule a recovery task...
8233 /* disable HW interrupts */
8234 bxe_int_disable(sc);
8235 bxe_release_alr(sc);
8239 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
8240 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
8241 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
8242 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
8243 if (!CHIP_IS_E1x(sc)) {
8244 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
8249 BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
8250 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
8252 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
8253 if (deasserted & (1 << index)) {
8254 group_mask = &sc->attn_group[index];
8257 "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index,
8258 group_mask->sig[0], group_mask->sig[1],
8259 group_mask->sig[2], group_mask->sig[3],
8260 group_mask->sig[4]);
8262 bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]);
8263 bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]);
8264 bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]);
8265 bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]);
8266 bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]);
8270 bxe_release_alr(sc);
8272 if (sc->devinfo.int_block == INT_BLOCK_HC) {
8273 reg_addr = (HC_REG_COMMAND_REG + port*32 +
8274 COMMAND_REG_ATTN_BITS_CLR);
8276 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
8281 "about to mask 0x%08x at %s addr 0x%08x\n", val,
8282 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
8283 REG_WR(sc, reg_addr, val);
8285 if (~sc->attn_state & deasserted) {
8286 BLOGE(sc, "IGU error\n");
8289 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8290 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8292 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8294 aeu_mask = REG_RD(sc, reg_addr);
8296 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n",
8297 aeu_mask, deasserted);
8298 aeu_mask |= (deasserted & 0x3ff);
8299 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
8301 REG_WR(sc, reg_addr, aeu_mask);
8302 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8304 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
8305 sc->attn_state &= ~deasserted;
8306 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
8310 bxe_attn_int(struct bxe_softc *sc)
8312 /* read local copy of bits */
8313 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
8314 uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
8315 uint32_t attn_state = sc->attn_state;
8317 /* look for changed bits */
8318 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
8319 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
8322 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n",
8323 attn_bits, attn_ack, asserted, deasserted);
8325 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
8326 BLOGE(sc, "BAD attention state\n");
8329 /* handle bits that were raised */
8331 bxe_attn_int_asserted(sc, asserted);
8335 bxe_attn_int_deasserted(sc, deasserted);
8340 bxe_update_dsb_idx(struct bxe_softc *sc)
8342 struct host_sp_status_block *def_sb = sc->def_sb;
8345 mb(); /* status block is written to by the chip */
8347 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
8348 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
8349 rc |= BXE_DEF_SB_ATT_IDX;
8352 if (sc->def_idx != def_sb->sp_sb.running_index) {
8353 sc->def_idx = def_sb->sp_sb.running_index;
8354 rc |= BXE_DEF_SB_IDX;
8362 static inline struct ecore_queue_sp_obj *
8363 bxe_cid_to_q_obj(struct bxe_softc *sc,
8366 BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid);
8367 return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj);
8371 bxe_handle_mcast_eqe(struct bxe_softc *sc)
8373 struct ecore_mcast_ramrod_params rparam;
8376 memset(&rparam, 0, sizeof(rparam));
8378 rparam.mcast_obj = &sc->mcast_obj;
8382 /* clear pending state for the last command */
8383 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
8385 /* if there are pending mcast commands - send them */
8386 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
8387 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
8390 "ERROR: Failed to send pending mcast commands (%d)\n", rc);
8394 BXE_MCAST_UNLOCK(sc);
8398 bxe_handle_classification_eqe(struct bxe_softc *sc,
8399 union event_ring_elem *elem)
8401 unsigned long ramrod_flags = 0;
8403 uint32_t cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8404 struct ecore_vlan_mac_obj *vlan_mac_obj;
8406 /* always push next commands out, don't wait here */
8407 bit_set(&ramrod_flags, RAMROD_CONT);
8409 switch (le32toh(elem->message.data.eth_event.echo) >> BXE_SWCID_SHIFT) {
8410 case ECORE_FILTER_MAC_PENDING:
8411 BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n");
8412 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
8415 case ECORE_FILTER_MCAST_PENDING:
8416 BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n");
8418 * This is only relevant for 57710 where multicast MACs are
8419 * configured as unicast MACs using the same ramrod.
8421 bxe_handle_mcast_eqe(sc);
8425 BLOGE(sc, "Unsupported classification command: %d\n",
8426 elem->message.data.eth_event.echo);
8430 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
8433 BLOGE(sc, "Failed to schedule new commands (%d)\n", rc);
8434 } else if (rc > 0) {
8435 BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n");
8440 bxe_handle_rx_mode_eqe(struct bxe_softc *sc,
8441 union event_ring_elem *elem)
8443 bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
8445 /* send rx_mode command again if was requested */
8446 if (bxe_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED,
8448 bxe_set_storm_rx_mode(sc);
8453 bxe_update_eq_prod(struct bxe_softc *sc,
8456 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
8457 wmb(); /* keep prod updates ordered */
8461 bxe_eq_int(struct bxe_softc *sc)
8463 uint16_t hw_cons, sw_cons, sw_prod;
8464 union event_ring_elem *elem;
8469 struct ecore_queue_sp_obj *q_obj;
8470 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
8471 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
8473 hw_cons = le16toh(*sc->eq_cons_sb);
8476 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
8477 * when we get to the next-page we need to adjust so the loop
8478 * condition below will be met. The next element is the size of a
8479 * regular element and hence incrementing by 1
8481 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
8486 * This function may never run in parallel with itself for a
8487 * specific sc and no need for a read memory barrier here.
8489 sw_cons = sc->eq_cons;
8490 sw_prod = sc->eq_prod;
8492 BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n",
8493 hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left));
8497 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
8499 elem = &sc->eq[EQ_DESC(sw_cons)];
8501 /* elem CID originates from FW, actually LE */
8502 cid = SW_CID(elem->message.data.cfc_del_event.cid);
8503 opcode = elem->message.opcode;
8505 /* handle eq element */
8508 case EVENT_RING_OPCODE_STAT_QUERY:
8509 BLOGD(sc, DBG_SP, "got statistics completion event %d\n",
8511 /* nothing to do with stats comp */
8514 case EVENT_RING_OPCODE_CFC_DEL:
8515 /* handle according to cid range */
8516 /* we may want to verify here that the sc state is HALTING */
8517 BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid);
8518 q_obj = bxe_cid_to_q_obj(sc, cid);
8519 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
8524 case EVENT_RING_OPCODE_STOP_TRAFFIC:
8525 BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n");
8526 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
8529 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_PAUSED);
8532 case EVENT_RING_OPCODE_START_TRAFFIC:
8533 BLOGD(sc, DBG_SP, "got START TRAFFIC\n");
8534 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) {
8537 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_RELEASED);
8540 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
8541 echo = elem->message.data.function_update_event.echo;
8542 if (echo == SWITCH_UPDATE) {
8543 BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n");
8544 if (f_obj->complete_cmd(sc, f_obj,
8545 ECORE_F_CMD_SWITCH_UPDATE)) {
8551 "AFEX: ramrod completed FUNCTION_UPDATE\n");
8555 case EVENT_RING_OPCODE_FORWARD_SETUP:
8556 q_obj = &bxe_fwd_sp_obj(sc, q_obj);
8557 if (q_obj->complete_cmd(sc, q_obj,
8558 ECORE_Q_CMD_SETUP_TX_ONLY)) {
8563 case EVENT_RING_OPCODE_FUNCTION_START:
8564 BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n");
8565 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
8570 case EVENT_RING_OPCODE_FUNCTION_STOP:
8571 BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n");
8572 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
8578 switch (opcode | sc->state) {
8579 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPEN):
8580 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPENING_WAITING_PORT):
8581 cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8582 BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid);
8583 rss_raw->clear_pending(rss_raw);
8586 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_OPEN):
8587 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_DIAG):
8588 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_CLOSING_WAITING_HALT):
8589 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_OPEN):
8590 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_DIAG):
8591 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8592 BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n");
8593 bxe_handle_classification_eqe(sc, elem);
8596 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_OPEN):
8597 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_DIAG):
8598 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8599 BLOGD(sc, DBG_SP, "got mcast ramrod\n");
8600 bxe_handle_mcast_eqe(sc);
8603 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_OPEN):
8604 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_DIAG):
8605 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8606 BLOGD(sc, DBG_SP, "got rx_mode ramrod\n");
8607 bxe_handle_rx_mode_eqe(sc, elem);
8611 /* unknown event log error and continue */
8612 BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n",
8613 elem->message.opcode, sc->state);
8621 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
8623 sc->eq_cons = sw_cons;
8624 sc->eq_prod = sw_prod;
8626 /* make sure that above mem writes were issued towards the memory */
8629 /* update producer */
8630 bxe_update_eq_prod(sc, sc->eq_prod);
8634 bxe_handle_sp_tq(void *context,
8637 struct bxe_softc *sc = (struct bxe_softc *)context;
8640 BLOGD(sc, DBG_SP, "---> SP TASK <---\n");
8642 /* what work needs to be performed? */
8643 status = bxe_update_dsb_idx(sc);
8645 BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status);
8648 if (status & BXE_DEF_SB_ATT_IDX) {
8649 BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n");
8651 status &= ~BXE_DEF_SB_ATT_IDX;
8654 /* SP events: STAT_QUERY and others */
8655 if (status & BXE_DEF_SB_IDX) {
8656 /* handle EQ completions */
8657 BLOGD(sc, DBG_SP, "---> EQ INTR <---\n");
8659 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
8660 le16toh(sc->def_idx), IGU_INT_NOP, 1);
8661 status &= ~BXE_DEF_SB_IDX;
8664 /* if status is non zero then something went wrong */
8665 if (__predict_false(status)) {
8666 BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status);
8669 /* ack status block only if something was actually handled */
8670 bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
8671 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
8674 * Must be called after the EQ processing (since eq leads to sriov
8675 * ramrod completion flows).
8676 * This flow may have been scheduled by the arrival of a ramrod
8677 * completion, or by the sriov code rescheduling itself.
8679 // XXX bxe_iov_sp_task(sc);
8684 bxe_handle_fp_tq(void *context,
8687 struct bxe_fastpath *fp = (struct bxe_fastpath *)context;
8688 struct bxe_softc *sc = fp->sc;
8689 uint8_t more_tx = FALSE;
8690 uint8_t more_rx = FALSE;
8692 BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index);
8695 * IFF_DRV_RUNNING state can't be checked here since we process
8696 * slowpath events on a client queue during setup. Instead
8697 * we need to add a "process/continue" flag here that the driver
8698 * can use to tell the task here not to do anything.
8701 if (!(sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
8706 /* update the fastpath index */
8707 bxe_update_fp_sb_idx(fp);
8709 /* XXX add loop here if ever support multiple tx CoS */
8710 /* fp->txdata[cos] */
8711 if (bxe_has_tx_work(fp)) {
8713 more_tx = bxe_txeof(sc, fp);
8714 BXE_FP_TX_UNLOCK(fp);
8717 if (bxe_has_rx_work(fp)) {
8718 more_rx = bxe_rxeof(sc, fp);
8721 if (more_rx /*|| more_tx*/) {
8722 /* still more work to do */
8723 taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
8727 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
8728 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
8732 bxe_task_fp(struct bxe_fastpath *fp)
8734 struct bxe_softc *sc = fp->sc;
8735 uint8_t more_tx = FALSE;
8736 uint8_t more_rx = FALSE;
8738 BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index);
8740 /* update the fastpath index */
8741 bxe_update_fp_sb_idx(fp);
8743 /* XXX add loop here if ever support multiple tx CoS */
8744 /* fp->txdata[cos] */
8745 if (bxe_has_tx_work(fp)) {
8747 more_tx = bxe_txeof(sc, fp);
8748 BXE_FP_TX_UNLOCK(fp);
8751 if (bxe_has_rx_work(fp)) {
8752 more_rx = bxe_rxeof(sc, fp);
8755 if (more_rx /*|| more_tx*/) {
8756 /* still more work to do, bail out if this ISR and process later */
8757 taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
8762 * Here we write the fastpath index taken before doing any tx or rx work.
8763 * It is very well possible other hw events occurred up to this point and
8764 * they were actually processed accordingly above. Since we're going to
8765 * write an older fastpath index, an interrupt is coming which we might
8766 * not do any work in.
8768 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
8769 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
8773 * Legacy interrupt entry point.
8775 * Verifies that the controller generated the interrupt and
8776 * then calls a separate routine to handle the various
8777 * interrupt causes: link, RX, and TX.
8780 bxe_intr_legacy(void *xsc)
8782 struct bxe_softc *sc = (struct bxe_softc *)xsc;
8783 struct bxe_fastpath *fp;
8784 uint16_t status, mask;
8787 BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n");
8790 * 0 for ustorm, 1 for cstorm
8791 * the bits returned from ack_int() are 0-15
8792 * bit 0 = attention status block
8793 * bit 1 = fast path status block
8794 * a mask of 0x2 or more = tx/rx event
8795 * a mask of 1 = slow path event
8798 status = bxe_ack_int(sc);
8800 /* the interrupt is not for us */
8801 if (__predict_false(status == 0)) {
8802 BLOGD(sc, DBG_INTR, "Not our interrupt!\n");
8806 BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status);
8808 FOR_EACH_ETH_QUEUE(sc, i) {
8810 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
8811 if (status & mask) {
8812 /* acknowledge and disable further fastpath interrupts */
8813 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8819 if (__predict_false(status & 0x1)) {
8820 /* acknowledge and disable further slowpath interrupts */
8821 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8823 /* schedule slowpath handler */
8824 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
8829 if (__predict_false(status)) {
8830 BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status);
8834 /* slowpath interrupt entry point */
8836 bxe_intr_sp(void *xsc)
8838 struct bxe_softc *sc = (struct bxe_softc *)xsc;
8840 BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n");
8842 /* acknowledge and disable further slowpath interrupts */
8843 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8845 /* schedule slowpath handler */
8846 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
8849 /* fastpath interrupt entry point */
8851 bxe_intr_fp(void *xfp)
8853 struct bxe_fastpath *fp = (struct bxe_fastpath *)xfp;
8854 struct bxe_softc *sc = fp->sc;
8856 BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index);
8859 "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n",
8860 curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id);
8862 /* acknowledge and disable further fastpath interrupts */
8863 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8868 /* Release all interrupts allocated by the driver. */
8870 bxe_interrupt_free(struct bxe_softc *sc)
8874 switch (sc->interrupt_mode) {
8875 case INTR_MODE_INTX:
8876 BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n");
8877 if (sc->intr[0].resource != NULL) {
8878 bus_release_resource(sc->dev,
8881 sc->intr[0].resource);
8885 for (i = 0; i < sc->intr_count; i++) {
8886 BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i);
8887 if (sc->intr[i].resource && sc->intr[i].rid) {
8888 bus_release_resource(sc->dev,
8891 sc->intr[i].resource);
8894 pci_release_msi(sc->dev);
8896 case INTR_MODE_MSIX:
8897 for (i = 0; i < sc->intr_count; i++) {
8898 BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i);
8899 if (sc->intr[i].resource && sc->intr[i].rid) {
8900 bus_release_resource(sc->dev,
8903 sc->intr[i].resource);
8906 pci_release_msi(sc->dev);
8909 /* nothing to do as initial allocation failed */
8915 * This function determines and allocates the appropriate
8916 * interrupt based on system capabilites and user request.
8918 * The user may force a particular interrupt mode, specify
8919 * the number of receive queues, specify the method for
8920 * distribuitng received frames to receive queues, or use
8921 * the default settings which will automatically select the
8922 * best supported combination. In addition, the OS may or
8923 * may not support certain combinations of these settings.
8924 * This routine attempts to reconcile the settings requested
8925 * by the user with the capabilites available from the system
8926 * to select the optimal combination of features.
8929 * 0 = Success, !0 = Failure.
8932 bxe_interrupt_alloc(struct bxe_softc *sc)
8936 int num_requested = 0;
8937 int num_allocated = 0;
8941 /* get the number of available MSI/MSI-X interrupts from the OS */
8942 if (sc->interrupt_mode > 0) {
8943 if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) {
8944 msix_count = pci_msix_count(sc->dev);
8947 if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) {
8948 msi_count = pci_msi_count(sc->dev);
8951 BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n",
8952 msi_count, msix_count);
8955 do { /* try allocating MSI-X interrupt resources (at least 2) */
8956 if (sc->interrupt_mode != INTR_MODE_MSIX) {
8960 if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) ||
8962 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
8966 /* ask for the necessary number of MSI-X vectors */
8967 num_requested = min((sc->num_queues + 1), msix_count);
8969 BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested);
8971 num_allocated = num_requested;
8972 if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) {
8973 BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc);
8974 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
8978 if (num_allocated < 2) { /* possible? */
8979 BLOGE(sc, "MSI-X allocation less than 2!\n");
8980 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
8981 pci_release_msi(sc->dev);
8985 BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n",
8986 num_requested, num_allocated);
8988 /* best effort so use the number of vectors allocated to us */
8989 sc->intr_count = num_allocated;
8990 sc->num_queues = num_allocated - 1;
8992 rid = 1; /* initial resource identifier */
8994 /* allocate the MSI-X vectors */
8995 for (i = 0; i < num_allocated; i++) {
8996 sc->intr[i].rid = (rid + i);
8998 if ((sc->intr[i].resource =
8999 bus_alloc_resource_any(sc->dev,
9002 RF_ACTIVE)) == NULL) {
9003 BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n",
9006 for (j = (i - 1); j >= 0; j--) {
9007 bus_release_resource(sc->dev,
9010 sc->intr[j].resource);
9015 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9016 pci_release_msi(sc->dev);
9020 BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i));
9024 do { /* try allocating MSI vector resources (at least 2) */
9025 if (sc->interrupt_mode != INTR_MODE_MSI) {
9029 if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) ||
9031 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9035 /* ask for a single MSI vector */
9038 BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested);
9040 num_allocated = num_requested;
9041 if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) {
9042 BLOGE(sc, "MSI alloc failed (%d)!\n", rc);
9043 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9047 if (num_allocated != 1) { /* possible? */
9048 BLOGE(sc, "MSI allocation is not 1!\n");
9049 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9050 pci_release_msi(sc->dev);
9054 BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n",
9055 num_requested, num_allocated);
9057 /* best effort so use the number of vectors allocated to us */
9058 sc->intr_count = num_allocated;
9059 sc->num_queues = num_allocated;
9061 rid = 1; /* initial resource identifier */
9063 sc->intr[0].rid = rid;
9065 if ((sc->intr[0].resource =
9066 bus_alloc_resource_any(sc->dev,
9069 RF_ACTIVE)) == NULL) {
9070 BLOGE(sc, "Failed to map MSI[0] (rid=%d)!\n", rid);
9073 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9074 pci_release_msi(sc->dev);
9078 BLOGD(sc, DBG_LOAD, "Mapped MSI[0] (rid=%d)\n", rid);
9081 do { /* try allocating INTx vector resources */
9082 if (sc->interrupt_mode != INTR_MODE_INTX) {
9086 BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n");
9088 /* only one vector for INTx */
9092 rid = 0; /* initial resource identifier */
9094 sc->intr[0].rid = rid;
9096 if ((sc->intr[0].resource =
9097 bus_alloc_resource_any(sc->dev,
9100 (RF_ACTIVE | RF_SHAREABLE))) == NULL) {
9101 BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid);
9104 sc->interrupt_mode = -1; /* Failed! */
9108 BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid);
9111 if (sc->interrupt_mode == -1) {
9112 BLOGE(sc, "Interrupt Allocation: FAILED!!!\n");
9116 "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n",
9117 sc->interrupt_mode, sc->num_queues);
9125 bxe_interrupt_detach(struct bxe_softc *sc)
9127 struct bxe_fastpath *fp;
9130 /* release interrupt resources */
9131 for (i = 0; i < sc->intr_count; i++) {
9132 if (sc->intr[i].resource && sc->intr[i].tag) {
9133 BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i);
9134 bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag);
9138 for (i = 0; i < sc->num_queues; i++) {
9141 taskqueue_drain(fp->tq, &fp->tq_task);
9142 taskqueue_drain(fp->tq, &fp->tx_task);
9143 while (taskqueue_cancel_timeout(fp->tq, &fp->tx_timeout_task,
9145 taskqueue_drain_timeout(fp->tq, &fp->tx_timeout_task);
9148 for (i = 0; i < sc->num_queues; i++) {
9150 if (fp->tq != NULL) {
9151 taskqueue_free(fp->tq);
9158 taskqueue_drain(sc->sp_tq, &sc->sp_tq_task);
9159 taskqueue_free(sc->sp_tq);
9165 * Enables interrupts and attach to the ISR.
9167 * When using multiple MSI/MSI-X vectors the first vector
9168 * is used for slowpath operations while all remaining
9169 * vectors are used for fastpath operations. If only a
9170 * single MSI/MSI-X vector is used (SINGLE_ISR) then the
9171 * ISR must look for both slowpath and fastpath completions.
9174 bxe_interrupt_attach(struct bxe_softc *sc)
9176 struct bxe_fastpath *fp;
9180 snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name),
9181 "bxe%d_sp_tq", sc->unit);
9182 TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc);
9183 sc->sp_tq = taskqueue_create(sc->sp_tq_name, M_NOWAIT,
9184 taskqueue_thread_enqueue,
9186 taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */
9187 "%s", sc->sp_tq_name);
9190 for (i = 0; i < sc->num_queues; i++) {
9192 snprintf(fp->tq_name, sizeof(fp->tq_name),
9193 "bxe%d_fp%d_tq", sc->unit, i);
9194 TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp);
9195 TASK_INIT(&fp->tx_task, 0, bxe_tx_mq_start_deferred, fp);
9196 fp->tq = taskqueue_create(fp->tq_name, M_NOWAIT,
9197 taskqueue_thread_enqueue,
9199 TIMEOUT_TASK_INIT(fp->tq, &fp->tx_timeout_task, 0,
9200 bxe_tx_mq_start_deferred, fp);
9201 taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */
9205 /* setup interrupt handlers */
9206 if (sc->interrupt_mode == INTR_MODE_MSIX) {
9207 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n");
9210 * Setup the interrupt handler. Note that we pass the driver instance
9211 * to the interrupt handler for the slowpath.
9213 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9214 (INTR_TYPE_NET | INTR_MPSAFE),
9215 NULL, bxe_intr_sp, sc,
9216 &sc->intr[0].tag)) != 0) {
9217 BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc);
9218 goto bxe_interrupt_attach_exit;
9221 bus_describe_intr(sc->dev, sc->intr[0].resource,
9222 sc->intr[0].tag, "sp");
9224 /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */
9226 /* initialize the fastpath vectors (note the first was used for sp) */
9227 for (i = 0; i < sc->num_queues; i++) {
9229 BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1));
9232 * Setup the interrupt handler. Note that we pass the
9233 * fastpath context to the interrupt handler in this
9236 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource,
9237 (INTR_TYPE_NET | INTR_MPSAFE),
9238 NULL, bxe_intr_fp, fp,
9239 &sc->intr[i + 1].tag)) != 0) {
9240 BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n",
9242 goto bxe_interrupt_attach_exit;
9245 bus_describe_intr(sc->dev, sc->intr[i + 1].resource,
9246 sc->intr[i + 1].tag, "fp%02d", i);
9248 /* bind the fastpath instance to a cpu */
9249 if (sc->num_queues > 1) {
9250 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i);
9253 fp->state = BXE_FP_STATE_IRQ;
9255 } else if (sc->interrupt_mode == INTR_MODE_MSI) {
9256 BLOGD(sc, DBG_LOAD, "Enabling MSI[0] vector\n");
9259 * Setup the interrupt handler. Note that we pass the
9260 * driver instance to the interrupt handler which
9261 * will handle both the slowpath and fastpath.
9263 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9264 (INTR_TYPE_NET | INTR_MPSAFE),
9265 NULL, bxe_intr_legacy, sc,
9266 &sc->intr[0].tag)) != 0) {
9267 BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc);
9268 goto bxe_interrupt_attach_exit;
9271 } else { /* (sc->interrupt_mode == INTR_MODE_INTX) */
9272 BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n");
9275 * Setup the interrupt handler. Note that we pass the
9276 * driver instance to the interrupt handler which
9277 * will handle both the slowpath and fastpath.
9279 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9280 (INTR_TYPE_NET | INTR_MPSAFE),
9281 NULL, bxe_intr_legacy, sc,
9282 &sc->intr[0].tag)) != 0) {
9283 BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc);
9284 goto bxe_interrupt_attach_exit;
9288 bxe_interrupt_attach_exit:
9293 static int bxe_init_hw_common_chip(struct bxe_softc *sc);
9294 static int bxe_init_hw_common(struct bxe_softc *sc);
9295 static int bxe_init_hw_port(struct bxe_softc *sc);
9296 static int bxe_init_hw_func(struct bxe_softc *sc);
9297 static void bxe_reset_common(struct bxe_softc *sc);
9298 static void bxe_reset_port(struct bxe_softc *sc);
9299 static void bxe_reset_func(struct bxe_softc *sc);
9300 static int bxe_gunzip_init(struct bxe_softc *sc);
9301 static void bxe_gunzip_end(struct bxe_softc *sc);
9302 static int bxe_init_firmware(struct bxe_softc *sc);
9303 static void bxe_release_firmware(struct bxe_softc *sc);
9306 ecore_func_sp_drv_ops bxe_func_sp_drv = {
9307 .init_hw_cmn_chip = bxe_init_hw_common_chip,
9308 .init_hw_cmn = bxe_init_hw_common,
9309 .init_hw_port = bxe_init_hw_port,
9310 .init_hw_func = bxe_init_hw_func,
9312 .reset_hw_cmn = bxe_reset_common,
9313 .reset_hw_port = bxe_reset_port,
9314 .reset_hw_func = bxe_reset_func,
9316 .gunzip_init = bxe_gunzip_init,
9317 .gunzip_end = bxe_gunzip_end,
9319 .init_fw = bxe_init_firmware,
9320 .release_fw = bxe_release_firmware,
9324 bxe_init_func_obj(struct bxe_softc *sc)
9328 ecore_init_func_obj(sc,
9330 BXE_SP(sc, func_rdata),
9331 BXE_SP_MAPPING(sc, func_rdata),
9332 BXE_SP(sc, func_afex_rdata),
9333 BXE_SP_MAPPING(sc, func_afex_rdata),
9338 bxe_init_hw(struct bxe_softc *sc,
9341 struct ecore_func_state_params func_params = { NULL };
9344 /* prepare the parameters for function state transitions */
9345 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
9347 func_params.f_obj = &sc->func_obj;
9348 func_params.cmd = ECORE_F_CMD_HW_INIT;
9350 func_params.params.hw_init.load_phase = load_code;
9353 * Via a plethora of function pointers, we will eventually reach
9354 * bxe_init_hw_common(), bxe_init_hw_port(), or bxe_init_hw_func().
9356 rc = ecore_func_state_change(sc, &func_params);
9362 bxe_fill(struct bxe_softc *sc,
9369 if (!(len % 4) && !(addr % 4)) {
9370 for (i = 0; i < len; i += 4) {
9371 REG_WR(sc, (addr + i), fill);
9374 for (i = 0; i < len; i++) {
9375 REG_WR8(sc, (addr + i), fill);
9380 /* writes FP SP data to FW - data_size in dwords */
9382 bxe_wr_fp_sb_data(struct bxe_softc *sc,
9384 uint32_t *sb_data_p,
9389 for (index = 0; index < data_size; index++) {
9391 (BAR_CSTRORM_INTMEM +
9392 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
9393 (sizeof(uint32_t) * index)),
9394 *(sb_data_p + index));
9399 bxe_zero_fp_sb(struct bxe_softc *sc,
9402 struct hc_status_block_data_e2 sb_data_e2;
9403 struct hc_status_block_data_e1x sb_data_e1x;
9404 uint32_t *sb_data_p;
9405 uint32_t data_size = 0;
9407 if (!CHIP_IS_E1x(sc)) {
9408 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9409 sb_data_e2.common.state = SB_DISABLED;
9410 sb_data_e2.common.p_func.vf_valid = FALSE;
9411 sb_data_p = (uint32_t *)&sb_data_e2;
9412 data_size = (sizeof(struct hc_status_block_data_e2) /
9415 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9416 sb_data_e1x.common.state = SB_DISABLED;
9417 sb_data_e1x.common.p_func.vf_valid = FALSE;
9418 sb_data_p = (uint32_t *)&sb_data_e1x;
9419 data_size = (sizeof(struct hc_status_block_data_e1x) /
9423 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9425 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)),
9426 0, CSTORM_STATUS_BLOCK_SIZE);
9427 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
9428 0, CSTORM_SYNC_BLOCK_SIZE);
9432 bxe_wr_sp_sb_data(struct bxe_softc *sc,
9433 struct hc_sp_status_block_data *sp_sb_data)
9438 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
9441 (BAR_CSTRORM_INTMEM +
9442 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
9443 (i * sizeof(uint32_t))),
9444 *((uint32_t *)sp_sb_data + i));
9449 bxe_zero_sp_sb(struct bxe_softc *sc)
9451 struct hc_sp_status_block_data sp_sb_data;
9453 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9455 sp_sb_data.state = SB_DISABLED;
9456 sp_sb_data.p_func.vf_valid = FALSE;
9458 bxe_wr_sp_sb_data(sc, &sp_sb_data);
9461 (BAR_CSTRORM_INTMEM +
9462 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
9463 0, CSTORM_SP_STATUS_BLOCK_SIZE);
9465 (BAR_CSTRORM_INTMEM +
9466 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
9467 0, CSTORM_SP_SYNC_BLOCK_SIZE);
9471 bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
9475 hc_sm->igu_sb_id = igu_sb_id;
9476 hc_sm->igu_seg_id = igu_seg_id;
9477 hc_sm->timer_value = 0xFF;
9478 hc_sm->time_to_expire = 0xFFFFFFFF;
9482 bxe_map_sb_state_machines(struct hc_index_data *index_data)
9484 /* zero out state machine indices */
9487 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9490 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9491 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
9492 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
9493 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
9498 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
9499 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9502 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
9503 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9504 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
9505 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9506 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
9507 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9508 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
9509 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9513 bxe_init_sb(struct bxe_softc *sc,
9520 struct hc_status_block_data_e2 sb_data_e2;
9521 struct hc_status_block_data_e1x sb_data_e1x;
9522 struct hc_status_block_sm *hc_sm_p;
9523 uint32_t *sb_data_p;
9527 if (CHIP_INT_MODE_IS_BC(sc)) {
9528 igu_seg_id = HC_SEG_ACCESS_NORM;
9530 igu_seg_id = IGU_SEG_ACCESS_NORM;
9533 bxe_zero_fp_sb(sc, fw_sb_id);
9535 if (!CHIP_IS_E1x(sc)) {
9536 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9537 sb_data_e2.common.state = SB_ENABLED;
9538 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
9539 sb_data_e2.common.p_func.vf_id = vfid;
9540 sb_data_e2.common.p_func.vf_valid = vf_valid;
9541 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
9542 sb_data_e2.common.same_igu_sb_1b = TRUE;
9543 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
9544 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
9545 hc_sm_p = sb_data_e2.common.state_machine;
9546 sb_data_p = (uint32_t *)&sb_data_e2;
9547 data_size = (sizeof(struct hc_status_block_data_e2) /
9549 bxe_map_sb_state_machines(sb_data_e2.index_data);
9551 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9552 sb_data_e1x.common.state = SB_ENABLED;
9553 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
9554 sb_data_e1x.common.p_func.vf_id = 0xff;
9555 sb_data_e1x.common.p_func.vf_valid = FALSE;
9556 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
9557 sb_data_e1x.common.same_igu_sb_1b = TRUE;
9558 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
9559 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
9560 hc_sm_p = sb_data_e1x.common.state_machine;
9561 sb_data_p = (uint32_t *)&sb_data_e1x;
9562 data_size = (sizeof(struct hc_status_block_data_e1x) /
9564 bxe_map_sb_state_machines(sb_data_e1x.index_data);
9567 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
9568 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
9570 BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id);
9572 /* write indices to HW - PCI guarantees endianity of regpairs */
9573 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9576 static inline uint8_t
9577 bxe_fp_qzone_id(struct bxe_fastpath *fp)
9579 if (CHIP_IS_E1x(fp->sc)) {
9580 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
9586 static inline uint32_t
9587 bxe_rx_ustorm_prods_offset(struct bxe_softc *sc,
9588 struct bxe_fastpath *fp)
9590 uint32_t offset = BAR_USTRORM_INTMEM;
9592 if (!CHIP_IS_E1x(sc)) {
9593 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
9595 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
9602 bxe_init_eth_fp(struct bxe_softc *sc,
9605 struct bxe_fastpath *fp = &sc->fp[idx];
9606 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
9607 unsigned long q_type = 0;
9613 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
9614 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
9616 fp->cl_id = (CHIP_IS_E1x(sc)) ?
9617 (SC_L_ID(sc) + idx) :
9618 /* want client ID same as IGU SB ID for non-E1 */
9620 fp->cl_qzone_id = bxe_fp_qzone_id(fp);
9622 /* setup sb indices */
9623 if (!CHIP_IS_E1x(sc)) {
9624 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
9625 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
9627 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
9628 fp->sb_running_index = fp->status_block.e1x_sb->sb.running_index;
9632 fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp);
9634 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
9637 * XXX If multiple CoS is ever supported then each fastpath structure
9638 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
9640 for (cos = 0; cos < sc->max_cos; cos++) {
9643 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
9645 /* nothing more for a VF to do */
9650 bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE,
9651 fp->fw_sb_id, fp->igu_sb_id);
9653 bxe_update_fp_sb_idx(fp);
9655 /* Configure Queue State object */
9656 bit_set(&q_type, ECORE_Q_TYPE_HAS_RX);
9657 bit_set(&q_type, ECORE_Q_TYPE_HAS_TX);
9659 ecore_init_queue_obj(sc,
9660 &sc->sp_objs[idx].q_obj,
9665 BXE_SP(sc, q_rdata),
9666 BXE_SP_MAPPING(sc, q_rdata),
9669 /* configure classification DBs */
9670 ecore_init_mac_obj(sc,
9671 &sc->sp_objs[idx].mac_obj,
9675 BXE_SP(sc, mac_rdata),
9676 BXE_SP_MAPPING(sc, mac_rdata),
9677 ECORE_FILTER_MAC_PENDING,
9679 ECORE_OBJ_TYPE_RX_TX,
9682 BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n",
9683 idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id);
9687 bxe_update_rx_prod(struct bxe_softc *sc,
9688 struct bxe_fastpath *fp,
9689 uint16_t rx_bd_prod,
9690 uint16_t rx_cq_prod,
9691 uint16_t rx_sge_prod)
9693 struct ustorm_eth_rx_producers rx_prods = { 0 };
9696 /* update producers */
9697 rx_prods.bd_prod = rx_bd_prod;
9698 rx_prods.cqe_prod = rx_cq_prod;
9699 rx_prods.sge_prod = rx_sge_prod;
9702 * Make sure that the BD and SGE data is updated before updating the
9703 * producers since FW might read the BD/SGE right after the producer
9705 * This is only applicable for weak-ordered memory model archs such
9706 * as IA-64. The following barrier is also mandatory since FW will
9707 * assumes BDs must have buffers.
9711 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
9713 (fp->ustorm_rx_prods_offset + (i * 4)),
9714 ((uint32_t *)&rx_prods)[i]);
9717 wmb(); /* keep prod updates ordered */
9720 "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n",
9721 fp->index, rx_bd_prod, rx_cq_prod, rx_sge_prod);
9725 bxe_init_rx_rings(struct bxe_softc *sc)
9727 struct bxe_fastpath *fp;
9730 for (i = 0; i < sc->num_queues; i++) {
9736 * Activate the BD ring...
9737 * Warning, this will generate an interrupt (to the TSTORM)
9738 * so this can only be done after the chip is initialized
9740 bxe_update_rx_prod(sc, fp,
9749 if (CHIP_IS_E1(sc)) {
9751 (BAR_USTRORM_INTMEM +
9752 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))),
9753 U64_LO(fp->rcq_dma.paddr));
9755 (BAR_USTRORM_INTMEM +
9756 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4),
9757 U64_HI(fp->rcq_dma.paddr));
9763 bxe_init_tx_ring_one(struct bxe_fastpath *fp)
9765 SET_FLAG(fp->tx_db.data.header.data, DOORBELL_HDR_T_DB_TYPE, 1);
9766 fp->tx_db.data.zero_fill1 = 0;
9767 fp->tx_db.data.prod = 0;
9769 fp->tx_pkt_prod = 0;
9770 fp->tx_pkt_cons = 0;
9773 fp->eth_q_stats.tx_pkts = 0;
9777 bxe_init_tx_rings(struct bxe_softc *sc)
9781 for (i = 0; i < sc->num_queues; i++) {
9782 bxe_init_tx_ring_one(&sc->fp[i]);
9787 bxe_init_def_sb(struct bxe_softc *sc)
9789 struct host_sp_status_block *def_sb = sc->def_sb;
9790 bus_addr_t mapping = sc->def_sb_dma.paddr;
9791 int igu_sp_sb_index;
9793 int port = SC_PORT(sc);
9794 int func = SC_FUNC(sc);
9795 int reg_offset, reg_offset_en5;
9798 struct hc_sp_status_block_data sp_sb_data;
9800 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9802 if (CHIP_INT_MODE_IS_BC(sc)) {
9803 igu_sp_sb_index = DEF_SB_IGU_ID;
9804 igu_seg_id = HC_SEG_ACCESS_DEF;
9806 igu_sp_sb_index = sc->igu_dsb_id;
9807 igu_seg_id = IGU_SEG_ACCESS_DEF;
9811 section = ((uint64_t)mapping +
9812 offsetof(struct host_sp_status_block, atten_status_block));
9813 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
9816 reg_offset = (port) ?
9817 MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
9818 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
9819 reg_offset_en5 = (port) ?
9820 MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
9821 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
9823 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
9824 /* take care of sig[0]..sig[4] */
9825 for (sindex = 0; sindex < 4; sindex++) {
9826 sc->attn_group[index].sig[sindex] =
9827 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index)));
9830 if (!CHIP_IS_E1x(sc)) {
9832 * enable5 is separate from the rest of the registers,
9833 * and the address skip is 4 and not 16 between the
9836 sc->attn_group[index].sig[4] =
9837 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
9839 sc->attn_group[index].sig[4] = 0;
9843 if (sc->devinfo.int_block == INT_BLOCK_HC) {
9844 reg_offset = (port) ?
9845 HC_REG_ATTN_MSG1_ADDR_L :
9846 HC_REG_ATTN_MSG0_ADDR_L;
9847 REG_WR(sc, reg_offset, U64_LO(section));
9848 REG_WR(sc, (reg_offset + 4), U64_HI(section));
9849 } else if (!CHIP_IS_E1x(sc)) {
9850 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
9851 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
9854 section = ((uint64_t)mapping +
9855 offsetof(struct host_sp_status_block, sp_sb));
9859 /* PCI guarantees endianity of regpair */
9860 sp_sb_data.state = SB_ENABLED;
9861 sp_sb_data.host_sb_addr.lo = U64_LO(section);
9862 sp_sb_data.host_sb_addr.hi = U64_HI(section);
9863 sp_sb_data.igu_sb_id = igu_sp_sb_index;
9864 sp_sb_data.igu_seg_id = igu_seg_id;
9865 sp_sb_data.p_func.pf_id = func;
9866 sp_sb_data.p_func.vnic_id = SC_VN(sc);
9867 sp_sb_data.p_func.vf_id = 0xff;
9869 bxe_wr_sp_sb_data(sc, &sp_sb_data);
9871 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
9875 bxe_init_sp_ring(struct bxe_softc *sc)
9877 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
9878 sc->spq_prod_idx = 0;
9879 sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
9880 sc->spq_prod_bd = sc->spq;
9881 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
9885 bxe_init_eq_ring(struct bxe_softc *sc)
9887 union event_ring_elem *elem;
9890 for (i = 1; i <= NUM_EQ_PAGES; i++) {
9891 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
9893 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
9895 (i % NUM_EQ_PAGES)));
9896 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
9898 (i % NUM_EQ_PAGES)));
9902 sc->eq_prod = NUM_EQ_DESC;
9903 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
9905 atomic_store_rel_long(&sc->eq_spq_left,
9906 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
9911 bxe_init_internal_common(struct bxe_softc *sc)
9916 * Zero this manually as its initialization is currently missing
9919 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
9921 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
9925 if (!CHIP_IS_E1x(sc)) {
9926 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
9927 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
9932 bxe_init_internal(struct bxe_softc *sc,
9935 switch (load_code) {
9936 case FW_MSG_CODE_DRV_LOAD_COMMON:
9937 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
9938 bxe_init_internal_common(sc);
9941 case FW_MSG_CODE_DRV_LOAD_PORT:
9945 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
9946 /* internal memory per function is initialized inside bxe_pf_init */
9950 BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code);
9956 storm_memset_func_cfg(struct bxe_softc *sc,
9957 struct tstorm_eth_function_common_config *tcfg,
9963 addr = (BAR_TSTRORM_INTMEM +
9964 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
9965 size = sizeof(struct tstorm_eth_function_common_config);
9966 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg);
9970 bxe_func_init(struct bxe_softc *sc,
9971 struct bxe_func_init_params *p)
9973 struct tstorm_eth_function_common_config tcfg = { 0 };
9975 if (CHIP_IS_E1x(sc)) {
9976 storm_memset_func_cfg(sc, &tcfg, p->func_id);
9979 /* Enable the function in the FW */
9980 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
9981 storm_memset_func_en(sc, p->func_id, 1);
9984 if (p->func_flgs & FUNC_FLG_SPQ) {
9985 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
9987 (XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(p->func_id)),
9993 * Calculates the sum of vn_min_rates.
9994 * It's needed for further normalizing of the min_rates.
9996 * sum of vn_min_rates.
9998 * 0 - if all the min_rates are 0.
9999 * In the later case fainess algorithm should be deactivated.
10000 * If all min rates are not zero then those that are zeroes will be set to 1.
10003 bxe_calc_vn_min(struct bxe_softc *sc,
10004 struct cmng_init_input *input)
10007 uint32_t vn_min_rate;
10011 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10012 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10013 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
10014 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
10016 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10017 /* skip hidden VNs */
10019 } else if (!vn_min_rate) {
10020 /* If min rate is zero - set it to 100 */
10021 vn_min_rate = DEF_MIN_RATE;
10026 input->vnic_min_rate[vn] = vn_min_rate;
10029 /* if ETS or all min rates are zeros - disable fairness */
10030 if (BXE_IS_ETS_ENABLED(sc)) {
10031 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10032 BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n");
10033 } else if (all_zero) {
10034 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10035 BLOGD(sc, DBG_LOAD,
10036 "Fariness disabled (all MIN values are zeroes)\n");
10038 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10042 static inline uint16_t
10043 bxe_extract_max_cfg(struct bxe_softc *sc,
10046 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
10047 FUNC_MF_CFG_MAX_BW_SHIFT);
10050 BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n");
10058 bxe_calc_vn_max(struct bxe_softc *sc,
10060 struct cmng_init_input *input)
10062 uint16_t vn_max_rate;
10063 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10066 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10069 max_cfg = bxe_extract_max_cfg(sc, vn_cfg);
10071 if (IS_MF_SI(sc)) {
10072 /* max_cfg in percents of linkspeed */
10073 vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100);
10074 } else { /* SD modes */
10075 /* max_cfg is absolute in 100Mb units */
10076 vn_max_rate = (max_cfg * 100);
10080 BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
10082 input->vnic_max_rate[vn] = vn_max_rate;
10086 bxe_cmng_fns_init(struct bxe_softc *sc,
10090 struct cmng_init_input input;
10093 memset(&input, 0, sizeof(struct cmng_init_input));
10095 input.port_rate = sc->link_vars.line_speed;
10097 if (cmng_type == CMNG_FNS_MINMAX) {
10098 /* read mf conf from shmem */
10100 bxe_read_mf_cfg(sc);
10103 /* get VN min rate and enable fairness if not 0 */
10104 bxe_calc_vn_min(sc, &input);
10106 /* get VN max rate */
10107 if (sc->port.pmf) {
10108 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10109 bxe_calc_vn_max(sc, vn, &input);
10113 /* always enable rate shaping and fairness */
10114 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
10116 ecore_init_cmng(&input, &sc->cmng);
10120 /* rate shaping and fairness are disabled */
10121 BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n");
10125 bxe_get_cmng_fns_mode(struct bxe_softc *sc)
10127 if (CHIP_REV_IS_SLOW(sc)) {
10128 return (CMNG_FNS_NONE);
10132 return (CMNG_FNS_MINMAX);
10135 return (CMNG_FNS_NONE);
10139 storm_memset_cmng(struct bxe_softc *sc,
10140 struct cmng_init *cmng,
10148 addr = (BAR_XSTRORM_INTMEM +
10149 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
10150 size = sizeof(struct cmng_struct_per_port);
10151 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port);
10153 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10154 func = func_by_vn(sc, vn);
10156 addr = (BAR_XSTRORM_INTMEM +
10157 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
10158 size = sizeof(struct rate_shaping_vars_per_vn);
10159 ecore_storm_memset_struct(sc, addr, size,
10160 (uint32_t *)&cmng->vnic.vnic_max_rate[vn]);
10162 addr = (BAR_XSTRORM_INTMEM +
10163 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
10164 size = sizeof(struct fairness_vars_per_vn);
10165 ecore_storm_memset_struct(sc, addr, size,
10166 (uint32_t *)&cmng->vnic.vnic_min_rate[vn]);
10171 bxe_pf_init(struct bxe_softc *sc)
10173 struct bxe_func_init_params func_init = { 0 };
10174 struct event_ring_data eq_data = { { 0 } };
10177 if (!CHIP_IS_E1x(sc)) {
10178 /* reset IGU PF statistics: MSIX + ATTN */
10181 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10182 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10183 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10187 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10188 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10189 (BXE_IGU_STAS_MSG_PF_CNT * 4) +
10190 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10194 /* function setup flags */
10195 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
10198 * This flag is relevant for E1x only.
10199 * E2 doesn't have a TPA configuration in a function level.
10201 flags |= (sc->ifnet->if_capenable & IFCAP_LRO) ? FUNC_FLG_TPA : 0;
10203 func_init.func_flgs = flags;
10204 func_init.pf_id = SC_FUNC(sc);
10205 func_init.func_id = SC_FUNC(sc);
10206 func_init.spq_map = sc->spq_dma.paddr;
10207 func_init.spq_prod = sc->spq_prod_idx;
10209 bxe_func_init(sc, &func_init);
10211 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
10214 * Congestion management values depend on the link rate.
10215 * There is no active link so initial link rate is set to 10Gbps.
10216 * When the link comes up the congestion management values are
10217 * re-calculated according to the actual link rate.
10219 sc->link_vars.line_speed = SPEED_10000;
10220 bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc));
10222 /* Only the PMF sets the HW */
10223 if (sc->port.pmf) {
10224 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
10227 /* init Event Queue - PCI bus guarantees correct endainity */
10228 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
10229 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
10230 eq_data.producer = sc->eq_prod;
10231 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
10232 eq_data.sb_id = DEF_SB_ID;
10233 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
10237 bxe_hc_int_enable(struct bxe_softc *sc)
10239 int port = SC_PORT(sc);
10240 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10241 uint32_t val = REG_RD(sc, addr);
10242 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10243 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10244 (sc->intr_count == 1)) ? TRUE : FALSE;
10245 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10248 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10249 HC_CONFIG_0_REG_INT_LINE_EN_0);
10250 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10251 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10253 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
10256 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
10257 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10258 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10259 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10261 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10262 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10263 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10264 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10266 if (!CHIP_IS_E1(sc)) {
10267 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n",
10270 REG_WR(sc, addr, val);
10272 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
10276 if (CHIP_IS_E1(sc)) {
10277 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF);
10280 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
10281 val, port, addr, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10283 REG_WR(sc, addr, val);
10285 /* ensure that HC_CONFIG is written before leading/trailing edge config */
10288 if (!CHIP_IS_E1(sc)) {
10289 /* init leading/trailing edge */
10291 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10292 if (sc->port.pmf) {
10293 /* enable nig and gpio3 attention */
10300 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val);
10301 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val);
10304 /* make sure that interrupts are indeed enabled from here on */
10309 bxe_igu_int_enable(struct bxe_softc *sc)
10312 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10313 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10314 (sc->intr_count == 1)) ? TRUE : FALSE;
10315 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10317 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10320 val &= ~(IGU_PF_CONF_INT_LINE_EN |
10321 IGU_PF_CONF_SINGLE_ISR_EN);
10322 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10323 IGU_PF_CONF_ATTN_BIT_EN);
10325 val |= IGU_PF_CONF_SINGLE_ISR_EN;
10328 val &= ~IGU_PF_CONF_INT_LINE_EN;
10329 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10330 IGU_PF_CONF_ATTN_BIT_EN |
10331 IGU_PF_CONF_SINGLE_ISR_EN);
10333 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
10334 val |= (IGU_PF_CONF_INT_LINE_EN |
10335 IGU_PF_CONF_ATTN_BIT_EN |
10336 IGU_PF_CONF_SINGLE_ISR_EN);
10339 /* clean previous status - need to configure igu prior to ack*/
10340 if ((!msix) || single_msix) {
10341 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10345 val |= IGU_PF_CONF_FUNC_EN;
10347 BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n",
10348 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10350 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10354 /* init leading/trailing edge */
10356 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10357 if (sc->port.pmf) {
10358 /* enable nig and gpio3 attention */
10365 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
10366 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
10368 /* make sure that interrupts are indeed enabled from here on */
10373 bxe_int_enable(struct bxe_softc *sc)
10375 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10376 bxe_hc_int_enable(sc);
10378 bxe_igu_int_enable(sc);
10383 bxe_hc_int_disable(struct bxe_softc *sc)
10385 int port = SC_PORT(sc);
10386 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10387 uint32_t val = REG_RD(sc, addr);
10390 * In E1 we must use only PCI configuration space to disable MSI/MSIX
10391 * capablility. It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC
10394 if (CHIP_IS_E1(sc)) {
10396 * Since IGU_PF_CONF_MSI_MSIX_EN still always on use mask register
10397 * to prevent from HC sending interrupts after we exit the function
10399 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0);
10401 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10402 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10403 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10405 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10406 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10407 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10408 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10411 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr);
10413 /* flush all outstanding writes */
10416 REG_WR(sc, addr, val);
10417 if (REG_RD(sc, addr) != val) {
10418 BLOGE(sc, "proper val not read from HC IGU!\n");
10423 bxe_igu_int_disable(struct bxe_softc *sc)
10425 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10427 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
10428 IGU_PF_CONF_INT_LINE_EN |
10429 IGU_PF_CONF_ATTN_BIT_EN);
10431 BLOGD(sc, DBG_INTR, "write %x to IGU\n", val);
10433 /* flush all outstanding writes */
10436 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10437 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
10438 BLOGE(sc, "proper val not read from IGU!\n");
10443 bxe_int_disable(struct bxe_softc *sc)
10445 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10446 bxe_hc_int_disable(sc);
10448 bxe_igu_int_disable(sc);
10453 bxe_nic_init(struct bxe_softc *sc,
10458 for (i = 0; i < sc->num_queues; i++) {
10459 bxe_init_eth_fp(sc, i);
10462 rmb(); /* ensure status block indices were read */
10464 bxe_init_rx_rings(sc);
10465 bxe_init_tx_rings(sc);
10471 /* initialize MOD_ABS interrupts */
10472 elink_init_mod_abs_int(sc, &sc->link_vars,
10473 sc->devinfo.chip_id,
10474 sc->devinfo.shmem_base,
10475 sc->devinfo.shmem2_base,
10478 bxe_init_def_sb(sc);
10479 bxe_update_dsb_idx(sc);
10480 bxe_init_sp_ring(sc);
10481 bxe_init_eq_ring(sc);
10482 bxe_init_internal(sc, load_code);
10484 bxe_stats_init(sc);
10486 /* flush all before enabling interrupts */
10489 bxe_int_enable(sc);
10491 /* check for SPIO5 */
10492 bxe_attn_int_deasserted0(sc,
10494 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
10496 AEU_INPUTS_ATTN_BITS_SPIO5);
10500 bxe_init_objs(struct bxe_softc *sc)
10502 /* mcast rules must be added to tx if tx switching is enabled */
10503 ecore_obj_type o_type =
10504 (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX :
10507 /* RX_MODE controlling object */
10508 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
10510 /* multicast configuration controlling object */
10511 ecore_init_mcast_obj(sc,
10517 BXE_SP(sc, mcast_rdata),
10518 BXE_SP_MAPPING(sc, mcast_rdata),
10519 ECORE_FILTER_MCAST_PENDING,
10523 /* Setup CAM credit pools */
10524 ecore_init_mac_credit_pool(sc,
10527 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10528 VNICS_PER_PATH(sc));
10530 ecore_init_vlan_credit_pool(sc,
10532 SC_ABS_FUNC(sc) >> 1,
10533 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10534 VNICS_PER_PATH(sc));
10536 /* RSS configuration object */
10537 ecore_init_rss_config_obj(sc,
10543 BXE_SP(sc, rss_rdata),
10544 BXE_SP_MAPPING(sc, rss_rdata),
10545 ECORE_FILTER_RSS_CONF_PENDING,
10546 &sc->sp_state, ECORE_OBJ_TYPE_RX);
10550 * Initialize the function. This must be called before sending CLIENT_SETUP
10551 * for the first client.
10554 bxe_func_start(struct bxe_softc *sc)
10556 struct ecore_func_state_params func_params = { NULL };
10557 struct ecore_func_start_params *start_params = &func_params.params.start;
10559 /* Prepare parameters for function state transitions */
10560 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
10562 func_params.f_obj = &sc->func_obj;
10563 func_params.cmd = ECORE_F_CMD_START;
10565 /* Function parameters */
10566 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
10567 start_params->sd_vlan_tag = OVLAN(sc);
10569 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
10570 start_params->network_cos_mode = STATIC_COS;
10571 } else { /* CHIP_IS_E1X */
10572 start_params->network_cos_mode = FW_WRR;
10575 //start_params->gre_tunnel_mode = 0;
10576 //start_params->gre_tunnel_rss = 0;
10578 return (ecore_func_state_change(sc, &func_params));
10582 bxe_set_power_state(struct bxe_softc *sc,
10587 /* If there is no power capability, silently succeed */
10588 if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) {
10589 BLOGW(sc, "No power capability\n");
10593 pmcsr = pci_read_config(sc->dev,
10594 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10599 pci_write_config(sc->dev,
10600 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10601 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2);
10603 if (pmcsr & PCIM_PSTAT_DMASK) {
10604 /* delay required during transition out of D3hot */
10611 /* XXX if there are other clients above don't shut down the power */
10613 /* don't shut down the power for emulation and FPGA */
10614 if (CHIP_REV_IS_SLOW(sc)) {
10618 pmcsr &= ~PCIM_PSTAT_DMASK;
10619 pmcsr |= PCIM_PSTAT_D3;
10622 pmcsr |= PCIM_PSTAT_PMEENABLE;
10625 pci_write_config(sc->dev,
10626 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10630 * No more memory access after this point until device is brought back
10636 BLOGE(sc, "Can't support PCI power state = 0x%x pmcsr 0x%x\n",
10645 /* return true if succeeded to acquire the lock */
10647 bxe_trylock_hw_lock(struct bxe_softc *sc,
10650 uint32_t lock_status;
10651 uint32_t resource_bit = (1 << resource);
10652 int func = SC_FUNC(sc);
10653 uint32_t hw_lock_control_reg;
10655 BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource);
10657 /* Validating that the resource is within range */
10658 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
10659 BLOGD(sc, DBG_LOAD,
10660 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
10661 resource, HW_LOCK_MAX_RESOURCE_VALUE);
10666 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
10668 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
10671 /* try to acquire the lock */
10672 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
10673 lock_status = REG_RD(sc, hw_lock_control_reg);
10674 if (lock_status & resource_bit) {
10678 BLOGE(sc, "Failed to get a resource lock 0x%x func %d "
10679 "lock_status 0x%x resource_bit 0x%x\n", resource, func,
10680 lock_status, resource_bit);
10686 * Get the recovery leader resource id according to the engine this function
10687 * belongs to. Currently only only 2 engines is supported.
10690 bxe_get_leader_lock_resource(struct bxe_softc *sc)
10693 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_1);
10695 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_0);
10699 /* try to acquire a leader lock for current engine */
10701 bxe_trylock_leader_lock(struct bxe_softc *sc)
10703 return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
10707 bxe_release_leader_lock(struct bxe_softc *sc)
10709 return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
10712 /* close gates #2, #3 and #4 */
10714 bxe_set_234_gates(struct bxe_softc *sc,
10719 /* gates #2 and #4a are closed/opened for "not E1" only */
10720 if (!CHIP_IS_E1(sc)) {
10722 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
10724 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
10728 if (CHIP_IS_E1x(sc)) {
10729 /* prevent interrupts from HC on both ports */
10730 val = REG_RD(sc, HC_REG_CONFIG_1);
10731 REG_WR(sc, HC_REG_CONFIG_1,
10732 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
10733 (val & ~(uint32_t)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
10735 val = REG_RD(sc, HC_REG_CONFIG_0);
10736 REG_WR(sc, HC_REG_CONFIG_0,
10737 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
10738 (val & ~(uint32_t)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
10740 /* Prevent incomming interrupts in IGU */
10741 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
10743 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
10745 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
10746 (val & ~(uint32_t)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
10749 BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n",
10750 close ? "closing" : "opening");
10755 /* poll for pending writes bit, it should get cleared in no more than 1s */
10757 bxe_er_poll_igu_vq(struct bxe_softc *sc)
10759 uint32_t cnt = 1000;
10760 uint32_t pend_bits = 0;
10763 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
10765 if (pend_bits == 0) {
10770 } while (--cnt > 0);
10773 BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits);
10780 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
10783 bxe_clp_reset_prep(struct bxe_softc *sc,
10784 uint32_t *magic_val)
10786 /* Do some magic... */
10787 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
10788 *magic_val = val & SHARED_MF_CLP_MAGIC;
10789 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
10792 /* restore the value of the 'magic' bit */
10794 bxe_clp_reset_done(struct bxe_softc *sc,
10795 uint32_t magic_val)
10797 /* Restore the 'magic' bit value... */
10798 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
10799 MFCFG_WR(sc, shared_mf_config.clp_mb,
10800 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
10803 /* prepare for MCP reset, takes care of CLP configurations */
10805 bxe_reset_mcp_prep(struct bxe_softc *sc,
10806 uint32_t *magic_val)
10809 uint32_t validity_offset;
10811 /* set `magic' bit in order to save MF config */
10812 if (!CHIP_IS_E1(sc)) {
10813 bxe_clp_reset_prep(sc, magic_val);
10816 /* get shmem offset */
10817 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
10819 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
10821 /* Clear validity map flags */
10823 REG_WR(sc, shmem + validity_offset, 0);
10827 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
10828 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
10831 bxe_mcp_wait_one(struct bxe_softc *sc)
10833 /* special handling for emulation and FPGA (10 times longer) */
10834 if (CHIP_REV_IS_SLOW(sc)) {
10835 DELAY((MCP_ONE_TIMEOUT*10) * 1000);
10837 DELAY((MCP_ONE_TIMEOUT) * 1000);
10841 /* initialize shmem_base and waits for validity signature to appear */
10843 bxe_init_shmem(struct bxe_softc *sc)
10849 sc->devinfo.shmem_base =
10850 sc->link_params.shmem_base =
10851 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
10853 if (sc->devinfo.shmem_base) {
10854 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
10855 if (val & SHR_MEM_VALIDITY_MB)
10859 bxe_mcp_wait_one(sc);
10861 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
10863 BLOGE(sc, "BAD MCP validity signature\n");
10869 bxe_reset_mcp_comp(struct bxe_softc *sc,
10870 uint32_t magic_val)
10872 int rc = bxe_init_shmem(sc);
10874 /* Restore the `magic' bit value */
10875 if (!CHIP_IS_E1(sc)) {
10876 bxe_clp_reset_done(sc, magic_val);
10883 bxe_pxp_prep(struct bxe_softc *sc)
10885 if (!CHIP_IS_E1(sc)) {
10886 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
10887 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
10893 * Reset the whole chip except for:
10895 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
10897 * - MISC (including AEU)
10902 bxe_process_kill_chip_reset(struct bxe_softc *sc,
10905 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
10906 uint32_t global_bits2, stay_reset2;
10909 * Bits that have to be set in reset_mask2 if we want to reset 'global'
10910 * (per chip) blocks.
10913 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
10914 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
10917 * Don't reset the following blocks.
10918 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
10919 * reset, as in 4 port device they might still be owned
10920 * by the MCP (there is only one leader per path).
10923 MISC_REGISTERS_RESET_REG_1_RST_HC |
10924 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
10925 MISC_REGISTERS_RESET_REG_1_RST_PXP;
10928 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
10929 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
10930 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
10931 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
10932 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
10933 MISC_REGISTERS_RESET_REG_2_RST_GRC |
10934 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
10935 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
10936 MISC_REGISTERS_RESET_REG_2_RST_ATC |
10937 MISC_REGISTERS_RESET_REG_2_PGLC |
10938 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
10939 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
10940 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
10941 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
10942 MISC_REGISTERS_RESET_REG_2_UMAC0 |
10943 MISC_REGISTERS_RESET_REG_2_UMAC1;
10946 * Keep the following blocks in reset:
10947 * - all xxMACs are handled by the elink code.
10950 MISC_REGISTERS_RESET_REG_2_XMAC |
10951 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
10953 /* Full reset masks according to the chip */
10954 reset_mask1 = 0xffffffff;
10956 if (CHIP_IS_E1(sc))
10957 reset_mask2 = 0xffff;
10958 else if (CHIP_IS_E1H(sc))
10959 reset_mask2 = 0x1ffff;
10960 else if (CHIP_IS_E2(sc))
10961 reset_mask2 = 0xfffff;
10962 else /* CHIP_IS_E3 */
10963 reset_mask2 = 0x3ffffff;
10965 /* Don't reset global blocks unless we need to */
10967 reset_mask2 &= ~global_bits2;
10970 * In case of attention in the QM, we need to reset PXP
10971 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
10972 * because otherwise QM reset would release 'close the gates' shortly
10973 * before resetting the PXP, then the PSWRQ would send a write
10974 * request to PGLUE. Then when PXP is reset, PGLUE would try to
10975 * read the payload data from PSWWR, but PSWWR would not
10976 * respond. The write queue in PGLUE would stuck, dmae commands
10977 * would not return. Therefore it's important to reset the second
10978 * reset register (containing the
10979 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
10980 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
10983 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
10984 reset_mask2 & (~not_reset_mask2));
10986 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
10987 reset_mask1 & (~not_reset_mask1));
10992 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
10993 reset_mask2 & (~stay_reset2));
10998 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
11003 bxe_process_kill(struct bxe_softc *sc,
11008 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
11009 uint32_t tags_63_32 = 0;
11011 /* Empty the Tetris buffer, wait for 1s */
11013 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
11014 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
11015 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
11016 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
11017 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
11018 if (CHIP_IS_E3(sc)) {
11019 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
11022 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
11023 ((port_is_idle_0 & 0x1) == 0x1) &&
11024 ((port_is_idle_1 & 0x1) == 0x1) &&
11025 (pgl_exp_rom2 == 0xffffffff) &&
11026 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
11029 } while (cnt-- > 0);
11032 BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there "
11033 "are still outstanding read requests after 1s! "
11034 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
11035 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
11036 sr_cnt, blk_cnt, port_is_idle_0,
11037 port_is_idle_1, pgl_exp_rom2);
11043 /* Close gates #2, #3 and #4 */
11044 bxe_set_234_gates(sc, TRUE);
11046 /* Poll for IGU VQs for 57712 and newer chips */
11047 if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) {
11051 /* XXX indicate that "process kill" is in progress to MCP */
11053 /* clear "unprepared" bit */
11054 REG_WR(sc, MISC_REG_UNPREPARED, 0);
11057 /* Make sure all is written to the chip before the reset */
11061 * Wait for 1ms to empty GLUE and PCI-E core queues,
11062 * PSWHST, GRC and PSWRD Tetris buffer.
11066 /* Prepare to chip reset: */
11069 bxe_reset_mcp_prep(sc, &val);
11076 /* reset the chip */
11077 bxe_process_kill_chip_reset(sc, global);
11080 /* clear errors in PGB */
11081 if (!CHIP_IS_E1(sc))
11082 REG_WR(sc, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
11084 /* Recover after reset: */
11086 if (global && bxe_reset_mcp_comp(sc, val)) {
11090 /* XXX add resetting the NO_MCP mode DB here */
11092 /* Open the gates #2, #3 and #4 */
11093 bxe_set_234_gates(sc, FALSE);
11096 * IGU/AEU preparation bring back the AEU/IGU to a reset state
11097 * re-enable attentions
11104 bxe_leader_reset(struct bxe_softc *sc)
11107 uint8_t global = bxe_reset_is_global(sc);
11108 uint32_t load_code;
11111 * If not going to reset MCP, load "fake" driver to reset HW while
11112 * driver is owner of the HW.
11114 if (!global && !BXE_NOMCP(sc)) {
11115 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
11116 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
11118 BLOGE(sc, "MCP response failure, aborting\n");
11120 goto exit_leader_reset;
11123 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
11124 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
11125 BLOGE(sc, "MCP unexpected response, aborting\n");
11127 goto exit_leader_reset2;
11130 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
11132 BLOGE(sc, "MCP response failure, aborting\n");
11134 goto exit_leader_reset2;
11138 /* try to recover after the failure */
11139 if (bxe_process_kill(sc, global)) {
11140 BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc));
11142 goto exit_leader_reset2;
11146 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
11149 bxe_set_reset_done(sc);
11151 bxe_clear_reset_global(sc);
11154 exit_leader_reset2:
11156 /* unload "fake driver" if it was loaded */
11157 if (!global && !BXE_NOMCP(sc)) {
11158 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
11159 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
11165 bxe_release_leader_lock(sc);
11172 * prepare INIT transition, parameters configured:
11173 * - HC configuration
11174 * - Queue's CDU context
11177 bxe_pf_q_prep_init(struct bxe_softc *sc,
11178 struct bxe_fastpath *fp,
11179 struct ecore_queue_init_params *init_params)
11182 int cxt_index, cxt_offset;
11184 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
11185 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
11187 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
11188 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
11191 init_params->rx.hc_rate =
11192 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
11193 init_params->tx.hc_rate =
11194 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
11197 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
11199 /* CQ index among the SB indices */
11200 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11201 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
11203 /* set maximum number of COSs supported by this queue */
11204 init_params->max_cos = sc->max_cos;
11206 BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n",
11207 fp->index, init_params->max_cos);
11209 /* set the context pointers queue object */
11210 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
11211 /* XXX change index/cid here if ever support multiple tx CoS */
11212 /* fp->txdata[cos]->cid */
11213 cxt_index = fp->index / ILT_PAGE_CIDS;
11214 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
11215 init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth;
11219 /* set flags that are common for the Tx-only and not normal connections */
11220 static unsigned long
11221 bxe_get_common_flags(struct bxe_softc *sc,
11222 struct bxe_fastpath *fp,
11223 uint8_t zero_stats)
11225 unsigned long flags = 0;
11227 /* PF driver will always initialize the Queue to an ACTIVE state */
11228 bxe_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
11231 * tx only connections collect statistics (on the same index as the
11232 * parent connection). The statistics are zeroed when the parent
11233 * connection is initialized.
11236 bxe_set_bit(ECORE_Q_FLG_STATS, &flags);
11238 bxe_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
11242 * tx only connections can support tx-switching, though their
11243 * CoS-ness doesn't survive the loopback
11245 if (sc->flags & BXE_TX_SWITCHING) {
11246 bxe_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
11249 bxe_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
11254 static unsigned long
11255 bxe_get_q_flags(struct bxe_softc *sc,
11256 struct bxe_fastpath *fp,
11259 unsigned long flags = 0;
11261 if (IS_MF_SD(sc)) {
11262 bxe_set_bit(ECORE_Q_FLG_OV, &flags);
11265 if (sc->ifnet->if_capenable & IFCAP_LRO) {
11266 bxe_set_bit(ECORE_Q_FLG_TPA, &flags);
11267 #if __FreeBSD_version >= 800000
11268 bxe_set_bit(ECORE_Q_FLG_TPA_IPV6, &flags);
11273 bxe_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
11274 bxe_set_bit(ECORE_Q_FLG_MCAST, &flags);
11277 bxe_set_bit(ECORE_Q_FLG_VLAN, &flags);
11279 /* merge with common flags */
11280 return (flags | bxe_get_common_flags(sc, fp, TRUE));
11284 bxe_pf_q_prep_general(struct bxe_softc *sc,
11285 struct bxe_fastpath *fp,
11286 struct ecore_general_setup_params *gen_init,
11289 gen_init->stat_id = bxe_stats_id(fp);
11290 gen_init->spcl_id = fp->cl_id;
11291 gen_init->mtu = sc->mtu;
11292 gen_init->cos = cos;
11296 bxe_pf_rx_q_prep(struct bxe_softc *sc,
11297 struct bxe_fastpath *fp,
11298 struct rxq_pause_params *pause,
11299 struct ecore_rxq_setup_params *rxq_init)
11301 uint8_t max_sge = 0;
11302 uint16_t sge_sz = 0;
11303 uint16_t tpa_agg_size = 0;
11305 pause->sge_th_lo = SGE_TH_LO(sc);
11306 pause->sge_th_hi = SGE_TH_HI(sc);
11308 /* validate SGE ring has enough to cross high threshold */
11309 if (sc->dropless_fc &&
11310 (pause->sge_th_hi + FW_PREFETCH_CNT) >
11311 (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)) {
11312 BLOGW(sc, "sge ring threshold limit\n");
11315 /* minimum max_aggregation_size is 2*MTU (two full buffers) */
11316 tpa_agg_size = (2 * sc->mtu);
11317 if (tpa_agg_size < sc->max_aggregation_size) {
11318 tpa_agg_size = sc->max_aggregation_size;
11321 max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT;
11322 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
11323 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
11324 sge_sz = (uint16_t)min(SGE_PAGES, 0xffff);
11326 /* pause - not for e1 */
11327 if (!CHIP_IS_E1(sc)) {
11328 pause->bd_th_lo = BD_TH_LO(sc);
11329 pause->bd_th_hi = BD_TH_HI(sc);
11331 pause->rcq_th_lo = RCQ_TH_LO(sc);
11332 pause->rcq_th_hi = RCQ_TH_HI(sc);
11334 /* validate rings have enough entries to cross high thresholds */
11335 if (sc->dropless_fc &&
11336 pause->bd_th_hi + FW_PREFETCH_CNT >
11337 sc->rx_ring_size) {
11338 BLOGW(sc, "rx bd ring threshold limit\n");
11341 if (sc->dropless_fc &&
11342 pause->rcq_th_hi + FW_PREFETCH_CNT >
11343 RCQ_NUM_PAGES * RCQ_USABLE_PER_PAGE) {
11344 BLOGW(sc, "rcq ring threshold limit\n");
11347 pause->pri_map = 1;
11351 rxq_init->dscr_map = fp->rx_dma.paddr;
11352 rxq_init->sge_map = fp->rx_sge_dma.paddr;
11353 rxq_init->rcq_map = fp->rcq_dma.paddr;
11354 rxq_init->rcq_np_map = (fp->rcq_dma.paddr + BCM_PAGE_SIZE);
11357 * This should be a maximum number of data bytes that may be
11358 * placed on the BD (not including paddings).
11360 rxq_init->buf_sz = (fp->rx_buf_size -
11361 IP_HEADER_ALIGNMENT_PADDING);
11363 rxq_init->cl_qzone_id = fp->cl_qzone_id;
11364 rxq_init->tpa_agg_sz = tpa_agg_size;
11365 rxq_init->sge_buf_sz = sge_sz;
11366 rxq_init->max_sges_pkt = max_sge;
11367 rxq_init->rss_engine_id = SC_FUNC(sc);
11368 rxq_init->mcast_engine_id = SC_FUNC(sc);
11371 * Maximum number or simultaneous TPA aggregation for this Queue.
11372 * For PF Clients it should be the maximum available number.
11373 * VF driver(s) may want to define it to a smaller value.
11375 rxq_init->max_tpa_queues = MAX_AGG_QS(sc);
11377 rxq_init->cache_line_log = BXE_RX_ALIGN_SHIFT;
11378 rxq_init->fw_sb_id = fp->fw_sb_id;
11380 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11383 * configure silent vlan removal
11384 * if multi function mode is afex, then mask default vlan
11386 if (IS_MF_AFEX(sc)) {
11387 rxq_init->silent_removal_value =
11388 sc->devinfo.mf_info.afex_def_vlan_tag;
11389 rxq_init->silent_removal_mask = EVL_VLID_MASK;
11394 bxe_pf_tx_q_prep(struct bxe_softc *sc,
11395 struct bxe_fastpath *fp,
11396 struct ecore_txq_setup_params *txq_init,
11400 * XXX If multiple CoS is ever supported then each fastpath structure
11401 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
11402 * fp->txdata[cos]->tx_dma.paddr;
11404 txq_init->dscr_map = fp->tx_dma.paddr;
11405 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
11406 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
11407 txq_init->fw_sb_id = fp->fw_sb_id;
11410 * set the TSS leading client id for TX classfication to the
11411 * leading RSS client id
11413 txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id);
11417 * This function performs 2 steps in a queue state machine:
11422 bxe_setup_queue(struct bxe_softc *sc,
11423 struct bxe_fastpath *fp,
11426 struct ecore_queue_state_params q_params = { NULL };
11427 struct ecore_queue_setup_params *setup_params =
11428 &q_params.params.setup;
11431 BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index);
11433 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
11435 q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
11437 /* we want to wait for completion in this context */
11438 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
11440 /* prepare the INIT parameters */
11441 bxe_pf_q_prep_init(sc, fp, &q_params.params.init);
11443 /* Set the command */
11444 q_params.cmd = ECORE_Q_CMD_INIT;
11446 /* Change the state to INIT */
11447 rc = ecore_queue_state_change(sc, &q_params);
11449 BLOGE(sc, "Queue(%d) INIT failed rc = %d\n", fp->index, rc);
11453 BLOGD(sc, DBG_LOAD, "init complete\n");
11455 /* now move the Queue to the SETUP state */
11456 memset(setup_params, 0, sizeof(*setup_params));
11458 /* set Queue flags */
11459 setup_params->flags = bxe_get_q_flags(sc, fp, leading);
11461 /* set general SETUP parameters */
11462 bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params,
11463 FIRST_TX_COS_INDEX);
11465 bxe_pf_rx_q_prep(sc, fp,
11466 &setup_params->pause_params,
11467 &setup_params->rxq_params);
11469 bxe_pf_tx_q_prep(sc, fp,
11470 &setup_params->txq_params,
11471 FIRST_TX_COS_INDEX);
11473 /* Set the command */
11474 q_params.cmd = ECORE_Q_CMD_SETUP;
11476 /* change the state to SETUP */
11477 rc = ecore_queue_state_change(sc, &q_params);
11479 BLOGE(sc, "Queue(%d) SETUP failed (rc = %d)\n", fp->index, rc);
11487 bxe_setup_leading(struct bxe_softc *sc)
11489 return (bxe_setup_queue(sc, &sc->fp[0], TRUE));
11493 bxe_config_rss_pf(struct bxe_softc *sc,
11494 struct ecore_rss_config_obj *rss_obj,
11495 uint8_t config_hash)
11497 struct ecore_config_rss_params params = { NULL };
11501 * Although RSS is meaningless when there is a single HW queue we
11502 * still need it enabled in order to have HW Rx hash generated.
11505 params.rss_obj = rss_obj;
11507 bxe_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
11509 bxe_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
11511 /* RSS configuration */
11512 bxe_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
11513 bxe_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
11514 bxe_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
11515 bxe_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
11516 if (rss_obj->udp_rss_v4) {
11517 bxe_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
11519 if (rss_obj->udp_rss_v6) {
11520 bxe_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
11524 params.rss_result_mask = MULTI_MASK;
11526 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
11530 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
11531 params.rss_key[i] = arc4random();
11534 bxe_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
11537 return (ecore_config_rss(sc, ¶ms));
11541 bxe_config_rss_eth(struct bxe_softc *sc,
11542 uint8_t config_hash)
11544 return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash));
11548 bxe_init_rss_pf(struct bxe_softc *sc)
11550 uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc);
11554 * Prepare the initial contents of the indirection table if
11557 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
11558 sc->rss_conf_obj.ind_table[i] =
11559 (sc->fp->cl_id + (i % num_eth_queues));
11563 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
11567 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
11568 * per-port, so if explicit configuration is needed, do it only
11571 * For 57712 and newer it's a per-function configuration.
11573 return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc)));
11577 bxe_set_mac_one(struct bxe_softc *sc,
11579 struct ecore_vlan_mac_obj *obj,
11582 unsigned long *ramrod_flags)
11584 struct ecore_vlan_mac_ramrod_params ramrod_param;
11587 memset(&ramrod_param, 0, sizeof(ramrod_param));
11589 /* fill in general parameters */
11590 ramrod_param.vlan_mac_obj = obj;
11591 ramrod_param.ramrod_flags = *ramrod_flags;
11593 /* fill a user request section if needed */
11594 if (!bxe_test_bit(RAMROD_CONT, ramrod_flags)) {
11595 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
11597 bxe_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
11599 /* Set the command: ADD or DEL */
11600 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
11601 ECORE_VLAN_MAC_DEL;
11604 rc = ecore_config_vlan_mac(sc, &ramrod_param);
11606 if (rc == ECORE_EXISTS) {
11607 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
11608 /* do not treat adding same MAC as error */
11610 } else if (rc < 0) {
11611 BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc);
11618 bxe_set_eth_mac(struct bxe_softc *sc,
11621 unsigned long ramrod_flags = 0;
11623 BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n");
11625 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11627 /* Eth MAC is set on RSS leading client (fp[0]) */
11628 return (bxe_set_mac_one(sc, sc->link_params.mac_addr,
11629 &sc->sp_objs->mac_obj,
11630 set, ECORE_ETH_MAC, &ramrod_flags));
11634 bxe_get_cur_phy_idx(struct bxe_softc *sc)
11636 uint32_t sel_phy_idx = 0;
11638 if (sc->link_params.num_phys <= 1) {
11639 return (ELINK_INT_PHY);
11642 if (sc->link_vars.link_up) {
11643 sel_phy_idx = ELINK_EXT_PHY1;
11644 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
11645 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
11646 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
11647 ELINK_SUPPORTED_FIBRE))
11648 sel_phy_idx = ELINK_EXT_PHY2;
11650 switch (elink_phy_selection(&sc->link_params)) {
11651 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
11652 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11653 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11654 sel_phy_idx = ELINK_EXT_PHY1;
11656 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11657 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11658 sel_phy_idx = ELINK_EXT_PHY2;
11663 return (sel_phy_idx);
11667 bxe_get_link_cfg_idx(struct bxe_softc *sc)
11669 uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc);
11672 * The selected activated PHY is always after swapping (in case PHY
11673 * swapping is enabled). So when swapping is enabled, we need to reverse
11674 * the configuration
11677 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11678 if (sel_phy_idx == ELINK_EXT_PHY1)
11679 sel_phy_idx = ELINK_EXT_PHY2;
11680 else if (sel_phy_idx == ELINK_EXT_PHY2)
11681 sel_phy_idx = ELINK_EXT_PHY1;
11684 return (ELINK_LINK_CONFIG_IDX(sel_phy_idx));
11688 bxe_set_requested_fc(struct bxe_softc *sc)
11691 * Initialize link parameters structure variables
11692 * It is recommended to turn off RX FC for jumbo frames
11693 * for better performance
11695 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
11696 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
11698 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
11703 bxe_calc_fc_adv(struct bxe_softc *sc)
11705 uint8_t cfg_idx = bxe_get_link_cfg_idx(sc);
11708 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
11711 switch (sc->link_vars.ieee_fc &
11712 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
11714 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
11715 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
11719 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
11720 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
11730 bxe_get_mf_speed(struct bxe_softc *sc)
11732 uint16_t line_speed = sc->link_vars.line_speed;
11735 bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]);
11737 /* calculate the current MAX line speed limit for the MF devices */
11738 if (IS_MF_SI(sc)) {
11739 line_speed = (line_speed * maxCfg) / 100;
11740 } else { /* SD mode */
11741 uint16_t vn_max_rate = maxCfg * 100;
11743 if (vn_max_rate < line_speed) {
11744 line_speed = vn_max_rate;
11749 return (line_speed);
11753 bxe_fill_report_data(struct bxe_softc *sc,
11754 struct bxe_link_report_data *data)
11756 uint16_t line_speed = bxe_get_mf_speed(sc);
11758 memset(data, 0, sizeof(*data));
11760 /* fill the report data with the effective line speed */
11761 data->line_speed = line_speed;
11764 if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) {
11765 bxe_set_bit(BXE_LINK_REPORT_LINK_DOWN, &data->link_report_flags);
11769 if (sc->link_vars.duplex == DUPLEX_FULL) {
11770 bxe_set_bit(BXE_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags);
11773 /* Rx Flow Control is ON */
11774 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
11775 bxe_set_bit(BXE_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
11778 /* Tx Flow Control is ON */
11779 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
11780 bxe_set_bit(BXE_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
11784 /* report link status to OS, should be called under phy_lock */
11786 bxe_link_report_locked(struct bxe_softc *sc)
11788 struct bxe_link_report_data cur_data;
11790 /* reread mf_cfg */
11791 if (IS_PF(sc) && !CHIP_IS_E1(sc)) {
11792 bxe_read_mf_cfg(sc);
11795 /* Read the current link report info */
11796 bxe_fill_report_data(sc, &cur_data);
11798 /* Don't report link down or exactly the same link status twice */
11799 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
11800 (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11801 &sc->last_reported_link.link_report_flags) &&
11802 bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11803 &cur_data.link_report_flags))) {
11807 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %x, last_reported_link = %x\n",
11808 cur_data.link_report_flags, sc->last_reported_link.link_report_flags);
11811 ELINK_DEBUG_P1(sc, "link status change count = %x\n", sc->link_cnt);
11812 /* report new link params and remember the state for the next time */
11813 memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
11815 if (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11816 &cur_data.link_report_flags)) {
11817 if_link_state_change(sc->ifnet, LINK_STATE_DOWN);
11819 const char *duplex;
11822 if (bxe_test_and_clear_bit(BXE_LINK_REPORT_FULL_DUPLEX,
11823 &cur_data.link_report_flags)) {
11825 ELINK_DEBUG_P0(sc, "link set to full duplex\n");
11828 ELINK_DEBUG_P0(sc, "link set to half duplex\n");
11832 * Handle the FC at the end so that only these flags would be
11833 * possibly set. This way we may easily check if there is no FC
11836 if (cur_data.link_report_flags) {
11837 if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11838 &cur_data.link_report_flags) &&
11839 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11840 &cur_data.link_report_flags)) {
11841 flow = "ON - receive & transmit";
11842 } else if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11843 &cur_data.link_report_flags) &&
11844 !bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11845 &cur_data.link_report_flags)) {
11846 flow = "ON - receive";
11847 } else if (!bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11848 &cur_data.link_report_flags) &&
11849 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11850 &cur_data.link_report_flags)) {
11851 flow = "ON - transmit";
11853 flow = "none"; /* possible? */
11859 if_link_state_change(sc->ifnet, LINK_STATE_UP);
11860 BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
11861 cur_data.line_speed, duplex, flow);
11866 bxe_link_report(struct bxe_softc *sc)
11868 bxe_acquire_phy_lock(sc);
11869 bxe_link_report_locked(sc);
11870 bxe_release_phy_lock(sc);
11874 bxe_link_status_update(struct bxe_softc *sc)
11876 if (sc->state != BXE_STATE_OPEN) {
11880 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
11881 elink_link_status_update(&sc->link_params, &sc->link_vars);
11883 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
11884 ELINK_SUPPORTED_10baseT_Full |
11885 ELINK_SUPPORTED_100baseT_Half |
11886 ELINK_SUPPORTED_100baseT_Full |
11887 ELINK_SUPPORTED_1000baseT_Full |
11888 ELINK_SUPPORTED_2500baseX_Full |
11889 ELINK_SUPPORTED_10000baseT_Full |
11890 ELINK_SUPPORTED_TP |
11891 ELINK_SUPPORTED_FIBRE |
11892 ELINK_SUPPORTED_Autoneg |
11893 ELINK_SUPPORTED_Pause |
11894 ELINK_SUPPORTED_Asym_Pause);
11895 sc->port.advertising[0] = sc->port.supported[0];
11897 sc->link_params.sc = sc;
11898 sc->link_params.port = SC_PORT(sc);
11899 sc->link_params.req_duplex[0] = DUPLEX_FULL;
11900 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
11901 sc->link_params.req_line_speed[0] = SPEED_10000;
11902 sc->link_params.speed_cap_mask[0] = 0x7f0000;
11903 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
11905 if (CHIP_REV_IS_FPGA(sc)) {
11906 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
11907 sc->link_vars.line_speed = ELINK_SPEED_1000;
11908 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
11909 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
11911 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
11912 sc->link_vars.line_speed = ELINK_SPEED_10000;
11913 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
11914 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
11917 sc->link_vars.link_up = 1;
11919 sc->link_vars.duplex = DUPLEX_FULL;
11920 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
11923 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0);
11924 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11925 bxe_link_report(sc);
11930 if (sc->link_vars.link_up) {
11931 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11933 bxe_stats_handle(sc, STATS_EVENT_STOP);
11935 bxe_link_report(sc);
11937 bxe_link_report(sc);
11938 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11943 bxe_initial_phy_init(struct bxe_softc *sc,
11946 int rc, cfg_idx = bxe_get_link_cfg_idx(sc);
11947 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
11948 struct elink_params *lp = &sc->link_params;
11950 bxe_set_requested_fc(sc);
11952 if (CHIP_REV_IS_SLOW(sc)) {
11953 uint32_t bond = CHIP_BOND_ID(sc);
11956 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
11957 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
11958 } else if (bond & 0x4) {
11959 if (CHIP_IS_E3(sc)) {
11960 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
11962 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
11964 } else if (bond & 0x8) {
11965 if (CHIP_IS_E3(sc)) {
11966 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
11968 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
11972 /* disable EMAC for E3 and above */
11974 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
11977 sc->link_params.feature_config_flags |= feat;
11980 bxe_acquire_phy_lock(sc);
11982 if (load_mode == LOAD_DIAG) {
11983 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
11984 /* Prefer doing PHY loopback at 10G speed, if possible */
11985 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
11986 if (lp->speed_cap_mask[cfg_idx] &
11987 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
11988 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
11990 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
11995 if (load_mode == LOAD_LOOPBACK_EXT) {
11996 lp->loopback_mode = ELINK_LOOPBACK_EXT;
11999 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
12001 bxe_release_phy_lock(sc);
12003 bxe_calc_fc_adv(sc);
12005 if (sc->link_vars.link_up) {
12006 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12007 bxe_link_report(sc);
12010 if (!CHIP_REV_IS_SLOW(sc)) {
12011 bxe_periodic_start(sc);
12014 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
12018 /* must be called under IF_ADDR_LOCK */
12020 bxe_init_mcast_macs_list(struct bxe_softc *sc,
12021 struct ecore_mcast_ramrod_params *p)
12023 struct ifnet *ifp = sc->ifnet;
12025 struct ifmultiaddr *ifma;
12026 struct ecore_mcast_list_elem *mc_mac;
12028 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
12029 if (ifma->ifma_addr->sa_family != AF_LINK) {
12036 ECORE_LIST_INIT(&p->mcast_list);
12037 p->mcast_list_len = 0;
12043 mc_mac = malloc(sizeof(*mc_mac) * mc_count, M_DEVBUF,
12044 (M_NOWAIT | M_ZERO));
12046 BLOGE(sc, "Failed to allocate temp mcast list\n");
12049 bzero(mc_mac, (sizeof(*mc_mac) * mc_count));
12051 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
12052 if (ifma->ifma_addr->sa_family != AF_LINK) {
12056 mc_mac->mac = (uint8_t *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
12057 ECORE_LIST_PUSH_TAIL(&mc_mac->link, &p->mcast_list);
12059 BLOGD(sc, DBG_LOAD,
12060 "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X and mc_count %d\n",
12061 mc_mac->mac[0], mc_mac->mac[1], mc_mac->mac[2],
12062 mc_mac->mac[3], mc_mac->mac[4], mc_mac->mac[5], mc_count);
12066 p->mcast_list_len = mc_count;
12073 bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params *p)
12075 struct ecore_mcast_list_elem *mc_mac =
12076 ECORE_LIST_FIRST_ENTRY(&p->mcast_list,
12077 struct ecore_mcast_list_elem,
12081 /* only a single free as all mc_macs are in the same heap array */
12082 free(mc_mac, M_DEVBUF);
12087 bxe_set_mc_list(struct bxe_softc *sc)
12089 struct ecore_mcast_ramrod_params rparam = { NULL };
12092 rparam.mcast_obj = &sc->mcast_obj;
12094 BXE_MCAST_LOCK(sc);
12096 /* first, clear all configured multicast MACs */
12097 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
12099 BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc);
12100 /* Manual backport parts of FreeBSD upstream r284470. */
12101 BXE_MCAST_UNLOCK(sc);
12105 /* configure a new MACs list */
12106 rc = bxe_init_mcast_macs_list(sc, &rparam);
12108 BLOGE(sc, "Failed to create mcast MACs list (%d)\n", rc);
12109 BXE_MCAST_UNLOCK(sc);
12113 /* Now add the new MACs */
12114 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD);
12116 BLOGE(sc, "Failed to set new mcast config (%d)\n", rc);
12119 bxe_free_mcast_macs_list(&rparam);
12121 BXE_MCAST_UNLOCK(sc);
12127 bxe_set_uc_list(struct bxe_softc *sc)
12129 struct ifnet *ifp = sc->ifnet;
12130 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
12131 struct ifaddr *ifa;
12132 unsigned long ramrod_flags = 0;
12135 #if __FreeBSD_version < 800000
12138 if_addr_rlock(ifp);
12141 /* first schedule a cleanup up of old configuration */
12142 rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE);
12144 BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc);
12145 #if __FreeBSD_version < 800000
12146 IF_ADDR_UNLOCK(ifp);
12148 if_addr_runlock(ifp);
12153 ifa = ifp->if_addr;
12155 if (ifa->ifa_addr->sa_family != AF_LINK) {
12156 ifa = TAILQ_NEXT(ifa, ifa_link);
12160 rc = bxe_set_mac_one(sc, (uint8_t *)LLADDR((struct sockaddr_dl *)ifa->ifa_addr),
12161 mac_obj, TRUE, ECORE_UC_LIST_MAC, &ramrod_flags);
12162 if (rc == -EEXIST) {
12163 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
12164 /* do not treat adding same MAC as an error */
12166 } else if (rc < 0) {
12167 BLOGE(sc, "Failed to schedule ADD operations (%d)\n", rc);
12168 #if __FreeBSD_version < 800000
12169 IF_ADDR_UNLOCK(ifp);
12171 if_addr_runlock(ifp);
12176 ifa = TAILQ_NEXT(ifa, ifa_link);
12179 #if __FreeBSD_version < 800000
12180 IF_ADDR_UNLOCK(ifp);
12182 if_addr_runlock(ifp);
12185 /* Execute the pending commands */
12186 bit_set(&ramrod_flags, RAMROD_CONT);
12187 return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */,
12188 ECORE_UC_LIST_MAC, &ramrod_flags));
12192 bxe_set_rx_mode(struct bxe_softc *sc)
12194 struct ifnet *ifp = sc->ifnet;
12195 uint32_t rx_mode = BXE_RX_MODE_NORMAL;
12197 if (sc->state != BXE_STATE_OPEN) {
12198 BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state);
12202 BLOGD(sc, DBG_SP, "ifp->if_flags=0x%x\n", ifp->if_flags);
12204 if (ifp->if_flags & IFF_PROMISC) {
12205 rx_mode = BXE_RX_MODE_PROMISC;
12206 } else if ((ifp->if_flags & IFF_ALLMULTI) ||
12207 ((ifp->if_amcount > BXE_MAX_MULTICAST) &&
12209 rx_mode = BXE_RX_MODE_ALLMULTI;
12212 /* some multicasts */
12213 if (bxe_set_mc_list(sc) < 0) {
12214 rx_mode = BXE_RX_MODE_ALLMULTI;
12216 if (bxe_set_uc_list(sc) < 0) {
12217 rx_mode = BXE_RX_MODE_PROMISC;
12222 sc->rx_mode = rx_mode;
12224 /* schedule the rx_mode command */
12225 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
12226 BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n");
12227 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
12232 bxe_set_storm_rx_mode(sc);
12237 /* update flags in shmem */
12239 bxe_update_drv_flags(struct bxe_softc *sc,
12243 uint32_t drv_flags;
12245 if (SHMEM2_HAS(sc, drv_flags)) {
12246 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12247 drv_flags = SHMEM2_RD(sc, drv_flags);
12250 SET_FLAGS(drv_flags, flags);
12252 RESET_FLAGS(drv_flags, flags);
12255 SHMEM2_WR(sc, drv_flags, drv_flags);
12256 BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags);
12258 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12262 /* periodic timer callout routine, only runs when the interface is up */
12265 bxe_periodic_callout_func(void *xsc)
12267 struct bxe_softc *sc = (struct bxe_softc *)xsc;
12270 if (!BXE_CORE_TRYLOCK(sc)) {
12271 /* just bail and try again next time */
12273 if ((sc->state == BXE_STATE_OPEN) &&
12274 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12275 /* schedule the next periodic callout */
12276 callout_reset(&sc->periodic_callout, hz,
12277 bxe_periodic_callout_func, sc);
12283 if ((sc->state != BXE_STATE_OPEN) ||
12284 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
12285 BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state);
12286 BXE_CORE_UNLOCK(sc);
12291 /* Check for TX timeouts on any fastpath. */
12292 FOR_EACH_QUEUE(sc, i) {
12293 if (bxe_watchdog(sc, &sc->fp[i]) != 0) {
12294 /* Ruh-Roh, chip was reset! */
12299 if (!CHIP_REV_IS_SLOW(sc)) {
12301 * This barrier is needed to ensure the ordering between the writing
12302 * to the sc->port.pmf in the bxe_nic_load() or bxe_pmf_update() and
12303 * the reading here.
12306 if (sc->port.pmf) {
12307 bxe_acquire_phy_lock(sc);
12308 elink_period_func(&sc->link_params, &sc->link_vars);
12309 bxe_release_phy_lock(sc);
12313 if (IS_PF(sc) && !(sc->flags & BXE_NO_PULSE)) {
12314 int mb_idx = SC_FW_MB_IDX(sc);
12315 uint32_t drv_pulse;
12316 uint32_t mcp_pulse;
12318 ++sc->fw_drv_pulse_wr_seq;
12319 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
12321 drv_pulse = sc->fw_drv_pulse_wr_seq;
12324 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
12325 MCP_PULSE_SEQ_MASK);
12328 * The delta between driver pulse and mcp response should
12329 * be 1 (before mcp response) or 0 (after mcp response).
12331 if ((drv_pulse != mcp_pulse) &&
12332 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
12333 /* someone lost a heartbeat... */
12334 BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
12335 drv_pulse, mcp_pulse);
12339 /* state is BXE_STATE_OPEN */
12340 bxe_stats_handle(sc, STATS_EVENT_UPDATE);
12342 BXE_CORE_UNLOCK(sc);
12344 if ((sc->state == BXE_STATE_OPEN) &&
12345 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12346 /* schedule the next periodic callout */
12347 callout_reset(&sc->periodic_callout, hz,
12348 bxe_periodic_callout_func, sc);
12353 bxe_periodic_start(struct bxe_softc *sc)
12355 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
12356 callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc);
12360 bxe_periodic_stop(struct bxe_softc *sc)
12362 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
12363 callout_drain(&sc->periodic_callout);
12366 /* start the controller */
12367 static __noinline int
12368 bxe_nic_load(struct bxe_softc *sc,
12375 BXE_CORE_LOCK_ASSERT(sc);
12377 BLOGD(sc, DBG_LOAD, "Starting NIC load...\n");
12379 sc->state = BXE_STATE_OPENING_WAITING_LOAD;
12382 /* must be called before memory allocation and HW init */
12383 bxe_ilt_set_info(sc);
12386 sc->last_reported_link_state = LINK_STATE_UNKNOWN;
12388 bxe_set_fp_rx_buf_size(sc);
12390 if (bxe_alloc_fp_buffers(sc) != 0) {
12391 BLOGE(sc, "Failed to allocate fastpath memory\n");
12392 sc->state = BXE_STATE_CLOSED;
12394 goto bxe_nic_load_error0;
12397 if (bxe_alloc_mem(sc) != 0) {
12398 sc->state = BXE_STATE_CLOSED;
12400 goto bxe_nic_load_error0;
12403 if (bxe_alloc_fw_stats_mem(sc) != 0) {
12404 sc->state = BXE_STATE_CLOSED;
12406 goto bxe_nic_load_error0;
12410 /* set pf load just before approaching the MCP */
12411 bxe_set_pf_load(sc);
12413 /* if MCP exists send load request and analyze response */
12414 if (!BXE_NOMCP(sc)) {
12415 /* attempt to load pf */
12416 if (bxe_nic_load_request(sc, &load_code) != 0) {
12417 sc->state = BXE_STATE_CLOSED;
12419 goto bxe_nic_load_error1;
12422 /* what did the MCP say? */
12423 if (bxe_nic_load_analyze_req(sc, load_code) != 0) {
12424 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12425 sc->state = BXE_STATE_CLOSED;
12427 goto bxe_nic_load_error2;
12430 BLOGI(sc, "Device has no MCP!\n");
12431 load_code = bxe_nic_load_no_mcp(sc);
12434 /* mark PMF if applicable */
12435 bxe_nic_load_pmf(sc, load_code);
12437 /* Init Function state controlling object */
12438 bxe_init_func_obj(sc);
12440 /* Initialize HW */
12441 if (bxe_init_hw(sc, load_code) != 0) {
12442 BLOGE(sc, "HW init failed\n");
12443 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12444 sc->state = BXE_STATE_CLOSED;
12446 goto bxe_nic_load_error2;
12450 /* set ALWAYS_ALIVE bit in shmem */
12451 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
12453 sc->flags |= BXE_NO_PULSE;
12455 /* attach interrupts */
12456 if (bxe_interrupt_attach(sc) != 0) {
12457 sc->state = BXE_STATE_CLOSED;
12459 goto bxe_nic_load_error2;
12462 bxe_nic_init(sc, load_code);
12464 /* Init per-function objects */
12467 // XXX bxe_iov_nic_init(sc);
12469 /* set AFEX default VLAN tag to an invalid value */
12470 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
12471 // XXX bxe_nic_load_afex_dcc(sc, load_code);
12473 sc->state = BXE_STATE_OPENING_WAITING_PORT;
12474 rc = bxe_func_start(sc);
12476 BLOGE(sc, "Function start failed! rc = %d\n", rc);
12477 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12478 sc->state = BXE_STATE_ERROR;
12479 goto bxe_nic_load_error3;
12482 /* send LOAD_DONE command to MCP */
12483 if (!BXE_NOMCP(sc)) {
12484 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12486 BLOGE(sc, "MCP response failure, aborting\n");
12487 sc->state = BXE_STATE_ERROR;
12489 goto bxe_nic_load_error3;
12493 rc = bxe_setup_leading(sc);
12495 BLOGE(sc, "Setup leading failed! rc = %d\n", rc);
12496 sc->state = BXE_STATE_ERROR;
12497 goto bxe_nic_load_error3;
12500 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
12501 rc = bxe_setup_queue(sc, &sc->fp[i], FALSE);
12503 BLOGE(sc, "Queue(%d) setup failed rc = %d\n", i, rc);
12504 sc->state = BXE_STATE_ERROR;
12505 goto bxe_nic_load_error3;
12509 rc = bxe_init_rss_pf(sc);
12511 BLOGE(sc, "PF RSS init failed\n");
12512 sc->state = BXE_STATE_ERROR;
12513 goto bxe_nic_load_error3;
12518 /* now when Clients are configured we are ready to work */
12519 sc->state = BXE_STATE_OPEN;
12521 /* Configure a ucast MAC */
12523 rc = bxe_set_eth_mac(sc, TRUE);
12526 BLOGE(sc, "Setting Ethernet MAC failed rc = %d\n", rc);
12527 sc->state = BXE_STATE_ERROR;
12528 goto bxe_nic_load_error3;
12531 if (sc->port.pmf) {
12532 rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN);
12534 sc->state = BXE_STATE_ERROR;
12535 goto bxe_nic_load_error3;
12539 sc->link_params.feature_config_flags &=
12540 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
12542 /* start fast path */
12544 /* Initialize Rx filter */
12545 bxe_set_rx_mode(sc);
12548 switch (/* XXX load_mode */LOAD_OPEN) {
12554 case LOAD_LOOPBACK_EXT:
12555 sc->state = BXE_STATE_DIAG;
12562 if (sc->port.pmf) {
12563 bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
12565 bxe_link_status_update(sc);
12568 /* start the periodic timer callout */
12569 bxe_periodic_start(sc);
12571 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
12572 /* mark driver is loaded in shmem2 */
12573 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
12574 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
12576 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
12577 DRV_FLAGS_CAPABILITIES_LOADED_L2));
12580 /* wait for all pending SP commands to complete */
12581 if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) {
12582 BLOGE(sc, "Timeout waiting for all SPs to complete!\n");
12583 bxe_periodic_stop(sc);
12584 bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE);
12588 /* Tell the stack the driver is running! */
12589 sc->ifnet->if_drv_flags = IFF_DRV_RUNNING;
12591 BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n");
12595 bxe_nic_load_error3:
12598 bxe_int_disable_sync(sc, 1);
12600 /* clean out queued objects */
12601 bxe_squeeze_objects(sc);
12604 bxe_interrupt_detach(sc);
12606 bxe_nic_load_error2:
12608 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
12609 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
12610 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
12615 bxe_nic_load_error1:
12617 /* clear pf_load status, as it was already set */
12619 bxe_clear_pf_load(sc);
12622 bxe_nic_load_error0:
12624 bxe_free_fw_stats_mem(sc);
12625 bxe_free_fp_buffers(sc);
12632 bxe_init_locked(struct bxe_softc *sc)
12634 int other_engine = SC_PATH(sc) ? 0 : 1;
12635 uint8_t other_load_status, load_status;
12636 uint8_t global = FALSE;
12639 BXE_CORE_LOCK_ASSERT(sc);
12641 /* check if the driver is already running */
12642 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
12643 BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n");
12647 bxe_set_power_state(sc, PCI_PM_D0);
12650 * If parity occurred during the unload, then attentions and/or
12651 * RECOVERY_IN_PROGRES may still be set. If so we want the first function
12652 * loaded on the current engine to complete the recovery. Parity recovery
12653 * is only relevant for PF driver.
12656 other_load_status = bxe_get_load_status(sc, other_engine);
12657 load_status = bxe_get_load_status(sc, SC_PATH(sc));
12659 if (!bxe_reset_is_done(sc, SC_PATH(sc)) ||
12660 bxe_chk_parity_attn(sc, &global, TRUE)) {
12663 * If there are attentions and they are in global blocks, set
12664 * the GLOBAL_RESET bit regardless whether it will be this
12665 * function that will complete the recovery or not.
12668 bxe_set_reset_global(sc);
12672 * Only the first function on the current engine should try
12673 * to recover in open. In case of attentions in global blocks
12674 * only the first in the chip should try to recover.
12676 if ((!load_status && (!global || !other_load_status)) &&
12677 bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) {
12678 BLOGI(sc, "Recovered during init\n");
12682 /* recovery has failed... */
12683 bxe_set_power_state(sc, PCI_PM_D3hot);
12684 sc->recovery_state = BXE_RECOVERY_FAILED;
12686 BLOGE(sc, "Recovery flow hasn't properly "
12687 "completed yet, try again later. "
12688 "If you still see this message after a "
12689 "few retries then power cycle is required.\n");
12692 goto bxe_init_locked_done;
12697 sc->recovery_state = BXE_RECOVERY_DONE;
12699 rc = bxe_nic_load(sc, LOAD_OPEN);
12701 bxe_init_locked_done:
12704 /* Tell the stack the driver is NOT running! */
12705 BLOGE(sc, "Initialization failed, "
12706 "stack notified driver is NOT running!\n");
12707 sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING;
12714 bxe_stop_locked(struct bxe_softc *sc)
12716 BXE_CORE_LOCK_ASSERT(sc);
12717 return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE));
12721 * Handles controller initialization when called from an unlocked routine.
12722 * ifconfig calls this function.
12728 bxe_init(void *xsc)
12730 struct bxe_softc *sc = (struct bxe_softc *)xsc;
12733 bxe_init_locked(sc);
12734 BXE_CORE_UNLOCK(sc);
12738 bxe_init_ifnet(struct bxe_softc *sc)
12742 /* ifconfig entrypoint for media type/status reporting */
12743 ifmedia_init(&sc->ifmedia, IFM_IMASK,
12744 bxe_ifmedia_update,
12745 bxe_ifmedia_status);
12747 /* set the default interface values */
12748 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL);
12749 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL);
12750 ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO));
12752 sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */
12753 BLOGI(sc, "IFMEDIA flags : %x\n", sc->ifmedia.ifm_media);
12755 /* allocate the ifnet structure */
12756 if ((ifp = if_alloc(IFT_ETHER)) == NULL) {
12757 BLOGE(sc, "Interface allocation failed!\n");
12761 ifp->if_softc = sc;
12762 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
12763 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
12764 ifp->if_ioctl = bxe_ioctl;
12765 ifp->if_start = bxe_tx_start;
12766 #if __FreeBSD_version >= 901504
12767 ifp->if_transmit = bxe_tx_mq_start;
12768 ifp->if_qflush = bxe_mq_flush;
12773 ifp->if_init = bxe_init;
12774 ifp->if_mtu = sc->mtu;
12775 ifp->if_hwassist = (CSUM_IP |
12781 ifp->if_capabilities =
12782 #if __FreeBSD_version < 700000
12784 IFCAP_VLAN_HWTAGGING |
12790 IFCAP_VLAN_HWTAGGING |
12792 IFCAP_VLAN_HWFILTER |
12793 IFCAP_VLAN_HWCSUM |
12801 ifp->if_capenable = ifp->if_capabilities;
12802 ifp->if_capenable &= ~IFCAP_WOL_MAGIC; /* XXX not yet... */
12803 #if __FreeBSD_version < 1000025
12804 ifp->if_baudrate = 1000000000;
12806 if_initbaudrate(ifp, IF_Gbps(10));
12808 ifp->if_snd.ifq_drv_maxlen = sc->tx_ring_size;
12810 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
12811 IFQ_SET_READY(&ifp->if_snd);
12815 /* attach to the Ethernet interface list */
12816 ether_ifattach(ifp, sc->link_params.mac_addr);
12822 bxe_deallocate_bars(struct bxe_softc *sc)
12826 for (i = 0; i < MAX_BARS; i++) {
12827 if (sc->bar[i].resource != NULL) {
12828 bus_release_resource(sc->dev,
12831 sc->bar[i].resource);
12832 BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n",
12839 bxe_allocate_bars(struct bxe_softc *sc)
12844 memset(sc->bar, 0, sizeof(sc->bar));
12846 for (i = 0; i < MAX_BARS; i++) {
12848 /* memory resources reside at BARs 0, 2, 4 */
12849 /* Run `pciconf -lb` to see mappings */
12850 if ((i != 0) && (i != 2) && (i != 4)) {
12854 sc->bar[i].rid = PCIR_BAR(i);
12858 flags |= RF_SHAREABLE;
12861 if ((sc->bar[i].resource =
12862 bus_alloc_resource_any(sc->dev,
12869 sc->bar[i].tag = rman_get_bustag(sc->bar[i].resource);
12870 sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource);
12871 sc->bar[i].kva = (vm_offset_t)rman_get_virtual(sc->bar[i].resource);
12873 BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %p-%p (%ld) -> %p\n",
12875 (void *)rman_get_start(sc->bar[i].resource),
12876 (void *)rman_get_end(sc->bar[i].resource),
12877 rman_get_size(sc->bar[i].resource),
12878 (void *)sc->bar[i].kva);
12885 bxe_get_function_num(struct bxe_softc *sc)
12890 * Read the ME register to get the function number. The ME register
12891 * holds the relative-function number and absolute-function number. The
12892 * absolute-function number appears only in E2 and above. Before that
12893 * these bits always contained zero, therefore we cannot blindly use them.
12896 val = REG_RD(sc, BAR_ME_REGISTER);
12899 (uint8_t)((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
12901 (uint8_t)((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) & 1;
12903 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
12904 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
12906 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
12909 BLOGD(sc, DBG_LOAD,
12910 "Relative function %d, Absolute function %d, Path %d\n",
12911 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
12915 bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc)
12917 uint32_t shmem2_size;
12919 uint32_t mf_cfg_offset_value;
12922 offset = (SHMEM_RD(sc, func_mb) +
12923 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
12926 if (sc->devinfo.shmem2_base != 0) {
12927 shmem2_size = SHMEM2_RD(sc, size);
12928 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
12929 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
12930 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
12931 offset = mf_cfg_offset_value;
12940 bxe_pcie_capability_read(struct bxe_softc *sc,
12946 /* ensure PCIe capability is enabled */
12947 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) {
12948 if (pcie_reg != 0) {
12949 BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg);
12950 return (pci_read_config(sc->dev, (pcie_reg + reg), width));
12954 BLOGE(sc, "PCIe capability NOT FOUND!!!\n");
12960 bxe_is_pcie_pending(struct bxe_softc *sc)
12962 return (bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA, 2) &
12963 PCIM_EXP_STA_TRANSACTION_PND);
12967 * Walk the PCI capabiites list for the device to find what features are
12968 * supported. These capabilites may be enabled/disabled by firmware so it's
12969 * best to walk the list rather than make assumptions.
12972 bxe_probe_pci_caps(struct bxe_softc *sc)
12974 uint16_t link_status;
12977 /* check if PCI Power Management is enabled */
12978 if (pci_find_cap(sc->dev, PCIY_PMG, ®) == 0) {
12980 BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg);
12982 sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG;
12983 sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg;
12987 link_status = bxe_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA, 2);
12989 /* handle PCIe 2.0 workarounds for 57710 */
12990 if (CHIP_IS_E1(sc)) {
12991 /* workaround for 57710 errata E4_57710_27462 */
12992 sc->devinfo.pcie_link_speed =
12993 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
12995 /* workaround for 57710 errata E4_57710_27488 */
12996 sc->devinfo.pcie_link_width =
12997 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
12998 if (sc->devinfo.pcie_link_speed > 1) {
12999 sc->devinfo.pcie_link_width =
13000 ((link_status & PCIM_LINK_STA_WIDTH) >> 4) >> 1;
13003 sc->devinfo.pcie_link_speed =
13004 (link_status & PCIM_LINK_STA_SPEED);
13005 sc->devinfo.pcie_link_width =
13006 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
13009 BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n",
13010 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
13012 sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG;
13013 sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg;
13015 /* check if MSI capability is enabled */
13016 if (pci_find_cap(sc->dev, PCIY_MSI, ®) == 0) {
13018 BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg);
13020 sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG;
13021 sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg;
13025 /* check if MSI-X capability is enabled */
13026 if (pci_find_cap(sc->dev, PCIY_MSIX, ®) == 0) {
13028 BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg);
13030 sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG;
13031 sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg;
13037 bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc)
13039 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13042 /* get the outer vlan if we're in switch-dependent mode */
13044 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13045 mf_info->ext_id = (uint16_t)val;
13047 mf_info->multi_vnics_mode = 1;
13049 if (!VALID_OVLAN(mf_info->ext_id)) {
13050 BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id);
13054 /* get the capabilities */
13055 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13056 FUNC_MF_CFG_PROTOCOL_ISCSI) {
13057 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
13058 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13059 FUNC_MF_CFG_PROTOCOL_FCOE) {
13060 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
13062 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
13065 mf_info->vnics_per_port =
13066 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13072 bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc)
13074 uint32_t retval = 0;
13077 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13079 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
13080 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
13081 retval |= MF_PROTO_SUPPORT_ETHERNET;
13083 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
13084 retval |= MF_PROTO_SUPPORT_ISCSI;
13086 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
13087 retval |= MF_PROTO_SUPPORT_FCOE;
13095 bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc)
13097 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13101 * There is no outer vlan if we're in switch-independent mode.
13102 * If the mac is valid then assume multi-function.
13105 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13107 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
13109 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13111 mf_info->vnics_per_port =
13112 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13118 bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc)
13120 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13121 uint32_t e1hov_tag;
13122 uint32_t func_config;
13123 uint32_t niv_config;
13125 mf_info->multi_vnics_mode = 1;
13127 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13128 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13129 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
13132 (uint16_t)((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
13133 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
13135 mf_info->default_vlan =
13136 (uint16_t)((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
13137 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
13139 mf_info->niv_allowed_priorities =
13140 (uint8_t)((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
13141 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
13143 mf_info->niv_default_cos =
13144 (uint8_t)((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
13145 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
13147 mf_info->afex_vlan_mode =
13148 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
13149 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
13151 mf_info->niv_mba_enabled =
13152 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
13153 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
13155 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13157 mf_info->vnics_per_port =
13158 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13164 bxe_check_valid_mf_cfg(struct bxe_softc *sc)
13166 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13173 BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n",
13175 BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n",
13176 mf_info->mf_config[SC_VN(sc)]);
13177 BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n",
13178 mf_info->multi_vnics_mode);
13179 BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n",
13180 mf_info->vnics_per_port);
13181 BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n",
13183 BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n",
13184 mf_info->min_bw[0], mf_info->min_bw[1],
13185 mf_info->min_bw[2], mf_info->min_bw[3]);
13186 BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n",
13187 mf_info->max_bw[0], mf_info->max_bw[1],
13188 mf_info->max_bw[2], mf_info->max_bw[3]);
13189 BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n",
13192 /* various MF mode sanity checks... */
13194 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
13195 BLOGE(sc, "Enumerated function %d is marked as hidden\n",
13200 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
13201 BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n",
13202 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
13206 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13207 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
13208 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
13209 BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n",
13210 SC_VN(sc), OVLAN(sc));
13214 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
13215 BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n",
13216 mf_info->multi_vnics_mode, OVLAN(sc));
13221 * Verify all functions are either MF or SF mode. If MF, make sure
13222 * sure that all non-hidden functions have a valid ovlan. If SF,
13223 * make sure that all non-hidden functions have an invalid ovlan.
13225 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13226 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13227 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13228 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13229 (((mf_info->multi_vnics_mode) && !VALID_OVLAN(ovlan1)) ||
13230 ((!mf_info->multi_vnics_mode) && VALID_OVLAN(ovlan1)))) {
13231 BLOGE(sc, "mf_mode=SD function %d MF config "
13232 "mismatch, multi_vnics_mode=%d ovlan=%d\n",
13233 i, mf_info->multi_vnics_mode, ovlan1);
13238 /* Verify all funcs on the same port each have a different ovlan. */
13239 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13240 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13241 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13242 /* iterate from the next function on the port to the max func */
13243 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
13244 mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config);
13245 ovlan2 = MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
13246 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13247 VALID_OVLAN(ovlan1) &&
13248 !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE) &&
13249 VALID_OVLAN(ovlan2) &&
13250 (ovlan1 == ovlan2)) {
13251 BLOGE(sc, "mf_mode=SD functions %d and %d "
13252 "have the same ovlan (%d)\n",
13258 } /* MULTI_FUNCTION_SD */
13264 bxe_get_mf_cfg_info(struct bxe_softc *sc)
13266 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13267 uint32_t val, mac_upper;
13270 /* initialize mf_info defaults */
13271 mf_info->vnics_per_port = 1;
13272 mf_info->multi_vnics_mode = FALSE;
13273 mf_info->path_has_ovlan = FALSE;
13274 mf_info->mf_mode = SINGLE_FUNCTION;
13276 if (!CHIP_IS_MF_CAP(sc)) {
13280 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
13281 BLOGE(sc, "Invalid mf_cfg_base!\n");
13285 /* get the MF mode (switch dependent / independent / single-function) */
13287 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13289 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK)
13291 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
13293 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13295 /* check for legal upper mac bytes */
13296 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
13297 mf_info->mf_mode = MULTI_FUNCTION_SI;
13299 BLOGE(sc, "Invalid config for Switch Independent mode\n");
13304 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
13305 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
13307 /* get outer vlan configuration */
13308 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13310 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
13311 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
13312 mf_info->mf_mode = MULTI_FUNCTION_SD;
13314 BLOGE(sc, "Invalid config for Switch Dependent mode\n");
13319 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
13321 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
13324 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
13327 * Mark MF mode as NIV if MCP version includes NPAR-SD support
13328 * and the MAC address is valid.
13330 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13332 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
13333 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
13334 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
13336 BLOGE(sc, "Invalid config for AFEX mode\n");
13343 BLOGE(sc, "Unknown MF mode (0x%08x)\n",
13344 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
13349 /* set path mf_mode (which could be different than function mf_mode) */
13350 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13351 mf_info->path_has_ovlan = TRUE;
13352 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
13354 * Decide on path multi vnics mode. If we're not in MF mode and in
13355 * 4-port mode, this is good enough to check vnic-0 of the other port
13358 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
13359 uint8_t other_port = !(PORT_ID(sc) & 1);
13360 uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port));
13362 val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag);
13364 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t)val) ? 1 : 0;
13368 if (mf_info->mf_mode == SINGLE_FUNCTION) {
13369 /* invalid MF config */
13370 if (SC_VN(sc) >= 1) {
13371 BLOGE(sc, "VNIC ID >= 1 in SF mode\n");
13378 /* get the MF configuration */
13379 mf_info->mf_config[SC_VN(sc)] =
13380 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13382 switch(mf_info->mf_mode)
13384 case MULTI_FUNCTION_SD:
13386 bxe_get_shmem_mf_cfg_info_sd(sc);
13389 case MULTI_FUNCTION_SI:
13391 bxe_get_shmem_mf_cfg_info_si(sc);
13394 case MULTI_FUNCTION_AFEX:
13396 bxe_get_shmem_mf_cfg_info_niv(sc);
13401 BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n",
13406 /* get the congestion management parameters */
13409 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13410 /* get min/max bw */
13411 val = MFCFG_RD(sc, func_mf_config[i].config);
13412 mf_info->min_bw[vnic] =
13413 ((val & FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT);
13414 mf_info->max_bw[vnic] =
13415 ((val & FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT);
13419 return (bxe_check_valid_mf_cfg(sc));
13423 bxe_get_shmem_info(struct bxe_softc *sc)
13426 uint32_t mac_hi, mac_lo, val;
13428 port = SC_PORT(sc);
13429 mac_hi = mac_lo = 0;
13431 sc->link_params.sc = sc;
13432 sc->link_params.port = port;
13434 /* get the hardware config info */
13435 sc->devinfo.hw_config =
13436 SHMEM_RD(sc, dev_info.shared_hw_config.config);
13437 sc->devinfo.hw_config2 =
13438 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
13440 sc->link_params.hw_led_mode =
13441 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
13442 SHARED_HW_CFG_LED_MODE_SHIFT);
13444 /* get the port feature config */
13446 SHMEM_RD(sc, dev_info.port_feature_config[port].config),
13448 /* get the link params */
13449 sc->link_params.speed_cap_mask[0] =
13450 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask);
13451 sc->link_params.speed_cap_mask[1] =
13452 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2);
13454 /* get the lane config */
13455 sc->link_params.lane_config =
13456 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
13458 /* get the link config */
13459 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
13460 sc->port.link_config[ELINK_INT_PHY] = val;
13461 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
13462 sc->port.link_config[ELINK_EXT_PHY1] =
13463 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
13465 /* get the override preemphasis flag and enable it or turn it off */
13466 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13467 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
13468 sc->link_params.feature_config_flags |=
13469 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13471 sc->link_params.feature_config_flags &=
13472 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13475 /* get the initial value of the link params */
13476 sc->link_params.multi_phy_config =
13477 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
13479 /* get external phy info */
13480 sc->port.ext_phy_config =
13481 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
13483 /* get the multifunction configuration */
13484 bxe_get_mf_cfg_info(sc);
13486 /* get the mac address */
13488 mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13489 mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
13491 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
13492 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
13495 if ((mac_lo == 0) && (mac_hi == 0)) {
13496 *sc->mac_addr_str = 0;
13497 BLOGE(sc, "No Ethernet address programmed!\n");
13499 sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8);
13500 sc->link_params.mac_addr[1] = (uint8_t)(mac_hi);
13501 sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24);
13502 sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16);
13503 sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8);
13504 sc->link_params.mac_addr[5] = (uint8_t)(mac_lo);
13505 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
13506 "%02x:%02x:%02x:%02x:%02x:%02x",
13507 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1],
13508 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3],
13509 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]);
13510 BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str);
13517 bxe_get_tunable_params(struct bxe_softc *sc)
13519 /* sanity checks */
13521 if ((bxe_interrupt_mode != INTR_MODE_INTX) &&
13522 (bxe_interrupt_mode != INTR_MODE_MSI) &&
13523 (bxe_interrupt_mode != INTR_MODE_MSIX)) {
13524 BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode);
13525 bxe_interrupt_mode = INTR_MODE_MSIX;
13528 if ((bxe_queue_count < 0) || (bxe_queue_count > MAX_RSS_CHAINS)) {
13529 BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count);
13530 bxe_queue_count = 0;
13533 if ((bxe_max_rx_bufs < 1) || (bxe_max_rx_bufs > RX_BD_USABLE)) {
13534 if (bxe_max_rx_bufs == 0) {
13535 bxe_max_rx_bufs = RX_BD_USABLE;
13537 BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs);
13538 bxe_max_rx_bufs = 2048;
13542 if ((bxe_hc_rx_ticks < 1) || (bxe_hc_rx_ticks > 100)) {
13543 BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks);
13544 bxe_hc_rx_ticks = 25;
13547 if ((bxe_hc_tx_ticks < 1) || (bxe_hc_tx_ticks > 100)) {
13548 BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks);
13549 bxe_hc_tx_ticks = 50;
13552 if (bxe_max_aggregation_size == 0) {
13553 bxe_max_aggregation_size = TPA_AGG_SIZE;
13556 if (bxe_max_aggregation_size > 0xffff) {
13557 BLOGW(sc, "invalid max_aggregation_size (%d)\n",
13558 bxe_max_aggregation_size);
13559 bxe_max_aggregation_size = TPA_AGG_SIZE;
13562 if ((bxe_mrrs < -1) || (bxe_mrrs > 3)) {
13563 BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs);
13567 if ((bxe_autogreeen < 0) || (bxe_autogreeen > 2)) {
13568 BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen);
13569 bxe_autogreeen = 0;
13572 if ((bxe_udp_rss < 0) || (bxe_udp_rss > 1)) {
13573 BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss);
13577 /* pull in user settings */
13579 sc->interrupt_mode = bxe_interrupt_mode;
13580 sc->max_rx_bufs = bxe_max_rx_bufs;
13581 sc->hc_rx_ticks = bxe_hc_rx_ticks;
13582 sc->hc_tx_ticks = bxe_hc_tx_ticks;
13583 sc->max_aggregation_size = bxe_max_aggregation_size;
13584 sc->mrrs = bxe_mrrs;
13585 sc->autogreeen = bxe_autogreeen;
13586 sc->udp_rss = bxe_udp_rss;
13588 if (bxe_interrupt_mode == INTR_MODE_INTX) {
13589 sc->num_queues = 1;
13590 } else { /* INTR_MODE_MSI or INTR_MODE_MSIX */
13592 min((bxe_queue_count ? bxe_queue_count : mp_ncpus),
13594 if (sc->num_queues > mp_ncpus) {
13595 sc->num_queues = mp_ncpus;
13599 BLOGD(sc, DBG_LOAD,
13602 "interrupt_mode=%d "
13607 "max_aggregation_size=%d "
13612 sc->interrupt_mode,
13617 sc->max_aggregation_size,
13624 bxe_media_detect(struct bxe_softc *sc)
13627 uint32_t phy_idx = bxe_get_cur_phy_idx(sc);
13629 switch (sc->link_params.phy[phy_idx].media_type) {
13630 case ELINK_ETH_PHY_SFPP_10G_FIBER:
13631 case ELINK_ETH_PHY_XFP_FIBER:
13632 BLOGI(sc, "Found 10Gb Fiber media.\n");
13633 sc->media = IFM_10G_SR;
13634 port_type = PORT_FIBRE;
13636 case ELINK_ETH_PHY_SFP_1G_FIBER:
13637 BLOGI(sc, "Found 1Gb Fiber media.\n");
13638 sc->media = IFM_1000_SX;
13639 port_type = PORT_FIBRE;
13641 case ELINK_ETH_PHY_KR:
13642 case ELINK_ETH_PHY_CX4:
13643 BLOGI(sc, "Found 10GBase-CX4 media.\n");
13644 sc->media = IFM_10G_CX4;
13645 port_type = PORT_FIBRE;
13647 case ELINK_ETH_PHY_DA_TWINAX:
13648 BLOGI(sc, "Found 10Gb Twinax media.\n");
13649 sc->media = IFM_10G_TWINAX;
13650 port_type = PORT_DA;
13652 case ELINK_ETH_PHY_BASE_T:
13653 if (sc->link_params.speed_cap_mask[0] &
13654 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
13655 BLOGI(sc, "Found 10GBase-T media.\n");
13656 sc->media = IFM_10G_T;
13657 port_type = PORT_TP;
13659 BLOGI(sc, "Found 1000Base-T media.\n");
13660 sc->media = IFM_1000_T;
13661 port_type = PORT_TP;
13664 case ELINK_ETH_PHY_NOT_PRESENT:
13665 BLOGI(sc, "Media not present.\n");
13667 port_type = PORT_OTHER;
13669 case ELINK_ETH_PHY_UNSPECIFIED:
13671 BLOGI(sc, "Unknown media!\n");
13673 port_type = PORT_OTHER;
13679 #define GET_FIELD(value, fname) \
13680 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
13681 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
13682 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
13685 bxe_get_igu_cam_info(struct bxe_softc *sc)
13687 int pfid = SC_FUNC(sc);
13690 uint8_t fid, igu_sb_cnt = 0;
13692 sc->igu_base_sb = 0xff;
13694 if (CHIP_INT_MODE_IS_BC(sc)) {
13695 int vn = SC_VN(sc);
13696 igu_sb_cnt = sc->igu_sb_cnt;
13697 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
13699 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
13700 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
13704 /* IGU in normal mode - read CAM */
13705 for (igu_sb_id = 0;
13706 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
13708 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
13709 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
13712 fid = IGU_FID(val);
13713 if ((fid & IGU_FID_ENCODE_IS_PF)) {
13714 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
13717 if (IGU_VEC(val) == 0) {
13718 /* default status block */
13719 sc->igu_dsb_id = igu_sb_id;
13721 if (sc->igu_base_sb == 0xff) {
13722 sc->igu_base_sb = igu_sb_id;
13730 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
13731 * that number of CAM entries will not be equal to the value advertised in
13732 * PCI. Driver should use the minimal value of both as the actual status
13735 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
13737 if (igu_sb_cnt == 0) {
13738 BLOGE(sc, "CAM configuration error\n");
13746 * Gather various information from the device config space, the device itself,
13747 * shmem, and the user input.
13750 bxe_get_device_info(struct bxe_softc *sc)
13755 /* Get the data for the device */
13756 sc->devinfo.vendor_id = pci_get_vendor(sc->dev);
13757 sc->devinfo.device_id = pci_get_device(sc->dev);
13758 sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev);
13759 sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev);
13761 /* get the chip revision (chip metal comes from pci config space) */
13762 sc->devinfo.chip_id =
13763 sc->link_params.chip_id =
13764 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
13765 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
13766 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
13767 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
13769 /* force 57811 according to MISC register */
13770 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
13771 if (CHIP_IS_57810(sc)) {
13772 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
13773 (sc->devinfo.chip_id & 0x0000ffff));
13774 } else if (CHIP_IS_57810_MF(sc)) {
13775 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
13776 (sc->devinfo.chip_id & 0x0000ffff));
13778 sc->devinfo.chip_id |= 0x1;
13781 BLOGD(sc, DBG_LOAD,
13782 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n",
13783 sc->devinfo.chip_id,
13784 ((sc->devinfo.chip_id >> 16) & 0xffff),
13785 ((sc->devinfo.chip_id >> 12) & 0xf),
13786 ((sc->devinfo.chip_id >> 4) & 0xff),
13787 ((sc->devinfo.chip_id >> 0) & 0xf));
13789 val = (REG_RD(sc, 0x2874) & 0x55);
13790 if ((sc->devinfo.chip_id & 0x1) ||
13791 (CHIP_IS_E1(sc) && val) ||
13792 (CHIP_IS_E1H(sc) && (val == 0x55))) {
13793 sc->flags |= BXE_ONE_PORT_FLAG;
13794 BLOGD(sc, DBG_LOAD, "single port device\n");
13797 /* set the doorbell size */
13798 sc->doorbell_size = (1 << BXE_DB_SHIFT);
13800 /* determine whether the device is in 2 port or 4 port mode */
13801 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/
13802 if (CHIP_IS_E2E3(sc)) {
13804 * Read port4mode_en_ovwr[0]:
13805 * If 1, four port mode is in port4mode_en_ovwr[1].
13806 * If 0, four port mode is in port4mode_en[0].
13808 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
13810 val = ((val >> 1) & 1);
13812 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
13815 sc->devinfo.chip_port_mode =
13816 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
13818 BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2");
13821 /* get the function and path info for the device */
13822 bxe_get_function_num(sc);
13824 /* get the shared memory base address */
13825 sc->devinfo.shmem_base =
13826 sc->link_params.shmem_base =
13827 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
13828 sc->devinfo.shmem2_base =
13829 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
13830 MISC_REG_GENERIC_CR_0));
13832 BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n",
13833 sc->devinfo.shmem_base, sc->devinfo.shmem2_base);
13835 if (!sc->devinfo.shmem_base) {
13836 /* this should ONLY prevent upcoming shmem reads */
13837 BLOGI(sc, "MCP not active\n");
13838 sc->flags |= BXE_NO_MCP_FLAG;
13842 /* make sure the shared memory contents are valid */
13843 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
13844 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
13845 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
13846 BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val);
13849 BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val);
13851 /* get the bootcode version */
13852 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
13853 snprintf(sc->devinfo.bc_ver_str,
13854 sizeof(sc->devinfo.bc_ver_str),
13856 ((sc->devinfo.bc_ver >> 24) & 0xff),
13857 ((sc->devinfo.bc_ver >> 16) & 0xff),
13858 ((sc->devinfo.bc_ver >> 8) & 0xff));
13859 BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str);
13861 /* get the bootcode shmem address */
13862 sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc);
13863 BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base);
13865 /* clean indirect addresses as they're not used */
13866 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
13868 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
13869 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
13870 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
13871 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
13872 if (CHIP_IS_E1x(sc)) {
13873 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
13874 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
13875 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
13876 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
13880 * Enable internal target-read (in case we are probed after PF
13881 * FLR). Must be done prior to any BAR read access. Only for
13884 if (!CHIP_IS_E1x(sc)) {
13885 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13889 /* get the nvram size */
13890 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
13891 sc->devinfo.flash_size =
13892 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
13893 BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size);
13895 /* get PCI capabilites */
13896 bxe_probe_pci_caps(sc);
13898 bxe_set_power_state(sc, PCI_PM_D0);
13900 /* get various configuration parameters from shmem */
13901 bxe_get_shmem_info(sc);
13903 if (sc->devinfo.pcie_msix_cap_reg != 0) {
13904 val = pci_read_config(sc->dev,
13905 (sc->devinfo.pcie_msix_cap_reg +
13908 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
13910 sc->igu_sb_cnt = 1;
13913 sc->igu_base_addr = BAR_IGU_INTMEM;
13915 /* initialize IGU parameters */
13916 if (CHIP_IS_E1x(sc)) {
13917 sc->devinfo.int_block = INT_BLOCK_HC;
13918 sc->igu_dsb_id = DEF_SB_IGU_ID;
13919 sc->igu_base_sb = 0;
13921 sc->devinfo.int_block = INT_BLOCK_IGU;
13923 /* do not allow device reset during IGU info preocessing */
13924 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
13926 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
13928 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
13931 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n");
13933 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
13934 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
13935 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
13937 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
13942 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
13943 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n");
13944 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
13949 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
13950 BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n");
13951 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
13953 BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n");
13956 rc = bxe_get_igu_cam_info(sc);
13958 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
13966 * Get base FW non-default (fast path) status block ID. This value is
13967 * used to initialize the fw_sb_id saved on the fp/queue structure to
13968 * determine the id used by the FW.
13970 if (CHIP_IS_E1x(sc)) {
13971 sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
13974 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
13975 * the same queue are indicated on the same IGU SB). So we prefer
13976 * FW and IGU SBs to be the same value.
13978 sc->base_fw_ndsb = sc->igu_base_sb;
13981 BLOGD(sc, DBG_LOAD,
13982 "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n",
13983 sc->igu_dsb_id, sc->igu_base_sb,
13984 sc->igu_sb_cnt, sc->base_fw_ndsb);
13986 elink_phy_probe(&sc->link_params);
13992 bxe_link_settings_supported(struct bxe_softc *sc,
13993 uint32_t switch_cfg)
13995 uint32_t cfg_size = 0;
13997 uint8_t port = SC_PORT(sc);
13999 /* aggregation of supported attributes of all external phys */
14000 sc->port.supported[0] = 0;
14001 sc->port.supported[1] = 0;
14003 switch (sc->link_params.num_phys) {
14005 sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported;
14009 sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported;
14013 if (sc->link_params.multi_phy_config &
14014 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
14015 sc->port.supported[1] =
14016 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14017 sc->port.supported[0] =
14018 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14020 sc->port.supported[0] =
14021 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14022 sc->port.supported[1] =
14023 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14029 if (!(sc->port.supported[0] || sc->port.supported[1])) {
14030 BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n",
14032 dev_info.port_hw_config[port].external_phy_config),
14034 dev_info.port_hw_config[port].external_phy_config2));
14038 if (CHIP_IS_E3(sc))
14039 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
14041 switch (switch_cfg) {
14042 case ELINK_SWITCH_CFG_1G:
14043 sc->port.phy_addr =
14044 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
14046 case ELINK_SWITCH_CFG_10G:
14047 sc->port.phy_addr =
14048 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
14051 BLOGE(sc, "Invalid switch config in link_config=0x%08x\n",
14052 sc->port.link_config[0]);
14057 BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr);
14059 /* mask what we support according to speed_cap_mask per configuration */
14060 for (idx = 0; idx < cfg_size; idx++) {
14061 if (!(sc->link_params.speed_cap_mask[idx] &
14062 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
14063 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half;
14066 if (!(sc->link_params.speed_cap_mask[idx] &
14067 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
14068 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full;
14071 if (!(sc->link_params.speed_cap_mask[idx] &
14072 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
14073 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half;
14076 if (!(sc->link_params.speed_cap_mask[idx] &
14077 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
14078 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full;
14081 if (!(sc->link_params.speed_cap_mask[idx] &
14082 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
14083 sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full;
14086 if (!(sc->link_params.speed_cap_mask[idx] &
14087 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
14088 sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full;
14091 if (!(sc->link_params.speed_cap_mask[idx] &
14092 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
14093 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full;
14096 if (!(sc->link_params.speed_cap_mask[idx] &
14097 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
14098 sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full;
14102 BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n",
14103 sc->port.supported[0], sc->port.supported[1]);
14104 ELINK_DEBUG_P2(sc, "PHY supported 0=0x%08x 1=0x%08x\n",
14105 sc->port.supported[0], sc->port.supported[1]);
14109 bxe_link_settings_requested(struct bxe_softc *sc)
14111 uint32_t link_config;
14113 uint32_t cfg_size = 0;
14115 sc->port.advertising[0] = 0;
14116 sc->port.advertising[1] = 0;
14118 switch (sc->link_params.num_phys) {
14128 for (idx = 0; idx < cfg_size; idx++) {
14129 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
14130 link_config = sc->port.link_config[idx];
14132 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
14133 case PORT_FEATURE_LINK_SPEED_AUTO:
14134 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
14135 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14136 sc->port.advertising[idx] |= sc->port.supported[idx];
14137 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
14138 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
14139 sc->port.advertising[idx] |=
14140 (ELINK_SUPPORTED_100baseT_Half |
14141 ELINK_SUPPORTED_100baseT_Full);
14143 /* force 10G, no AN */
14144 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14145 sc->port.advertising[idx] |=
14146 (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
14151 case PORT_FEATURE_LINK_SPEED_10M_FULL:
14152 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) {
14153 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14154 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full |
14157 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14158 "speed_cap_mask=0x%08x\n",
14159 link_config, sc->link_params.speed_cap_mask[idx]);
14164 case PORT_FEATURE_LINK_SPEED_10M_HALF:
14165 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) {
14166 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14167 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14168 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half |
14170 ELINK_DEBUG_P1(sc, "driver requesting DUPLEX_HALF req_duplex = %x!\n",
14171 sc->link_params.req_duplex[idx]);
14173 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14174 "speed_cap_mask=0x%08x\n",
14175 link_config, sc->link_params.speed_cap_mask[idx]);
14180 case PORT_FEATURE_LINK_SPEED_100M_FULL:
14181 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) {
14182 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14183 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full |
14186 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14187 "speed_cap_mask=0x%08x\n",
14188 link_config, sc->link_params.speed_cap_mask[idx]);
14193 case PORT_FEATURE_LINK_SPEED_100M_HALF:
14194 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) {
14195 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14196 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14197 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half |
14200 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14201 "speed_cap_mask=0x%08x\n",
14202 link_config, sc->link_params.speed_cap_mask[idx]);
14207 case PORT_FEATURE_LINK_SPEED_1G:
14208 if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) {
14209 sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000;
14210 sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full |
14213 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14214 "speed_cap_mask=0x%08x\n",
14215 link_config, sc->link_params.speed_cap_mask[idx]);
14220 case PORT_FEATURE_LINK_SPEED_2_5G:
14221 if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) {
14222 sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500;
14223 sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full |
14226 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14227 "speed_cap_mask=0x%08x\n",
14228 link_config, sc->link_params.speed_cap_mask[idx]);
14233 case PORT_FEATURE_LINK_SPEED_10G_CX4:
14234 if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) {
14235 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14236 sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full |
14239 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14240 "speed_cap_mask=0x%08x\n",
14241 link_config, sc->link_params.speed_cap_mask[idx]);
14246 case PORT_FEATURE_LINK_SPEED_20G:
14247 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
14251 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14252 "speed_cap_mask=0x%08x\n",
14253 link_config, sc->link_params.speed_cap_mask[idx]);
14254 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14255 sc->port.advertising[idx] = sc->port.supported[idx];
14259 sc->link_params.req_flow_ctrl[idx] =
14260 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
14262 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
14263 if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
14264 sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE;
14266 bxe_set_requested_fc(sc);
14270 BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d "
14271 "req_flow_ctrl=0x%x advertising=0x%x\n",
14272 sc->link_params.req_line_speed[idx],
14273 sc->link_params.req_duplex[idx],
14274 sc->link_params.req_flow_ctrl[idx],
14275 sc->port.advertising[idx]);
14276 ELINK_DEBUG_P3(sc, "req_line_speed=%d req_duplex=%d "
14277 "advertising=0x%x\n",
14278 sc->link_params.req_line_speed[idx],
14279 sc->link_params.req_duplex[idx],
14280 sc->port.advertising[idx]);
14285 bxe_get_phy_info(struct bxe_softc *sc)
14287 uint8_t port = SC_PORT(sc);
14288 uint32_t config = sc->port.config;
14291 /* shmem data already read in bxe_get_shmem_info() */
14293 ELINK_DEBUG_P3(sc, "lane_config=0x%08x speed_cap_mask0=0x%08x "
14294 "link_config0=0x%08x\n",
14295 sc->link_params.lane_config,
14296 sc->link_params.speed_cap_mask[0],
14297 sc->port.link_config[0]);
14300 bxe_link_settings_supported(sc, sc->link_params.switch_cfg);
14301 bxe_link_settings_requested(sc);
14303 if (sc->autogreeen == AUTO_GREEN_FORCE_ON) {
14304 sc->link_params.feature_config_flags |=
14305 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14306 } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) {
14307 sc->link_params.feature_config_flags &=
14308 ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14309 } else if (config & PORT_FEAT_CFG_AUTOGREEEN_ENABLED) {
14310 sc->link_params.feature_config_flags |=
14311 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14314 /* configure link feature according to nvram value */
14316 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) &
14317 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
14318 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
14319 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
14320 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
14321 ELINK_EEE_MODE_ENABLE_LPI |
14322 ELINK_EEE_MODE_OUTPUT_TIME);
14324 sc->link_params.eee_mode = 0;
14327 /* get the media type */
14328 bxe_media_detect(sc);
14329 ELINK_DEBUG_P1(sc, "detected media type\n", sc->media);
14333 bxe_get_params(struct bxe_softc *sc)
14335 /* get user tunable params */
14336 bxe_get_tunable_params(sc);
14338 /* select the RX and TX ring sizes */
14339 sc->tx_ring_size = TX_BD_USABLE;
14340 sc->rx_ring_size = RX_BD_USABLE;
14342 /* XXX disable WoL */
14347 bxe_set_modes_bitmap(struct bxe_softc *sc)
14349 uint32_t flags = 0;
14351 if (CHIP_REV_IS_FPGA(sc)) {
14352 SET_FLAGS(flags, MODE_FPGA);
14353 } else if (CHIP_REV_IS_EMUL(sc)) {
14354 SET_FLAGS(flags, MODE_EMUL);
14356 SET_FLAGS(flags, MODE_ASIC);
14359 if (CHIP_IS_MODE_4_PORT(sc)) {
14360 SET_FLAGS(flags, MODE_PORT4);
14362 SET_FLAGS(flags, MODE_PORT2);
14365 if (CHIP_IS_E2(sc)) {
14366 SET_FLAGS(flags, MODE_E2);
14367 } else if (CHIP_IS_E3(sc)) {
14368 SET_FLAGS(flags, MODE_E3);
14369 if (CHIP_REV(sc) == CHIP_REV_Ax) {
14370 SET_FLAGS(flags, MODE_E3_A0);
14371 } else /*if (CHIP_REV(sc) == CHIP_REV_Bx)*/ {
14372 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
14377 SET_FLAGS(flags, MODE_MF);
14378 switch (sc->devinfo.mf_info.mf_mode) {
14379 case MULTI_FUNCTION_SD:
14380 SET_FLAGS(flags, MODE_MF_SD);
14382 case MULTI_FUNCTION_SI:
14383 SET_FLAGS(flags, MODE_MF_SI);
14385 case MULTI_FUNCTION_AFEX:
14386 SET_FLAGS(flags, MODE_MF_AFEX);
14390 SET_FLAGS(flags, MODE_SF);
14393 #if defined(__LITTLE_ENDIAN)
14394 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
14395 #else /* __BIG_ENDIAN */
14396 SET_FLAGS(flags, MODE_BIG_ENDIAN);
14399 INIT_MODE_FLAGS(sc) = flags;
14403 bxe_alloc_hsi_mem(struct bxe_softc *sc)
14405 struct bxe_fastpath *fp;
14406 bus_addr_t busaddr;
14407 int max_agg_queues;
14409 bus_size_t max_size;
14410 bus_size_t max_seg_size;
14415 /* XXX zero out all vars here and call bxe_alloc_hsi_mem on error */
14417 /* allocate the parent bus DMA tag */
14418 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */
14420 0, /* boundary limit */
14421 BUS_SPACE_MAXADDR, /* restricted low */
14422 BUS_SPACE_MAXADDR, /* restricted hi */
14423 NULL, /* addr filter() */
14424 NULL, /* addr filter() arg */
14425 BUS_SPACE_MAXSIZE_32BIT, /* max map size */
14426 BUS_SPACE_UNRESTRICTED, /* num discontinuous */
14427 BUS_SPACE_MAXSIZE_32BIT, /* max seg size */
14430 NULL, /* lock() arg */
14431 &sc->parent_dma_tag); /* returned dma tag */
14433 BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc);
14437 /************************/
14438 /* DEFAULT STATUS BLOCK */
14439 /************************/
14441 if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block),
14442 &sc->def_sb_dma, "default status block") != 0) {
14444 bus_dma_tag_destroy(sc->parent_dma_tag);
14448 sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
14454 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14455 &sc->eq_dma, "event queue") != 0) {
14457 bxe_dma_free(sc, &sc->def_sb_dma);
14459 bus_dma_tag_destroy(sc->parent_dma_tag);
14463 sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr;
14469 if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath),
14470 &sc->sp_dma, "slow path") != 0) {
14472 bxe_dma_free(sc, &sc->eq_dma);
14474 bxe_dma_free(sc, &sc->def_sb_dma);
14476 bus_dma_tag_destroy(sc->parent_dma_tag);
14480 sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr;
14482 /*******************/
14483 /* SLOW PATH QUEUE */
14484 /*******************/
14486 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14487 &sc->spq_dma, "slow path queue") != 0) {
14489 bxe_dma_free(sc, &sc->sp_dma);
14491 bxe_dma_free(sc, &sc->eq_dma);
14493 bxe_dma_free(sc, &sc->def_sb_dma);
14495 bus_dma_tag_destroy(sc->parent_dma_tag);
14499 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
14501 /***************************/
14502 /* FW DECOMPRESSION BUFFER */
14503 /***************************/
14505 if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
14506 "fw decompression buffer") != 0) {
14508 bxe_dma_free(sc, &sc->spq_dma);
14510 bxe_dma_free(sc, &sc->sp_dma);
14512 bxe_dma_free(sc, &sc->eq_dma);
14514 bxe_dma_free(sc, &sc->def_sb_dma);
14516 bus_dma_tag_destroy(sc->parent_dma_tag);
14520 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
14523 malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) {
14525 bxe_dma_free(sc, &sc->gz_buf_dma);
14527 bxe_dma_free(sc, &sc->spq_dma);
14529 bxe_dma_free(sc, &sc->sp_dma);
14531 bxe_dma_free(sc, &sc->eq_dma);
14533 bxe_dma_free(sc, &sc->def_sb_dma);
14535 bus_dma_tag_destroy(sc->parent_dma_tag);
14543 /* allocate DMA memory for each fastpath structure */
14544 for (i = 0; i < sc->num_queues; i++) {
14549 /*******************/
14550 /* FP STATUS BLOCK */
14551 /*******************/
14553 snprintf(buf, sizeof(buf), "fp %d status block", i);
14554 if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block),
14555 &fp->sb_dma, buf) != 0) {
14556 /* XXX unwind and free previous fastpath allocations */
14557 BLOGE(sc, "Failed to alloc %s\n", buf);
14560 if (CHIP_IS_E2E3(sc)) {
14561 fp->status_block.e2_sb =
14562 (struct host_hc_status_block_e2 *)fp->sb_dma.vaddr;
14564 fp->status_block.e1x_sb =
14565 (struct host_hc_status_block_e1x *)fp->sb_dma.vaddr;
14569 /******************/
14570 /* FP TX BD CHAIN */
14571 /******************/
14573 snprintf(buf, sizeof(buf), "fp %d tx bd chain", i);
14574 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES),
14575 &fp->tx_dma, buf) != 0) {
14576 /* XXX unwind and free previous fastpath allocations */
14577 BLOGE(sc, "Failed to alloc %s\n", buf);
14580 fp->tx_chain = (union eth_tx_bd_types *)fp->tx_dma.vaddr;
14583 /* link together the tx bd chain pages */
14584 for (j = 1; j <= TX_BD_NUM_PAGES; j++) {
14585 /* index into the tx bd chain array to last entry per page */
14586 struct eth_tx_next_bd *tx_next_bd =
14587 &fp->tx_chain[TX_BD_TOTAL_PER_PAGE * j - 1].next_bd;
14588 /* point to the next page and wrap from last page */
14589 busaddr = (fp->tx_dma.paddr +
14590 (BCM_PAGE_SIZE * (j % TX_BD_NUM_PAGES)));
14591 tx_next_bd->addr_hi = htole32(U64_HI(busaddr));
14592 tx_next_bd->addr_lo = htole32(U64_LO(busaddr));
14595 /******************/
14596 /* FP RX BD CHAIN */
14597 /******************/
14599 snprintf(buf, sizeof(buf), "fp %d rx bd chain", i);
14600 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES),
14601 &fp->rx_dma, buf) != 0) {
14602 /* XXX unwind and free previous fastpath allocations */
14603 BLOGE(sc, "Failed to alloc %s\n", buf);
14606 fp->rx_chain = (struct eth_rx_bd *)fp->rx_dma.vaddr;
14609 /* link together the rx bd chain pages */
14610 for (j = 1; j <= RX_BD_NUM_PAGES; j++) {
14611 /* index into the rx bd chain array to last entry per page */
14612 struct eth_rx_bd *rx_bd =
14613 &fp->rx_chain[RX_BD_TOTAL_PER_PAGE * j - 2];
14614 /* point to the next page and wrap from last page */
14615 busaddr = (fp->rx_dma.paddr +
14616 (BCM_PAGE_SIZE * (j % RX_BD_NUM_PAGES)));
14617 rx_bd->addr_hi = htole32(U64_HI(busaddr));
14618 rx_bd->addr_lo = htole32(U64_LO(busaddr));
14621 /*******************/
14622 /* FP RX RCQ CHAIN */
14623 /*******************/
14625 snprintf(buf, sizeof(buf), "fp %d rcq chain", i);
14626 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES),
14627 &fp->rcq_dma, buf) != 0) {
14628 /* XXX unwind and free previous fastpath allocations */
14629 BLOGE(sc, "Failed to alloc %s\n", buf);
14632 fp->rcq_chain = (union eth_rx_cqe *)fp->rcq_dma.vaddr;
14635 /* link together the rcq chain pages */
14636 for (j = 1; j <= RCQ_NUM_PAGES; j++) {
14637 /* index into the rcq chain array to last entry per page */
14638 struct eth_rx_cqe_next_page *rx_cqe_next =
14639 (struct eth_rx_cqe_next_page *)
14640 &fp->rcq_chain[RCQ_TOTAL_PER_PAGE * j - 1];
14641 /* point to the next page and wrap from last page */
14642 busaddr = (fp->rcq_dma.paddr +
14643 (BCM_PAGE_SIZE * (j % RCQ_NUM_PAGES)));
14644 rx_cqe_next->addr_hi = htole32(U64_HI(busaddr));
14645 rx_cqe_next->addr_lo = htole32(U64_LO(busaddr));
14648 /*******************/
14649 /* FP RX SGE CHAIN */
14650 /*******************/
14652 snprintf(buf, sizeof(buf), "fp %d sge chain", i);
14653 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES),
14654 &fp->rx_sge_dma, buf) != 0) {
14655 /* XXX unwind and free previous fastpath allocations */
14656 BLOGE(sc, "Failed to alloc %s\n", buf);
14659 fp->rx_sge_chain = (struct eth_rx_sge *)fp->rx_sge_dma.vaddr;
14662 /* link together the sge chain pages */
14663 for (j = 1; j <= RX_SGE_NUM_PAGES; j++) {
14664 /* index into the rcq chain array to last entry per page */
14665 struct eth_rx_sge *rx_sge =
14666 &fp->rx_sge_chain[RX_SGE_TOTAL_PER_PAGE * j - 2];
14667 /* point to the next page and wrap from last page */
14668 busaddr = (fp->rx_sge_dma.paddr +
14669 (BCM_PAGE_SIZE * (j % RX_SGE_NUM_PAGES)));
14670 rx_sge->addr_hi = htole32(U64_HI(busaddr));
14671 rx_sge->addr_lo = htole32(U64_LO(busaddr));
14674 /***********************/
14675 /* FP TX MBUF DMA MAPS */
14676 /***********************/
14678 /* set required sizes before mapping to conserve resources */
14679 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) {
14680 max_size = BXE_TSO_MAX_SIZE;
14681 max_segments = BXE_TSO_MAX_SEGMENTS;
14682 max_seg_size = BXE_TSO_MAX_SEG_SIZE;
14684 max_size = (MCLBYTES * BXE_MAX_SEGMENTS);
14685 max_segments = BXE_MAX_SEGMENTS;
14686 max_seg_size = MCLBYTES;
14689 /* create a dma tag for the tx mbufs */
14690 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14692 0, /* boundary limit */
14693 BUS_SPACE_MAXADDR, /* restricted low */
14694 BUS_SPACE_MAXADDR, /* restricted hi */
14695 NULL, /* addr filter() */
14696 NULL, /* addr filter() arg */
14697 max_size, /* max map size */
14698 max_segments, /* num discontinuous */
14699 max_seg_size, /* max seg size */
14702 NULL, /* lock() arg */
14703 &fp->tx_mbuf_tag); /* returned dma tag */
14705 /* XXX unwind and free previous fastpath allocations */
14706 BLOGE(sc, "Failed to create dma tag for "
14707 "'fp %d tx mbufs' (%d)\n", i, rc);
14711 /* create dma maps for each of the tx mbuf clusters */
14712 for (j = 0; j < TX_BD_TOTAL; j++) {
14713 if (bus_dmamap_create(fp->tx_mbuf_tag,
14715 &fp->tx_mbuf_chain[j].m_map)) {
14716 /* XXX unwind and free previous fastpath allocations */
14717 BLOGE(sc, "Failed to create dma map for "
14718 "'fp %d tx mbuf %d' (%d)\n", i, j, rc);
14723 /***********************/
14724 /* FP RX MBUF DMA MAPS */
14725 /***********************/
14727 /* create a dma tag for the rx mbufs */
14728 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14730 0, /* boundary limit */
14731 BUS_SPACE_MAXADDR, /* restricted low */
14732 BUS_SPACE_MAXADDR, /* restricted hi */
14733 NULL, /* addr filter() */
14734 NULL, /* addr filter() arg */
14735 MJUM9BYTES, /* max map size */
14736 1, /* num discontinuous */
14737 MJUM9BYTES, /* max seg size */
14740 NULL, /* lock() arg */
14741 &fp->rx_mbuf_tag); /* returned dma tag */
14743 /* XXX unwind and free previous fastpath allocations */
14744 BLOGE(sc, "Failed to create dma tag for "
14745 "'fp %d rx mbufs' (%d)\n", i, rc);
14749 /* create dma maps for each of the rx mbuf clusters */
14750 for (j = 0; j < RX_BD_TOTAL; j++) {
14751 if (bus_dmamap_create(fp->rx_mbuf_tag,
14753 &fp->rx_mbuf_chain[j].m_map)) {
14754 /* XXX unwind and free previous fastpath allocations */
14755 BLOGE(sc, "Failed to create dma map for "
14756 "'fp %d rx mbuf %d' (%d)\n", i, j, rc);
14761 /* create dma map for the spare rx mbuf cluster */
14762 if (bus_dmamap_create(fp->rx_mbuf_tag,
14764 &fp->rx_mbuf_spare_map)) {
14765 /* XXX unwind and free previous fastpath allocations */
14766 BLOGE(sc, "Failed to create dma map for "
14767 "'fp %d spare rx mbuf' (%d)\n", i, rc);
14771 /***************************/
14772 /* FP RX SGE MBUF DMA MAPS */
14773 /***************************/
14775 /* create a dma tag for the rx sge mbufs */
14776 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14778 0, /* boundary limit */
14779 BUS_SPACE_MAXADDR, /* restricted low */
14780 BUS_SPACE_MAXADDR, /* restricted hi */
14781 NULL, /* addr filter() */
14782 NULL, /* addr filter() arg */
14783 BCM_PAGE_SIZE, /* max map size */
14784 1, /* num discontinuous */
14785 BCM_PAGE_SIZE, /* max seg size */
14788 NULL, /* lock() arg */
14789 &fp->rx_sge_mbuf_tag); /* returned dma tag */
14791 /* XXX unwind and free previous fastpath allocations */
14792 BLOGE(sc, "Failed to create dma tag for "
14793 "'fp %d rx sge mbufs' (%d)\n", i, rc);
14797 /* create dma maps for the rx sge mbuf clusters */
14798 for (j = 0; j < RX_SGE_TOTAL; j++) {
14799 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
14801 &fp->rx_sge_mbuf_chain[j].m_map)) {
14802 /* XXX unwind and free previous fastpath allocations */
14803 BLOGE(sc, "Failed to create dma map for "
14804 "'fp %d rx sge mbuf %d' (%d)\n", i, j, rc);
14809 /* create dma map for the spare rx sge mbuf cluster */
14810 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
14812 &fp->rx_sge_mbuf_spare_map)) {
14813 /* XXX unwind and free previous fastpath allocations */
14814 BLOGE(sc, "Failed to create dma map for "
14815 "'fp %d spare rx sge mbuf' (%d)\n", i, rc);
14819 /***************************/
14820 /* FP RX TPA MBUF DMA MAPS */
14821 /***************************/
14823 /* create dma maps for the rx tpa mbuf clusters */
14824 max_agg_queues = MAX_AGG_QS(sc);
14826 for (j = 0; j < max_agg_queues; j++) {
14827 if (bus_dmamap_create(fp->rx_mbuf_tag,
14829 &fp->rx_tpa_info[j].bd.m_map)) {
14830 /* XXX unwind and free previous fastpath allocations */
14831 BLOGE(sc, "Failed to create dma map for "
14832 "'fp %d rx tpa mbuf %d' (%d)\n", i, j, rc);
14837 /* create dma map for the spare rx tpa mbuf cluster */
14838 if (bus_dmamap_create(fp->rx_mbuf_tag,
14840 &fp->rx_tpa_info_mbuf_spare_map)) {
14841 /* XXX unwind and free previous fastpath allocations */
14842 BLOGE(sc, "Failed to create dma map for "
14843 "'fp %d spare rx tpa mbuf' (%d)\n", i, rc);
14847 bxe_init_sge_ring_bit_mask(fp);
14854 bxe_free_hsi_mem(struct bxe_softc *sc)
14856 struct bxe_fastpath *fp;
14857 int max_agg_queues;
14860 if (sc->parent_dma_tag == NULL) {
14861 return; /* assume nothing was allocated */
14864 for (i = 0; i < sc->num_queues; i++) {
14867 /*******************/
14868 /* FP STATUS BLOCK */
14869 /*******************/
14871 bxe_dma_free(sc, &fp->sb_dma);
14872 memset(&fp->status_block, 0, sizeof(fp->status_block));
14874 /******************/
14875 /* FP TX BD CHAIN */
14876 /******************/
14878 bxe_dma_free(sc, &fp->tx_dma);
14879 fp->tx_chain = NULL;
14881 /******************/
14882 /* FP RX BD CHAIN */
14883 /******************/
14885 bxe_dma_free(sc, &fp->rx_dma);
14886 fp->rx_chain = NULL;
14888 /*******************/
14889 /* FP RX RCQ CHAIN */
14890 /*******************/
14892 bxe_dma_free(sc, &fp->rcq_dma);
14893 fp->rcq_chain = NULL;
14895 /*******************/
14896 /* FP RX SGE CHAIN */
14897 /*******************/
14899 bxe_dma_free(sc, &fp->rx_sge_dma);
14900 fp->rx_sge_chain = NULL;
14902 /***********************/
14903 /* FP TX MBUF DMA MAPS */
14904 /***********************/
14906 if (fp->tx_mbuf_tag != NULL) {
14907 for (j = 0; j < TX_BD_TOTAL; j++) {
14908 if (fp->tx_mbuf_chain[j].m_map != NULL) {
14909 bus_dmamap_unload(fp->tx_mbuf_tag,
14910 fp->tx_mbuf_chain[j].m_map);
14911 bus_dmamap_destroy(fp->tx_mbuf_tag,
14912 fp->tx_mbuf_chain[j].m_map);
14916 bus_dma_tag_destroy(fp->tx_mbuf_tag);
14917 fp->tx_mbuf_tag = NULL;
14920 /***********************/
14921 /* FP RX MBUF DMA MAPS */
14922 /***********************/
14924 if (fp->rx_mbuf_tag != NULL) {
14925 for (j = 0; j < RX_BD_TOTAL; j++) {
14926 if (fp->rx_mbuf_chain[j].m_map != NULL) {
14927 bus_dmamap_unload(fp->rx_mbuf_tag,
14928 fp->rx_mbuf_chain[j].m_map);
14929 bus_dmamap_destroy(fp->rx_mbuf_tag,
14930 fp->rx_mbuf_chain[j].m_map);
14934 if (fp->rx_mbuf_spare_map != NULL) {
14935 bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
14936 bus_dmamap_destroy(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
14939 /***************************/
14940 /* FP RX TPA MBUF DMA MAPS */
14941 /***************************/
14943 max_agg_queues = MAX_AGG_QS(sc);
14945 for (j = 0; j < max_agg_queues; j++) {
14946 if (fp->rx_tpa_info[j].bd.m_map != NULL) {
14947 bus_dmamap_unload(fp->rx_mbuf_tag,
14948 fp->rx_tpa_info[j].bd.m_map);
14949 bus_dmamap_destroy(fp->rx_mbuf_tag,
14950 fp->rx_tpa_info[j].bd.m_map);
14954 if (fp->rx_tpa_info_mbuf_spare_map != NULL) {
14955 bus_dmamap_unload(fp->rx_mbuf_tag,
14956 fp->rx_tpa_info_mbuf_spare_map);
14957 bus_dmamap_destroy(fp->rx_mbuf_tag,
14958 fp->rx_tpa_info_mbuf_spare_map);
14961 bus_dma_tag_destroy(fp->rx_mbuf_tag);
14962 fp->rx_mbuf_tag = NULL;
14965 /***************************/
14966 /* FP RX SGE MBUF DMA MAPS */
14967 /***************************/
14969 if (fp->rx_sge_mbuf_tag != NULL) {
14970 for (j = 0; j < RX_SGE_TOTAL; j++) {
14971 if (fp->rx_sge_mbuf_chain[j].m_map != NULL) {
14972 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
14973 fp->rx_sge_mbuf_chain[j].m_map);
14974 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
14975 fp->rx_sge_mbuf_chain[j].m_map);
14979 if (fp->rx_sge_mbuf_spare_map != NULL) {
14980 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
14981 fp->rx_sge_mbuf_spare_map);
14982 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
14983 fp->rx_sge_mbuf_spare_map);
14986 bus_dma_tag_destroy(fp->rx_sge_mbuf_tag);
14987 fp->rx_sge_mbuf_tag = NULL;
14991 /***************************/
14992 /* FW DECOMPRESSION BUFFER */
14993 /***************************/
14995 bxe_dma_free(sc, &sc->gz_buf_dma);
14997 free(sc->gz_strm, M_DEVBUF);
14998 sc->gz_strm = NULL;
15000 /*******************/
15001 /* SLOW PATH QUEUE */
15002 /*******************/
15004 bxe_dma_free(sc, &sc->spq_dma);
15011 bxe_dma_free(sc, &sc->sp_dma);
15018 bxe_dma_free(sc, &sc->eq_dma);
15021 /************************/
15022 /* DEFAULT STATUS BLOCK */
15023 /************************/
15025 bxe_dma_free(sc, &sc->def_sb_dma);
15028 bus_dma_tag_destroy(sc->parent_dma_tag);
15029 sc->parent_dma_tag = NULL;
15033 * Previous driver DMAE transaction may have occurred when pre-boot stage
15034 * ended and boot began. This would invalidate the addresses of the
15035 * transaction, resulting in was-error bit set in the PCI causing all
15036 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
15037 * the interrupt which detected this from the pglueb and the was-done bit
15040 bxe_prev_interrupted_dmae(struct bxe_softc *sc)
15044 if (!CHIP_IS_E1x(sc)) {
15045 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
15046 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
15047 BLOGD(sc, DBG_LOAD,
15048 "Clearing 'was-error' bit that was set in pglueb");
15049 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc));
15055 bxe_prev_mcp_done(struct bxe_softc *sc)
15057 uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
15058 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
15060 BLOGE(sc, "MCP response failure, aborting\n");
15067 static struct bxe_prev_list_node *
15068 bxe_prev_path_get_entry(struct bxe_softc *sc)
15070 struct bxe_prev_list_node *tmp;
15072 LIST_FOREACH(tmp, &bxe_prev_list, node) {
15073 if ((sc->pcie_bus == tmp->bus) &&
15074 (sc->pcie_device == tmp->slot) &&
15075 (SC_PATH(sc) == tmp->path)) {
15084 bxe_prev_is_path_marked(struct bxe_softc *sc)
15086 struct bxe_prev_list_node *tmp;
15089 mtx_lock(&bxe_prev_mtx);
15091 tmp = bxe_prev_path_get_entry(sc);
15094 BLOGD(sc, DBG_LOAD,
15095 "Path %d/%d/%d was marked by AER\n",
15096 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15099 BLOGD(sc, DBG_LOAD,
15100 "Path %d/%d/%d was already cleaned from previous drivers\n",
15101 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15105 mtx_unlock(&bxe_prev_mtx);
15111 bxe_prev_mark_path(struct bxe_softc *sc,
15112 uint8_t after_undi)
15114 struct bxe_prev_list_node *tmp;
15116 mtx_lock(&bxe_prev_mtx);
15118 /* Check whether the entry for this path already exists */
15119 tmp = bxe_prev_path_get_entry(sc);
15122 BLOGD(sc, DBG_LOAD,
15123 "Re-marking AER in path %d/%d/%d\n",
15124 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15126 BLOGD(sc, DBG_LOAD,
15127 "Removing AER indication from path %d/%d/%d\n",
15128 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15132 mtx_unlock(&bxe_prev_mtx);
15136 mtx_unlock(&bxe_prev_mtx);
15138 /* Create an entry for this path and add it */
15139 tmp = malloc(sizeof(struct bxe_prev_list_node), M_DEVBUF,
15140 (M_NOWAIT | M_ZERO));
15142 BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n");
15146 tmp->bus = sc->pcie_bus;
15147 tmp->slot = sc->pcie_device;
15148 tmp->path = SC_PATH(sc);
15150 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
15152 mtx_lock(&bxe_prev_mtx);
15154 BLOGD(sc, DBG_LOAD,
15155 "Marked path %d/%d/%d - finished previous unload\n",
15156 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15157 LIST_INSERT_HEAD(&bxe_prev_list, tmp, node);
15159 mtx_unlock(&bxe_prev_mtx);
15165 bxe_do_flr(struct bxe_softc *sc)
15169 /* only E2 and onwards support FLR */
15170 if (CHIP_IS_E1x(sc)) {
15171 BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n");
15175 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
15176 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
15177 BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n",
15178 sc->devinfo.bc_ver);
15182 /* Wait for Transaction Pending bit clean */
15183 for (i = 0; i < 4; i++) {
15185 DELAY(((1 << (i - 1)) * 100) * 1000);
15188 if (!bxe_is_pcie_pending(sc)) {
15193 BLOGE(sc, "PCIE transaction is not cleared, "
15194 "proceeding with reset anyway\n");
15198 BLOGD(sc, DBG_LOAD, "Initiating FLR\n");
15199 bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
15204 struct bxe_mac_vals {
15205 uint32_t xmac_addr;
15207 uint32_t emac_addr;
15209 uint32_t umac_addr;
15211 uint32_t bmac_addr;
15212 uint32_t bmac_val[2];
15216 bxe_prev_unload_close_mac(struct bxe_softc *sc,
15217 struct bxe_mac_vals *vals)
15219 uint32_t val, base_addr, offset, mask, reset_reg;
15220 uint8_t mac_stopped = FALSE;
15221 uint8_t port = SC_PORT(sc);
15222 uint32_t wb_data[2];
15224 /* reset addresses as they also mark which values were changed */
15225 vals->bmac_addr = 0;
15226 vals->umac_addr = 0;
15227 vals->xmac_addr = 0;
15228 vals->emac_addr = 0;
15230 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
15232 if (!CHIP_IS_E3(sc)) {
15233 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
15234 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
15235 if ((mask & reset_reg) && val) {
15236 BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n");
15237 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
15238 : NIG_REG_INGRESS_BMAC0_MEM;
15239 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
15240 : BIGMAC_REGISTER_BMAC_CONTROL;
15243 * use rd/wr since we cannot use dmae. This is safe
15244 * since MCP won't access the bus due to the request
15245 * to unload, and no function on the path can be
15246 * loaded at this time.
15248 wb_data[0] = REG_RD(sc, base_addr + offset);
15249 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
15250 vals->bmac_addr = base_addr + offset;
15251 vals->bmac_val[0] = wb_data[0];
15252 vals->bmac_val[1] = wb_data[1];
15253 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
15254 REG_WR(sc, vals->bmac_addr, wb_data[0]);
15255 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
15258 BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n");
15259 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4;
15260 vals->emac_val = REG_RD(sc, vals->emac_addr);
15261 REG_WR(sc, vals->emac_addr, 0);
15262 mac_stopped = TRUE;
15264 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
15265 BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n");
15266 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
15267 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
15268 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1));
15269 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1));
15270 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
15271 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
15272 REG_WR(sc, vals->xmac_addr, 0);
15273 mac_stopped = TRUE;
15276 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
15277 if (mask & reset_reg) {
15278 BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n");
15279 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
15280 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
15281 vals->umac_val = REG_RD(sc, vals->umac_addr);
15282 REG_WR(sc, vals->umac_addr, 0);
15283 mac_stopped = TRUE;
15292 #define BXE_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
15293 #define BXE_PREV_UNDI_RCQ(val) ((val) & 0xffff)
15294 #define BXE_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
15295 #define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
15298 bxe_prev_unload_undi_inc(struct bxe_softc *sc,
15303 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port));
15305 rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc;
15306 bd = BXE_PREV_UNDI_BD(tmp_reg) + inc;
15308 tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd);
15309 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg);
15311 BLOGD(sc, DBG_LOAD,
15312 "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
15317 bxe_prev_unload_common(struct bxe_softc *sc)
15319 uint32_t reset_reg, tmp_reg = 0, rc;
15320 uint8_t prev_undi = FALSE;
15321 struct bxe_mac_vals mac_vals;
15322 uint32_t timer_count = 1000;
15326 * It is possible a previous function received 'common' answer,
15327 * but hasn't loaded yet, therefore creating a scenario of
15328 * multiple functions receiving 'common' on the same path.
15330 BLOGD(sc, DBG_LOAD, "Common unload Flow\n");
15332 memset(&mac_vals, 0, sizeof(mac_vals));
15334 if (bxe_prev_is_path_marked(sc)) {
15335 return (bxe_prev_mcp_done(sc));
15338 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
15340 /* Reset should be performed after BRB is emptied */
15341 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
15342 /* Close the MAC Rx to prevent BRB from filling up */
15343 bxe_prev_unload_close_mac(sc, &mac_vals);
15345 /* close LLH filters towards the BRB */
15346 elink_set_rx_filter(&sc->link_params, 0);
15349 * Check if the UNDI driver was previously loaded.
15350 * UNDI driver initializes CID offset for normal bell to 0x7
15352 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
15353 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
15354 if (tmp_reg == 0x7) {
15355 BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n");
15357 /* clear the UNDI indication */
15358 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
15359 /* clear possible idle check errors */
15360 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
15364 /* wait until BRB is empty */
15365 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15366 while (timer_count) {
15367 prev_brb = tmp_reg;
15369 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15374 BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg);
15376 /* reset timer as long as BRB actually gets emptied */
15377 if (prev_brb > tmp_reg) {
15378 timer_count = 1000;
15383 /* If UNDI resides in memory, manually increment it */
15385 bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
15391 if (!timer_count) {
15392 BLOGE(sc, "Failed to empty BRB\n");
15396 /* No packets are in the pipeline, path is ready for reset */
15397 bxe_reset_common(sc);
15399 if (mac_vals.xmac_addr) {
15400 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
15402 if (mac_vals.umac_addr) {
15403 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
15405 if (mac_vals.emac_addr) {
15406 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
15408 if (mac_vals.bmac_addr) {
15409 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
15410 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
15413 rc = bxe_prev_mark_path(sc, prev_undi);
15415 bxe_prev_mcp_done(sc);
15419 return (bxe_prev_mcp_done(sc));
15423 bxe_prev_unload_uncommon(struct bxe_softc *sc)
15427 BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n");
15429 /* Test if previous unload process was already finished for this path */
15430 if (bxe_prev_is_path_marked(sc)) {
15431 return (bxe_prev_mcp_done(sc));
15434 BLOGD(sc, DBG_LOAD, "Path is unmarked\n");
15437 * If function has FLR capabilities, and existing FW version matches
15438 * the one required, then FLR will be sufficient to clean any residue
15439 * left by previous driver
15441 rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
15443 /* fw version is good */
15444 BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n");
15445 rc = bxe_do_flr(sc);
15449 /* FLR was performed */
15450 BLOGD(sc, DBG_LOAD, "FLR successful\n");
15454 BLOGD(sc, DBG_LOAD, "Could not FLR\n");
15456 /* Close the MCP request, return failure*/
15457 rc = bxe_prev_mcp_done(sc);
15459 rc = BXE_PREV_WAIT_NEEDED;
15466 bxe_prev_unload(struct bxe_softc *sc)
15468 int time_counter = 10;
15469 uint32_t fw, hw_lock_reg, hw_lock_val;
15473 * Clear HW from errors which may have resulted from an interrupted
15474 * DMAE transaction.
15476 bxe_prev_interrupted_dmae(sc);
15478 /* Release previously held locks */
15480 (SC_FUNC(sc) <= 5) ?
15481 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
15482 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
15484 hw_lock_val = (REG_RD(sc, hw_lock_reg));
15486 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
15487 BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n");
15488 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
15489 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
15491 BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n");
15492 REG_WR(sc, hw_lock_reg, 0xffffffff);
15494 BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n");
15497 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
15498 BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n");
15499 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
15503 /* Lock MCP using an unload request */
15504 fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
15506 BLOGE(sc, "MCP response failure, aborting\n");
15511 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
15512 rc = bxe_prev_unload_common(sc);
15516 /* non-common reply from MCP night require looping */
15517 rc = bxe_prev_unload_uncommon(sc);
15518 if (rc != BXE_PREV_WAIT_NEEDED) {
15523 } while (--time_counter);
15525 if (!time_counter || rc) {
15526 BLOGE(sc, "Failed to unload previous driver!"
15527 " time_counter %d rc %d\n", time_counter, rc);
15535 bxe_dcbx_set_state(struct bxe_softc *sc,
15537 uint32_t dcbx_enabled)
15539 if (!CHIP_IS_E1x(sc)) {
15540 sc->dcb_state = dcb_on;
15541 sc->dcbx_enabled = dcbx_enabled;
15543 sc->dcb_state = FALSE;
15544 sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID;
15546 BLOGD(sc, DBG_LOAD,
15547 "DCB state [%s:%s]\n",
15548 dcb_on ? "ON" : "OFF",
15549 (dcbx_enabled == BXE_DCBX_ENABLED_OFF) ? "user-mode" :
15550 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static" :
15551 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_ON) ?
15552 "on-chip with negotiation" : "invalid");
15555 /* must be called after sriov-enable */
15557 bxe_set_qm_cid_count(struct bxe_softc *sc)
15559 int cid_count = BXE_L2_MAX_CID(sc);
15561 if (IS_SRIOV(sc)) {
15562 cid_count += BXE_VF_CIDS;
15565 if (CNIC_SUPPORT(sc)) {
15566 cid_count += CNIC_CID_MAX;
15569 return (roundup(cid_count, QM_CID_ROUND));
15573 bxe_init_multi_cos(struct bxe_softc *sc)
15577 uint32_t pri_map = 0; /* XXX change to user config */
15579 for (pri = 0; pri < BXE_MAX_PRIORITY; pri++) {
15580 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
15581 if (cos < sc->max_cos) {
15582 sc->prio_to_cos[pri] = cos;
15584 BLOGW(sc, "Invalid COS %d for priority %d "
15585 "(max COS is %d), setting to 0\n",
15586 cos, pri, (sc->max_cos - 1));
15587 sc->prio_to_cos[pri] = 0;
15593 bxe_sysctl_state(SYSCTL_HANDLER_ARGS)
15595 struct bxe_softc *sc;
15599 error = sysctl_handle_int(oidp, &result, 0, req);
15601 if (error || !req->newptr) {
15607 sc = (struct bxe_softc *)arg1;
15609 BLOGI(sc, "... dumping driver state ...\n");
15610 temp = SHMEM2_RD(sc, temperature_in_half_celsius);
15611 BLOGI(sc, "\t Device Temperature = %d Celsius\n", (temp/2));
15618 bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS)
15620 struct bxe_softc *sc = (struct bxe_softc *)arg1;
15621 uint32_t *eth_stats = (uint32_t *)&sc->eth_stats;
15623 uint64_t value = 0;
15624 int index = (int)arg2;
15626 if (index >= BXE_NUM_ETH_STATS) {
15627 BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index);
15631 offset = (eth_stats + bxe_eth_stats_arr[index].offset);
15633 switch (bxe_eth_stats_arr[index].size) {
15635 value = (uint64_t)*offset;
15638 value = HILO_U64(*offset, *(offset + 1));
15641 BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n",
15642 index, bxe_eth_stats_arr[index].size);
15646 return (sysctl_handle_64(oidp, &value, 0, req));
15650 bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS)
15652 struct bxe_softc *sc = (struct bxe_softc *)arg1;
15653 uint32_t *eth_stats;
15655 uint64_t value = 0;
15656 uint32_t q_stat = (uint32_t)arg2;
15657 uint32_t fp_index = ((q_stat >> 16) & 0xffff);
15658 uint32_t index = (q_stat & 0xffff);
15660 eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats;
15662 if (index >= BXE_NUM_ETH_Q_STATS) {
15663 BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index);
15667 offset = (eth_stats + bxe_eth_q_stats_arr[index].offset);
15669 switch (bxe_eth_q_stats_arr[index].size) {
15671 value = (uint64_t)*offset;
15674 value = HILO_U64(*offset, *(offset + 1));
15677 BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n",
15678 index, bxe_eth_q_stats_arr[index].size);
15682 return (sysctl_handle_64(oidp, &value, 0, req));
15685 static void bxe_force_link_reset(struct bxe_softc *sc)
15688 bxe_acquire_phy_lock(sc);
15689 elink_link_reset(&sc->link_params, &sc->link_vars, 1);
15690 bxe_release_phy_lock(sc);
15694 bxe_sysctl_pauseparam(SYSCTL_HANDLER_ARGS)
15696 struct bxe_softc *sc = (struct bxe_softc *)arg1;;
15697 uint32_t cfg_idx = bxe_get_link_cfg_idx(sc);
15703 error = sysctl_handle_int(oidp, &sc->bxe_pause_param, 0, req);
15705 if (error || !req->newptr) {
15708 if ((sc->bxe_pause_param < 0) || (sc->bxe_pause_param > 8)) {
15709 BLOGW(sc, "invalid pause param (%d) - use intergers between 1 & 8\n",sc->bxe_pause_param);
15710 sc->bxe_pause_param = 8;
15713 result = (sc->bxe_pause_param << PORT_FEATURE_FLOW_CONTROL_SHIFT);
15716 if((result & 0x400) && !(sc->port.supported[cfg_idx] & ELINK_SUPPORTED_Autoneg)) {
15717 BLOGW(sc, "Does not support Autoneg pause_param %d\n", sc->bxe_pause_param);
15723 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_AUTO;
15724 if(result & ELINK_FLOW_CTRL_RX)
15725 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_RX;
15727 if(result & ELINK_FLOW_CTRL_TX)
15728 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_TX;
15729 if(sc->link_params.req_flow_ctrl[cfg_idx] == ELINK_FLOW_CTRL_AUTO)
15730 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_NONE;
15732 if(result & 0x400) {
15733 if (sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG) {
15734 sc->link_params.req_flow_ctrl[cfg_idx] =
15735 ELINK_FLOW_CTRL_AUTO;
15737 sc->link_params.req_fc_auto_adv = 0;
15738 if (result & ELINK_FLOW_CTRL_RX)
15739 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_RX;
15741 if (result & ELINK_FLOW_CTRL_TX)
15742 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_TX;
15743 if (!sc->link_params.req_fc_auto_adv)
15744 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_NONE;
15747 if (sc->link_vars.link_up) {
15748 bxe_stats_handle(sc, STATS_EVENT_STOP);
15750 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
15751 bxe_force_link_reset(sc);
15752 bxe_acquire_phy_lock(sc);
15754 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
15756 bxe_release_phy_lock(sc);
15758 bxe_calc_fc_adv(sc);
15766 bxe_add_sysctls(struct bxe_softc *sc)
15768 struct sysctl_ctx_list *ctx;
15769 struct sysctl_oid_list *children;
15770 struct sysctl_oid *queue_top, *queue;
15771 struct sysctl_oid_list *queue_top_children, *queue_children;
15772 char queue_num_buf[32];
15776 ctx = device_get_sysctl_ctx(sc->dev);
15777 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
15779 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "version",
15780 CTLFLAG_RD, BXE_DRIVER_VERSION, 0,
15783 snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d",
15784 BCM_5710_FW_MAJOR_VERSION,
15785 BCM_5710_FW_MINOR_VERSION,
15786 BCM_5710_FW_REVISION_VERSION,
15787 BCM_5710_FW_ENGINEERING_VERSION);
15789 snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s",
15790 ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION) ? "Single" :
15791 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD) ? "MF-SD" :
15792 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI) ? "MF-SI" :
15793 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" :
15795 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "mf_vnics",
15796 CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0,
15797 "multifunction vnics per port");
15799 snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d",
15800 ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" :
15801 (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" :
15802 (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" :
15804 sc->devinfo.pcie_link_width);
15806 sc->debug = bxe_debug;
15808 #if __FreeBSD_version >= 900000
15809 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version",
15810 CTLFLAG_RD, sc->devinfo.bc_ver_str, 0,
15811 "bootcode version");
15812 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version",
15813 CTLFLAG_RD, sc->fw_ver_str, 0,
15814 "firmware version");
15815 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode",
15816 CTLFLAG_RD, sc->mf_mode_str, 0,
15817 "multifunction mode");
15818 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr",
15819 CTLFLAG_RD, sc->mac_addr_str, 0,
15821 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link",
15822 CTLFLAG_RD, sc->pci_link_str, 0,
15823 "pci link status");
15824 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "debug",
15825 CTLFLAG_RW, &sc->debug,
15826 "debug logging mode");
15828 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version",
15829 CTLFLAG_RD, &sc->devinfo.bc_ver_str, 0,
15830 "bootcode version");
15831 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version",
15832 CTLFLAG_RD, &sc->fw_ver_str, 0,
15833 "firmware version");
15834 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode",
15835 CTLFLAG_RD, &sc->mf_mode_str, 0,
15836 "multifunction mode");
15837 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr",
15838 CTLFLAG_RD, &sc->mac_addr_str, 0,
15840 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link",
15841 CTLFLAG_RD, &sc->pci_link_str, 0,
15842 "pci link status");
15843 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "debug",
15844 CTLFLAG_RW, &sc->debug, 0,
15845 "debug logging mode");
15846 #endif /* #if __FreeBSD_version >= 900000 */
15848 sc->trigger_grcdump = 0;
15849 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "trigger_grcdump",
15850 CTLFLAG_RW, &sc->trigger_grcdump, 0,
15851 "trigger grcdump should be invoked"
15852 " before collecting grcdump");
15854 sc->grcdump_started = 0;
15855 sc->grcdump_done = 0;
15856 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "grcdump_done",
15857 CTLFLAG_RD, &sc->grcdump_done, 0,
15858 "set by driver when grcdump is done");
15860 sc->rx_budget = bxe_rx_budget;
15861 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_budget",
15862 CTLFLAG_RW, &sc->rx_budget, 0,
15863 "rx processing budget");
15865 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_param",
15866 CTLTYPE_UINT | CTLFLAG_RW, sc, 0,
15867 bxe_sysctl_pauseparam, "IU",
15868 "need pause frames- DEF:0/TX:1/RX:2/BOTH:3/AUTO:4/AUTOTX:5/AUTORX:6/AUTORXTX:7/NONE:8");
15871 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "state",
15872 CTLTYPE_UINT | CTLFLAG_RW, sc, 0,
15873 bxe_sysctl_state, "IU", "dump driver state");
15875 for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
15876 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
15877 bxe_eth_stats_arr[i].string,
15878 CTLTYPE_U64 | CTLFLAG_RD, sc, i,
15879 bxe_sysctl_eth_stat, "LU",
15880 bxe_eth_stats_arr[i].string);
15883 /* add a new parent node for all queues "dev.bxe.#.queue" */
15884 queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "queue",
15885 CTLFLAG_RD, NULL, "queue");
15886 queue_top_children = SYSCTL_CHILDREN(queue_top);
15888 for (i = 0; i < sc->num_queues; i++) {
15889 /* add a new parent node for a single queue "dev.bxe.#.queue.#" */
15890 snprintf(queue_num_buf, sizeof(queue_num_buf), "%d", i);
15891 queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO,
15892 queue_num_buf, CTLFLAG_RD, NULL,
15894 queue_children = SYSCTL_CHILDREN(queue);
15896 for (j = 0; j < BXE_NUM_ETH_Q_STATS; j++) {
15897 q_stat = ((i << 16) | j);
15898 SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO,
15899 bxe_eth_q_stats_arr[j].string,
15900 CTLTYPE_U64 | CTLFLAG_RD, sc, q_stat,
15901 bxe_sysctl_eth_q_stat, "LU",
15902 bxe_eth_q_stats_arr[j].string);
15908 bxe_alloc_buf_rings(struct bxe_softc *sc)
15910 #if __FreeBSD_version >= 901504
15913 struct bxe_fastpath *fp;
15915 for (i = 0; i < sc->num_queues; i++) {
15919 fp->tx_br = buf_ring_alloc(BXE_BR_SIZE, M_DEVBUF,
15920 M_NOWAIT, &fp->tx_mtx);
15921 if (fp->tx_br == NULL)
15929 bxe_free_buf_rings(struct bxe_softc *sc)
15931 #if __FreeBSD_version >= 901504
15934 struct bxe_fastpath *fp;
15936 for (i = 0; i < sc->num_queues; i++) {
15941 buf_ring_free(fp->tx_br, M_DEVBUF);
15950 bxe_init_fp_mutexs(struct bxe_softc *sc)
15953 struct bxe_fastpath *fp;
15955 for (i = 0; i < sc->num_queues; i++) {
15959 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name),
15960 "bxe%d_fp%d_tx_lock", sc->unit, i);
15961 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF);
15963 snprintf(fp->rx_mtx_name, sizeof(fp->rx_mtx_name),
15964 "bxe%d_fp%d_rx_lock", sc->unit, i);
15965 mtx_init(&fp->rx_mtx, fp->rx_mtx_name, NULL, MTX_DEF);
15970 bxe_destroy_fp_mutexs(struct bxe_softc *sc)
15973 struct bxe_fastpath *fp;
15975 for (i = 0; i < sc->num_queues; i++) {
15979 if (mtx_initialized(&fp->tx_mtx)) {
15980 mtx_destroy(&fp->tx_mtx);
15983 if (mtx_initialized(&fp->rx_mtx)) {
15984 mtx_destroy(&fp->rx_mtx);
15991 * Device attach function.
15993 * Allocates device resources, performs secondary chip identification, and
15994 * initializes driver instance variables. This function is called from driver
15995 * load after a successful probe.
15998 * 0 = Success, >0 = Failure
16001 bxe_attach(device_t dev)
16003 struct bxe_softc *sc;
16005 sc = device_get_softc(dev);
16007 BLOGD(sc, DBG_LOAD, "Starting attach...\n");
16009 sc->state = BXE_STATE_CLOSED;
16012 sc->unit = device_get_unit(dev);
16014 BLOGD(sc, DBG_LOAD, "softc = %p\n", sc);
16016 sc->pcie_bus = pci_get_bus(dev);
16017 sc->pcie_device = pci_get_slot(dev);
16018 sc->pcie_func = pci_get_function(dev);
16020 /* enable bus master capability */
16021 pci_enable_busmaster(dev);
16024 if (bxe_allocate_bars(sc) != 0) {
16028 /* initialize the mutexes */
16029 bxe_init_mutexes(sc);
16031 /* prepare the periodic callout */
16032 callout_init(&sc->periodic_callout, 0);
16034 /* prepare the chip taskqueue */
16035 sc->chip_tq_flags = CHIP_TQ_NONE;
16036 snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name),
16037 "bxe%d_chip_tq", sc->unit);
16038 TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc);
16039 sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT,
16040 taskqueue_thread_enqueue,
16042 taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */
16043 "%s", sc->chip_tq_name);
16045 /* get device info and set params */
16046 if (bxe_get_device_info(sc) != 0) {
16047 BLOGE(sc, "getting device info\n");
16048 bxe_deallocate_bars(sc);
16049 pci_disable_busmaster(dev);
16053 /* get final misc params */
16054 bxe_get_params(sc);
16056 /* set the default MTU (changed via ifconfig) */
16057 sc->mtu = ETHERMTU;
16059 bxe_set_modes_bitmap(sc);
16062 * If in AFEX mode and the function is configured for FCoE
16063 * then bail... no L2 allowed.
16066 /* get phy settings from shmem and 'and' against admin settings */
16067 bxe_get_phy_info(sc);
16069 /* initialize the FreeBSD ifnet interface */
16070 if (bxe_init_ifnet(sc) != 0) {
16071 bxe_release_mutexes(sc);
16072 bxe_deallocate_bars(sc);
16073 pci_disable_busmaster(dev);
16077 if (bxe_add_cdev(sc) != 0) {
16078 if (sc->ifnet != NULL) {
16079 ether_ifdetach(sc->ifnet);
16081 ifmedia_removeall(&sc->ifmedia);
16082 bxe_release_mutexes(sc);
16083 bxe_deallocate_bars(sc);
16084 pci_disable_busmaster(dev);
16088 /* allocate device interrupts */
16089 if (bxe_interrupt_alloc(sc) != 0) {
16091 if (sc->ifnet != NULL) {
16092 ether_ifdetach(sc->ifnet);
16094 ifmedia_removeall(&sc->ifmedia);
16095 bxe_release_mutexes(sc);
16096 bxe_deallocate_bars(sc);
16097 pci_disable_busmaster(dev);
16101 bxe_init_fp_mutexs(sc);
16103 if (bxe_alloc_buf_rings(sc) != 0) {
16104 bxe_free_buf_rings(sc);
16105 bxe_interrupt_free(sc);
16107 if (sc->ifnet != NULL) {
16108 ether_ifdetach(sc->ifnet);
16110 ifmedia_removeall(&sc->ifmedia);
16111 bxe_release_mutexes(sc);
16112 bxe_deallocate_bars(sc);
16113 pci_disable_busmaster(dev);
16118 if (bxe_alloc_ilt_mem(sc) != 0) {
16119 bxe_free_buf_rings(sc);
16120 bxe_interrupt_free(sc);
16122 if (sc->ifnet != NULL) {
16123 ether_ifdetach(sc->ifnet);
16125 ifmedia_removeall(&sc->ifmedia);
16126 bxe_release_mutexes(sc);
16127 bxe_deallocate_bars(sc);
16128 pci_disable_busmaster(dev);
16132 /* allocate the host hardware/software hsi structures */
16133 if (bxe_alloc_hsi_mem(sc) != 0) {
16134 bxe_free_ilt_mem(sc);
16135 bxe_free_buf_rings(sc);
16136 bxe_interrupt_free(sc);
16138 if (sc->ifnet != NULL) {
16139 ether_ifdetach(sc->ifnet);
16141 ifmedia_removeall(&sc->ifmedia);
16142 bxe_release_mutexes(sc);
16143 bxe_deallocate_bars(sc);
16144 pci_disable_busmaster(dev);
16148 /* need to reset chip if UNDI was active */
16149 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
16152 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
16153 DRV_MSG_SEQ_NUMBER_MASK);
16154 BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq);
16155 bxe_prev_unload(sc);
16160 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16162 if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) &&
16163 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) &&
16164 SHMEM2_RD(sc, dcbx_lldp_params_offset) &&
16165 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) {
16166 bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON);
16167 bxe_dcbx_init_params(sc);
16169 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16173 /* calculate qm_cid_count */
16174 sc->qm_cid_count = bxe_set_qm_cid_count(sc);
16175 BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count);
16178 bxe_init_multi_cos(sc);
16180 bxe_add_sysctls(sc);
16186 * Device detach function.
16188 * Stops the controller, resets the controller, and releases resources.
16191 * 0 = Success, >0 = Failure
16194 bxe_detach(device_t dev)
16196 struct bxe_softc *sc;
16199 sc = device_get_softc(dev);
16201 BLOGD(sc, DBG_LOAD, "Starting detach...\n");
16204 if (ifp != NULL && ifp->if_vlantrunk != NULL) {
16205 BLOGE(sc, "Cannot detach while VLANs are in use.\n");
16211 /* stop the periodic callout */
16212 bxe_periodic_stop(sc);
16214 /* stop the chip taskqueue */
16215 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE);
16217 taskqueue_drain(sc->chip_tq, &sc->chip_tq_task);
16218 taskqueue_free(sc->chip_tq);
16219 sc->chip_tq = NULL;
16222 /* stop and reset the controller if it was open */
16223 if (sc->state != BXE_STATE_CLOSED) {
16225 bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE);
16226 sc->state = BXE_STATE_DISABLED;
16227 BXE_CORE_UNLOCK(sc);
16230 /* release the network interface */
16232 ether_ifdetach(ifp);
16234 ifmedia_removeall(&sc->ifmedia);
16236 /* XXX do the following based on driver state... */
16238 /* free the host hardware/software hsi structures */
16239 bxe_free_hsi_mem(sc);
16242 bxe_free_ilt_mem(sc);
16244 bxe_free_buf_rings(sc);
16246 /* release the interrupts */
16247 bxe_interrupt_free(sc);
16249 /* Release the mutexes*/
16250 bxe_destroy_fp_mutexs(sc);
16251 bxe_release_mutexes(sc);
16254 /* Release the PCIe BAR mapped memory */
16255 bxe_deallocate_bars(sc);
16257 /* Release the FreeBSD interface. */
16258 if (sc->ifnet != NULL) {
16259 if_free(sc->ifnet);
16262 pci_disable_busmaster(dev);
16268 * Device shutdown function.
16270 * Stops and resets the controller.
16276 bxe_shutdown(device_t dev)
16278 struct bxe_softc *sc;
16280 sc = device_get_softc(dev);
16282 BLOGD(sc, DBG_LOAD, "Starting shutdown...\n");
16284 /* stop the periodic callout */
16285 bxe_periodic_stop(sc);
16288 bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE);
16289 BXE_CORE_UNLOCK(sc);
16295 bxe_igu_ack_sb(struct bxe_softc *sc,
16302 uint32_t igu_addr = sc->igu_base_addr;
16303 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
16304 bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr);
16308 bxe_igu_clear_sb_gen(struct bxe_softc *sc,
16313 uint32_t data, ctl, cnt = 100;
16314 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
16315 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
16316 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
16317 uint32_t sb_bit = 1 << (idu_sb_id%32);
16318 uint32_t func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
16319 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
16321 /* Not supported in BC mode */
16322 if (CHIP_INT_MODE_IS_BC(sc)) {
16326 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
16327 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
16328 IGU_REGULAR_CLEANUP_SET |
16329 IGU_REGULAR_BCLEANUP);
16331 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
16332 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
16333 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
16335 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16336 data, igu_addr_data);
16337 REG_WR(sc, igu_addr_data, data);
16339 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16340 BUS_SPACE_BARRIER_WRITE);
16343 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16344 ctl, igu_addr_ctl);
16345 REG_WR(sc, igu_addr_ctl, ctl);
16347 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16348 BUS_SPACE_BARRIER_WRITE);
16351 /* wait for clean up to finish */
16352 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
16356 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
16357 BLOGD(sc, DBG_LOAD,
16358 "Unable to finish IGU cleanup: "
16359 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
16360 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
16365 bxe_igu_clear_sb(struct bxe_softc *sc,
16368 bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
16377 /*******************/
16378 /* ECORE CALLBACKS */
16379 /*******************/
16382 bxe_reset_common(struct bxe_softc *sc)
16384 uint32_t val = 0x1400;
16387 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f);
16389 if (CHIP_IS_E3(sc)) {
16390 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
16391 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
16394 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
16398 bxe_common_init_phy(struct bxe_softc *sc)
16400 uint32_t shmem_base[2];
16401 uint32_t shmem2_base[2];
16403 /* Avoid common init in case MFW supports LFA */
16404 if (SHMEM2_RD(sc, size) >
16405 (uint32_t)offsetof(struct shmem2_region,
16406 lfa_host_addr[SC_PORT(sc)])) {
16410 shmem_base[0] = sc->devinfo.shmem_base;
16411 shmem2_base[0] = sc->devinfo.shmem2_base;
16413 if (!CHIP_IS_E1x(sc)) {
16414 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
16415 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
16418 bxe_acquire_phy_lock(sc);
16419 elink_common_init_phy(sc, shmem_base, shmem2_base,
16420 sc->devinfo.chip_id, 0);
16421 bxe_release_phy_lock(sc);
16425 bxe_pf_disable(struct bxe_softc *sc)
16427 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
16429 val &= ~IGU_PF_CONF_FUNC_EN;
16431 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
16432 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
16433 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
16437 bxe_init_pxp(struct bxe_softc *sc)
16440 int r_order, w_order;
16442 devctl = bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL, 2);
16444 BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl);
16446 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
16448 if (sc->mrrs == -1) {
16449 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
16451 BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs);
16452 r_order = sc->mrrs;
16455 ecore_init_pxp_arb(sc, r_order, w_order);
16459 bxe_get_pretend_reg(struct bxe_softc *sc)
16461 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
16462 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
16463 return (base + (SC_ABS_FUNC(sc)) * stride);
16467 * Called only on E1H or E2.
16468 * When pretending to be PF, the pretend value is the function number 0..7.
16469 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
16473 bxe_pretend_func(struct bxe_softc *sc,
16474 uint16_t pretend_func_val)
16476 uint32_t pretend_reg;
16478 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) {
16482 /* get my own pretend register */
16483 pretend_reg = bxe_get_pretend_reg(sc);
16484 REG_WR(sc, pretend_reg, pretend_func_val);
16485 REG_RD(sc, pretend_reg);
16490 bxe_iov_init_dmae(struct bxe_softc *sc)
16496 bxe_iov_init_dq(struct bxe_softc *sc)
16501 /* send a NIG loopback debug packet */
16503 bxe_lb_pckt(struct bxe_softc *sc)
16505 uint32_t wb_write[3];
16507 /* Ethernet source and destination addresses */
16508 wb_write[0] = 0x55555555;
16509 wb_write[1] = 0x55555555;
16510 wb_write[2] = 0x20; /* SOP */
16511 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16513 /* NON-IP protocol */
16514 wb_write[0] = 0x09000000;
16515 wb_write[1] = 0x55555555;
16516 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
16517 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16521 * Some of the internal memories are not directly readable from the driver.
16522 * To test them we send debug packets.
16525 bxe_int_mem_test(struct bxe_softc *sc)
16531 if (CHIP_REV_IS_FPGA(sc)) {
16533 } else if (CHIP_REV_IS_EMUL(sc)) {
16539 /* disable inputs of parser neighbor blocks */
16540 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16541 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16542 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16543 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16545 /* write 0 to parser credits for CFC search request */
16546 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16548 /* send Ethernet packet */
16551 /* TODO do i reset NIG statistic? */
16552 /* Wait until NIG register shows 1 packet of size 0x10 */
16553 count = 1000 * factor;
16555 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16556 val = *BXE_SP(sc, wb_data[0]);
16566 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16570 /* wait until PRS register shows 1 packet */
16571 count = (1000 * factor);
16573 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16583 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16587 /* Reset and init BRB, PRS */
16588 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16590 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16592 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16593 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16595 /* Disable inputs of parser neighbor blocks */
16596 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16597 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16598 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16599 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16601 /* Write 0 to parser credits for CFC search request */
16602 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16604 /* send 10 Ethernet packets */
16605 for (i = 0; i < 10; i++) {
16609 /* Wait until NIG register shows 10+1 packets of size 11*0x10 = 0xb0 */
16610 count = (1000 * factor);
16612 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16613 val = *BXE_SP(sc, wb_data[0]);
16623 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16627 /* Wait until PRS register shows 2 packets */
16628 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16630 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16633 /* Write 1 to parser credits for CFC search request */
16634 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
16636 /* Wait until PRS register shows 3 packets */
16637 DELAY(10000 * factor);
16639 /* Wait until NIG register shows 1 packet of size 0x10 */
16640 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16642 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16645 /* clear NIG EOP FIFO */
16646 for (i = 0; i < 11; i++) {
16647 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);
16650 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);
16652 BLOGE(sc, "clear of NIG failed val=0x%x\n", val);
16656 /* Reset and init BRB, PRS, NIG */
16657 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16659 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16661 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16662 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16663 if (!CNIC_SUPPORT(sc)) {
16665 REG_WR(sc, PRS_REG_NIC_MODE, 1);
16668 /* Enable inputs of parser neighbor blocks */
16669 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff);
16670 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1);
16671 REG_WR(sc, CFC_REG_DEBUG0, 0x0);
16672 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1);
16678 bxe_setup_fan_failure_detection(struct bxe_softc *sc)
16685 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
16686 SHARED_HW_CFG_FAN_FAILURE_MASK);
16688 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
16692 * The fan failure mechanism is usually related to the PHY type since
16693 * the power consumption of the board is affected by the PHY. Currently,
16694 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
16696 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
16697 for (port = PORT_0; port < PORT_MAX; port++) {
16698 is_required |= elink_fan_failure_det_req(sc,
16699 sc->devinfo.shmem_base,
16700 sc->devinfo.shmem2_base,
16705 BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required);
16707 if (is_required == 0) {
16711 /* Fan failure is indicated by SPIO 5 */
16712 bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
16714 /* set to active low mode */
16715 val = REG_RD(sc, MISC_REG_SPIO_INT);
16716 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
16717 REG_WR(sc, MISC_REG_SPIO_INT, val);
16719 /* enable interrupt to signal the IGU */
16720 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
16721 val |= MISC_SPIO_SPIO5;
16722 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
16726 bxe_enable_blocks_attention(struct bxe_softc *sc)
16730 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
16731 if (!CHIP_IS_E1x(sc)) {
16732 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
16734 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
16736 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
16737 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
16739 * mask read length error interrupts in brb for parser
16740 * (parsing unit and 'checksum and crc' unit)
16741 * these errors are legal (PU reads fixed length and CAC can cause
16742 * read length error on truncated packets)
16744 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
16745 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
16746 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
16747 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
16748 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
16749 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
16750 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
16751 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
16752 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
16753 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
16754 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
16755 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
16756 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
16757 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
16758 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
16759 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
16760 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
16761 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
16762 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
16764 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
16765 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
16766 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
16767 if (!CHIP_IS_E1x(sc)) {
16768 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
16769 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
16771 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
16773 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
16774 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
16775 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
16776 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
16778 if (!CHIP_IS_E1x(sc)) {
16779 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
16780 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
16783 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
16784 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
16785 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
16786 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
16790 * bxe_init_hw_common - initialize the HW at the COMMON phase.
16792 * @sc: driver handle
16795 bxe_init_hw_common(struct bxe_softc *sc)
16797 uint8_t abs_func_id;
16800 BLOGD(sc, DBG_LOAD, "starting common init for func %d\n",
16804 * take the RESET lock to protect undi_unload flow from accessing
16805 * registers while we are resetting the chip
16807 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
16809 bxe_reset_common(sc);
16811 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
16814 if (CHIP_IS_E3(sc)) {
16815 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
16816 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
16819 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
16821 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
16823 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
16824 BLOGD(sc, DBG_LOAD, "after misc block init\n");
16826 if (!CHIP_IS_E1x(sc)) {
16828 * 4-port mode or 2-port mode we need to turn off master-enable for
16829 * everyone. After that we turn it back on for self. So, we disregard
16830 * multi-function, and always disable all functions on the given path,
16831 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
16833 for (abs_func_id = SC_PATH(sc);
16834 abs_func_id < (E2_FUNC_MAX * 2);
16835 abs_func_id += 2) {
16836 if (abs_func_id == SC_ABS_FUNC(sc)) {
16837 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
16841 bxe_pretend_func(sc, abs_func_id);
16843 /* clear pf enable */
16844 bxe_pf_disable(sc);
16846 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
16850 BLOGD(sc, DBG_LOAD, "after pf disable\n");
16852 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
16854 if (CHIP_IS_E1(sc)) {
16856 * enable HW interrupt from PXP on USDM overflow
16857 * bit 16 on INT_MASK_0
16859 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
16862 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
16865 #ifdef __BIG_ENDIAN
16866 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
16867 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
16868 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
16869 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
16870 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
16871 /* make sure this value is 0 */
16872 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
16874 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
16875 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
16876 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
16877 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
16878 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
16881 ecore_ilt_init_page_size(sc, INITOP_SET);
16883 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
16884 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
16887 /* let the HW do it's magic... */
16890 /* finish PXP init */
16891 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
16893 BLOGE(sc, "PXP2 CFG failed PXP2_REG_RQ_CFG_DONE val = 0x%x\n",
16897 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
16899 BLOGE(sc, "PXP2 RD_INIT failed val = 0x%x\n", val);
16903 BLOGD(sc, DBG_LOAD, "after pxp init\n");
16906 * Timer bug workaround for E2 only. We need to set the entire ILT to have
16907 * entries with value "0" and valid bit on. This needs to be done by the
16908 * first PF that is loaded in a path (i.e. common phase)
16910 if (!CHIP_IS_E1x(sc)) {
16912 * In E2 there is a bug in the timers block that can cause function 6 / 7
16913 * (i.e. vnic3) to start even if it is marked as "scan-off".
16914 * This occurs when a different function (func2,3) is being marked
16915 * as "scan-off". Real-life scenario for example: if a driver is being
16916 * load-unloaded while func6,7 are down. This will cause the timer to access
16917 * the ilt, translate to a logical address and send a request to read/write.
16918 * Since the ilt for the function that is down is not valid, this will cause
16919 * a translation error which is unrecoverable.
16920 * The Workaround is intended to make sure that when this happens nothing
16921 * fatal will occur. The workaround:
16922 * 1. First PF driver which loads on a path will:
16923 * a. After taking the chip out of reset, by using pretend,
16924 * it will write "0" to the following registers of
16926 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
16927 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
16928 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
16929 * And for itself it will write '1' to
16930 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
16931 * dmae-operations (writing to pram for example.)
16932 * note: can be done for only function 6,7 but cleaner this
16934 * b. Write zero+valid to the entire ILT.
16935 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
16936 * VNIC3 (of that port). The range allocated will be the
16937 * entire ILT. This is needed to prevent ILT range error.
16938 * 2. Any PF driver load flow:
16939 * a. ILT update with the physical addresses of the allocated
16941 * b. Wait 20msec. - note that this timeout is needed to make
16942 * sure there are no requests in one of the PXP internal
16943 * queues with "old" ILT addresses.
16944 * c. PF enable in the PGLC.
16945 * d. Clear the was_error of the PF in the PGLC. (could have
16946 * occurred while driver was down)
16947 * e. PF enable in the CFC (WEAK + STRONG)
16948 * f. Timers scan enable
16949 * 3. PF driver unload flow:
16950 * a. Clear the Timers scan_en.
16951 * b. Polling for scan_on=0 for that PF.
16952 * c. Clear the PF enable bit in the PXP.
16953 * d. Clear the PF enable in the CFC (WEAK + STRONG)
16954 * e. Write zero+valid to all ILT entries (The valid bit must
16956 * f. If this is VNIC 3 of a port then also init
16957 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16958 * to the last enrty in the ILT.
16961 * Currently the PF error in the PGLC is non recoverable.
16962 * In the future the there will be a recovery routine for this error.
16963 * Currently attention is masked.
16964 * Having an MCP lock on the load/unload process does not guarantee that
16965 * there is no Timer disable during Func6/7 enable. This is because the
16966 * Timers scan is currently being cleared by the MCP on FLR.
16967 * Step 2.d can be done only for PF6/7 and the driver can also check if
16968 * there is error before clearing it. But the flow above is simpler and
16970 * All ILT entries are written by zero+valid and not just PF6/7
16971 * ILT entries since in the future the ILT entries allocation for
16972 * PF-s might be dynamic.
16974 struct ilt_client_info ilt_cli;
16975 struct ecore_ilt ilt;
16977 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
16978 memset(&ilt, 0, sizeof(struct ecore_ilt));
16980 /* initialize dummy TM client */
16982 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
16983 ilt_cli.client_num = ILT_CLIENT_TM;
16986 * Step 1: set zeroes to all ilt page entries with valid bit on
16987 * Step 2: set the timers first/last ilt entry to point
16988 * to the entire range to prevent ILT range error for 3rd/4th
16989 * vnic (this code assumes existence of the vnic)
16991 * both steps performed by call to ecore_ilt_client_init_op()
16992 * with dummy TM client
16994 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
16995 * and his brother are split registers
16998 bxe_pretend_func(sc, (SC_PATH(sc) + 6));
16999 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
17000 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
17002 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN);
17003 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN);
17004 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
17007 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
17008 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
17010 if (!CHIP_IS_E1x(sc)) {
17011 int factor = CHIP_REV_IS_EMUL(sc) ? 1000 :
17012 (CHIP_REV_IS_FPGA(sc) ? 400 : 0);
17014 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
17015 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
17017 /* let the HW do it's magic... */
17020 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
17021 } while (factor-- && (val != 1));
17024 BLOGE(sc, "ATC_INIT failed val = 0x%x\n", val);
17029 BLOGD(sc, DBG_LOAD, "after pglue and atc init\n");
17031 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
17033 bxe_iov_init_dmae(sc);
17035 /* clean the DMAE memory */
17036 sc->dmae_ready = 1;
17037 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
17039 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
17041 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
17043 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
17045 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
17047 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
17048 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
17049 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
17050 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
17052 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
17054 /* QM queues pointers table */
17055 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
17057 /* soft reset pulse */
17058 REG_WR(sc, QM_REG_SOFT_RESET, 1);
17059 REG_WR(sc, QM_REG_SOFT_RESET, 0);
17061 if (CNIC_SUPPORT(sc))
17062 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
17064 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
17065 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT);
17066 if (!CHIP_REV_IS_SLOW(sc)) {
17067 /* enable hw interrupt from doorbell Q */
17068 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
17071 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
17073 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
17074 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
17076 if (!CHIP_IS_E1(sc)) {
17077 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
17080 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
17081 if (IS_MF_AFEX(sc)) {
17083 * configure that AFEX and VLAN headers must be
17084 * received in AFEX mode
17086 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
17087 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
17088 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
17089 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
17090 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
17093 * Bit-map indicating which L2 hdrs may appear
17094 * after the basic Ethernet header
17096 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
17097 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17101 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
17102 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
17103 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
17104 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
17106 if (!CHIP_IS_E1x(sc)) {
17107 /* reset VFC memories */
17108 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17109 VFC_MEMORIES_RST_REG_CAM_RST |
17110 VFC_MEMORIES_RST_REG_RAM_RST);
17111 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17112 VFC_MEMORIES_RST_REG_CAM_RST |
17113 VFC_MEMORIES_RST_REG_RAM_RST);
17118 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
17119 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
17120 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
17121 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
17123 /* sync semi rtc */
17124 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
17126 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
17129 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
17130 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
17131 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
17133 if (!CHIP_IS_E1x(sc)) {
17134 if (IS_MF_AFEX(sc)) {
17136 * configure that AFEX and VLAN headers must be
17137 * sent in AFEX mode
17139 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
17140 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
17141 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
17142 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
17143 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
17145 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
17146 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17150 REG_WR(sc, SRC_REG_SOFT_RST, 1);
17152 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
17154 if (CNIC_SUPPORT(sc)) {
17155 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
17156 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
17157 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
17158 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
17159 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
17160 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
17161 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
17162 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
17163 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
17164 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
17166 REG_WR(sc, SRC_REG_SOFT_RST, 0);
17168 if (sizeof(union cdu_context) != 1024) {
17169 /* we currently assume that a context is 1024 bytes */
17170 BLOGE(sc, "please adjust the size of cdu_context(%ld)\n",
17171 (long)sizeof(union cdu_context));
17174 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
17175 val = (4 << 24) + (0 << 12) + 1024;
17176 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
17178 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
17180 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
17181 /* enable context validation interrupt from CFC */
17182 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
17184 /* set the thresholds to prevent CFC/CDU race */
17185 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
17186 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
17188 if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) {
17189 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
17192 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
17193 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
17195 /* Reset PCIE errors for debug */
17196 REG_WR(sc, 0x2814, 0xffffffff);
17197 REG_WR(sc, 0x3820, 0xffffffff);
17199 if (!CHIP_IS_E1x(sc)) {
17200 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
17201 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
17202 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
17203 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
17204 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
17205 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
17206 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
17207 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
17208 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
17209 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
17210 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
17213 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
17215 if (!CHIP_IS_E1(sc)) {
17216 /* in E3 this done in per-port section */
17217 if (!CHIP_IS_E3(sc))
17218 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
17221 if (CHIP_IS_E1H(sc)) {
17222 /* not applicable for E2 (and above ...) */
17223 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
17226 if (CHIP_REV_IS_SLOW(sc)) {
17230 /* finish CFC init */
17231 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
17233 BLOGE(sc, "CFC LL_INIT failed val=0x%x\n", val);
17236 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
17238 BLOGE(sc, "CFC AC_INIT failed val=0x%x\n", val);
17241 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
17243 BLOGE(sc, "CFC CAM_INIT failed val=0x%x\n", val);
17246 REG_WR(sc, CFC_REG_DEBUG0, 0);
17248 if (CHIP_IS_E1(sc)) {
17249 /* read NIG statistic to see if this is our first up since powerup */
17250 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
17251 val = *BXE_SP(sc, wb_data[0]);
17253 /* do internal memory self test */
17254 if ((val == 0) && bxe_int_mem_test(sc)) {
17255 BLOGE(sc, "internal mem self test failed val=0x%x\n", val);
17260 bxe_setup_fan_failure_detection(sc);
17262 /* clear PXP2 attentions */
17263 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
17265 bxe_enable_blocks_attention(sc);
17267 if (!CHIP_REV_IS_SLOW(sc)) {
17268 ecore_enable_blocks_parity(sc);
17271 if (!BXE_NOMCP(sc)) {
17272 if (CHIP_IS_E1x(sc)) {
17273 bxe_common_init_phy(sc);
17281 * bxe_init_hw_common_chip - init HW at the COMMON_CHIP phase.
17283 * @sc: driver handle
17286 bxe_init_hw_common_chip(struct bxe_softc *sc)
17288 int rc = bxe_init_hw_common(sc);
17291 BLOGE(sc, "bxe_init_hw_common failed rc=%d\n", rc);
17295 /* In E2 2-PORT mode, same ext phy is used for the two paths */
17296 if (!BXE_NOMCP(sc)) {
17297 bxe_common_init_phy(sc);
17304 bxe_init_hw_port(struct bxe_softc *sc)
17306 int port = SC_PORT(sc);
17307 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
17308 uint32_t low, high;
17311 BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port);
17313 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
17315 ecore_init_block(sc, BLOCK_MISC, init_phase);
17316 ecore_init_block(sc, BLOCK_PXP, init_phase);
17317 ecore_init_block(sc, BLOCK_PXP2, init_phase);
17320 * Timers bug workaround: disables the pf_master bit in pglue at
17321 * common phase, we need to enable it here before any dmae access are
17322 * attempted. Therefore we manually added the enable-master to the
17323 * port phase (it also happens in the function phase)
17325 if (!CHIP_IS_E1x(sc)) {
17326 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17329 ecore_init_block(sc, BLOCK_ATC, init_phase);
17330 ecore_init_block(sc, BLOCK_DMAE, init_phase);
17331 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
17332 ecore_init_block(sc, BLOCK_QM, init_phase);
17334 ecore_init_block(sc, BLOCK_TCM, init_phase);
17335 ecore_init_block(sc, BLOCK_UCM, init_phase);
17336 ecore_init_block(sc, BLOCK_CCM, init_phase);
17337 ecore_init_block(sc, BLOCK_XCM, init_phase);
17339 /* QM cid (connection) count */
17340 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
17342 if (CNIC_SUPPORT(sc)) {
17343 ecore_init_block(sc, BLOCK_TM, init_phase);
17344 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20);
17345 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
17348 ecore_init_block(sc, BLOCK_DORQ, init_phase);
17350 ecore_init_block(sc, BLOCK_BRB1, init_phase);
17352 if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) {
17354 low = (BXE_ONE_PORT(sc) ? 160 : 246);
17355 } else if (sc->mtu > 4096) {
17356 if (BXE_ONE_PORT(sc)) {
17360 /* (24*1024 + val*4)/256 */
17361 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
17364 low = (BXE_ONE_PORT(sc) ? 80 : 160);
17366 high = (low + 56); /* 14*1024/256 */
17367 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
17368 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
17371 if (CHIP_IS_MODE_4_PORT(sc)) {
17372 REG_WR(sc, SC_PORT(sc) ?
17373 BRB1_REG_MAC_GUARANTIED_1 :
17374 BRB1_REG_MAC_GUARANTIED_0, 40);
17377 ecore_init_block(sc, BLOCK_PRS, init_phase);
17378 if (CHIP_IS_E3B0(sc)) {
17379 if (IS_MF_AFEX(sc)) {
17380 /* configure headers for AFEX mode */
17381 REG_WR(sc, SC_PORT(sc) ?
17382 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17383 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
17384 REG_WR(sc, SC_PORT(sc) ?
17385 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
17386 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
17387 REG_WR(sc, SC_PORT(sc) ?
17388 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
17389 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
17391 /* Ovlan exists only if we are in multi-function +
17392 * switch-dependent mode, in switch-independent there
17393 * is no ovlan headers
17395 REG_WR(sc, SC_PORT(sc) ?
17396 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17397 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
17398 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
17402 ecore_init_block(sc, BLOCK_TSDM, init_phase);
17403 ecore_init_block(sc, BLOCK_CSDM, init_phase);
17404 ecore_init_block(sc, BLOCK_USDM, init_phase);
17405 ecore_init_block(sc, BLOCK_XSDM, init_phase);
17407 ecore_init_block(sc, BLOCK_TSEM, init_phase);
17408 ecore_init_block(sc, BLOCK_USEM, init_phase);
17409 ecore_init_block(sc, BLOCK_CSEM, init_phase);
17410 ecore_init_block(sc, BLOCK_XSEM, init_phase);
17412 ecore_init_block(sc, BLOCK_UPB, init_phase);
17413 ecore_init_block(sc, BLOCK_XPB, init_phase);
17415 ecore_init_block(sc, BLOCK_PBF, init_phase);
17417 if (CHIP_IS_E1x(sc)) {
17418 /* configure PBF to work without PAUSE mtu 9000 */
17419 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
17421 /* update threshold */
17422 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
17423 /* update init credit */
17424 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
17426 /* probe changes */
17427 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1);
17429 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0);
17432 if (CNIC_SUPPORT(sc)) {
17433 ecore_init_block(sc, BLOCK_SRC, init_phase);
17436 ecore_init_block(sc, BLOCK_CDU, init_phase);
17437 ecore_init_block(sc, BLOCK_CFC, init_phase);
17439 if (CHIP_IS_E1(sc)) {
17440 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
17441 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
17443 ecore_init_block(sc, BLOCK_HC, init_phase);
17445 ecore_init_block(sc, BLOCK_IGU, init_phase);
17447 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
17448 /* init aeu_mask_attn_func_0/1:
17449 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
17450 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
17451 * bits 4-7 are used for "per vn group attention" */
17452 val = IS_MF(sc) ? 0xF7 : 0x7;
17453 /* Enable DCBX attention for all but E1 */
17454 val |= CHIP_IS_E1(sc) ? 0 : 0x10;
17455 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
17457 ecore_init_block(sc, BLOCK_NIG, init_phase);
17459 if (!CHIP_IS_E1x(sc)) {
17460 /* Bit-map indicating which L2 hdrs may appear after the
17461 * basic Ethernet header
17463 if (IS_MF_AFEX(sc)) {
17464 REG_WR(sc, SC_PORT(sc) ?
17465 NIG_REG_P1_HDRS_AFTER_BASIC :
17466 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
17468 REG_WR(sc, SC_PORT(sc) ?
17469 NIG_REG_P1_HDRS_AFTER_BASIC :
17470 NIG_REG_P0_HDRS_AFTER_BASIC,
17471 IS_MF_SD(sc) ? 7 : 6);
17474 if (CHIP_IS_E3(sc)) {
17475 REG_WR(sc, SC_PORT(sc) ?
17476 NIG_REG_LLH1_MF_MODE :
17477 NIG_REG_LLH_MF_MODE, IS_MF(sc));
17480 if (!CHIP_IS_E3(sc)) {
17481 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
17484 if (!CHIP_IS_E1(sc)) {
17485 /* 0x2 disable mf_ov, 0x1 enable */
17486 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
17487 (IS_MF_SD(sc) ? 0x1 : 0x2));
17489 if (!CHIP_IS_E1x(sc)) {
17491 switch (sc->devinfo.mf_info.mf_mode) {
17492 case MULTI_FUNCTION_SD:
17495 case MULTI_FUNCTION_SI:
17496 case MULTI_FUNCTION_AFEX:
17501 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
17502 NIG_REG_LLH0_CLS_TYPE), val);
17504 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
17505 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
17506 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
17509 /* If SPIO5 is set to generate interrupts, enable it for this port */
17510 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17511 if (val & MISC_SPIO_SPIO5) {
17512 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
17513 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
17514 val = REG_RD(sc, reg_addr);
17515 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
17516 REG_WR(sc, reg_addr, val);
17523 bxe_flr_clnup_reg_poll(struct bxe_softc *sc,
17526 uint32_t poll_count)
17528 uint32_t cur_cnt = poll_count;
17531 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
17532 DELAY(FLR_WAIT_INTERVAL);
17539 bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc,
17544 uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
17547 BLOGE(sc, "%s usage count=%d\n", msg, val);
17554 /* Common routines with VF FLR cleanup */
17556 bxe_flr_clnup_poll_count(struct bxe_softc *sc)
17558 /* adjust polling timeout */
17559 if (CHIP_REV_IS_EMUL(sc)) {
17560 return (FLR_POLL_CNT * 2000);
17563 if (CHIP_REV_IS_FPGA(sc)) {
17564 return (FLR_POLL_CNT * 120);
17567 return (FLR_POLL_CNT);
17571 bxe_poll_hw_usage_counters(struct bxe_softc *sc,
17574 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
17575 if (bxe_flr_clnup_poll_hw_counter(sc,
17576 CFC_REG_NUM_LCIDS_INSIDE_PF,
17577 "CFC PF usage counter timed out",
17582 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
17583 if (bxe_flr_clnup_poll_hw_counter(sc,
17584 DORQ_REG_PF_USAGE_CNT,
17585 "DQ PF usage counter timed out",
17590 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
17591 if (bxe_flr_clnup_poll_hw_counter(sc,
17592 QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc),
17593 "QM PF usage counter timed out",
17598 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
17599 if (bxe_flr_clnup_poll_hw_counter(sc,
17600 TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc),
17601 "Timers VNIC usage counter timed out",
17606 if (bxe_flr_clnup_poll_hw_counter(sc,
17607 TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc),
17608 "Timers NUM_SCANS usage counter timed out",
17613 /* Wait DMAE PF usage counter to zero */
17614 if (bxe_flr_clnup_poll_hw_counter(sc,
17615 dmae_reg_go_c[INIT_DMAE_C(sc)],
17616 "DMAE dommand register timed out",
17624 #define OP_GEN_PARAM(param) \
17625 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
17626 #define OP_GEN_TYPE(type) \
17627 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
17628 #define OP_GEN_AGG_VECT(index) \
17629 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
17632 bxe_send_final_clnup(struct bxe_softc *sc,
17633 uint8_t clnup_func,
17636 uint32_t op_gen_command = 0;
17637 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
17638 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
17641 if (REG_RD(sc, comp_addr)) {
17642 BLOGE(sc, "Cleanup complete was not 0 before sending\n");
17646 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
17647 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
17648 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
17649 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
17651 BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n");
17652 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
17654 if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
17655 BLOGE(sc, "FW final cleanup did not succeed\n");
17656 BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n",
17657 (REG_RD(sc, comp_addr)));
17658 bxe_panic(sc, ("FLR cleanup failed\n"));
17662 /* Zero completion for nxt FLR */
17663 REG_WR(sc, comp_addr, 0);
17669 bxe_pbf_pN_buf_flushed(struct bxe_softc *sc,
17670 struct pbf_pN_buf_regs *regs,
17671 uint32_t poll_count)
17673 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
17674 uint32_t cur_cnt = poll_count;
17676 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
17677 crd = crd_start = REG_RD(sc, regs->crd);
17678 init_crd = REG_RD(sc, regs->init_crd);
17680 BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
17681 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : s:%x\n", regs->pN, crd);
17682 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
17684 while ((crd != init_crd) &&
17685 ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) <
17686 (init_crd - crd_start))) {
17688 DELAY(FLR_WAIT_INTERVAL);
17689 crd = REG_RD(sc, regs->crd);
17690 crd_freed = REG_RD(sc, regs->crd_freed);
17692 BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN);
17693 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : c:%x\n", regs->pN, crd);
17694 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed);
17699 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n",
17700 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
17704 bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc,
17705 struct pbf_pN_cmd_regs *regs,
17706 uint32_t poll_count)
17708 uint32_t occup, to_free, freed, freed_start;
17709 uint32_t cur_cnt = poll_count;
17711 occup = to_free = REG_RD(sc, regs->lines_occup);
17712 freed = freed_start = REG_RD(sc, regs->lines_freed);
17714 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
17715 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
17718 ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) {
17720 DELAY(FLR_WAIT_INTERVAL);
17721 occup = REG_RD(sc, regs->lines_occup);
17722 freed = REG_RD(sc, regs->lines_freed);
17724 BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN);
17725 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
17726 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
17731 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n",
17732 poll_count - cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
17736 bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count)
17738 struct pbf_pN_cmd_regs cmd_regs[] = {
17739 {0, (CHIP_IS_E3B0(sc)) ?
17740 PBF_REG_TQ_OCCUPANCY_Q0 :
17741 PBF_REG_P0_TQ_OCCUPANCY,
17742 (CHIP_IS_E3B0(sc)) ?
17743 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
17744 PBF_REG_P0_TQ_LINES_FREED_CNT},
17745 {1, (CHIP_IS_E3B0(sc)) ?
17746 PBF_REG_TQ_OCCUPANCY_Q1 :
17747 PBF_REG_P1_TQ_OCCUPANCY,
17748 (CHIP_IS_E3B0(sc)) ?
17749 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
17750 PBF_REG_P1_TQ_LINES_FREED_CNT},
17751 {4, (CHIP_IS_E3B0(sc)) ?
17752 PBF_REG_TQ_OCCUPANCY_LB_Q :
17753 PBF_REG_P4_TQ_OCCUPANCY,
17754 (CHIP_IS_E3B0(sc)) ?
17755 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
17756 PBF_REG_P4_TQ_LINES_FREED_CNT}
17759 struct pbf_pN_buf_regs buf_regs[] = {
17760 {0, (CHIP_IS_E3B0(sc)) ?
17761 PBF_REG_INIT_CRD_Q0 :
17762 PBF_REG_P0_INIT_CRD ,
17763 (CHIP_IS_E3B0(sc)) ?
17764 PBF_REG_CREDIT_Q0 :
17766 (CHIP_IS_E3B0(sc)) ?
17767 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
17768 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
17769 {1, (CHIP_IS_E3B0(sc)) ?
17770 PBF_REG_INIT_CRD_Q1 :
17771 PBF_REG_P1_INIT_CRD,
17772 (CHIP_IS_E3B0(sc)) ?
17773 PBF_REG_CREDIT_Q1 :
17775 (CHIP_IS_E3B0(sc)) ?
17776 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
17777 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
17778 {4, (CHIP_IS_E3B0(sc)) ?
17779 PBF_REG_INIT_CRD_LB_Q :
17780 PBF_REG_P4_INIT_CRD,
17781 (CHIP_IS_E3B0(sc)) ?
17782 PBF_REG_CREDIT_LB_Q :
17784 (CHIP_IS_E3B0(sc)) ?
17785 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
17786 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
17791 /* Verify the command queues are flushed P0, P1, P4 */
17792 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
17793 bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
17796 /* Verify the transmission buffers are flushed P0, P1, P4 */
17797 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
17798 bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
17803 bxe_hw_enable_status(struct bxe_softc *sc)
17807 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
17808 BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
17810 val = REG_RD(sc, PBF_REG_DISABLE_PF);
17811 BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val);
17813 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
17814 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
17816 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
17817 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
17819 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
17820 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
17822 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
17823 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
17825 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
17826 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
17828 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
17829 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val);
17833 bxe_pf_flr_clnup(struct bxe_softc *sc)
17835 uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc);
17837 BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc));
17839 /* Re-enable PF target read access */
17840 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
17842 /* Poll HW usage counters */
17843 BLOGD(sc, DBG_LOAD, "Polling usage counters\n");
17844 if (bxe_poll_hw_usage_counters(sc, poll_cnt)) {
17848 /* Zero the igu 'trailing edge' and 'leading edge' */
17850 /* Send the FW cleanup command */
17851 if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) {
17857 /* Verify TX hw is flushed */
17858 bxe_tx_hw_flushed(sc, poll_cnt);
17860 /* Wait 100ms (not adjusted according to platform) */
17863 /* Verify no pending pci transactions */
17864 if (bxe_is_pcie_pending(sc)) {
17865 BLOGE(sc, "PCIE Transactions still pending\n");
17869 bxe_hw_enable_status(sc);
17872 * Master enable - Due to WB DMAE writes performed before this
17873 * register is re-initialized as part of the regular function init
17875 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17881 bxe_init_hw_func(struct bxe_softc *sc)
17883 int port = SC_PORT(sc);
17884 int func = SC_FUNC(sc);
17885 int init_phase = PHASE_PF0 + func;
17886 struct ecore_ilt *ilt = sc->ilt;
17887 uint16_t cdu_ilt_start;
17888 uint32_t addr, val;
17889 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
17890 int i, main_mem_width, rc;
17892 BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func);
17895 if (!CHIP_IS_E1x(sc)) {
17896 rc = bxe_pf_flr_clnup(sc);
17898 BLOGE(sc, "FLR cleanup failed!\n");
17899 // XXX bxe_fw_dump(sc);
17900 // XXX bxe_idle_chk(sc);
17905 /* set MSI reconfigure capability */
17906 if (sc->devinfo.int_block == INT_BLOCK_HC) {
17907 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
17908 val = REG_RD(sc, addr);
17909 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
17910 REG_WR(sc, addr, val);
17913 ecore_init_block(sc, BLOCK_PXP, init_phase);
17914 ecore_init_block(sc, BLOCK_PXP2, init_phase);
17917 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
17919 for (i = 0; i < L2_ILT_LINES(sc); i++) {
17920 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
17921 ilt->lines[cdu_ilt_start + i].page_mapping =
17922 sc->context[i].vcxt_dma.paddr;
17923 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
17925 ecore_ilt_init_op(sc, INITOP_SET);
17928 REG_WR(sc, PRS_REG_NIC_MODE, 1);
17929 BLOGD(sc, DBG_LOAD, "NIC MODE configured\n");
17931 if (!CHIP_IS_E1x(sc)) {
17932 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
17934 /* Turn on a single ISR mode in IGU if driver is going to use
17937 if (sc->interrupt_mode != INTR_MODE_MSIX) {
17938 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
17942 * Timers workaround bug: function init part.
17943 * Need to wait 20msec after initializing ILT,
17944 * needed to make sure there are no requests in
17945 * one of the PXP internal queues with "old" ILT addresses
17950 * Master enable - Due to WB DMAE writes performed before this
17951 * register is re-initialized as part of the regular function
17954 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17955 /* Enable the function in IGU */
17956 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
17959 sc->dmae_ready = 1;
17961 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
17963 if (!CHIP_IS_E1x(sc))
17964 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
17966 ecore_init_block(sc, BLOCK_ATC, init_phase);
17967 ecore_init_block(sc, BLOCK_DMAE, init_phase);
17968 ecore_init_block(sc, BLOCK_NIG, init_phase);
17969 ecore_init_block(sc, BLOCK_SRC, init_phase);
17970 ecore_init_block(sc, BLOCK_MISC, init_phase);
17971 ecore_init_block(sc, BLOCK_TCM, init_phase);
17972 ecore_init_block(sc, BLOCK_UCM, init_phase);
17973 ecore_init_block(sc, BLOCK_CCM, init_phase);
17974 ecore_init_block(sc, BLOCK_XCM, init_phase);
17975 ecore_init_block(sc, BLOCK_TSEM, init_phase);
17976 ecore_init_block(sc, BLOCK_USEM, init_phase);
17977 ecore_init_block(sc, BLOCK_CSEM, init_phase);
17978 ecore_init_block(sc, BLOCK_XSEM, init_phase);
17980 if (!CHIP_IS_E1x(sc))
17981 REG_WR(sc, QM_REG_PF_EN, 1);
17983 if (!CHIP_IS_E1x(sc)) {
17984 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17985 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17986 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17987 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17989 ecore_init_block(sc, BLOCK_QM, init_phase);
17991 ecore_init_block(sc, BLOCK_TM, init_phase);
17992 ecore_init_block(sc, BLOCK_DORQ, init_phase);
17994 bxe_iov_init_dq(sc);
17996 ecore_init_block(sc, BLOCK_BRB1, init_phase);
17997 ecore_init_block(sc, BLOCK_PRS, init_phase);
17998 ecore_init_block(sc, BLOCK_TSDM, init_phase);
17999 ecore_init_block(sc, BLOCK_CSDM, init_phase);
18000 ecore_init_block(sc, BLOCK_USDM, init_phase);
18001 ecore_init_block(sc, BLOCK_XSDM, init_phase);
18002 ecore_init_block(sc, BLOCK_UPB, init_phase);
18003 ecore_init_block(sc, BLOCK_XPB, init_phase);
18004 ecore_init_block(sc, BLOCK_PBF, init_phase);
18005 if (!CHIP_IS_E1x(sc))
18006 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
18008 ecore_init_block(sc, BLOCK_CDU, init_phase);
18010 ecore_init_block(sc, BLOCK_CFC, init_phase);
18012 if (!CHIP_IS_E1x(sc))
18013 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
18016 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
18017 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc));
18020 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
18022 /* HC init per function */
18023 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18024 if (CHIP_IS_E1H(sc)) {
18025 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18027 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18028 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18030 ecore_init_block(sc, BLOCK_HC, init_phase);
18033 int num_segs, sb_idx, prod_offset;
18035 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18037 if (!CHIP_IS_E1x(sc)) {
18038 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18039 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18042 ecore_init_block(sc, BLOCK_IGU, init_phase);
18044 if (!CHIP_IS_E1x(sc)) {
18048 * E2 mode: address 0-135 match to the mapping memory;
18049 * 136 - PF0 default prod; 137 - PF1 default prod;
18050 * 138 - PF2 default prod; 139 - PF3 default prod;
18051 * 140 - PF0 attn prod; 141 - PF1 attn prod;
18052 * 142 - PF2 attn prod; 143 - PF3 attn prod;
18053 * 144-147 reserved.
18055 * E1.5 mode - In backward compatible mode;
18056 * for non default SB; each even line in the memory
18057 * holds the U producer and each odd line hold
18058 * the C producer. The first 128 producers are for
18059 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
18060 * producers are for the DSB for each PF.
18061 * Each PF has five segments: (the order inside each
18062 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
18063 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
18064 * 144-147 attn prods;
18066 /* non-default-status-blocks */
18067 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18068 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
18069 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
18070 prod_offset = (sc->igu_base_sb + sb_idx) *
18073 for (i = 0; i < num_segs; i++) {
18074 addr = IGU_REG_PROD_CONS_MEMORY +
18075 (prod_offset + i) * 4;
18076 REG_WR(sc, addr, 0);
18078 /* send consumer update with value 0 */
18079 bxe_ack_sb(sc, sc->igu_base_sb + sb_idx,
18080 USTORM_ID, 0, IGU_INT_NOP, 1);
18081 bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
18084 /* default-status-blocks */
18085 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18086 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
18088 if (CHIP_IS_MODE_4_PORT(sc))
18089 dsb_idx = SC_FUNC(sc);
18091 dsb_idx = SC_VN(sc);
18093 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
18094 IGU_BC_BASE_DSB_PROD + dsb_idx :
18095 IGU_NORM_BASE_DSB_PROD + dsb_idx);
18098 * igu prods come in chunks of E1HVN_MAX (4) -
18099 * does not matters what is the current chip mode
18101 for (i = 0; i < (num_segs * E1HVN_MAX);
18103 addr = IGU_REG_PROD_CONS_MEMORY +
18104 (prod_offset + i)*4;
18105 REG_WR(sc, addr, 0);
18107 /* send consumer update with 0 */
18108 if (CHIP_INT_MODE_IS_BC(sc)) {
18109 bxe_ack_sb(sc, sc->igu_dsb_id,
18110 USTORM_ID, 0, IGU_INT_NOP, 1);
18111 bxe_ack_sb(sc, sc->igu_dsb_id,
18112 CSTORM_ID, 0, IGU_INT_NOP, 1);
18113 bxe_ack_sb(sc, sc->igu_dsb_id,
18114 XSTORM_ID, 0, IGU_INT_NOP, 1);
18115 bxe_ack_sb(sc, sc->igu_dsb_id,
18116 TSTORM_ID, 0, IGU_INT_NOP, 1);
18117 bxe_ack_sb(sc, sc->igu_dsb_id,
18118 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18120 bxe_ack_sb(sc, sc->igu_dsb_id,
18121 USTORM_ID, 0, IGU_INT_NOP, 1);
18122 bxe_ack_sb(sc, sc->igu_dsb_id,
18123 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18125 bxe_igu_clear_sb(sc, sc->igu_dsb_id);
18127 /* !!! these should become driver const once
18128 rf-tool supports split-68 const */
18129 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
18130 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
18131 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
18132 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
18133 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
18134 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
18138 /* Reset PCIE errors for debug */
18139 REG_WR(sc, 0x2114, 0xffffffff);
18140 REG_WR(sc, 0x2120, 0xffffffff);
18142 if (CHIP_IS_E1x(sc)) {
18143 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
18144 main_mem_base = HC_REG_MAIN_MEMORY +
18145 SC_PORT(sc) * (main_mem_size * 4);
18146 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
18147 main_mem_width = 8;
18149 val = REG_RD(sc, main_mem_prty_clr);
18151 BLOGD(sc, DBG_LOAD,
18152 "Parity errors in HC block during function init (0x%x)!\n",
18156 /* Clear "false" parity errors in MSI-X table */
18157 for (i = main_mem_base;
18158 i < main_mem_base + main_mem_size * 4;
18159 i += main_mem_width) {
18160 bxe_read_dmae(sc, i, main_mem_width / 4);
18161 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data),
18162 i, main_mem_width / 4);
18164 /* Clear HC parity attention */
18165 REG_RD(sc, main_mem_prty_clr);
18169 /* Enable STORMs SP logging */
18170 REG_WR8(sc, BAR_USTRORM_INTMEM +
18171 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18172 REG_WR8(sc, BAR_TSTRORM_INTMEM +
18173 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18174 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18175 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18176 REG_WR8(sc, BAR_XSTRORM_INTMEM +
18177 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18180 elink_phy_probe(&sc->link_params);
18186 bxe_link_reset(struct bxe_softc *sc)
18188 if (!BXE_NOMCP(sc)) {
18189 bxe_acquire_phy_lock(sc);
18190 elink_lfa_reset(&sc->link_params, &sc->link_vars);
18191 bxe_release_phy_lock(sc);
18193 if (!CHIP_REV_IS_SLOW(sc)) {
18194 BLOGW(sc, "Bootcode is missing - cannot reset link\n");
18200 bxe_reset_port(struct bxe_softc *sc)
18202 int port = SC_PORT(sc);
18205 ELINK_DEBUG_P0(sc, "bxe_reset_port called\n");
18206 /* reset physical Link */
18207 bxe_link_reset(sc);
18209 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
18211 /* Do not rcv packets to BRB */
18212 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
18213 /* Do not direct rcv packets that are not for MCP to the BRB */
18214 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
18215 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
18217 /* Configure AEU */
18218 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
18222 /* Check for BRB port occupancy */
18223 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
18225 BLOGD(sc, DBG_LOAD,
18226 "BRB1 is not empty, %d blocks are occupied\n", val);
18229 /* TODO: Close Doorbell port? */
18233 bxe_ilt_wr(struct bxe_softc *sc,
18238 uint32_t wb_write[2];
18240 if (CHIP_IS_E1(sc)) {
18241 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
18243 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
18246 wb_write[0] = ONCHIP_ADDR1(addr);
18247 wb_write[1] = ONCHIP_ADDR2(addr);
18248 REG_WR_DMAE(sc, reg, wb_write, 2);
18252 bxe_clear_func_ilt(struct bxe_softc *sc,
18255 uint32_t i, base = FUNC_ILT_BASE(func);
18256 for (i = base; i < base + ILT_PER_FUNC; i++) {
18257 bxe_ilt_wr(sc, i, 0);
18262 bxe_reset_func(struct bxe_softc *sc)
18264 struct bxe_fastpath *fp;
18265 int port = SC_PORT(sc);
18266 int func = SC_FUNC(sc);
18269 /* Disable the function in the FW */
18270 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
18271 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
18272 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
18273 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
18276 FOR_EACH_ETH_QUEUE(sc, i) {
18278 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18279 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
18284 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18285 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
18288 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
18289 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0);
18292 /* Configure IGU */
18293 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18294 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18295 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18297 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18298 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18301 if (CNIC_LOADED(sc)) {
18302 /* Disable Timer scan */
18303 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
18305 * Wait for at least 10ms and up to 2 second for the timers
18308 for (i = 0; i < 200; i++) {
18310 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4))
18316 bxe_clear_func_ilt(sc, func);
18319 * Timers workaround bug for E2: if this is vnic-3,
18320 * we need to set the entire ilt range for this timers.
18322 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
18323 struct ilt_client_info ilt_cli;
18324 /* use dummy TM client */
18325 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
18327 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
18328 ilt_cli.client_num = ILT_CLIENT_TM;
18330 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
18333 /* this assumes that reset_port() called before reset_func()*/
18334 if (!CHIP_IS_E1x(sc)) {
18335 bxe_pf_disable(sc);
18338 sc->dmae_ready = 0;
18342 bxe_gunzip_init(struct bxe_softc *sc)
18348 bxe_gunzip_end(struct bxe_softc *sc)
18354 bxe_init_firmware(struct bxe_softc *sc)
18356 if (CHIP_IS_E1(sc)) {
18357 ecore_init_e1_firmware(sc);
18358 sc->iro_array = e1_iro_arr;
18359 } else if (CHIP_IS_E1H(sc)) {
18360 ecore_init_e1h_firmware(sc);
18361 sc->iro_array = e1h_iro_arr;
18362 } else if (!CHIP_IS_E1x(sc)) {
18363 ecore_init_e2_firmware(sc);
18364 sc->iro_array = e2_iro_arr;
18366 BLOGE(sc, "Unsupported chip revision\n");
18374 bxe_release_firmware(struct bxe_softc *sc)
18381 ecore_gunzip(struct bxe_softc *sc,
18382 const uint8_t *zbuf,
18385 /* XXX : Implement... */
18386 BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n");
18391 ecore_reg_wr_ind(struct bxe_softc *sc,
18395 bxe_reg_wr_ind(sc, addr, val);
18399 ecore_write_dmae_phys_len(struct bxe_softc *sc,
18400 bus_addr_t phys_addr,
18404 bxe_write_dmae_phys_len(sc, phys_addr, addr, len);
18408 ecore_storm_memset_struct(struct bxe_softc *sc,
18414 for (i = 0; i < size/4; i++) {
18415 REG_WR(sc, addr + (i * 4), data[i]);
18421 * character device - ioctl interface definitions
18425 #include "bxe_dump.h"
18426 #include "bxe_ioctl.h"
18427 #include <sys/conf.h>
18429 static int bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
18430 struct thread *td);
18432 static struct cdevsw bxe_cdevsw = {
18433 .d_version = D_VERSION,
18434 .d_ioctl = bxe_eioctl,
18435 .d_name = "bxecnic",
18438 #define BXE_PATH(sc) (CHIP_IS_E1x(sc) ? 0 : (sc->pcie_func & 1))
18441 #define DUMP_ALL_PRESETS 0x1FFF
18442 #define DUMP_MAX_PRESETS 13
18443 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
18444 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
18445 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
18446 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
18447 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
18449 #define IS_REG_IN_PRESET(presets, idx) \
18450 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
18454 bxe_get_preset_regs_len(struct bxe_softc *sc, uint32_t preset)
18456 if (CHIP_IS_E1(sc))
18457 return dump_num_registers[0][preset-1];
18458 else if (CHIP_IS_E1H(sc))
18459 return dump_num_registers[1][preset-1];
18460 else if (CHIP_IS_E2(sc))
18461 return dump_num_registers[2][preset-1];
18462 else if (CHIP_IS_E3A0(sc))
18463 return dump_num_registers[3][preset-1];
18464 else if (CHIP_IS_E3B0(sc))
18465 return dump_num_registers[4][preset-1];
18471 bxe_get_total_regs_len32(struct bxe_softc *sc)
18473 uint32_t preset_idx;
18474 int regdump_len32 = 0;
18477 /* Calculate the total preset regs length */
18478 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
18479 regdump_len32 += bxe_get_preset_regs_len(sc, preset_idx);
18482 return regdump_len32;
18485 static const uint32_t *
18486 __bxe_get_page_addr_ar(struct bxe_softc *sc)
18488 if (CHIP_IS_E2(sc))
18489 return page_vals_e2;
18490 else if (CHIP_IS_E3(sc))
18491 return page_vals_e3;
18497 __bxe_get_page_reg_num(struct bxe_softc *sc)
18499 if (CHIP_IS_E2(sc))
18500 return PAGE_MODE_VALUES_E2;
18501 else if (CHIP_IS_E3(sc))
18502 return PAGE_MODE_VALUES_E3;
18507 static const uint32_t *
18508 __bxe_get_page_write_ar(struct bxe_softc *sc)
18510 if (CHIP_IS_E2(sc))
18511 return page_write_regs_e2;
18512 else if (CHIP_IS_E3(sc))
18513 return page_write_regs_e3;
18519 __bxe_get_page_write_num(struct bxe_softc *sc)
18521 if (CHIP_IS_E2(sc))
18522 return PAGE_WRITE_REGS_E2;
18523 else if (CHIP_IS_E3(sc))
18524 return PAGE_WRITE_REGS_E3;
18529 static const struct reg_addr *
18530 __bxe_get_page_read_ar(struct bxe_softc *sc)
18532 if (CHIP_IS_E2(sc))
18533 return page_read_regs_e2;
18534 else if (CHIP_IS_E3(sc))
18535 return page_read_regs_e3;
18541 __bxe_get_page_read_num(struct bxe_softc *sc)
18543 if (CHIP_IS_E2(sc))
18544 return PAGE_READ_REGS_E2;
18545 else if (CHIP_IS_E3(sc))
18546 return PAGE_READ_REGS_E3;
18552 bxe_is_reg_in_chip(struct bxe_softc *sc, const struct reg_addr *reg_info)
18554 if (CHIP_IS_E1(sc))
18555 return IS_E1_REG(reg_info->chips);
18556 else if (CHIP_IS_E1H(sc))
18557 return IS_E1H_REG(reg_info->chips);
18558 else if (CHIP_IS_E2(sc))
18559 return IS_E2_REG(reg_info->chips);
18560 else if (CHIP_IS_E3A0(sc))
18561 return IS_E3A0_REG(reg_info->chips);
18562 else if (CHIP_IS_E3B0(sc))
18563 return IS_E3B0_REG(reg_info->chips);
18569 bxe_is_wreg_in_chip(struct bxe_softc *sc, const struct wreg_addr *wreg_info)
18571 if (CHIP_IS_E1(sc))
18572 return IS_E1_REG(wreg_info->chips);
18573 else if (CHIP_IS_E1H(sc))
18574 return IS_E1H_REG(wreg_info->chips);
18575 else if (CHIP_IS_E2(sc))
18576 return IS_E2_REG(wreg_info->chips);
18577 else if (CHIP_IS_E3A0(sc))
18578 return IS_E3A0_REG(wreg_info->chips);
18579 else if (CHIP_IS_E3B0(sc))
18580 return IS_E3B0_REG(wreg_info->chips);
18586 * bxe_read_pages_regs - read "paged" registers
18588 * @bp device handle
18591 * Reads "paged" memories: memories that may only be read by first writing to a
18592 * specific address ("write address") and then reading from a specific address
18593 * ("read address"). There may be more than one write address per "page" and
18594 * more than one read address per write address.
18597 bxe_read_pages_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
18599 uint32_t i, j, k, n;
18601 /* addresses of the paged registers */
18602 const uint32_t *page_addr = __bxe_get_page_addr_ar(sc);
18603 /* number of paged registers */
18604 int num_pages = __bxe_get_page_reg_num(sc);
18605 /* write addresses */
18606 const uint32_t *write_addr = __bxe_get_page_write_ar(sc);
18607 /* number of write addresses */
18608 int write_num = __bxe_get_page_write_num(sc);
18609 /* read addresses info */
18610 const struct reg_addr *read_addr = __bxe_get_page_read_ar(sc);
18611 /* number of read addresses */
18612 int read_num = __bxe_get_page_read_num(sc);
18613 uint32_t addr, size;
18615 for (i = 0; i < num_pages; i++) {
18616 for (j = 0; j < write_num; j++) {
18617 REG_WR(sc, write_addr[j], page_addr[i]);
18619 for (k = 0; k < read_num; k++) {
18620 if (IS_REG_IN_PRESET(read_addr[k].presets, preset)) {
18621 size = read_addr[k].size;
18622 for (n = 0; n < size; n++) {
18623 addr = read_addr[k].addr + n*4;
18624 *p++ = REG_RD(sc, addr);
18635 bxe_get_preset_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
18637 uint32_t i, j, addr;
18638 const struct wreg_addr *wreg_addr_p = NULL;
18640 if (CHIP_IS_E1(sc))
18641 wreg_addr_p = &wreg_addr_e1;
18642 else if (CHIP_IS_E1H(sc))
18643 wreg_addr_p = &wreg_addr_e1h;
18644 else if (CHIP_IS_E2(sc))
18645 wreg_addr_p = &wreg_addr_e2;
18646 else if (CHIP_IS_E3A0(sc))
18647 wreg_addr_p = &wreg_addr_e3;
18648 else if (CHIP_IS_E3B0(sc))
18649 wreg_addr_p = &wreg_addr_e3b0;
18653 /* Read the idle_chk registers */
18654 for (i = 0; i < IDLE_REGS_COUNT; i++) {
18655 if (bxe_is_reg_in_chip(sc, &idle_reg_addrs[i]) &&
18656 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
18657 for (j = 0; j < idle_reg_addrs[i].size; j++)
18658 *p++ = REG_RD(sc, idle_reg_addrs[i].addr + j*4);
18662 /* Read the regular registers */
18663 for (i = 0; i < REGS_COUNT; i++) {
18664 if (bxe_is_reg_in_chip(sc, ®_addrs[i]) &&
18665 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
18666 for (j = 0; j < reg_addrs[i].size; j++)
18667 *p++ = REG_RD(sc, reg_addrs[i].addr + j*4);
18671 /* Read the CAM registers */
18672 if (bxe_is_wreg_in_chip(sc, wreg_addr_p) &&
18673 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
18674 for (i = 0; i < wreg_addr_p->size; i++) {
18675 *p++ = REG_RD(sc, wreg_addr_p->addr + i*4);
18677 /* In case of wreg_addr register, read additional
18678 registers from read_regs array
18680 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
18681 addr = *(wreg_addr_p->read_regs);
18682 *p++ = REG_RD(sc, addr + j*4);
18687 /* Paged registers are supported in E2 & E3 only */
18688 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
18689 /* Read "paged" registers */
18690 bxe_read_pages_regs(sc, p, preset);
18697 bxe_grc_dump(struct bxe_softc *sc)
18700 uint32_t preset_idx;
18703 struct dump_header *d_hdr;
18707 uint32_t cmd_offset;
18708 struct ecore_ilt *ilt = SC_ILT(sc);
18709 struct bxe_fastpath *fp;
18710 struct ilt_client_info *ilt_cli;
18714 if (sc->grcdump_done || sc->grcdump_started)
18717 sc->grcdump_started = 1;
18718 BLOGI(sc, "Started collecting grcdump\n");
18720 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
18721 sizeof(struct dump_header);
18723 sc->grc_dump = malloc(grc_dump_size, M_DEVBUF, M_NOWAIT);
18725 if (sc->grc_dump == NULL) {
18726 BLOGW(sc, "Unable to allocate memory for grcdump collection\n");
18732 /* Disable parity attentions as long as following dump may
18733 * cause false alarms by reading never written registers. We
18734 * will re-enable parity attentions right after the dump.
18737 /* Disable parity on path 0 */
18738 bxe_pretend_func(sc, 0);
18740 ecore_disable_blocks_parity(sc);
18742 /* Disable parity on path 1 */
18743 bxe_pretend_func(sc, 1);
18744 ecore_disable_blocks_parity(sc);
18746 /* Return to current function */
18747 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
18749 buf = sc->grc_dump;
18750 d_hdr = sc->grc_dump;
18752 d_hdr->header_size = (sizeof(struct dump_header) >> 2) - 1;
18753 d_hdr->version = BNX2X_DUMP_VERSION;
18754 d_hdr->preset = DUMP_ALL_PRESETS;
18756 if (CHIP_IS_E1(sc)) {
18757 d_hdr->dump_meta_data = DUMP_CHIP_E1;
18758 } else if (CHIP_IS_E1H(sc)) {
18759 d_hdr->dump_meta_data = DUMP_CHIP_E1H;
18760 } else if (CHIP_IS_E2(sc)) {
18761 d_hdr->dump_meta_data = DUMP_CHIP_E2 |
18762 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18763 } else if (CHIP_IS_E3A0(sc)) {
18764 d_hdr->dump_meta_data = DUMP_CHIP_E3A0 |
18765 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18766 } else if (CHIP_IS_E3B0(sc)) {
18767 d_hdr->dump_meta_data = DUMP_CHIP_E3B0 |
18768 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18771 buf += sizeof(struct dump_header);
18773 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
18775 /* Skip presets with IOR */
18776 if ((preset_idx == 2) || (preset_idx == 5) || (preset_idx == 8) ||
18777 (preset_idx == 11))
18780 rval = bxe_get_preset_regs(sc, (uint32_t *)buf, preset_idx);
18785 size = bxe_get_preset_regs_len(sc, preset_idx) * (sizeof (uint32_t));
18790 bxe_pretend_func(sc, 0);
18791 ecore_clear_blocks_parity(sc);
18792 ecore_enable_blocks_parity(sc);
18794 bxe_pretend_func(sc, 1);
18795 ecore_clear_blocks_parity(sc);
18796 ecore_enable_blocks_parity(sc);
18798 /* Return to current function */
18799 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
18803 if(sc->state == BXE_STATE_OPEN) {
18804 if(sc->fw_stats_req != NULL) {
18805 BLOGI(sc, "fw stats start_paddr %#jx end_paddr %#jx vaddr %p size 0x%x\n",
18806 (uintmax_t)sc->fw_stats_req_mapping,
18807 (uintmax_t)sc->fw_stats_data_mapping,
18808 sc->fw_stats_req, (sc->fw_stats_req_size + sc->fw_stats_data_size));
18810 if(sc->def_sb != NULL) {
18811 BLOGI(sc, "def_status_block paddr %p vaddr %p size 0x%zx\n",
18812 (void *)sc->def_sb_dma.paddr, sc->def_sb,
18813 sizeof(struct host_sp_status_block));
18815 if(sc->eq_dma.vaddr != NULL) {
18816 BLOGI(sc, "event_queue paddr %#jx vaddr %p size 0x%x\n",
18817 (uintmax_t)sc->eq_dma.paddr, sc->eq_dma.vaddr, BCM_PAGE_SIZE);
18819 if(sc->sp_dma.vaddr != NULL) {
18820 BLOGI(sc, "slow path paddr %#jx vaddr %p size 0x%zx\n",
18821 (uintmax_t)sc->sp_dma.paddr, sc->sp_dma.vaddr,
18822 sizeof(struct bxe_slowpath));
18824 if(sc->spq_dma.vaddr != NULL) {
18825 BLOGI(sc, "slow path queue paddr %#jx vaddr %p size 0x%x\n",
18826 (uintmax_t)sc->spq_dma.paddr, sc->spq_dma.vaddr, BCM_PAGE_SIZE);
18828 if(sc->gz_buf_dma.vaddr != NULL) {
18829 BLOGI(sc, "fw_buf paddr %#jx vaddr %p size 0x%x\n",
18830 (uintmax_t)sc->gz_buf_dma.paddr, sc->gz_buf_dma.vaddr,
18833 for (i = 0; i < sc->num_queues; i++) {
18835 if(fp->sb_dma.vaddr != NULL && fp->tx_dma.vaddr != NULL &&
18836 fp->rx_dma.vaddr != NULL && fp->rcq_dma.vaddr != NULL &&
18837 fp->rx_sge_dma.vaddr != NULL) {
18839 BLOGI(sc, "FP status block fp %d paddr %#jx vaddr %p size 0x%zx\n", i,
18840 (uintmax_t)fp->sb_dma.paddr, fp->sb_dma.vaddr,
18841 sizeof(union bxe_host_hc_status_block));
18842 BLOGI(sc, "TX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
18843 (uintmax_t)fp->tx_dma.paddr, fp->tx_dma.vaddr,
18844 (BCM_PAGE_SIZE * TX_BD_NUM_PAGES));
18845 BLOGI(sc, "RX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
18846 (uintmax_t)fp->rx_dma.paddr, fp->rx_dma.vaddr,
18847 (BCM_PAGE_SIZE * RX_BD_NUM_PAGES));
18848 BLOGI(sc, "RX RCQ CHAIN fp %d paddr %#jx vaddr %p size 0x%zx\n", i,
18849 (uintmax_t)fp->rcq_dma.paddr, fp->rcq_dma.vaddr,
18850 (BCM_PAGE_SIZE * RCQ_NUM_PAGES));
18851 BLOGI(sc, "RX SGE CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
18852 (uintmax_t)fp->rx_sge_dma.paddr, fp->rx_sge_dma.vaddr,
18853 (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES));
18857 ilt_cli = &ilt->clients[1];
18858 if(ilt->lines != NULL) {
18859 for (i = ilt_cli->start; i <= ilt_cli->end; i++) {
18860 BLOGI(sc, "ECORE_ILT paddr %#jx vaddr %p size 0x%x\n",
18861 (uintmax_t)(((struct bxe_dma *)((&ilt->lines[i])->page))->paddr),
18862 ((struct bxe_dma *)((&ilt->lines[i])->page))->vaddr, BCM_PAGE_SIZE);
18868 cmd_offset = DMAE_REG_CMD_MEM;
18869 for (i = 0; i < 224; i++) {
18870 reg_addr = (cmd_offset +(i * 4));
18871 reg_val = REG_RD(sc, reg_addr);
18872 BLOGI(sc, "DMAE_REG_CMD_MEM i=%d reg_addr 0x%x reg_val 0x%08x\n",i,
18873 reg_addr, reg_val);
18877 BLOGI(sc, "Collection of grcdump done\n");
18878 sc->grcdump_done = 1;
18883 bxe_add_cdev(struct bxe_softc *sc)
18885 sc->eeprom = malloc(BXE_EEPROM_MAX_DATA_LEN, M_DEVBUF, M_NOWAIT);
18887 if (sc->eeprom == NULL) {
18888 BLOGW(sc, "Unable to alloc for eeprom size buffer\n");
18892 sc->ioctl_dev = make_dev(&bxe_cdevsw,
18893 sc->ifnet->if_dunit,
18898 if_name(sc->ifnet));
18900 if (sc->ioctl_dev == NULL) {
18901 free(sc->eeprom, M_DEVBUF);
18906 sc->ioctl_dev->si_drv1 = sc;
18912 bxe_del_cdev(struct bxe_softc *sc)
18914 if (sc->ioctl_dev != NULL)
18915 destroy_dev(sc->ioctl_dev);
18917 if (sc->eeprom != NULL) {
18918 free(sc->eeprom, M_DEVBUF);
18921 sc->ioctl_dev = NULL;
18926 static bool bxe_is_nvram_accessible(struct bxe_softc *sc)
18929 if ((sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) == 0)
18937 bxe_wr_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
18941 if(!bxe_is_nvram_accessible(sc)) {
18942 BLOGW(sc, "Cannot access eeprom when interface is down\n");
18945 rval = bxe_nvram_write(sc, offset, (uint8_t *)data, len);
18952 bxe_rd_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
18956 if(!bxe_is_nvram_accessible(sc)) {
18957 BLOGW(sc, "Cannot access eeprom when interface is down\n");
18960 rval = bxe_nvram_read(sc, offset, (uint8_t *)data, len);
18966 bxe_eeprom_rd_wr(struct bxe_softc *sc, bxe_eeprom_t *eeprom)
18970 switch (eeprom->eeprom_cmd) {
18972 case BXE_EEPROM_CMD_SET_EEPROM:
18974 rval = copyin(eeprom->eeprom_data, sc->eeprom,
18975 eeprom->eeprom_data_len);
18980 rval = bxe_wr_eeprom(sc, sc->eeprom, eeprom->eeprom_offset,
18981 eeprom->eeprom_data_len);
18984 case BXE_EEPROM_CMD_GET_EEPROM:
18986 rval = bxe_rd_eeprom(sc, sc->eeprom, eeprom->eeprom_offset,
18987 eeprom->eeprom_data_len);
18993 rval = copyout(sc->eeprom, eeprom->eeprom_data,
18994 eeprom->eeprom_data_len);
19003 BLOGW(sc, "ioctl cmd %d failed rval %d\n", eeprom->eeprom_cmd, rval);
19010 bxe_get_settings(struct bxe_softc *sc, bxe_dev_setting_t *dev_p)
19012 uint32_t ext_phy_config;
19013 int port = SC_PORT(sc);
19014 int cfg_idx = bxe_get_link_cfg_idx(sc);
19016 dev_p->supported = sc->port.supported[cfg_idx] |
19017 (sc->port.supported[cfg_idx ^ 1] &
19018 (ELINK_SUPPORTED_TP | ELINK_SUPPORTED_FIBRE));
19019 dev_p->advertising = sc->port.advertising[cfg_idx];
19020 if(sc->link_params.phy[bxe_get_cur_phy_idx(sc)].media_type ==
19021 ELINK_ETH_PHY_SFP_1G_FIBER) {
19022 dev_p->supported = ~(ELINK_SUPPORTED_10000baseT_Full);
19023 dev_p->advertising &= ~(ADVERTISED_10000baseT_Full);
19025 if ((sc->state == BXE_STATE_OPEN) && sc->link_vars.link_up &&
19026 !(sc->flags & BXE_MF_FUNC_DIS)) {
19027 dev_p->duplex = sc->link_vars.duplex;
19028 if (IS_MF(sc) && !BXE_NOMCP(sc))
19029 dev_p->speed = bxe_get_mf_speed(sc);
19031 dev_p->speed = sc->link_vars.line_speed;
19033 dev_p->duplex = DUPLEX_UNKNOWN;
19034 dev_p->speed = SPEED_UNKNOWN;
19037 dev_p->port = bxe_media_detect(sc);
19039 ext_phy_config = SHMEM_RD(sc,
19040 dev_info.port_hw_config[port].external_phy_config);
19041 if((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) ==
19042 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
19043 dev_p->phy_address = sc->port.phy_addr;
19044 else if(((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) !=
19045 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
19046 ((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) !=
19047 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
19048 dev_p->phy_address = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
19050 dev_p->phy_address = 0;
19052 if(sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG)
19053 dev_p->autoneg = AUTONEG_ENABLE;
19055 dev_p->autoneg = AUTONEG_DISABLE;
19062 bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
19065 struct bxe_softc *sc;
19068 bxe_grcdump_t *dump = NULL;
19070 bxe_drvinfo_t *drv_infop = NULL;
19071 bxe_dev_setting_t *dev_p;
19072 bxe_dev_setting_t dev_set;
19073 bxe_get_regs_t *reg_p;
19074 bxe_reg_rdw_t *reg_rdw_p;
19075 bxe_pcicfg_rdw_t *cfg_rdw_p;
19076 bxe_perm_mac_addr_t *mac_addr_p;
19079 if ((sc = (struct bxe_softc *)dev->si_drv1) == NULL)
19084 dump = (bxe_grcdump_t *)data;
19088 case BXE_GRC_DUMP_SIZE:
19089 dump->pci_func = sc->pcie_func;
19090 dump->grcdump_size =
19091 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
19092 sizeof(struct dump_header);
19097 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
19098 sizeof(struct dump_header);
19099 if ((!sc->trigger_grcdump) || (dump->grcdump == NULL) ||
19100 (dump->grcdump_size < grc_dump_size)) {
19105 if((sc->trigger_grcdump) && (!sc->grcdump_done) &&
19106 (!sc->grcdump_started)) {
19107 rval = bxe_grc_dump(sc);
19110 if((!rval) && (sc->grcdump_done) && (sc->grcdump_started) &&
19111 (sc->grc_dump != NULL)) {
19112 dump->grcdump_dwords = grc_dump_size >> 2;
19113 rval = copyout(sc->grc_dump, dump->grcdump, grc_dump_size);
19114 free(sc->grc_dump, M_DEVBUF);
19115 sc->grc_dump = NULL;
19116 sc->grcdump_started = 0;
19117 sc->grcdump_done = 0;
19123 drv_infop = (bxe_drvinfo_t *)data;
19124 snprintf(drv_infop->drv_name, BXE_DRV_NAME_LENGTH, "%s", "bxe");
19125 snprintf(drv_infop->drv_version, BXE_DRV_VERSION_LENGTH, "v:%s",
19126 BXE_DRIVER_VERSION);
19127 snprintf(drv_infop->mfw_version, BXE_MFW_VERSION_LENGTH, "%s",
19128 sc->devinfo.bc_ver_str);
19129 snprintf(drv_infop->stormfw_version, BXE_STORMFW_VERSION_LENGTH,
19130 "%s", sc->fw_ver_str);
19131 drv_infop->eeprom_dump_len = sc->devinfo.flash_size;
19132 drv_infop->reg_dump_len =
19133 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t))
19134 + sizeof(struct dump_header);
19135 snprintf(drv_infop->bus_info, BXE_BUS_INFO_LENGTH, "%d:%d:%d",
19136 sc->pcie_bus, sc->pcie_device, sc->pcie_func);
19139 case BXE_DEV_SETTING:
19140 dev_p = (bxe_dev_setting_t *)data;
19141 bxe_get_settings(sc, &dev_set);
19142 dev_p->supported = dev_set.supported;
19143 dev_p->advertising = dev_set.advertising;
19144 dev_p->speed = dev_set.speed;
19145 dev_p->duplex = dev_set.duplex;
19146 dev_p->port = dev_set.port;
19147 dev_p->phy_address = dev_set.phy_address;
19148 dev_p->autoneg = dev_set.autoneg;
19154 reg_p = (bxe_get_regs_t *)data;
19155 grc_dump_size = reg_p->reg_buf_len;
19157 if((!sc->grcdump_done) && (!sc->grcdump_started)) {
19160 if((sc->grcdump_done) && (sc->grcdump_started) &&
19161 (sc->grc_dump != NULL)) {
19162 rval = copyout(sc->grc_dump, reg_p->reg_buf, grc_dump_size);
19163 free(sc->grc_dump, M_DEVBUF);
19164 sc->grc_dump = NULL;
19165 sc->grcdump_started = 0;
19166 sc->grcdump_done = 0;
19172 reg_rdw_p = (bxe_reg_rdw_t *)data;
19173 if((reg_rdw_p->reg_cmd == BXE_READ_REG_CMD) &&
19174 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT))
19175 reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id);
19177 if((reg_rdw_p->reg_cmd == BXE_WRITE_REG_CMD) &&
19178 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT))
19179 REG_WR(sc, reg_rdw_p->reg_id, reg_rdw_p->reg_val);
19183 case BXE_RDW_PCICFG:
19184 cfg_rdw_p = (bxe_pcicfg_rdw_t *)data;
19185 if(cfg_rdw_p->cfg_cmd == BXE_READ_PCICFG) {
19187 cfg_rdw_p->cfg_val = pci_read_config(sc->dev, cfg_rdw_p->cfg_id,
19188 cfg_rdw_p->cfg_width);
19190 } else if(cfg_rdw_p->cfg_cmd == BXE_WRITE_PCICFG) {
19191 pci_write_config(sc->dev, cfg_rdw_p->cfg_id, cfg_rdw_p->cfg_val,
19192 cfg_rdw_p->cfg_width);
19194 BLOGW(sc, "BXE_RDW_PCICFG ioctl wrong cmd passed\n");
19199 mac_addr_p = (bxe_perm_mac_addr_t *)data;
19200 snprintf(mac_addr_p->mac_addr_str, sizeof(sc->mac_addr_str), "%s",
19205 rval = bxe_eeprom_rd_wr(sc, (bxe_eeprom_t *)data);