2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
36 #include <sys/socket.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/queue.h>
41 #include <sys/taskqueue.h>
43 #include <sys/sglist.h>
44 #include <sys/sysctl.h>
46 #include <sys/counter.h>
48 #include <net/ethernet.h>
50 #include <net/if_vlan_var.h>
51 #include <netinet/in.h>
52 #include <netinet/ip.h>
53 #include <netinet/ip6.h>
54 #include <netinet/tcp.h>
55 #include <machine/in_cksum.h>
56 #include <machine/md_var.h>
60 #include <machine/bus.h>
61 #include <sys/selinfo.h>
62 #include <net/if_var.h>
63 #include <net/netmap.h>
64 #include <dev/netmap/netmap_kern.h>
67 #include "common/common.h"
68 #include "common/t4_regs.h"
69 #include "common/t4_regs_values.h"
70 #include "common/t4_msg.h"
72 #include "t4_mp_ring.h"
74 #ifdef T4_PKT_TIMESTAMP
75 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
77 #define RX_COPY_THRESHOLD MINCLSIZE
81 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
82 * 0-7 are valid values.
84 static int fl_pktshift = 2;
85 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
88 * Pad ethernet payload up to this boundary.
89 * -1: driver should figure out a good value.
91 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
94 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
98 * -1: driver should figure out a good value.
99 * 64 or 128 are the only other valid values.
101 static int spg_len = -1;
102 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
106 * -1: no congestion feedback (not recommended).
107 * 0: backpressure the channel instead of dropping packets right away.
108 * 1: no backpressure, drop packets for the congested queue immediately.
110 static int cong_drop = 0;
111 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
114 * Deliver multiple frames in the same free list buffer if they fit.
115 * -1: let the driver decide whether to enable buffer packing or not.
116 * 0: disable buffer packing.
117 * 1: enable buffer packing.
119 static int buffer_packing = -1;
120 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
123 * Start next frame in a packed buffer at this boundary.
124 * -1: driver should figure out a good value.
125 * T4: driver will ignore this and use the same value as fl_pad above.
126 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
128 static int fl_pack = -1;
129 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
132 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
133 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
134 * 1: ok to create mbuf(s) within a cluster if there is room.
136 static int allow_mbufs_in_cluster = 1;
137 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
140 * Largest rx cluster size that the driver is allowed to allocate.
142 static int largest_rx_cluster = MJUM16BYTES;
143 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
146 * Size of cluster allocation that's most likely to succeed. The driver will
147 * fall back to this size if it fails to allocate clusters larger than this.
149 static int safest_rx_cluster = PAGE_SIZE;
150 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
153 u_int wr_type; /* type 0 or type 1 */
154 u_int npkt; /* # of packets in this work request */
155 u_int plen; /* total payload (sum of all packets) */
156 u_int len16; /* # of 16B pieces used by this work request */
159 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
162 struct sglist_seg seg[TX_SGL_SEGS];
165 static int service_iq(struct sge_iq *, int);
166 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
167 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
168 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
169 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
170 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
172 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
173 bus_addr_t *, void **);
174 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
176 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
178 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
179 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
180 struct sysctl_oid *, struct sge_fl *);
181 static int alloc_fwq(struct adapter *);
182 static int free_fwq(struct adapter *);
183 static int alloc_mgmtq(struct adapter *);
184 static int free_mgmtq(struct adapter *);
185 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
186 struct sysctl_oid *);
187 static int free_rxq(struct vi_info *, struct sge_rxq *);
189 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
190 struct sysctl_oid *);
191 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
194 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
195 struct sysctl_oid *);
196 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
197 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
198 struct sysctl_oid *);
199 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
201 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
202 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
204 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
206 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
207 static int free_eq(struct adapter *, struct sge_eq *);
208 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
209 struct sysctl_oid *);
210 static int free_wrq(struct adapter *, struct sge_wrq *);
211 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
212 struct sysctl_oid *);
213 static int free_txq(struct vi_info *, struct sge_txq *);
214 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
215 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
216 static int refill_fl(struct adapter *, struct sge_fl *, int);
217 static void refill_sfl(void *);
218 static int alloc_fl_sdesc(struct sge_fl *);
219 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
220 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
221 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
222 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
224 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
225 static inline u_int txpkt_len16(u_int, u_int);
226 static inline u_int txpkt_vm_len16(u_int, u_int);
227 static inline u_int txpkts0_len16(u_int);
228 static inline u_int txpkts1_len16(void);
229 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
230 struct mbuf *, u_int);
231 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
232 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
233 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
234 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
235 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
236 struct mbuf *, const struct txpkts *, u_int);
237 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
238 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
239 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
240 static inline uint16_t read_hw_cidx(struct sge_eq *);
241 static inline u_int reclaimable_tx_desc(struct sge_eq *);
242 static inline u_int total_available_tx_desc(struct sge_eq *);
243 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
244 static void tx_reclaim(void *, int);
245 static __be64 get_flit(struct sglist_seg *, int, int);
246 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
248 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
250 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
251 static void wrq_tx_drain(void *, int);
252 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
254 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
255 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
256 static int sysctl_tc(SYSCTL_HANDLER_ARGS);
258 static counter_u64_t extfree_refs;
259 static counter_u64_t extfree_rels;
261 an_handler_t t4_an_handler;
262 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
263 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
267 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl)
271 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl);
273 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n",
280 t4_register_an_handler(an_handler_t h)
284 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled;
285 loc = (uintptr_t *) &t4_an_handler;
286 atomic_store_rel_ptr(loc, new);
292 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl)
294 const struct cpl_fw6_msg *cpl =
295 __containerof(rpl, struct cpl_fw6_msg, data[0]);
298 panic("%s: fw_msg type %d", __func__, cpl->type);
300 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type);
306 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
310 if (type >= nitems(t4_fw_msg_handler))
314 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
315 * handler dispatch table. Reject any attempt to install a handler for
318 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL)
321 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled;
322 loc = (uintptr_t *) &t4_fw_msg_handler[type];
323 atomic_store_rel_ptr(loc, new);
329 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
333 panic("%s: opcode 0x%02x on iq %p with payload %p",
334 __func__, rss->opcode, iq, m);
336 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n",
337 __func__, rss->opcode, iq, m);
344 t4_register_cpl_handler(int opcode, cpl_handler_t h)
348 if (opcode >= nitems(t4_cpl_handler))
351 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled;
352 loc = (uintptr_t *) &t4_cpl_handler[opcode];
353 atomic_store_rel_ptr(loc, new);
359 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
366 if (fl_pktshift < 0 || fl_pktshift > 7) {
367 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
368 " using 2 instead.\n", fl_pktshift);
372 if (spg_len != 64 && spg_len != 128) {
375 #if defined(__i386__) || defined(__amd64__)
376 len = cpu_clflush_line_size > 64 ? 128 : 64;
381 printf("Invalid hw.cxgbe.spg_len value (%d),"
382 " using %d instead.\n", spg_len, len);
387 if (cong_drop < -1 || cong_drop > 1) {
388 printf("Invalid hw.cxgbe.cong_drop value (%d),"
389 " using 0 instead.\n", cong_drop);
393 extfree_refs = counter_u64_alloc(M_WAITOK);
394 extfree_rels = counter_u64_alloc(M_WAITOK);
395 counter_u64_zero(extfree_refs);
396 counter_u64_zero(extfree_rels);
398 t4_an_handler = an_not_handled;
399 for (i = 0; i < nitems(t4_fw_msg_handler); i++)
400 t4_fw_msg_handler[i] = fw_msg_not_handled;
401 for (i = 0; i < nitems(t4_cpl_handler); i++)
402 t4_cpl_handler[i] = cpl_not_handled;
404 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
405 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
406 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
407 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
408 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
409 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
413 t4_sge_modunload(void)
416 counter_u64_free(extfree_refs);
417 counter_u64_free(extfree_rels);
421 t4_sge_extfree_refs(void)
425 rels = counter_u64_fetch(extfree_rels);
426 refs = counter_u64_fetch(extfree_refs);
428 return (refs - rels);
432 setup_pad_and_pack_boundaries(struct adapter *sc)
435 int pad, pack, pad_shift;
437 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
438 X_INGPADBOUNDARY_SHIFT;
440 if (fl_pad < (1 << pad_shift) ||
441 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
444 * If there is any chance that we might use buffer packing and
445 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
446 * it to the minimum allowed in all other cases.
448 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
451 * For fl_pad = 0 we'll still write a reasonable value to the
452 * register but all the freelists will opt out of padding.
453 * We'll complain here only if the user tried to set it to a
454 * value greater than 0 that was invalid.
457 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
458 " (%d), using %d instead.\n", fl_pad, pad);
461 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
462 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
463 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
466 if (fl_pack != -1 && fl_pack != pad) {
467 /* Complain but carry on. */
468 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
469 " using %d instead.\n", fl_pack, pad);
475 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
476 !powerof2(fl_pack)) {
477 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
478 MPASS(powerof2(pack));
486 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
487 " (%d), using %d instead.\n", fl_pack, pack);
490 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
492 v = V_INGPACKBOUNDARY(0);
494 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
496 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
497 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
501 * adap->params.vpd.cclk must be set up before this is called.
504 t4_tweak_chip_settings(struct adapter *sc)
508 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
509 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
510 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
511 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
512 static int sge_flbuf_sizes[] = {
514 #if MJUMPAGESIZE != MCLBYTES
516 MJUMPAGESIZE - CL_METADATA_SIZE,
517 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
521 MCLBYTES - MSIZE - CL_METADATA_SIZE,
522 MJUM9BYTES - CL_METADATA_SIZE,
523 MJUM16BYTES - CL_METADATA_SIZE,
526 KASSERT(sc->flags & MASTER_PF,
527 ("%s: trying to change chip settings when not master.", __func__));
529 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
530 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
531 V_EGRSTATUSPAGESIZE(spg_len == 128);
532 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
534 setup_pad_and_pack_boundaries(sc);
536 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
537 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
538 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
539 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
540 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
541 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
542 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
543 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
544 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
546 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
547 ("%s: hw buffer size table too big", __func__));
548 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
549 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
553 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
554 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
555 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
557 KASSERT(intr_timer[0] <= timer_max,
558 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
560 for (i = 1; i < nitems(intr_timer); i++) {
561 KASSERT(intr_timer[i] >= intr_timer[i - 1],
562 ("%s: timers not listed in increasing order (%d)",
565 while (intr_timer[i] > timer_max) {
566 if (i == nitems(intr_timer) - 1) {
567 intr_timer[i] = timer_max;
570 intr_timer[i] += intr_timer[i - 1];
575 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
576 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
577 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
578 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
579 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
580 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
581 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
582 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
583 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
585 /* 4K, 16K, 64K, 256K DDP "page sizes" */
586 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
587 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
589 m = v = F_TDDPTAGTCB;
590 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
592 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
594 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
595 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
599 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
600 * padding is in use, the buffer's start and end need to be aligned to the pad
601 * boundary as well. We'll just make sure that the size is a multiple of the
602 * boundary here, it is up to the buffer allocation code to make sure the start
603 * of the buffer is aligned as well.
606 hwsz_ok(struct adapter *sc, int hwsz)
608 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
610 return (hwsz >= 64 && (hwsz & mask) == 0);
614 * XXX: driver really should be able to deal with unexpected settings.
617 t4_read_chip_settings(struct adapter *sc)
619 struct sge *s = &sc->sge;
620 struct sge_params *sp = &sc->params.sge;
623 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
624 static int sw_buf_sizes[] = { /* Sorted by size */
626 #if MJUMPAGESIZE != MCLBYTES
632 struct sw_zone_info *swz, *safe_swz;
633 struct hw_buf_info *hwb;
637 r = sc->params.sge.sge_control;
639 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
644 * If this changes then every single use of PAGE_SHIFT in the driver
645 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
647 if (sp->page_shift != PAGE_SHIFT) {
648 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
652 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
653 hwb = &s->hw_buf_info[0];
654 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
655 r = sc->params.sge.sge_fl_buffer_size[i];
657 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
662 * Create a sorted list in decreasing order of hw buffer sizes (and so
663 * increasing order of spare area) for each software zone.
665 * If padding is enabled then the start and end of the buffer must align
666 * to the pad boundary; if packing is enabled then they must align with
667 * the pack boundary as well. Allocations from the cluster zones are
668 * aligned to min(size, 4K), so the buffer starts at that alignment and
669 * ends at hwb->size alignment. If mbuf inlining is allowed the
670 * starting alignment will be reduced to MSIZE and the driver will
671 * exercise appropriate caution when deciding on the best buffer layout
674 n = 0; /* no usable buffer size to begin with */
675 swz = &s->sw_zone_info[0];
677 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
678 int8_t head = -1, tail = -1;
680 swz->size = sw_buf_sizes[i];
681 swz->zone = m_getzone(swz->size);
682 swz->type = m_gettype(swz->size);
684 if (swz->size < PAGE_SIZE) {
685 MPASS(powerof2(swz->size));
686 if (fl_pad && (swz->size % sp->pad_boundary != 0))
690 if (swz->size == safest_rx_cluster)
693 hwb = &s->hw_buf_info[0];
694 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
695 if (hwb->zidx != -1 || hwb->size > swz->size)
699 MPASS(hwb->size % sp->pad_boundary == 0);
704 else if (hwb->size < s->hw_buf_info[tail].size) {
705 s->hw_buf_info[tail].next = j;
709 struct hw_buf_info *t;
711 for (cur = &head; *cur != -1; cur = &t->next) {
712 t = &s->hw_buf_info[*cur];
713 if (hwb->size == t->size) {
717 if (hwb->size > t->size) {
725 swz->head_hwidx = head;
726 swz->tail_hwidx = tail;
730 if (swz->size - s->hw_buf_info[tail].size >=
732 sc->flags |= BUF_PACKING_OK;
736 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
742 if (safe_swz != NULL) {
743 s->safe_hwidx1 = safe_swz->head_hwidx;
744 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
747 hwb = &s->hw_buf_info[i];
750 MPASS(hwb->size % sp->pad_boundary == 0);
752 spare = safe_swz->size - hwb->size;
753 if (spare >= CL_METADATA_SIZE) {
760 if (sc->flags & IS_VF)
763 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
764 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
766 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
770 m = v = F_TDDPTAGTCB;
771 r = t4_read_reg(sc, A_ULP_RX_CTL);
773 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
777 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
779 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
780 r = t4_read_reg(sc, A_TP_PARA_REG5);
782 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
786 t4_init_tp_params(sc);
788 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
789 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
795 t4_create_dma_tag(struct adapter *sc)
799 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
800 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
801 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
804 device_printf(sc->dev,
805 "failed to create main DMA tag: %d\n", rc);
812 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
813 struct sysctl_oid_list *children)
815 struct sge_params *sp = &sc->params.sge;
817 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
818 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
819 "freelist buffer sizes");
821 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
822 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
824 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
825 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
827 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
828 NULL, sp->spg_len, "status page size (bytes)");
830 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
831 NULL, cong_drop, "congestion drop setting");
833 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
834 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
838 t4_destroy_dma_tag(struct adapter *sc)
841 bus_dma_tag_destroy(sc->dmat);
847 * Allocate and initialize the firmware event queue and the management queue.
849 * Returns errno on failure. Resources allocated up to that point may still be
850 * allocated. Caller is responsible for cleanup in case this function fails.
853 t4_setup_adapter_queues(struct adapter *sc)
857 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
859 sysctl_ctx_init(&sc->ctx);
860 sc->flags |= ADAP_SYSCTL_CTX;
863 * Firmware event queue
870 * Management queue. This is just a control queue that uses the fwq as
873 if (!(sc->flags & IS_VF))
874 rc = alloc_mgmtq(sc);
883 t4_teardown_adapter_queues(struct adapter *sc)
886 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
888 /* Do this before freeing the queue */
889 if (sc->flags & ADAP_SYSCTL_CTX) {
890 sysctl_ctx_free(&sc->ctx);
891 sc->flags &= ~ADAP_SYSCTL_CTX;
901 first_vector(struct vi_info *vi)
903 struct adapter *sc = vi->pi->adapter;
905 if (sc->intr_count == 1)
908 return (vi->first_intr);
912 * Given an arbitrary "index," come up with an iq that can be used by other
913 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc.
914 * The iq returned is guaranteed to be something that takes direct interrupts.
916 static struct sge_iq *
917 vi_intr_iq(struct vi_info *vi, int idx)
919 struct adapter *sc = vi->pi->adapter;
920 struct sge *s = &sc->sge;
921 struct sge_iq *iq = NULL;
924 if (sc->intr_count == 1)
925 return (&sc->sge.fwq);
929 ("%s: vi %p has no exclusive interrupts, total interrupts = %d",
930 __func__, vi, sc->intr_count));
933 if (vi->flags & INTR_RXQ) {
935 iq = &s->rxq[vi->first_rxq + i].iq;
941 if (vi->flags & INTR_OFLD_RXQ) {
942 if (i < vi->nofldrxq) {
943 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq;
949 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
950 vi, vi->flags & INTR_ALL, idx, nintr);
953 KASSERT(iq->flags & IQ_INTR,
954 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi,
955 vi->flags & INTR_ALL, idx));
959 /* Maximum payload that can be delivered with a single iq descriptor */
961 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
967 payload = sc->tt.rx_coalesce ?
968 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
971 /* large enough even when hw VLAN extraction is disabled */
972 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
973 ETHER_VLAN_ENCAP_LEN + mtu;
982 t4_setup_vi_queues(struct vi_info *vi)
984 int rc = 0, i, j, intr_idx, iqid;
987 struct sge_wrq *ctrlq;
989 struct sge_ofld_rxq *ofld_rxq;
990 struct sge_wrq *ofld_txq;
994 struct sge_nm_rxq *nm_rxq;
995 struct sge_nm_txq *nm_txq;
998 struct port_info *pi = vi->pi;
999 struct adapter *sc = pi->adapter;
1000 struct ifnet *ifp = vi->ifp;
1001 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1002 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1003 int maxp, mtu = ifp->if_mtu;
1005 /* Interrupt vector to start from (when using multiple vectors) */
1006 intr_idx = first_vector(vi);
1009 saved_idx = intr_idx;
1010 if (ifp->if_capabilities & IFCAP_NETMAP) {
1012 /* netmap is supported with direct interrupts only. */
1013 MPASS(vi->flags & INTR_RXQ);
1016 * We don't have buffers to back the netmap rx queues
1017 * right now so we create the queues in a way that
1018 * doesn't set off any congestion signal in the chip.
1020 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1021 CTLFLAG_RD, NULL, "rx queues");
1022 for_each_nm_rxq(vi, i, nm_rxq) {
1023 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1029 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1030 CTLFLAG_RD, NULL, "tx queues");
1031 for_each_nm_txq(vi, i, nm_txq) {
1032 iqid = vi->first_nm_rxq + (i % vi->nnmrxq);
1033 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid);
1039 /* Normal rx queues and netmap rx queues share the same interrupts. */
1040 intr_idx = saved_idx;
1044 * First pass over all NIC and TOE rx queues:
1045 * a) initialize iq and fl
1046 * b) allocate queue iff it will take direct interrupts.
1048 maxp = mtu_to_max_payload(sc, mtu, 0);
1049 if (vi->flags & INTR_RXQ) {
1050 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1051 CTLFLAG_RD, NULL, "rx queues");
1053 for_each_rxq(vi, i, rxq) {
1055 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1057 snprintf(name, sizeof(name), "%s rxq%d-fl",
1058 device_get_nameunit(vi->dev), i);
1059 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1061 if (vi->flags & INTR_RXQ) {
1062 rxq->iq.flags |= IQ_INTR;
1063 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1070 if (ifp->if_capabilities & IFCAP_NETMAP)
1071 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1074 maxp = mtu_to_max_payload(sc, mtu, 1);
1075 if (vi->flags & INTR_OFLD_RXQ) {
1076 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1078 "rx queues for offloaded TCP connections");
1080 for_each_ofld_rxq(vi, i, ofld_rxq) {
1082 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx,
1085 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1086 device_get_nameunit(vi->dev), i);
1087 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1089 if (vi->flags & INTR_OFLD_RXQ) {
1090 ofld_rxq->iq.flags |= IQ_INTR;
1091 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1100 * Second pass over all NIC and TOE rx queues. The queues forwarding
1101 * their interrupts are allocated now.
1104 if (!(vi->flags & INTR_RXQ)) {
1105 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1106 CTLFLAG_RD, NULL, "rx queues");
1107 for_each_rxq(vi, i, rxq) {
1108 MPASS(!(rxq->iq.flags & IQ_INTR));
1110 intr_idx = vi_intr_iq(vi, j)->abs_id;
1112 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1119 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) {
1120 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1122 "rx queues for offloaded TCP connections");
1123 for_each_ofld_rxq(vi, i, ofld_rxq) {
1124 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1126 intr_idx = vi_intr_iq(vi, j)->abs_id;
1128 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1137 * Now the tx queues. Only one pass needed.
1139 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1142 for_each_txq(vi, i, txq) {
1143 iqid = vi_intr_iq(vi, j)->cntxt_id;
1144 snprintf(name, sizeof(name), "%s txq%d",
1145 device_get_nameunit(vi->dev), i);
1146 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid,
1149 rc = alloc_txq(vi, txq, i, oid);
1155 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1156 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1157 for_each_ofld_txq(vi, i, ofld_txq) {
1158 struct sysctl_oid *oid2;
1160 iqid = vi_intr_iq(vi, j)->cntxt_id;
1161 snprintf(name, sizeof(name), "%s ofld_txq%d",
1162 device_get_nameunit(vi->dev), i);
1163 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1166 snprintf(name, sizeof(name), "%d", i);
1167 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1168 name, CTLFLAG_RD, NULL, "offload tx queue");
1170 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1178 * Finally, the control queue.
1180 if (!IS_MAIN_VI(vi) || sc->flags & IS_VF)
1182 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1183 NULL, "ctrl queue");
1184 ctrlq = &sc->sge.ctrlq[pi->port_id];
1185 iqid = vi_intr_iq(vi, 0)->cntxt_id;
1186 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev));
1187 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid,
1189 rc = alloc_wrq(sc, vi, ctrlq, oid);
1193 t4_teardown_vi_queues(vi);
1202 t4_teardown_vi_queues(struct vi_info *vi)
1205 struct port_info *pi = vi->pi;
1206 struct adapter *sc = pi->adapter;
1207 struct sge_rxq *rxq;
1208 struct sge_txq *txq;
1210 struct sge_ofld_rxq *ofld_rxq;
1211 struct sge_wrq *ofld_txq;
1214 struct sge_nm_rxq *nm_rxq;
1215 struct sge_nm_txq *nm_txq;
1218 /* Do this before freeing the queues */
1219 if (vi->flags & VI_SYSCTL_CTX) {
1220 sysctl_ctx_free(&vi->ctx);
1221 vi->flags &= ~VI_SYSCTL_CTX;
1225 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1226 for_each_nm_txq(vi, i, nm_txq) {
1227 free_nm_txq(vi, nm_txq);
1230 for_each_nm_rxq(vi, i, nm_rxq) {
1231 free_nm_rxq(vi, nm_rxq);
1237 * Take down all the tx queues first, as they reference the rx queues
1238 * (for egress updates, etc.).
1241 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
1242 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1244 for_each_txq(vi, i, txq) {
1248 for_each_ofld_txq(vi, i, ofld_txq) {
1249 free_wrq(sc, ofld_txq);
1254 * Then take down the rx queues that forward their interrupts, as they
1255 * reference other rx queues.
1258 for_each_rxq(vi, i, rxq) {
1259 if ((rxq->iq.flags & IQ_INTR) == 0)
1263 for_each_ofld_rxq(vi, i, ofld_rxq) {
1264 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1265 free_ofld_rxq(vi, ofld_rxq);
1270 * Then take down the rx queues that take direct interrupts.
1273 for_each_rxq(vi, i, rxq) {
1274 if (rxq->iq.flags & IQ_INTR)
1278 for_each_ofld_rxq(vi, i, ofld_rxq) {
1279 if (ofld_rxq->iq.flags & IQ_INTR)
1280 free_ofld_rxq(vi, ofld_rxq);
1288 * Deals with errors and the firmware event queue. All data rx queues forward
1289 * their interrupt to the firmware event queue.
1292 t4_intr_all(void *arg)
1294 struct adapter *sc = arg;
1295 struct sge_iq *fwq = &sc->sge.fwq;
1298 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1300 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1304 /* Deals with error interrupts */
1306 t4_intr_err(void *arg)
1308 struct adapter *sc = arg;
1310 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1311 t4_slow_intr_handler(sc);
1315 t4_intr_evt(void *arg)
1317 struct sge_iq *iq = arg;
1319 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1321 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1328 struct sge_iq *iq = arg;
1330 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1332 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1337 t4_vi_intr(void *arg)
1339 struct irq *irq = arg;
1342 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) {
1343 t4_nm_intr(irq->nm_rxq);
1344 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON);
1347 if (irq->rxq != NULL)
1352 * Deals with anything and everything on the given ingress queue.
1355 service_iq(struct sge_iq *iq, int budget)
1358 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1359 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1360 struct adapter *sc = iq->adapter;
1361 struct iq_desc *d = &iq->desc[iq->cidx];
1362 int ndescs = 0, limit;
1363 int rsp_type, refill;
1365 uint16_t fl_hw_cidx;
1367 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1368 #if defined(INET) || defined(INET6)
1369 const struct timeval lro_timeout = {0, sc->lro_timeout};
1372 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1374 limit = budget ? budget : iq->qsize / 16;
1376 if (iq->flags & IQ_HAS_FL) {
1378 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1381 fl_hw_cidx = 0; /* to silence gcc warning */
1385 * We always come back and check the descriptor ring for new indirect
1386 * interrupts and other responses after running a single handler.
1389 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1395 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1396 lq = be32toh(d->rsp.pldbuflen_qid);
1399 case X_RSPD_TYPE_FLBUF:
1401 KASSERT(iq->flags & IQ_HAS_FL,
1402 ("%s: data for an iq (%p) with no freelist",
1405 m0 = get_fl_payload(sc, fl, lq);
1406 if (__predict_false(m0 == NULL))
1408 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1409 #ifdef T4_PKT_TIMESTAMP
1411 * 60 bit timestamp for the payload is
1412 * *(uint64_t *)m0->m_pktdat. Note that it is
1413 * in the leading free-space in the mbuf. The
1414 * kernel can clobber it during a pullup,
1415 * m_copymdata, etc. You need to make sure that
1416 * the mbuf reaches you unmolested if you care
1417 * about the timestamp.
1419 *(uint64_t *)m0->m_pktdat =
1420 be64toh(ctrl->u.last_flit) &
1426 case X_RSPD_TYPE_CPL:
1427 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1428 ("%s: bad opcode %02x.", __func__,
1430 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1433 case X_RSPD_TYPE_INTR:
1436 * Interrupts should be forwarded only to queues
1437 * that are not forwarding their interrupts.
1438 * This means service_iq can recurse but only 1
1441 KASSERT(budget == 0,
1442 ("%s: budget %u, rsp_type %u", __func__,
1446 * There are 1K interrupt-capable queues (qids 0
1447 * through 1023). A response type indicating a
1448 * forwarded interrupt with a qid >= 1K is an
1449 * iWARP async notification.
1452 t4_an_handler(iq, &d->rsp);
1456 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1458 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1460 if (service_iq(q, q->qsize / 16) == 0) {
1461 atomic_cmpset_int(&q->state,
1462 IQS_BUSY, IQS_IDLE);
1464 STAILQ_INSERT_TAIL(&iql, q,
1472 ("%s: illegal response type %d on iq %p",
1473 __func__, rsp_type, iq));
1475 "%s: illegal response type %d on iq %p",
1476 device_get_nameunit(sc->dev), rsp_type, iq);
1481 if (__predict_false(++iq->cidx == iq->sidx)) {
1483 iq->gen ^= F_RSPD_GEN;
1486 if (__predict_false(++ndescs == limit)) {
1487 t4_write_reg(sc, sc->sge_gts_reg,
1489 V_INGRESSQID(iq->cntxt_id) |
1490 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1493 #if defined(INET) || defined(INET6)
1494 if (iq->flags & IQ_LRO_ENABLED &&
1495 sc->lro_timeout != 0) {
1496 tcp_lro_flush_inactive(&rxq->lro,
1502 if (iq->flags & IQ_HAS_FL) {
1504 refill_fl(sc, fl, 32);
1507 return (EINPROGRESS);
1512 refill_fl(sc, fl, 32);
1514 fl_hw_cidx = fl->hw_cidx;
1519 if (STAILQ_EMPTY(&iql))
1523 * Process the head only, and send it to the back of the list if
1524 * it's still not done.
1526 q = STAILQ_FIRST(&iql);
1527 STAILQ_REMOVE_HEAD(&iql, link);
1528 if (service_iq(q, q->qsize / 8) == 0)
1529 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1531 STAILQ_INSERT_TAIL(&iql, q, link);
1534 #if defined(INET) || defined(INET6)
1535 if (iq->flags & IQ_LRO_ENABLED) {
1536 struct lro_ctrl *lro = &rxq->lro;
1537 struct lro_entry *l;
1539 while (!SLIST_EMPTY(&lro->lro_active)) {
1540 l = SLIST_FIRST(&lro->lro_active);
1541 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1542 tcp_lro_flush(lro, l);
1547 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1548 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1550 if (iq->flags & IQ_HAS_FL) {
1554 starved = refill_fl(sc, fl, 64);
1556 if (__predict_false(starved != 0))
1557 add_fl_to_sfl(sc, fl);
1564 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1566 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1569 MPASS(cll->region3 >= CL_METADATA_SIZE);
1574 static inline struct cluster_metadata *
1575 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1579 if (cl_has_metadata(fl, cll)) {
1580 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1582 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1588 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1590 uma_zone_t zone = arg1;
1593 uma_zfree(zone, cl);
1594 counter_u64_add(extfree_rels, 1);
1596 return (EXT_FREE_OK);
1600 * The mbuf returned by this function could be allocated from zone_mbuf or
1601 * constructed in spare room in the cluster.
1603 * The mbuf carries the payload in one of these ways
1604 * a) frame inside the mbuf (mbuf from zone_mbuf)
1605 * b) m_cljset (for clusters without metadata) zone_mbuf
1606 * c) m_extaddref (cluster with metadata) inline mbuf
1607 * d) m_extaddref (cluster with metadata) zone_mbuf
1609 static struct mbuf *
1610 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1614 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1615 struct cluster_layout *cll = &sd->cll;
1616 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1617 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1618 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1622 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1623 len = min(remaining, blen);
1624 payload = sd->cl + cll->region1 + fl->rx_offset;
1625 if (fl->flags & FL_BUF_PACKING) {
1626 const u_int l = fr_offset + len;
1627 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1629 if (fl->rx_offset + len + pad < hwb->size)
1631 MPASS(fl->rx_offset + blen <= hwb->size);
1633 MPASS(fl->rx_offset == 0); /* not packing */
1637 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1640 * Copy payload into a freshly allocated mbuf.
1643 m = fr_offset == 0 ?
1644 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1647 fl->mbuf_allocated++;
1648 #ifdef T4_PKT_TIMESTAMP
1649 /* Leave room for a timestamp */
1652 /* copy data to mbuf */
1653 bcopy(payload, mtod(m, caddr_t), len);
1655 } else if (sd->nmbuf * MSIZE < cll->region1) {
1658 * There's spare room in the cluster for an mbuf. Create one
1659 * and associate it with the payload that's in the cluster.
1663 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1664 /* No bzero required */
1665 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA,
1666 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1669 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1671 if (sd->nmbuf++ == 0)
1672 counter_u64_add(extfree_refs, 1);
1677 * Grab an mbuf from zone_mbuf and associate it with the
1678 * payload in the cluster.
1681 m = fr_offset == 0 ?
1682 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1685 fl->mbuf_allocated++;
1687 m_extaddref(m, payload, blen, &clm->refcount,
1688 rxb_free, swz->zone, sd->cl);
1689 if (sd->nmbuf++ == 0)
1690 counter_u64_add(extfree_refs, 1);
1692 m_cljset(m, sd->cl, swz->type);
1693 sd->cl = NULL; /* consumed, not a recycle candidate */
1697 m->m_pkthdr.len = remaining;
1700 if (fl->flags & FL_BUF_PACKING) {
1701 fl->rx_offset += blen;
1702 MPASS(fl->rx_offset <= hwb->size);
1703 if (fl->rx_offset < hwb->size)
1704 return (m); /* without advancing the cidx */
1707 if (__predict_false(++fl->cidx % 8 == 0)) {
1708 uint16_t cidx = fl->cidx / 8;
1710 if (__predict_false(cidx == fl->sidx))
1711 fl->cidx = cidx = 0;
1719 static struct mbuf *
1720 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1722 struct mbuf *m0, *m, **pnext;
1724 const u_int total = G_RSPD_LEN(len_newbuf);
1726 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1727 M_ASSERTPKTHDR(fl->m0);
1728 MPASS(fl->m0->m_pkthdr.len == total);
1729 MPASS(fl->remaining < total);
1733 remaining = fl->remaining;
1734 fl->flags &= ~FL_BUF_RESUME;
1738 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1740 if (__predict_false(++fl->cidx % 8 == 0)) {
1741 uint16_t cidx = fl->cidx / 8;
1743 if (__predict_false(cidx == fl->sidx))
1744 fl->cidx = cidx = 0;
1750 * Payload starts at rx_offset in the current hw buffer. Its length is
1751 * 'len' and it may span multiple hw buffers.
1754 m0 = get_scatter_segment(sc, fl, 0, total);
1757 remaining = total - m0->m_len;
1758 pnext = &m0->m_next;
1759 while (remaining > 0) {
1761 MPASS(fl->rx_offset == 0);
1762 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1763 if (__predict_false(m == NULL)) {
1766 fl->remaining = remaining;
1767 fl->flags |= FL_BUF_RESUME;
1772 remaining -= m->m_len;
1781 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1783 struct sge_rxq *rxq = iq_to_rxq(iq);
1784 struct ifnet *ifp = rxq->ifp;
1785 struct adapter *sc = iq->adapter;
1786 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1787 #if defined(INET) || defined(INET6)
1788 struct lro_ctrl *lro = &rxq->lro;
1791 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1794 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1795 m0->m_len -= sc->params.sge.fl_pktshift;
1796 m0->m_data += sc->params.sge.fl_pktshift;
1798 m0->m_pkthdr.rcvif = ifp;
1799 M_HASHTYPE_SET(m0, M_HASHTYPE_OPAQUE);
1800 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1802 if (cpl->csum_calc && !cpl->err_vec) {
1803 if (ifp->if_capenable & IFCAP_RXCSUM &&
1804 cpl->l2info & htobe32(F_RXF_IP)) {
1805 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1806 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1808 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1809 cpl->l2info & htobe32(F_RXF_IP6)) {
1810 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1815 if (__predict_false(cpl->ip_frag))
1816 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1818 m0->m_pkthdr.csum_data = 0xffff;
1822 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1823 m0->m_flags |= M_VLANTAG;
1824 rxq->vlan_extraction++;
1827 #if defined(INET) || defined(INET6)
1828 if (iq->flags & IQ_LRO_ENABLED &&
1829 tcp_lro_rx(lro, m0, 0) == 0) {
1830 /* queued for LRO */
1833 ifp->if_input(ifp, m0);
1839 * Must drain the wrq or make sure that someone else will.
1842 wrq_tx_drain(void *arg, int n)
1844 struct sge_wrq *wrq = arg;
1845 struct sge_eq *eq = &wrq->eq;
1848 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1849 drain_wrq_wr_list(wrq->adapter, wrq);
1854 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1856 struct sge_eq *eq = &wrq->eq;
1857 u_int available, dbdiff; /* # of hardware descriptors */
1860 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1862 EQ_LOCK_ASSERT_OWNED(eq);
1863 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1864 wr = STAILQ_FIRST(&wrq->wr_list);
1865 MPASS(wr != NULL); /* Must be called with something useful to do */
1866 MPASS(eq->pidx == eq->dbidx);
1870 eq->cidx = read_hw_cidx(eq);
1871 if (eq->pidx == eq->cidx)
1872 available = eq->sidx - 1;
1874 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1876 MPASS(wr->wrq == wrq);
1877 n = howmany(wr->wr_len, EQ_ESIZE);
1881 dst = (void *)&eq->desc[eq->pidx];
1882 if (__predict_true(eq->sidx - eq->pidx > n)) {
1883 /* Won't wrap, won't end exactly at the status page. */
1884 bcopy(&wr->wr[0], dst, wr->wr_len);
1887 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1889 bcopy(&wr->wr[0], dst, first_portion);
1890 if (wr->wr_len > first_portion) {
1891 bcopy(&wr->wr[first_portion], &eq->desc[0],
1892 wr->wr_len - first_portion);
1894 eq->pidx = n - (eq->sidx - eq->pidx);
1896 wrq->tx_wrs_copied++;
1898 if (available < eq->sidx / 4 &&
1899 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1900 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1902 eq->equeqidx = eq->pidx;
1903 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1904 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1905 eq->equeqidx = eq->pidx;
1910 ring_eq_db(sc, eq, dbdiff);
1914 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1916 MPASS(wrq->nwr_pending > 0);
1918 MPASS(wrq->ndesc_needed >= n);
1919 wrq->ndesc_needed -= n;
1920 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1923 ring_eq_db(sc, eq, dbdiff);
1927 * Doesn't fail. Holds on to work requests it can't send right away.
1930 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1933 struct sge_eq *eq = &wrq->eq;
1936 EQ_LOCK_ASSERT_OWNED(eq);
1938 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1939 MPASS((wr->wr_len & 0x7) == 0);
1941 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1943 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1945 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1946 return; /* commit_wrq_wr will drain wr_list as well. */
1948 drain_wrq_wr_list(sc, wrq);
1950 /* Doorbell must have caught up to the pidx. */
1951 MPASS(eq->pidx == eq->dbidx);
1955 t4_update_fl_bufsize(struct ifnet *ifp)
1957 struct vi_info *vi = ifp->if_softc;
1958 struct adapter *sc = vi->pi->adapter;
1959 struct sge_rxq *rxq;
1961 struct sge_ofld_rxq *ofld_rxq;
1964 int i, maxp, mtu = ifp->if_mtu;
1966 maxp = mtu_to_max_payload(sc, mtu, 0);
1967 for_each_rxq(vi, i, rxq) {
1971 find_best_refill_source(sc, fl, maxp);
1975 maxp = mtu_to_max_payload(sc, mtu, 1);
1976 for_each_ofld_rxq(vi, i, ofld_rxq) {
1980 find_best_refill_source(sc, fl, maxp);
1987 mbuf_nsegs(struct mbuf *m)
1991 KASSERT(m->m_pkthdr.l5hlen > 0,
1992 ("%s: mbuf %p missing information on # of segments.", __func__, m));
1994 return (m->m_pkthdr.l5hlen);
1998 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2002 m->m_pkthdr.l5hlen = nsegs;
2006 mbuf_len16(struct mbuf *m)
2011 n = m->m_pkthdr.PH_loc.eigth[0];
2012 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2018 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2022 m->m_pkthdr.PH_loc.eigth[0] = len16;
2026 needs_tso(struct mbuf *m)
2031 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
2032 KASSERT(m->m_pkthdr.tso_segsz > 0,
2033 ("%s: TSO requested in mbuf %p but MSS not provided",
2042 needs_l3_csum(struct mbuf *m)
2047 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
2053 needs_l4_csum(struct mbuf *m)
2058 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2059 CSUM_TCP_IPV6 | CSUM_TSO))
2065 needs_vlan_insertion(struct mbuf *m)
2070 if (m->m_flags & M_VLANTAG) {
2071 KASSERT(m->m_pkthdr.ether_vtag != 0,
2072 ("%s: HWVLAN requested in mbuf %p but tag not provided",
2080 m_advance(struct mbuf **pm, int *poffset, int len)
2082 struct mbuf *m = *pm;
2083 int offset = *poffset;
2089 if (offset + len < m->m_len) {
2091 p = mtod(m, uintptr_t) + offset;
2094 len -= m->m_len - offset;
2105 same_paddr(char *a, char *b)
2110 else if (a != NULL && b != NULL) {
2111 vm_offset_t x = (vm_offset_t)a;
2112 vm_offset_t y = (vm_offset_t)b;
2114 if ((x & PAGE_MASK) == (y & PAGE_MASK) &&
2115 pmap_kextract(x) == pmap_kextract(y))
2123 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2124 * must have at least one mbuf that's not empty.
2127 count_mbuf_nsegs(struct mbuf *m)
2129 char *prev_end, *start;
2136 for (; m; m = m->m_next) {
2139 if (__predict_false(len == 0))
2141 start = mtod(m, char *);
2143 nsegs += sglist_count(start, len);
2144 if (same_paddr(prev_end, start))
2146 prev_end = start + len;
2154 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2155 * a) caller can assume it's been freed if this function returns with an error.
2156 * b) it may get defragged up if the gather list is too long for the hardware.
2159 parse_pkt(struct adapter *sc, struct mbuf **mp)
2161 struct mbuf *m0 = *mp, *m;
2162 int rc, nsegs, defragged = 0, offset;
2163 struct ether_header *eh;
2165 #if defined(INET) || defined(INET6)
2171 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2180 * First count the number of gather list segments in the payload.
2181 * Defrag the mbuf if nsegs exceeds the hardware limit.
2184 MPASS(m0->m_pkthdr.len > 0);
2185 nsegs = count_mbuf_nsegs(m0);
2186 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2187 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2191 *mp = m0 = m; /* update caller's copy after defrag */
2195 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2196 m0 = m_pullup(m0, m0->m_pkthdr.len);
2198 /* Should have left well enough alone. */
2202 *mp = m0; /* update caller's copy after pullup */
2205 set_mbuf_nsegs(m0, nsegs);
2206 if (sc->flags & IS_VF)
2207 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2209 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2211 if (!needs_tso(m0) &&
2212 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0))))
2216 eh = mtod(m, struct ether_header *);
2217 eh_type = ntohs(eh->ether_type);
2218 if (eh_type == ETHERTYPE_VLAN) {
2219 struct ether_vlan_header *evh = (void *)eh;
2221 eh_type = ntohs(evh->evl_proto);
2222 m0->m_pkthdr.l2hlen = sizeof(*evh);
2224 m0->m_pkthdr.l2hlen = sizeof(*eh);
2227 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2231 case ETHERTYPE_IPV6:
2233 struct ip6_hdr *ip6 = l3hdr;
2235 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2237 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2244 struct ip *ip = l3hdr;
2246 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2251 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2252 " with the same INET/INET6 options as the kernel.",
2256 #if defined(INET) || defined(INET6)
2257 if (needs_tso(m0)) {
2258 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2259 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2267 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2269 struct sge_eq *eq = &wrq->eq;
2270 struct adapter *sc = wrq->adapter;
2271 int ndesc, available;
2276 ndesc = howmany(len16, EQ_ESIZE / 16);
2277 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2281 if (!STAILQ_EMPTY(&wrq->wr_list))
2282 drain_wrq_wr_list(sc, wrq);
2284 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2287 wr = alloc_wrqe(len16 * 16, wrq);
2288 if (__predict_false(wr == NULL))
2291 cookie->ndesc = ndesc;
2295 eq->cidx = read_hw_cidx(eq);
2296 if (eq->pidx == eq->cidx)
2297 available = eq->sidx - 1;
2299 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2300 if (available < ndesc)
2303 cookie->pidx = eq->pidx;
2304 cookie->ndesc = ndesc;
2305 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2307 w = &eq->desc[eq->pidx];
2308 IDXINCR(eq->pidx, ndesc, eq->sidx);
2309 if (__predict_false(eq->pidx < ndesc - 1)) {
2311 wrq->ss_pidx = cookie->pidx;
2312 wrq->ss_len = len16 * 16;
2321 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2323 struct sge_eq *eq = &wrq->eq;
2324 struct adapter *sc = wrq->adapter;
2326 struct wrq_cookie *prev, *next;
2328 if (cookie->pidx == -1) {
2329 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2335 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2336 pidx = cookie->pidx;
2337 MPASS(pidx >= 0 && pidx < eq->sidx);
2338 if (__predict_false(w == &wrq->ss[0])) {
2339 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2341 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2342 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2343 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2346 wrq->tx_wrs_direct++;
2349 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2350 next = TAILQ_NEXT(cookie, link);
2352 MPASS(pidx == eq->dbidx);
2353 if (next == NULL || ndesc >= 16)
2354 ring_eq_db(wrq->adapter, eq, ndesc);
2356 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2358 next->ndesc += ndesc;
2361 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2362 prev->ndesc += ndesc;
2364 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2366 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2367 drain_wrq_wr_list(sc, wrq);
2370 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2371 /* Doorbell must have caught up to the pidx. */
2372 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2379 can_resume_eth_tx(struct mp_ring *r)
2381 struct sge_eq *eq = r->cookie;
2383 return (total_available_tx_desc(eq) > eq->sidx / 8);
2387 cannot_use_txpkts(struct mbuf *m)
2389 /* maybe put a GL limit too, to avoid silliness? */
2391 return (needs_tso(m));
2395 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2396 * be consumed. Return the actual number consumed. 0 indicates a stall.
2399 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2401 struct sge_txq *txq = r->cookie;
2402 struct sge_eq *eq = &txq->eq;
2403 struct ifnet *ifp = txq->ifp;
2404 struct vi_info *vi = ifp->if_softc;
2405 struct port_info *pi = vi->pi;
2406 struct adapter *sc = pi->adapter;
2407 u_int total, remaining; /* # of packets */
2408 u_int available, dbdiff; /* # of hardware descriptors */
2410 struct mbuf *m0, *tail;
2412 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2414 remaining = IDXDIFF(pidx, cidx, r->size);
2415 MPASS(remaining > 0); /* Must not be called without work to do. */
2419 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) {
2420 while (cidx != pidx) {
2421 m0 = r->items[cidx];
2423 if (++cidx == r->size)
2426 reclaim_tx_descs(txq, 2048);
2431 /* How many hardware descriptors do we have readily available. */
2432 if (eq->pidx == eq->cidx)
2433 available = eq->sidx - 1;
2435 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2436 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2438 while (remaining > 0) {
2440 m0 = r->items[cidx];
2442 MPASS(m0->m_nextpkt == NULL);
2444 if (available < SGE_MAX_WR_NDESC) {
2445 available += reclaim_tx_descs(txq, 64);
2446 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2447 break; /* out of descriptors */
2450 next_cidx = cidx + 1;
2451 if (__predict_false(next_cidx == r->size))
2454 wr = (void *)&eq->desc[eq->pidx];
2455 if (sc->flags & IS_VF) {
2458 ETHER_BPF_MTAP(ifp, m0);
2459 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2461 } else if (remaining > 1 &&
2462 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2464 /* pkts at cidx, next_cidx should both be in txp. */
2465 MPASS(txp.npkt == 2);
2466 tail = r->items[next_cidx];
2467 MPASS(tail->m_nextpkt == NULL);
2468 ETHER_BPF_MTAP(ifp, m0);
2469 ETHER_BPF_MTAP(ifp, tail);
2470 m0->m_nextpkt = tail;
2472 if (__predict_false(++next_cidx == r->size))
2475 while (next_cidx != pidx) {
2476 if (add_to_txpkts(r->items[next_cidx], &txp,
2479 tail->m_nextpkt = r->items[next_cidx];
2480 tail = tail->m_nextpkt;
2481 ETHER_BPF_MTAP(ifp, tail);
2482 if (__predict_false(++next_cidx == r->size))
2486 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2488 remaining -= txp.npkt;
2492 ETHER_BPF_MTAP(ifp, m0);
2493 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2495 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2499 IDXINCR(eq->pidx, n, eq->sidx);
2501 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2502 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2503 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2505 eq->equeqidx = eq->pidx;
2506 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2507 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2508 eq->equeqidx = eq->pidx;
2511 if (dbdiff >= 16 && remaining >= 4) {
2512 ring_eq_db(sc, eq, dbdiff);
2513 available += reclaim_tx_descs(txq, 4 * dbdiff);
2520 ring_eq_db(sc, eq, dbdiff);
2521 reclaim_tx_descs(txq, 32);
2530 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2534 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2535 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2536 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2537 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2541 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2542 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2543 if (pktc_idx >= 0) {
2544 iq->intr_params |= F_QINTR_CNT_EN;
2545 iq->intr_pktc_idx = pktc_idx;
2547 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2548 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2552 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2556 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2557 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2558 if (sc->flags & BUF_PACKING_OK &&
2559 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2560 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2561 fl->flags |= FL_BUF_PACKING;
2562 find_best_refill_source(sc, fl, maxp);
2563 find_safe_refill_source(sc, fl);
2567 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2568 uint8_t tx_chan, uint16_t iqid, char *name)
2570 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2572 eq->flags = eqtype & EQ_TYPEMASK;
2573 eq->tx_chan = tx_chan;
2575 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2576 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2580 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2581 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2585 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2586 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2588 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2592 rc = bus_dmamem_alloc(*tag, va,
2593 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2595 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2599 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2601 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2606 free_ring(sc, *tag, *map, *pa, *va);
2612 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2613 bus_addr_t pa, void *va)
2616 bus_dmamap_unload(tag, map);
2618 bus_dmamem_free(tag, va, map);
2620 bus_dma_tag_destroy(tag);
2626 * Allocates the ring for an ingress queue and an optional freelist. If the
2627 * freelist is specified it will be allocated and then associated with the
2630 * Returns errno on failure. Resources allocated up to that point may still be
2631 * allocated. Caller is responsible for cleanup in case this function fails.
2633 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2634 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2635 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2638 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2639 int intr_idx, int cong)
2641 int rc, i, cntxt_id;
2644 struct port_info *pi = vi->pi;
2645 struct adapter *sc = iq->adapter;
2646 struct sge_params *sp = &sc->params.sge;
2649 len = iq->qsize * IQ_ESIZE;
2650 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2651 (void **)&iq->desc);
2655 bzero(&c, sizeof(c));
2656 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2657 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2658 V_FW_IQ_CMD_VFN(0));
2660 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2663 /* Special handling for firmware event queue */
2664 if (iq == &sc->sge.fwq)
2665 v |= F_FW_IQ_CMD_IQASYNCH;
2667 if (iq->flags & IQ_INTR) {
2668 KASSERT(intr_idx < sc->intr_count,
2669 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2671 v |= F_FW_IQ_CMD_IQANDST;
2672 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2674 c.type_to_iqandstindex = htobe32(v |
2675 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2676 V_FW_IQ_CMD_VIID(vi->viid) |
2677 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2678 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2679 F_FW_IQ_CMD_IQGTSMODE |
2680 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2681 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2682 c.iqsize = htobe16(iq->qsize);
2683 c.iqaddr = htobe64(iq->ba);
2685 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2688 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2690 len = fl->qsize * EQ_ESIZE;
2691 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2692 &fl->ba, (void **)&fl->desc);
2696 /* Allocate space for one software descriptor per buffer. */
2697 rc = alloc_fl_sdesc(fl);
2699 device_printf(sc->dev,
2700 "failed to setup fl software descriptors: %d\n",
2705 if (fl->flags & FL_BUF_PACKING) {
2706 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
2707 fl->buf_boundary = sp->pack_boundary;
2709 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
2710 fl->buf_boundary = 16;
2712 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
2713 fl->buf_boundary = sp->pad_boundary;
2715 c.iqns_to_fl0congen |=
2716 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2717 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2718 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2719 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2722 c.iqns_to_fl0congen |=
2723 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2724 F_FW_IQ_CMD_FL0CONGCIF |
2725 F_FW_IQ_CMD_FL0CONGEN);
2727 c.fl0dcaen_to_fl0cidxfthresh =
2728 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
2729 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
2730 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
2731 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
2732 c.fl0size = htobe16(fl->qsize);
2733 c.fl0addr = htobe64(fl->ba);
2736 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2738 device_printf(sc->dev,
2739 "failed to create ingress queue: %d\n", rc);
2744 iq->gen = F_RSPD_GEN;
2745 iq->intr_next = iq->intr_params;
2746 iq->cntxt_id = be16toh(c.iqid);
2747 iq->abs_id = be16toh(c.physiqid);
2748 iq->flags |= IQ_ALLOCATED;
2750 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2751 if (cntxt_id >= sc->sge.niq) {
2752 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2753 cntxt_id, sc->sge.niq - 1);
2755 sc->sge.iqmap[cntxt_id] = iq;
2760 iq->flags |= IQ_HAS_FL;
2761 fl->cntxt_id = be16toh(c.fl0id);
2762 fl->pidx = fl->cidx = 0;
2764 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2765 if (cntxt_id >= sc->sge.neq) {
2766 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2767 __func__, cntxt_id, sc->sge.neq - 1);
2769 sc->sge.eqmap[cntxt_id] = (void *)fl;
2772 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2773 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
2774 uint32_t mask = (1 << s_qpp) - 1;
2775 volatile uint8_t *udb;
2777 udb = sc->udbs_base + UDBS_DB_OFFSET;
2778 udb += (qid >> s_qpp) << PAGE_SHIFT;
2780 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2781 udb += qid << UDBS_SEG_SHIFT;
2784 fl->udb = (volatile void *)udb;
2786 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
2789 /* Enough to make sure the SGE doesn't think it's starved */
2790 refill_fl(sc, fl, fl->lowat);
2794 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
2795 uint32_t param, val;
2797 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2798 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2799 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2804 for (i = 0; i < 4; i++) {
2805 if (cong & (1 << i))
2806 val |= 1 << (i << 2);
2810 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2812 /* report error but carry on */
2813 device_printf(sc->dev,
2814 "failed to set congestion manager context for "
2815 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2819 /* Enable IQ interrupts */
2820 atomic_store_rel_int(&iq->state, IQS_IDLE);
2821 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
2822 V_INGRESSQID(iq->cntxt_id));
2828 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
2831 struct adapter *sc = iq->adapter;
2835 return (0); /* nothing to do */
2837 dev = vi ? vi->dev : sc->dev;
2839 if (iq->flags & IQ_ALLOCATED) {
2840 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2841 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2842 fl ? fl->cntxt_id : 0xffff, 0xffff);
2845 "failed to free queue %p: %d\n", iq, rc);
2848 iq->flags &= ~IQ_ALLOCATED;
2851 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2853 bzero(iq, sizeof(*iq));
2856 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2860 free_fl_sdesc(sc, fl);
2862 if (mtx_initialized(&fl->fl_lock))
2863 mtx_destroy(&fl->fl_lock);
2865 bzero(fl, sizeof(*fl));
2872 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
2873 struct sysctl_oid *oid, struct sge_fl *fl)
2875 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2877 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2879 children = SYSCTL_CHILDREN(oid);
2881 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2882 &fl->ba, "bus address of descriptor ring");
2883 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2884 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
2885 "desc ring size in bytes");
2886 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2887 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2888 "SGE context id of the freelist");
2889 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2890 fl_pad ? 1 : 0, "padding enabled");
2891 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2892 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2893 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2894 0, "consumer index");
2895 if (fl->flags & FL_BUF_PACKING) {
2896 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2897 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2899 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2900 0, "producer index");
2901 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2902 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2903 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2904 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2905 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2906 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2907 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2908 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2909 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2910 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2914 alloc_fwq(struct adapter *sc)
2917 struct sge_iq *fwq = &sc->sge.fwq;
2918 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2919 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2921 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2922 fwq->flags |= IQ_INTR; /* always */
2923 if (sc->flags & IS_VF)
2926 intr_idx = sc->intr_count > 1 ? 1 : 0;
2927 fwq->set_tcb_rpl = t4_filter_rpl;
2928 fwq->l2t_write_rpl = do_l2t_write_rpl;
2930 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
2932 device_printf(sc->dev,
2933 "failed to create firmware event queue: %d\n", rc);
2937 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2938 NULL, "firmware event queue");
2939 children = SYSCTL_CHILDREN(oid);
2941 SYSCTL_ADD_UAUTO(&sc->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2942 &fwq->ba, "bus address of descriptor ring");
2943 SYSCTL_ADD_INT(&sc->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2944 fwq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
2945 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2946 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2947 "absolute id of the queue");
2948 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2949 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2950 "SGE context id of the queue");
2951 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2952 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2959 free_fwq(struct adapter *sc)
2961 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2965 alloc_mgmtq(struct adapter *sc)
2968 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2970 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2971 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2973 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2974 NULL, "management queue");
2976 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2977 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2978 sc->sge.fwq.cntxt_id, name);
2979 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2981 device_printf(sc->dev,
2982 "failed to create management queue: %d\n", rc);
2990 free_mgmtq(struct adapter *sc)
2993 return free_wrq(sc, &sc->sge.mgmtq);
2997 tnl_cong(struct port_info *pi, int drop)
3005 return (pi->rx_chan_map);
3009 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3010 struct sysctl_oid *oid)
3013 struct adapter *sc = vi->pi->adapter;
3014 struct sysctl_oid_list *children;
3017 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3018 tnl_cong(vi->pi, cong_drop));
3023 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3025 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3026 ("iq_base mismatch"));
3027 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3028 ("PF with non-zero iq_base"));
3031 * The freelist is just barely above the starvation threshold right now,
3032 * fill it up a bit more.
3035 refill_fl(sc, &rxq->fl, 128);
3036 FL_UNLOCK(&rxq->fl);
3038 #if defined(INET) || defined(INET6)
3039 rc = tcp_lro_init(&rxq->lro);
3042 rxq->lro.ifp = vi->ifp; /* also indicates LRO init'ed */
3044 if (vi->ifp->if_capenable & IFCAP_LRO)
3045 rxq->iq.flags |= IQ_LRO_ENABLED;
3049 children = SYSCTL_CHILDREN(oid);
3051 snprintf(name, sizeof(name), "%d", idx);
3052 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3054 children = SYSCTL_CHILDREN(oid);
3056 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3057 &rxq->iq.ba, "bus address of descriptor ring");
3058 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3059 rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3060 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3061 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
3062 "absolute id of the queue");
3063 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3064 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
3065 "SGE context id of the queue");
3066 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3067 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
3069 #if defined(INET) || defined(INET6)
3070 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3071 &rxq->lro.lro_queued, 0, NULL);
3072 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3073 &rxq->lro.lro_flushed, 0, NULL);
3075 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3076 &rxq->rxcsum, "# of times hardware assisted with checksum");
3077 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3078 CTLFLAG_RD, &rxq->vlan_extraction,
3079 "# of times hardware extracted 802.1Q tag");
3081 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3087 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3091 #if defined(INET) || defined(INET6)
3093 tcp_lro_free(&rxq->lro);
3094 rxq->lro.ifp = NULL;
3098 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3100 bzero(rxq, sizeof(*rxq));
3107 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3108 int intr_idx, int idx, struct sysctl_oid *oid)
3110 struct port_info *pi = vi->pi;
3112 struct sysctl_oid_list *children;
3115 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
3120 children = SYSCTL_CHILDREN(oid);
3122 snprintf(name, sizeof(name), "%d", idx);
3123 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3125 children = SYSCTL_CHILDREN(oid);
3127 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3128 &ofld_rxq->iq.ba, "bus address of descriptor ring");
3129 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3130 ofld_rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3131 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3132 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
3133 "I", "absolute id of the queue");
3134 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3135 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
3136 "I", "SGE context id of the queue");
3137 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3138 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
3141 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3147 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3151 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3153 bzero(ofld_rxq, sizeof(*ofld_rxq));
3161 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3162 int idx, struct sysctl_oid *oid)
3165 struct sysctl_oid_list *children;
3166 struct sysctl_ctx_list *ctx;
3169 struct adapter *sc = vi->pi->adapter;
3170 struct netmap_adapter *na = NA(vi->ifp);
3174 len = vi->qsize_rxq * IQ_ESIZE;
3175 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3176 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3180 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3181 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3182 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3188 nm_rxq->iq_cidx = 0;
3189 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3190 nm_rxq->iq_gen = F_RSPD_GEN;
3191 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3192 nm_rxq->fl_sidx = na->num_rx_desc;
3193 nm_rxq->intr_idx = intr_idx;
3196 children = SYSCTL_CHILDREN(oid);
3198 snprintf(name, sizeof(name), "%d", idx);
3199 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3201 children = SYSCTL_CHILDREN(oid);
3203 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3204 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3205 "I", "absolute id of the queue");
3206 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3207 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3208 "I", "SGE context id of the queue");
3209 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3210 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3213 children = SYSCTL_CHILDREN(oid);
3214 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3216 children = SYSCTL_CHILDREN(oid);
3218 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3219 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3220 "I", "SGE context id of the freelist");
3221 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3222 &nm_rxq->fl_cidx, 0, "consumer index");
3223 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3224 &nm_rxq->fl_pidx, 0, "producer index");
3231 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3233 struct adapter *sc = vi->pi->adapter;
3235 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3237 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3244 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3245 struct sysctl_oid *oid)
3249 struct port_info *pi = vi->pi;
3250 struct adapter *sc = pi->adapter;
3251 struct netmap_adapter *na = NA(vi->ifp);
3253 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3255 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3256 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3257 &nm_txq->ba, (void **)&nm_txq->desc);
3261 nm_txq->pidx = nm_txq->cidx = 0;
3262 nm_txq->sidx = na->num_tx_desc;
3264 nm_txq->iqidx = iqidx;
3265 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3266 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3267 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3268 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3270 snprintf(name, sizeof(name), "%d", idx);
3271 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3272 NULL, "netmap tx queue");
3273 children = SYSCTL_CHILDREN(oid);
3275 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3276 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3277 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3278 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3280 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3281 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3288 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3290 struct adapter *sc = vi->pi->adapter;
3292 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3300 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3303 struct fw_eq_ctrl_cmd c;
3304 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3306 bzero(&c, sizeof(c));
3308 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3309 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3310 V_FW_EQ_CTRL_CMD_VFN(0));
3311 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3312 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3313 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3314 c.physeqid_pkd = htobe32(0);
3315 c.fetchszm_to_iqid =
3316 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3317 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3318 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3320 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3321 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3322 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3323 c.eqaddr = htobe64(eq->ba);
3325 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3327 device_printf(sc->dev,
3328 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3331 eq->flags |= EQ_ALLOCATED;
3333 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3334 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3335 if (cntxt_id >= sc->sge.neq)
3336 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3337 cntxt_id, sc->sge.neq - 1);
3338 sc->sge.eqmap[cntxt_id] = eq;
3344 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3347 struct fw_eq_eth_cmd c;
3348 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3350 bzero(&c, sizeof(c));
3352 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3353 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3354 V_FW_EQ_ETH_CMD_VFN(0));
3355 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3356 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3357 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3358 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3359 c.fetchszm_to_iqid =
3360 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3361 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3362 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3363 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3364 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3365 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3366 c.eqaddr = htobe64(eq->ba);
3368 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3370 device_printf(vi->dev,
3371 "failed to create Ethernet egress queue: %d\n", rc);
3374 eq->flags |= EQ_ALLOCATED;
3376 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3377 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3378 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3379 if (cntxt_id >= sc->sge.neq)
3380 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3381 cntxt_id, sc->sge.neq - 1);
3382 sc->sge.eqmap[cntxt_id] = eq;
3389 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3392 struct fw_eq_ofld_cmd c;
3393 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3395 bzero(&c, sizeof(c));
3397 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3398 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3399 V_FW_EQ_OFLD_CMD_VFN(0));
3400 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3401 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3402 c.fetchszm_to_iqid =
3403 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3404 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3405 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3407 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3408 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3409 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3410 c.eqaddr = htobe64(eq->ba);
3412 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3414 device_printf(vi->dev,
3415 "failed to create egress queue for TCP offload: %d\n", rc);
3418 eq->flags |= EQ_ALLOCATED;
3420 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3421 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3422 if (cntxt_id >= sc->sge.neq)
3423 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3424 cntxt_id, sc->sge.neq - 1);
3425 sc->sge.eqmap[cntxt_id] = eq;
3432 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3437 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3439 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3440 len = qsize * EQ_ESIZE;
3441 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3442 &eq->ba, (void **)&eq->desc);
3446 eq->pidx = eq->cidx = 0;
3447 eq->equeqidx = eq->dbidx = 0;
3448 eq->doorbells = sc->doorbells;
3450 switch (eq->flags & EQ_TYPEMASK) {
3452 rc = ctrl_eq_alloc(sc, eq);
3456 rc = eth_eq_alloc(sc, vi, eq);
3461 rc = ofld_eq_alloc(sc, vi, eq);
3466 panic("%s: invalid eq type %d.", __func__,
3467 eq->flags & EQ_TYPEMASK);
3470 device_printf(sc->dev,
3471 "failed to allocate egress queue(%d): %d\n",
3472 eq->flags & EQ_TYPEMASK, rc);
3475 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3476 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3477 isset(&eq->doorbells, DOORBELL_WCWR)) {
3478 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3479 uint32_t mask = (1 << s_qpp) - 1;
3480 volatile uint8_t *udb;
3482 udb = sc->udbs_base + UDBS_DB_OFFSET;
3483 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3484 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3485 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3486 clrbit(&eq->doorbells, DOORBELL_WCWR);
3488 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3491 eq->udb = (volatile void *)udb;
3498 free_eq(struct adapter *sc, struct sge_eq *eq)
3502 if (eq->flags & EQ_ALLOCATED) {
3503 switch (eq->flags & EQ_TYPEMASK) {
3505 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3510 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3516 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3522 panic("%s: invalid eq type %d.", __func__,
3523 eq->flags & EQ_TYPEMASK);
3526 device_printf(sc->dev,
3527 "failed to free egress queue (%d): %d\n",
3528 eq->flags & EQ_TYPEMASK, rc);
3531 eq->flags &= ~EQ_ALLOCATED;
3534 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3536 if (mtx_initialized(&eq->eq_lock))
3537 mtx_destroy(&eq->eq_lock);
3539 bzero(eq, sizeof(*eq));
3544 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3545 struct sysctl_oid *oid)
3548 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3549 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3551 rc = alloc_eq(sc, vi, &wrq->eq);
3556 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3557 TAILQ_INIT(&wrq->incomplete_wrs);
3558 STAILQ_INIT(&wrq->wr_list);
3559 wrq->nwr_pending = 0;
3560 wrq->ndesc_needed = 0;
3562 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3563 &wrq->eq.ba, "bus address of descriptor ring");
3564 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3565 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
3566 "desc ring size in bytes");
3567 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3568 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3569 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3570 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3572 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3573 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3575 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3576 wrq->eq.sidx, "status page index");
3577 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3578 &wrq->tx_wrs_direct, "# of work requests (direct)");
3579 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3580 &wrq->tx_wrs_copied, "# of work requests (copied)");
3581 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
3582 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
3588 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3592 rc = free_eq(sc, &wrq->eq);
3596 bzero(wrq, sizeof(*wrq));
3601 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3602 struct sysctl_oid *oid)
3605 struct port_info *pi = vi->pi;
3606 struct adapter *sc = pi->adapter;
3607 struct sge_eq *eq = &txq->eq;
3609 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3611 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3614 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3618 rc = alloc_eq(sc, vi, eq);
3620 mp_ring_free(txq->r);
3625 /* Can't fail after this point. */
3628 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
3630 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
3631 ("eq_base mismatch"));
3632 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
3633 ("PF with non-zero eq_base"));
3635 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3637 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3638 if (sc->flags & IS_VF)
3639 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
3640 V_TXPKT_INTF(pi->tx_chan));
3642 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3643 V_TXPKT_INTF(pi->tx_chan) |
3644 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3645 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3646 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3648 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3651 snprintf(name, sizeof(name), "%d", idx);
3652 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3654 children = SYSCTL_CHILDREN(oid);
3656 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3657 &eq->ba, "bus address of descriptor ring");
3658 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3659 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3660 "desc ring size in bytes");
3661 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3662 &eq->abs_id, 0, "absolute id of the queue");
3663 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3664 &eq->cntxt_id, 0, "SGE context id of the queue");
3665 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3666 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3668 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3669 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3671 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3672 eq->sidx, "status page index");
3674 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
3675 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
3676 "traffic class (-1 means none)");
3678 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3679 &txq->txcsum, "# of times hardware assisted with checksum");
3680 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3681 CTLFLAG_RD, &txq->vlan_insertion,
3682 "# of times hardware inserted 802.1Q tag");
3683 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3684 &txq->tso_wrs, "# of TSO work requests");
3685 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3686 &txq->imm_wrs, "# of work requests with immediate data");
3687 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3688 &txq->sgl_wrs, "# of work requests with direct SGL");
3689 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3690 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3691 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3692 CTLFLAG_RD, &txq->txpkts0_wrs,
3693 "# of txpkts (type 0) work requests");
3694 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3695 CTLFLAG_RD, &txq->txpkts1_wrs,
3696 "# of txpkts (type 1) work requests");
3697 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3698 CTLFLAG_RD, &txq->txpkts0_pkts,
3699 "# of frames tx'd using type0 txpkts work requests");
3700 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3701 CTLFLAG_RD, &txq->txpkts1_pkts,
3702 "# of frames tx'd using type1 txpkts work requests");
3704 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3705 CTLFLAG_RD, &txq->r->enqueues,
3706 "# of enqueues to the mp_ring for this queue");
3707 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3708 CTLFLAG_RD, &txq->r->drops,
3709 "# of drops in the mp_ring for this queue");
3710 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3711 CTLFLAG_RD, &txq->r->starts,
3712 "# of normal consumer starts in the mp_ring for this queue");
3713 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3714 CTLFLAG_RD, &txq->r->stalls,
3715 "# of consumer stalls in the mp_ring for this queue");
3716 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3717 CTLFLAG_RD, &txq->r->restarts,
3718 "# of consumer restarts in the mp_ring for this queue");
3719 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3720 CTLFLAG_RD, &txq->r->abdications,
3721 "# of consumer abdications in the mp_ring for this queue");
3727 free_txq(struct vi_info *vi, struct sge_txq *txq)
3730 struct adapter *sc = vi->pi->adapter;
3731 struct sge_eq *eq = &txq->eq;
3733 rc = free_eq(sc, eq);
3737 sglist_free(txq->gl);
3738 free(txq->sdesc, M_CXGBE);
3739 mp_ring_free(txq->r);
3741 bzero(txq, sizeof(*txq));
3746 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3748 bus_addr_t *ba = arg;
3751 ("%s meant for single segment mappings only.", __func__));
3753 *ba = error ? 0 : segs->ds_addr;
3757 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3761 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3765 v = fl->dbval | V_PIDX(n);
3767 *fl->udb = htole32(v);
3769 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
3770 IDXINCR(fl->dbidx, n, fl->sidx);
3774 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are
3775 * recycled do not count towards this allocation budget.
3777 * Returns non-zero to indicate that this freelist should be added to the list
3778 * of starving freelists.
3781 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3784 struct fl_sdesc *sd;
3787 struct cluster_layout *cll;
3788 struct sw_zone_info *swz;
3789 struct cluster_metadata *clm;
3791 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3793 FL_LOCK_ASSERT_OWNED(fl);
3796 * We always stop at the begining of the hardware descriptor that's just
3797 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3798 * which would mean an empty freelist to the chip.
3800 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3801 if (fl->pidx == max_pidx * 8)
3804 d = &fl->desc[fl->pidx];
3805 sd = &fl->sdesc[fl->pidx];
3806 cll = &fl->cll_def; /* default layout */
3807 swz = &sc->sge.sw_zone_info[cll->zidx];
3811 if (sd->cl != NULL) {
3813 if (sd->nmbuf == 0) {
3815 * Fast recycle without involving any atomics on
3816 * the cluster's metadata (if the cluster has
3817 * metadata). This happens when all frames
3818 * received in the cluster were small enough to
3819 * fit within a single mbuf each.
3821 fl->cl_fast_recycled++;
3823 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3825 MPASS(clm->refcount == 1);
3831 * Cluster is guaranteed to have metadata. Clusters
3832 * without metadata always take the fast recycle path
3833 * when they're recycled.
3835 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3838 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3840 counter_u64_add(extfree_rels, 1);
3843 sd->cl = NULL; /* gave up my reference */
3845 MPASS(sd->cl == NULL);
3847 cl = uma_zalloc(swz->zone, M_NOWAIT);
3848 if (__predict_false(cl == NULL)) {
3849 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3850 fl->cll_def.zidx == fl->cll_alt.zidx)
3853 /* fall back to the safe zone */
3855 swz = &sc->sge.sw_zone_info[cll->zidx];
3861 pa = pmap_kextract((vm_offset_t)cl);
3865 *d = htobe64(pa | cll->hwidx);
3866 clm = cl_metadata(sc, fl, cll, cl);
3878 if (__predict_false(++fl->pidx % 8 == 0)) {
3879 uint16_t pidx = fl->pidx / 8;
3881 if (__predict_false(pidx == fl->sidx)) {
3887 if (pidx == max_pidx)
3890 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3895 if (fl->pidx / 8 != fl->dbidx)
3898 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3902 * Attempt to refill all starving freelists.
3905 refill_sfl(void *arg)
3907 struct adapter *sc = arg;
3908 struct sge_fl *fl, *fl_temp;
3910 mtx_assert(&sc->sfl_lock, MA_OWNED);
3911 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3913 refill_fl(sc, fl, 64);
3914 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3915 TAILQ_REMOVE(&sc->sfl, fl, link);
3916 fl->flags &= ~FL_STARVING;
3921 if (!TAILQ_EMPTY(&sc->sfl))
3922 callout_schedule(&sc->sfl_callout, hz / 5);
3926 alloc_fl_sdesc(struct sge_fl *fl)
3929 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3936 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3938 struct fl_sdesc *sd;
3939 struct cluster_metadata *clm;
3940 struct cluster_layout *cll;
3944 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3949 clm = cl_metadata(sc, fl, cll, sd->cl);
3951 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3952 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3953 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3954 counter_u64_add(extfree_rels, 1);
3959 free(fl->sdesc, M_CXGBE);
3964 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3971 rc = sglist_append_mbuf(gl, m);
3972 if (__predict_false(rc != 0)) {
3973 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3974 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3977 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3978 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3979 mbuf_nsegs(m), gl->sg_nseg));
3980 KASSERT(gl->sg_nseg > 0 &&
3981 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
3982 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
3983 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
3987 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
3990 txpkt_len16(u_int nsegs, u_int tso)
3996 nsegs--; /* first segment is part of ulptx_sgl */
3997 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
3998 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4000 n += sizeof(struct cpl_tx_pkt_lso_core);
4002 return (howmany(n, 16));
4006 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4010 txpkt_vm_len16(u_int nsegs, u_int tso)
4016 nsegs--; /* first segment is part of ulptx_sgl */
4017 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4018 sizeof(struct cpl_tx_pkt_core) +
4019 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4021 n += sizeof(struct cpl_tx_pkt_lso_core);
4023 return (howmany(n, 16));
4027 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4031 txpkts0_len16(u_int nsegs)
4037 nsegs--; /* first segment is part of ulptx_sgl */
4038 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4039 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4040 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4042 return (howmany(n, 16));
4046 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4054 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4056 return (howmany(n, 16));
4060 imm_payload(u_int ndesc)
4064 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4065 sizeof(struct cpl_tx_pkt_core);
4071 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4072 * software descriptor, and advance the pidx. It is guaranteed that enough
4073 * descriptors are available.
4075 * The return value is the # of hardware descriptors used.
4078 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4079 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4081 struct sge_eq *eq = &txq->eq;
4082 struct tx_sdesc *txsd;
4083 struct cpl_tx_pkt_core *cpl;
4084 uint32_t ctrl; /* used in many unrelated places */
4086 int csum_type, len16, ndesc, pktlen, nsegs;
4089 TXQ_LOCK_ASSERT_OWNED(txq);
4091 MPASS(available > 0 && available < eq->sidx);
4093 len16 = mbuf_len16(m0);
4094 nsegs = mbuf_nsegs(m0);
4095 pktlen = m0->m_pkthdr.len;
4096 ctrl = sizeof(struct cpl_tx_pkt_core);
4098 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4099 ndesc = howmany(len16, EQ_ESIZE / 16);
4100 MPASS(ndesc <= available);
4102 /* Firmware work request header */
4103 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4104 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4105 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4107 ctrl = V_FW_WR_LEN16(len16);
4108 wr->equiq_to_len16 = htobe32(ctrl);
4113 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4114 * vlantci is ignored unless the ethtype is 0x8100, so it's
4115 * simpler to always copy it rather than making it
4116 * conditional. Also, it seems that we do not have to set
4117 * vlantci or fake the ethtype when doing VLAN tag insertion.
4119 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4122 if (needs_tso(m0)) {
4123 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4125 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4126 m0->m_pkthdr.l4hlen > 0,
4127 ("%s: mbuf %p needs TSO but missing header lengths",
4130 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4131 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4132 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4133 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4134 ctrl |= V_LSO_ETHHDR_LEN(1);
4135 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4138 lso->lso_ctrl = htobe32(ctrl);
4139 lso->ipid_ofst = htobe16(0);
4140 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4141 lso->seqno_offset = htobe32(0);
4142 lso->len = htobe32(pktlen);
4144 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4145 csum_type = TX_CSUM_TCPIP6;
4147 csum_type = TX_CSUM_TCPIP;
4149 cpl = (void *)(lso + 1);
4153 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP)
4154 csum_type = TX_CSUM_TCPIP;
4155 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP)
4156 csum_type = TX_CSUM_UDPIP;
4157 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP)
4158 csum_type = TX_CSUM_TCPIP6;
4159 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP)
4160 csum_type = TX_CSUM_UDPIP6;
4162 else if (m0->m_pkthdr.csum_flags & CSUM_IP) {
4164 * XXX: The firmware appears to stomp on the
4165 * fragment/flags field of the IP header when
4166 * using TX_CSUM_IP. Fall back to doing
4167 * software checksums.
4175 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen +
4176 offsetof(struct ip, ip_sum));
4177 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen +
4178 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen);
4179 m0->m_pkthdr.csum_flags &= ~CSUM_IP;
4183 cpl = (void *)(wr + 1);
4186 /* Checksum offload */
4188 if (needs_l3_csum(m0) == 0)
4189 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4190 if (csum_type >= 0) {
4191 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0,
4192 ("%s: mbuf %p needs checksum offload but missing header lengths",
4195 if (chip_id(sc) <= CHELSIO_T5) {
4196 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4199 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4202 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
4203 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
4205 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4206 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4207 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4208 txq->txcsum++; /* some hardware assistance provided */
4210 /* VLAN tag insertion */
4211 if (needs_vlan_insertion(m0)) {
4212 ctrl1 |= F_TXPKT_VLAN_VLD |
4213 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4214 txq->vlan_insertion++;
4218 cpl->ctrl0 = txq->cpl_ctrl0;
4220 cpl->len = htobe16(pktlen);
4221 cpl->ctrl1 = htobe64(ctrl1);
4224 dst = (void *)(cpl + 1);
4227 * A packet using TSO will use up an entire descriptor for the
4228 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4229 * If this descriptor is the last descriptor in the ring, wrap
4230 * around to the front of the ring explicitly for the start of
4233 if (dst == (void *)&eq->desc[eq->sidx]) {
4234 dst = (void *)&eq->desc[0];
4235 write_gl_to_txd(txq, m0, &dst, 0);
4237 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4242 txsd = &txq->sdesc[eq->pidx];
4244 txsd->desc_used = ndesc;
4250 * Write a txpkt WR for this packet to the hardware descriptors, update the
4251 * software descriptor, and advance the pidx. It is guaranteed that enough
4252 * descriptors are available.
4254 * The return value is the # of hardware descriptors used.
4257 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
4258 struct mbuf *m0, u_int available)
4260 struct sge_eq *eq = &txq->eq;
4261 struct tx_sdesc *txsd;
4262 struct cpl_tx_pkt_core *cpl;
4263 uint32_t ctrl; /* used in many unrelated places */
4265 int len16, ndesc, pktlen, nsegs;
4268 TXQ_LOCK_ASSERT_OWNED(txq);
4270 MPASS(available > 0 && available < eq->sidx);
4272 len16 = mbuf_len16(m0);
4273 nsegs = mbuf_nsegs(m0);
4274 pktlen = m0->m_pkthdr.len;
4275 ctrl = sizeof(struct cpl_tx_pkt_core);
4277 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4278 else if (pktlen <= imm_payload(2) && available >= 2) {
4279 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4281 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4282 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4285 ndesc = howmany(len16, EQ_ESIZE / 16);
4286 MPASS(ndesc <= available);
4288 /* Firmware work request header */
4289 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4290 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4291 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4293 ctrl = V_FW_WR_LEN16(len16);
4294 wr->equiq_to_len16 = htobe32(ctrl);
4297 if (needs_tso(m0)) {
4298 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4300 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4301 m0->m_pkthdr.l4hlen > 0,
4302 ("%s: mbuf %p needs TSO but missing header lengths",
4305 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4306 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4307 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4308 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4309 ctrl |= V_LSO_ETHHDR_LEN(1);
4310 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4313 lso->lso_ctrl = htobe32(ctrl);
4314 lso->ipid_ofst = htobe16(0);
4315 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4316 lso->seqno_offset = htobe32(0);
4317 lso->len = htobe32(pktlen);
4319 cpl = (void *)(lso + 1);
4323 cpl = (void *)(wr + 1);
4325 /* Checksum offload */
4327 if (needs_l3_csum(m0) == 0)
4328 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4329 if (needs_l4_csum(m0) == 0)
4330 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4331 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4332 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4333 txq->txcsum++; /* some hardware assistance provided */
4335 /* VLAN tag insertion */
4336 if (needs_vlan_insertion(m0)) {
4337 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4338 txq->vlan_insertion++;
4342 cpl->ctrl0 = txq->cpl_ctrl0;
4344 cpl->len = htobe16(pktlen);
4345 cpl->ctrl1 = htobe64(ctrl1);
4348 dst = (void *)(cpl + 1);
4351 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4356 for (m = m0; m != NULL; m = m->m_next) {
4357 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4363 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4370 txsd = &txq->sdesc[eq->pidx];
4372 txsd->desc_used = ndesc;
4378 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4380 u_int needed, nsegs1, nsegs2, l1, l2;
4382 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4385 nsegs1 = mbuf_nsegs(m);
4386 nsegs2 = mbuf_nsegs(n);
4387 if (nsegs1 + nsegs2 == 2) {
4389 l1 = l2 = txpkts1_len16();
4392 l1 = txpkts0_len16(nsegs1);
4393 l2 = txpkts0_len16(nsegs2);
4395 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4396 needed = howmany(txp->len16, EQ_ESIZE / 16);
4397 if (needed > SGE_MAX_WR_NDESC || needed > available)
4400 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4401 if (txp->plen > 65535)
4405 set_mbuf_len16(m, l1);
4406 set_mbuf_len16(n, l2);
4412 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4414 u_int plen, len16, needed, nsegs;
4416 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4418 nsegs = mbuf_nsegs(m);
4419 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4422 plen = txp->plen + m->m_pkthdr.len;
4426 if (txp->wr_type == 0)
4427 len16 = txpkts0_len16(nsegs);
4429 len16 = txpkts1_len16();
4430 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4431 if (needed > SGE_MAX_WR_NDESC || needed > available)
4436 txp->len16 += len16;
4437 set_mbuf_len16(m, len16);
4443 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4444 * the software descriptor, and advance the pidx. It is guaranteed that enough
4445 * descriptors are available.
4447 * The return value is the # of hardware descriptors used.
4450 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4451 struct mbuf *m0, const struct txpkts *txp, u_int available)
4453 struct sge_eq *eq = &txq->eq;
4454 struct tx_sdesc *txsd;
4455 struct cpl_tx_pkt_core *cpl;
4458 int ndesc, checkwrap;
4462 TXQ_LOCK_ASSERT_OWNED(txq);
4463 MPASS(txp->npkt > 0);
4464 MPASS(txp->plen < 65536);
4466 MPASS(m0->m_nextpkt != NULL);
4467 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4468 MPASS(available > 0 && available < eq->sidx);
4470 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4471 MPASS(ndesc <= available);
4473 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4474 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4475 ctrl = V_FW_WR_LEN16(txp->len16);
4476 wr->equiq_to_len16 = htobe32(ctrl);
4477 wr->plen = htobe16(txp->plen);
4478 wr->npkt = txp->npkt;
4480 wr->type = txp->wr_type;
4484 * At this point we are 16B into a hardware descriptor. If checkwrap is
4485 * set then we know the WR is going to wrap around somewhere. We'll
4486 * check for that at appropriate points.
4488 checkwrap = eq->sidx - ndesc < eq->pidx;
4489 for (m = m0; m != NULL; m = m->m_nextpkt) {
4490 if (txp->wr_type == 0) {
4491 struct ulp_txpkt *ulpmc;
4492 struct ulptx_idata *ulpsc;
4494 /* ULP master command */
4496 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4497 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4498 ulpmc->len = htobe32(mbuf_len16(m));
4500 /* ULP subcommand */
4501 ulpsc = (void *)(ulpmc + 1);
4502 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4504 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4506 cpl = (void *)(ulpsc + 1);
4508 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4509 cpl = (void *)&eq->desc[0];
4510 txq->txpkts0_pkts += txp->npkt;
4514 txq->txpkts1_pkts += txp->npkt;
4518 /* Checksum offload */
4520 if (needs_l3_csum(m) == 0)
4521 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4522 if (needs_l4_csum(m) == 0)
4523 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4524 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4525 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4526 txq->txcsum++; /* some hardware assistance provided */
4528 /* VLAN tag insertion */
4529 if (needs_vlan_insertion(m)) {
4530 ctrl1 |= F_TXPKT_VLAN_VLD |
4531 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4532 txq->vlan_insertion++;
4536 cpl->ctrl0 = txq->cpl_ctrl0;
4538 cpl->len = htobe16(m->m_pkthdr.len);
4539 cpl->ctrl1 = htobe64(ctrl1);
4543 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4544 flitp = (void *)&eq->desc[0];
4546 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4550 txsd = &txq->sdesc[eq->pidx];
4552 txsd->desc_used = ndesc;
4558 * If the SGL ends on an address that is not 16 byte aligned, this function will
4559 * add a 0 filled flit at the end.
4562 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4564 struct sge_eq *eq = &txq->eq;
4565 struct sglist *gl = txq->gl;
4566 struct sglist_seg *seg;
4567 __be64 *flitp, *wrap;
4568 struct ulptx_sgl *usgl;
4569 int i, nflits, nsegs;
4571 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4572 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4573 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4574 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4577 nsegs = gl->sg_nseg;
4580 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4581 flitp = (__be64 *)(*to);
4582 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4583 seg = &gl->sg_segs[0];
4584 usgl = (void *)flitp;
4587 * We start at a 16 byte boundary somewhere inside the tx descriptor
4588 * ring, so we're at least 16 bytes away from the status page. There is
4589 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4592 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4593 V_ULPTX_NSGE(nsegs));
4594 usgl->len0 = htobe32(seg->ss_len);
4595 usgl->addr0 = htobe64(seg->ss_paddr);
4598 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4600 /* Won't wrap around at all */
4602 for (i = 0; i < nsegs - 1; i++, seg++) {
4603 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4604 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4607 usgl->sge[i / 2].len[1] = htobe32(0);
4611 /* Will wrap somewhere in the rest of the SGL */
4613 /* 2 flits already written, write the rest flit by flit */
4614 flitp = (void *)(usgl + 1);
4615 for (i = 0; i < nflits - 2; i++) {
4617 flitp = (void *)eq->desc;
4618 *flitp++ = get_flit(seg, nsegs - 1, i);
4623 MPASS(((uintptr_t)flitp) & 0xf);
4627 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4628 if (__predict_false(flitp == wrap))
4629 *to = (void *)eq->desc;
4631 *to = (void *)flitp;
4635 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4638 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4639 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4641 if (__predict_true((uintptr_t)(*to) + len <=
4642 (uintptr_t)&eq->desc[eq->sidx])) {
4643 bcopy(from, *to, len);
4646 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4648 bcopy(from, *to, portion);
4650 portion = len - portion; /* remaining */
4651 bcopy(from, (void *)eq->desc, portion);
4652 (*to) = (caddr_t)eq->desc + portion;
4657 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4665 clrbit(&db, DOORBELL_WCWR);
4668 switch (ffs(db) - 1) {
4670 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4673 case DOORBELL_WCWR: {
4674 volatile uint64_t *dst, *src;
4678 * Queues whose 128B doorbell segment fits in the page do not
4679 * use relative qid (udb_qid is always 0). Only queues with
4680 * doorbell segments can do WCWR.
4682 KASSERT(eq->udb_qid == 0 && n == 1,
4683 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4684 __func__, eq->doorbells, n, eq->dbidx, eq));
4686 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4689 src = (void *)&eq->desc[i];
4690 while (src != (void *)&eq->desc[i + 1])
4696 case DOORBELL_UDBWC:
4697 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4702 t4_write_reg(sc, sc->sge_kdoorbell_reg,
4703 V_QID(eq->cntxt_id) | V_PIDX(n));
4707 IDXINCR(eq->dbidx, n, eq->sidx);
4711 reclaimable_tx_desc(struct sge_eq *eq)
4715 hw_cidx = read_hw_cidx(eq);
4716 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4720 total_available_tx_desc(struct sge_eq *eq)
4722 uint16_t hw_cidx, pidx;
4724 hw_cidx = read_hw_cidx(eq);
4727 if (pidx == hw_cidx)
4728 return (eq->sidx - 1);
4730 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4733 static inline uint16_t
4734 read_hw_cidx(struct sge_eq *eq)
4736 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4737 uint16_t cidx = spg->cidx; /* stable snapshot */
4739 return (be16toh(cidx));
4743 * Reclaim 'n' descriptors approximately.
4746 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4748 struct tx_sdesc *txsd;
4749 struct sge_eq *eq = &txq->eq;
4750 u_int can_reclaim, reclaimed;
4752 TXQ_LOCK_ASSERT_OWNED(txq);
4756 can_reclaim = reclaimable_tx_desc(eq);
4757 while (can_reclaim && reclaimed < n) {
4759 struct mbuf *m, *nextpkt;
4761 txsd = &txq->sdesc[eq->cidx];
4762 ndesc = txsd->desc_used;
4764 /* Firmware doesn't return "partial" credits. */
4765 KASSERT(can_reclaim >= ndesc,
4766 ("%s: unexpected number of credits: %d, %d",
4767 __func__, can_reclaim, ndesc));
4769 for (m = txsd->m; m != NULL; m = nextpkt) {
4770 nextpkt = m->m_nextpkt;
4771 m->m_nextpkt = NULL;
4775 can_reclaim -= ndesc;
4776 IDXINCR(eq->cidx, ndesc, eq->sidx);
4783 tx_reclaim(void *arg, int n)
4785 struct sge_txq *txq = arg;
4786 struct sge_eq *eq = &txq->eq;
4789 if (TXQ_TRYLOCK(txq) == 0)
4791 n = reclaim_tx_descs(txq, 32);
4792 if (eq->cidx == eq->pidx)
4793 eq->equeqidx = eq->pidx;
4799 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4801 int i = (idx / 3) * 2;
4807 rc = htobe32(segs[i].ss_len);
4809 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4814 return (htobe64(segs[i].ss_paddr));
4816 return (htobe64(segs[i + 1].ss_paddr));
4823 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4825 int8_t zidx, hwidx, idx;
4826 uint16_t region1, region3;
4827 int spare, spare_needed, n;
4828 struct sw_zone_info *swz;
4829 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4832 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4833 * large enough for the max payload and cluster metadata. Otherwise
4834 * settle for the largest bufsize that leaves enough room in the cluster
4837 * Without buffer packing: Look for the smallest zone which has a
4838 * bufsize large enough for the max payload. Settle for the largest
4839 * bufsize available if there's nothing big enough for max payload.
4841 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4842 swz = &sc->sge.sw_zone_info[0];
4844 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4845 if (swz->size > largest_rx_cluster) {
4846 if (__predict_true(hwidx != -1))
4850 * This is a misconfiguration. largest_rx_cluster is
4851 * preventing us from finding a refill source. See
4852 * dev.t5nex.<n>.buffer_sizes to figure out why.
4854 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4855 " refill source for fl %p (dma %u). Ignored.\n",
4856 largest_rx_cluster, fl, maxp);
4858 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4859 hwb = &hwb_list[idx];
4860 spare = swz->size - hwb->size;
4861 if (spare < spare_needed)
4864 hwidx = idx; /* best option so far */
4865 if (hwb->size >= maxp) {
4867 if ((fl->flags & FL_BUF_PACKING) == 0)
4868 goto done; /* stop looking (not packing) */
4870 if (swz->size >= safest_rx_cluster)
4871 goto done; /* stop looking (packing) */
4873 break; /* keep looking, next zone */
4877 /* A usable hwidx has been located. */
4879 hwb = &hwb_list[hwidx];
4881 swz = &sc->sge.sw_zone_info[zidx];
4883 region3 = swz->size - hwb->size;
4886 * Stay within this zone and see if there is a better match when mbuf
4887 * inlining is allowed. Remember that the hwidx's are sorted in
4888 * decreasing order of size (so in increasing order of spare area).
4890 for (idx = hwidx; idx != -1; idx = hwb->next) {
4891 hwb = &hwb_list[idx];
4892 spare = swz->size - hwb->size;
4894 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4898 * Do not inline mbufs if doing so would violate the pad/pack
4899 * boundary alignment requirement.
4901 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
4903 if (fl->flags & FL_BUF_PACKING &&
4904 (MSIZE % sc->params.sge.pack_boundary) != 0)
4907 if (spare < CL_METADATA_SIZE + MSIZE)
4909 n = (spare - CL_METADATA_SIZE) / MSIZE;
4910 if (n > howmany(hwb->size, maxp))
4914 if (fl->flags & FL_BUF_PACKING) {
4915 region1 = n * MSIZE;
4916 region3 = spare - region1;
4919 region3 = spare - region1;
4924 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4925 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4926 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4927 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4928 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4929 sc->sge.sw_zone_info[zidx].size,
4930 ("%s: bad buffer layout for fl %p, maxp %d. "
4931 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4932 sc->sge.sw_zone_info[zidx].size, region1,
4933 sc->sge.hw_buf_info[hwidx].size, region3));
4934 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4935 KASSERT(region3 >= CL_METADATA_SIZE,
4936 ("%s: no room for metadata. fl %p, maxp %d; "
4937 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4938 sc->sge.sw_zone_info[zidx].size, region1,
4939 sc->sge.hw_buf_info[hwidx].size, region3));
4940 KASSERT(region1 % MSIZE == 0,
4941 ("%s: bad mbuf region for fl %p, maxp %d. "
4942 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4943 sc->sge.sw_zone_info[zidx].size, region1,
4944 sc->sge.hw_buf_info[hwidx].size, region3));
4947 fl->cll_def.zidx = zidx;
4948 fl->cll_def.hwidx = hwidx;
4949 fl->cll_def.region1 = region1;
4950 fl->cll_def.region3 = region3;
4954 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4956 struct sge *s = &sc->sge;
4957 struct hw_buf_info *hwb;
4958 struct sw_zone_info *swz;
4962 if (fl->flags & FL_BUF_PACKING)
4963 hwidx = s->safe_hwidx2; /* with room for metadata */
4964 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4965 hwidx = s->safe_hwidx2;
4966 hwb = &s->hw_buf_info[hwidx];
4967 swz = &s->sw_zone_info[hwb->zidx];
4968 spare = swz->size - hwb->size;
4970 /* no good if there isn't room for an mbuf as well */
4971 if (spare < CL_METADATA_SIZE + MSIZE)
4972 hwidx = s->safe_hwidx1;
4974 hwidx = s->safe_hwidx1;
4977 /* No fallback source */
4978 fl->cll_alt.hwidx = -1;
4979 fl->cll_alt.zidx = -1;
4984 hwb = &s->hw_buf_info[hwidx];
4985 swz = &s->sw_zone_info[hwb->zidx];
4986 spare = swz->size - hwb->size;
4987 fl->cll_alt.hwidx = hwidx;
4988 fl->cll_alt.zidx = hwb->zidx;
4989 if (allow_mbufs_in_cluster &&
4990 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
4991 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
4993 fl->cll_alt.region1 = 0;
4994 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
4998 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5000 mtx_lock(&sc->sfl_lock);
5002 if ((fl->flags & FL_DOOMED) == 0) {
5003 fl->flags |= FL_STARVING;
5004 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5005 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5008 mtx_unlock(&sc->sfl_lock);
5012 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5014 struct sge_wrq *wrq = (void *)eq;
5016 atomic_readandclear_int(&eq->equiq);
5017 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5021 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5023 struct sge_txq *txq = (void *)eq;
5025 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5027 atomic_readandclear_int(&eq->equiq);
5028 mp_ring_check_drainage(txq->r, 0);
5029 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5033 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5036 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5037 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5038 struct adapter *sc = iq->adapter;
5039 struct sge *s = &sc->sge;
5041 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5042 &handle_wrq_egr_update, &handle_eth_egr_update,
5043 &handle_wrq_egr_update};
5045 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5048 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5049 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5054 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5055 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5056 offsetof(struct cpl_fw6_msg, data));
5059 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5061 struct adapter *sc = iq->adapter;
5062 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5064 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5067 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5068 const struct rss_header *rss2;
5070 rss2 = (const struct rss_header *)&cpl->data[0];
5071 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5074 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5078 * t4_handle_wrerr_rpl - process a FW work request error message
5079 * @adap: the adapter
5080 * @rpl: start of the FW message
5083 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5085 u8 opcode = *(const u8 *)rpl;
5086 const struct fw_error_cmd *e = (const void *)rpl;
5089 if (opcode != FW_ERROR_CMD) {
5091 "%s: Received WRERR_RPL message with opcode %#x\n",
5092 device_get_nameunit(adap->dev), opcode);
5095 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5096 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5098 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5099 case FW_ERROR_TYPE_EXCEPTION:
5100 log(LOG_ERR, "exception info:\n");
5101 for (i = 0; i < nitems(e->u.exception.info); i++)
5102 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5103 be32toh(e->u.exception.info[i]));
5106 case FW_ERROR_TYPE_HWMODULE:
5107 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5108 be32toh(e->u.hwmodule.regaddr),
5109 be32toh(e->u.hwmodule.regval));
5111 case FW_ERROR_TYPE_WR:
5112 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5113 be16toh(e->u.wr.cidx),
5114 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5115 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5116 be32toh(e->u.wr.eqid));
5117 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5118 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5122 case FW_ERROR_TYPE_ACL:
5123 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5124 be16toh(e->u.acl.cidx),
5125 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5126 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5127 be32toh(e->u.acl.eqid),
5128 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5130 for (i = 0; i < nitems(e->u.acl.val); i++)
5131 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5135 log(LOG_ERR, "type %#x\n",
5136 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5143 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5145 uint16_t *id = arg1;
5148 return sysctl_handle_int(oidp, &i, 0, req);
5152 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5154 struct sge *s = arg1;
5155 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5156 struct sw_zone_info *swz = &s->sw_zone_info[0];
5161 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5162 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5163 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5168 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5172 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5178 sysctl_tc(SYSCTL_HANDLER_ARGS)
5180 struct vi_info *vi = arg1;
5181 struct port_info *pi;
5183 struct sge_txq *txq;
5184 struct tx_sched_class *tc;
5185 int qidx = arg2, rc, tc_idx;
5186 uint32_t fw_queue, fw_class;
5188 MPASS(qidx >= 0 && qidx < vi->ntxq);
5191 txq = &sc->sge.txq[vi->first_txq + qidx];
5193 tc_idx = txq->tc_idx;
5194 rc = sysctl_handle_int(oidp, &tc_idx, 0, req);
5195 if (rc != 0 || req->newptr == NULL)
5198 /* Note that -1 is legitimate input (it means unbind). */
5199 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls)
5202 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc");
5206 if (tc_idx == txq->tc_idx) {
5207 rc = 0; /* No change, nothing to do. */
5211 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
5212 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) |
5213 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id);
5216 fw_class = 0xffffffff; /* Unbind. */
5219 * Bind to a different class. Ethernet txq's are only allowed
5220 * to bind to cl-rl mode-class for now. XXX: too restrictive.
5222 tc = &pi->tc[tc_idx];
5223 if (tc->flags & TX_SC_OK &&
5224 tc->params.level == SCHED_CLASS_LEVEL_CL_RL &&
5225 tc->params.mode == SCHED_CLASS_MODE_CLASS) {
5226 /* Ok to proceed. */
5229 rc = tc->flags & TX_SC_OK ? EBUSY : ENXIO;
5234 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class);
5236 if (txq->tc_idx != -1) {
5237 tc = &pi->tc[txq->tc_idx];
5238 MPASS(tc->refcount > 0);
5242 tc = &pi->tc[tc_idx];
5245 txq->tc_idx = tc_idx;
5248 end_synchronized_op(sc, 0);