2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
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5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
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9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
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15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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29 #include <machine/atomic.h>
32 mlx5e_send_nop(struct mlx5e_sq *sq, u32 ds_cnt, bool notify_hw)
34 u16 pi = sq->pc & sq->wq.sz_m1;
35 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
37 memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));
39 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
40 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
41 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
43 sq->mbuf[pi].mbuf = NULL;
44 sq->mbuf[pi].num_bytes = 0;
45 sq->mbuf[pi].num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
46 sq->pc += sq->mbuf[pi].num_wqebbs;
48 mlx5e_tx_notify_hw(sq, wqe, 0);
51 #if (__FreeBSD_version >= 1100000)
52 static uint32_t mlx5e_hash_value;
55 mlx5e_hash_init(void *arg)
57 mlx5e_hash_value = m_ether_tcpip_hash_init();
60 /* Make kernel call mlx5e_hash_init after the random stack finished initializing */
61 SYSINIT(mlx5e_hash_init, SI_SUB_RANDOM, SI_ORDER_ANY, &mlx5e_hash_init, NULL);
64 static struct mlx5e_sq *
65 mlx5e_select_queue(struct ifnet *ifp, struct mbuf *mb)
67 struct mlx5e_priv *priv = ifp->if_softc;
71 /* check if channels are successfully opened */
72 if (unlikely(priv->channel == NULL))
75 /* obtain VLAN information if present */
76 if (mb->m_flags & M_VLANTAG) {
77 tc = (mb->m_pkthdr.ether_vtag >> 13);
78 if (tc >= priv->num_tc)
79 tc = priv->default_vlan_prio;
81 tc = priv->default_vlan_prio;
84 ch = priv->params.num_channels;
86 /* check if flowid is set */
87 if (M_HASHTYPE_GET(mb) != M_HASHTYPE_NONE) {
88 ch = (mb->m_pkthdr.flowid % 128) % ch;
90 #if (__FreeBSD_version >= 1100000)
91 ch = m_ether_tcpip_hash(MBUF_HASHFLAG_L3 |
92 MBUF_HASHFLAG_L4, mb, mlx5e_hash_value) % ch;
95 * m_ether_tcpip_hash not present in stable, so just
96 * throw unhashed mbufs on queue 0
102 /* check if channel is allocated */
103 if (unlikely(priv->channel[ch] == NULL))
106 return (&priv->channel[ch]->sq[tc]);
110 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq, struct mbuf *mb)
112 return (MIN(MLX5E_MAX_TX_INLINE, mb->m_len));
116 mlx5e_get_header_size(struct mbuf *mb)
118 struct ether_vlan_header *eh;
121 int ip_hlen, tcp_hlen;
126 eh = mtod(mb, struct ether_vlan_header *);
127 if (mb->m_len < ETHER_HDR_LEN)
129 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
130 eth_type = ntohs(eh->evl_proto);
131 eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
133 eth_type = ntohs(eh->evl_encap_proto);
134 eth_hdr_len = ETHER_HDR_LEN;
136 if (mb->m_len < eth_hdr_len)
140 ip = (struct ip *)(mb->m_data + eth_hdr_len);
141 if (mb->m_len < eth_hdr_len + sizeof(*ip))
143 if (ip->ip_p != IPPROTO_TCP)
145 ip_hlen = ip->ip_hl << 2;
146 eth_hdr_len += ip_hlen;
149 ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len);
150 if (mb->m_len < eth_hdr_len + sizeof(*ip6))
152 if (ip6->ip6_nxt != IPPROTO_TCP)
154 eth_hdr_len += sizeof(*ip6);
159 if (mb->m_len < eth_hdr_len + sizeof(*th))
161 th = (struct tcphdr *)(mb->m_data + eth_hdr_len);
162 tcp_hlen = th->th_off << 2;
163 eth_hdr_len += tcp_hlen;
164 if (mb->m_len < eth_hdr_len)
166 return (eth_hdr_len);
170 * The return value is not going back to the stack because of
174 mlx5e_sq_xmit(struct mlx5e_sq *sq, struct mbuf **mbp)
176 bus_dma_segment_t segs[MLX5E_MAX_TX_MBUF_FRAGS];
177 struct mlx5_wqe_data_seg *dseg;
178 struct mlx5e_tx_wqe *wqe;
183 struct mbuf *mb = *mbp;
190 * Return ENOBUFS if the queue is full, this may trigger reinsertion
191 * of the mbuf into the drbr (see mlx5e_xmit_locked)
193 if (unlikely(!mlx5e_sq_has_room_for(sq, 2 * MLX5_SEND_WQE_MAX_WQEBBS))) {
197 /* Align SQ edge with NOPs to avoid WQE wrap around */
198 pi = ((~sq->pc) & sq->wq.sz_m1);
199 if (pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1)) {
200 /* Send one multi NOP message instead of many */
201 mlx5e_send_nop(sq, (pi + 1) * MLX5_SEND_WQEBB_NUM_DS, false);
202 pi = ((~sq->pc) & sq->wq.sz_m1);
203 if (pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1)) {
209 /* Setup local variables */
210 pi = sq->pc & sq->wq.sz_m1;
211 wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
212 ifp = sq->channel->ifp;
214 memset(wqe, 0, sizeof(*wqe));
216 /* Send a copy of the frame to the BPF listener, if any */
217 if (ifp != NULL && ifp->if_bpf != NULL)
218 ETHER_BPF_MTAP(ifp, mb);
220 if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) {
221 wqe->eth.cs_flags |= MLX5_ETH_WQE_L3_CSUM;
223 if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) {
224 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_CSUM;
226 if (wqe->eth.cs_flags == 0) {
227 sq->stats.csum_offload_none++;
229 if (mb->m_pkthdr.csum_flags & CSUM_TSO) {
231 u32 mss = mb->m_pkthdr.tso_segsz;
234 wqe->eth.mss = cpu_to_be16(mss);
235 opcode = MLX5_OPCODE_LSO;
236 ihs = mlx5e_get_header_size(mb);
237 payload_len = mb->m_pkthdr.len - ihs;
238 if (payload_len == 0)
241 num_pkts = DIV_ROUND_UP(payload_len, mss);
242 sq->mbuf[pi].num_bytes = payload_len + (num_pkts * ihs);
244 sq->stats.tso_packets++;
245 sq->stats.tso_bytes += payload_len;
247 opcode = MLX5_OPCODE_SEND;
248 ihs = mlx5e_get_inline_hdr_size(sq, mb);
249 sq->mbuf[pi].num_bytes = max_t (unsigned int,
250 mb->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
252 if (mb->m_flags & M_VLANTAG) {
253 struct ether_vlan_header *eh =
254 (struct ether_vlan_header *)wqe->eth.inline_hdr_start;
257 if (ihs > (MLX5E_MAX_TX_INLINE - ETHER_VLAN_ENCAP_LEN))
258 ihs = (MLX5E_MAX_TX_INLINE - ETHER_VLAN_ENCAP_LEN);
259 else if (ihs < ETHER_HDR_LEN) {
263 m_copydata(mb, 0, ETHER_HDR_LEN, (caddr_t)eh);
264 m_adj(mb, ETHER_HDR_LEN);
265 /* Insert 4 bytes VLAN tag into data stream */
266 eh->evl_proto = eh->evl_encap_proto;
267 eh->evl_encap_proto = htons(ETHERTYPE_VLAN);
268 eh->evl_tag = htons(mb->m_pkthdr.ether_vtag);
269 /* Copy rest of header data, if any */
270 m_copydata(mb, 0, ihs - ETHER_HDR_LEN, (caddr_t)(eh + 1));
271 m_adj(mb, ihs - ETHER_HDR_LEN);
272 /* Extend header by 4 bytes */
273 ihs += ETHER_VLAN_ENCAP_LEN;
275 m_copydata(mb, 0, ihs, wqe->eth.inline_hdr_start);
279 wqe->eth.inline_hdr_sz = cpu_to_be16(ihs);
281 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
282 if (likely(ihs > sizeof(wqe->eth.inline_hdr_start))) {
283 ds_cnt += DIV_ROUND_UP(ihs - sizeof(wqe->eth.inline_hdr_start),
286 dseg = ((struct mlx5_wqe_data_seg *)&wqe->ctrl) + ds_cnt;
288 /* Trim off empty mbufs */
289 while (mb->m_len == 0) {
291 /* Check if all data has been inlined */
296 err = bus_dmamap_load_mbuf_sg(sq->dma_tag, sq->mbuf[pi].dma_map,
297 mb, segs, &nsegs, BUS_DMA_NOWAIT);
300 * Update *mbp before defrag in case it was trimmed in the
304 /* Update statistics */
305 sq->stats.defragged++;
306 /* Too many mbuf fragments */
307 mb = m_defrag(*mbp, M_NOWAIT);
313 err = bus_dmamap_load_mbuf_sg(sq->dma_tag, sq->mbuf[pi].dma_map,
314 mb, segs, &nsegs, BUS_DMA_NOWAIT);
322 for (x = 0; x != nsegs; x++) {
323 if (segs[x].ds_len == 0)
325 dseg->addr = cpu_to_be64((uint64_t)segs[x].ds_addr);
326 dseg->lkey = sq->mkey_be;
327 dseg->byte_count = cpu_to_be32((uint32_t)segs[x].ds_len);
331 ds_cnt = (dseg - ((struct mlx5_wqe_data_seg *)&wqe->ctrl));
333 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
334 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
335 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
337 /* Store pointer to mbuf */
338 sq->mbuf[pi].mbuf = mb;
339 sq->mbuf[pi].num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
340 sq->pc += sq->mbuf[pi].num_wqebbs;
342 /* Make sure all mbuf data is written to RAM */
344 bus_dmamap_sync(sq->dma_tag, sq->mbuf[pi].dma_map, BUS_DMASYNC_PREWRITE);
346 mlx5e_tx_notify_hw(sq, wqe, 0);
359 mlx5e_poll_tx_cq(struct mlx5e_sq *sq, int budget)
364 * sq->cc must be updated only after mlx5_cqwq_update_db_record(),
365 * otherwise a cq overrun may occur
370 struct mlx5_cqe64 *cqe;
374 cqe = mlx5e_get_cqe(&sq->cq);
378 ci = sqcc & sq->wq.sz_m1;
379 mb = sq->mbuf[ci].mbuf;
380 sq->mbuf[ci].mbuf = NULL; /* Safety clear */
383 if (sq->mbuf[ci].num_bytes == 0) {
388 bus_dmamap_sync(sq->dma_tag, sq->mbuf[ci].dma_map,
389 BUS_DMASYNC_POSTWRITE);
390 bus_dmamap_unload(sq->dma_tag, sq->mbuf[ci].dma_map);
392 /* Free transmitted mbuf */
395 sqcc += sq->mbuf[ci].num_wqebbs;
398 mlx5_cqwq_update_db_record(&sq->cq.wq);
400 /* Ensure cq space is freed before enabling more cqes */
405 if (atomic_cmpset_int(&sq->queue_state, MLX5E_SQ_FULL, MLX5E_SQ_READY))
406 taskqueue_enqueue(sq->sq_tq, &sq->sq_task);
410 mlx5e_xmit_locked(struct ifnet *ifp, struct mlx5e_sq *sq, struct mbuf *mb)
415 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
417 err = drbr_enqueue(ifp, sq->br, mb);
423 * If we can't insert mbuf into drbr, try to xmit anyway.
424 * We keep the error we got so we could return that after xmit.
426 err = drbr_enqueue(ifp, sq->br, mb);
428 /* Process the queue */
429 while ((next = drbr_peek(ifp, sq->br)) != NULL) {
430 if (mlx5e_sq_xmit(sq, &next) != 0) {
432 drbr_advance(ifp, sq->br);
434 drbr_putback(ifp, sq->br, next);
435 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_FULL);
439 drbr_advance(ifp, sq->br);
440 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
447 mlx5e_xmit(struct ifnet *ifp, struct mbuf *mb)
452 sq = mlx5e_select_queue(ifp, mb);
453 if (unlikely(sq == NULL)) {
454 /* Invalid send queue */
458 if (mtx_trylock(&sq->lock)) {
459 ret = mlx5e_xmit_locked(ifp, sq, mb);
460 mtx_unlock(&sq->lock);
462 ret = drbr_enqueue(ifp, sq->br, mb);
463 taskqueue_enqueue(sq->sq_tq, &sq->sq_task);
470 mlx5e_tx_cq_comp(struct mlx5_core_cq *mcq)
472 struct mlx5e_sq *sq = container_of(mcq, struct mlx5e_sq, cq.mcq);
474 mtx_lock(&sq->comp_lock);
475 mlx5e_poll_tx_cq(sq, MLX5E_BUDGET_MAX);
476 mlx5e_cq_arm(&sq->cq);
477 mtx_unlock(&sq->comp_lock);
481 mlx5e_tx_que(void *context, int pending)
483 struct mlx5e_sq *sq = context;
484 struct ifnet *ifp = sq->channel->ifp;
486 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
488 if (!drbr_empty(ifp, sq->br))
489 mlx5e_xmit_locked(ifp, sq, NULL);
490 mtx_unlock(&sq->lock);