2 * Copyright (c) 2013-2016 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
30 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
31 * Content: Contains Hardware dependant functions
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
40 #include "ql_inline.h"
44 #include "ql_minidump.h"
50 static void qla_del_rcv_cntxt(qla_host_t *ha);
51 static int qla_init_rcv_cntxt(qla_host_t *ha);
52 static void qla_del_xmt_cntxt(qla_host_t *ha);
53 static int qla_init_xmt_cntxt(qla_host_t *ha);
54 static int qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox,
55 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause);
56 static int qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx,
57 uint32_t num_intrs, uint32_t create);
58 static int qla_config_rss(qla_host_t *ha, uint16_t cntxt_id);
59 static int qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id,
60 int tenable, int rcv);
61 static int qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode);
62 static int qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id);
64 static int qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd,
66 static int qla_hw_add_all_mcast(qla_host_t *ha);
67 static int qla_hw_del_all_mcast(qla_host_t *ha);
68 static int qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds);
70 static int qla_init_nic_func(qla_host_t *ha);
71 static int qla_stop_nic_func(qla_host_t *ha);
72 static int qla_query_fw_dcbx_caps(qla_host_t *ha);
73 static int qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits);
74 static int qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits);
75 static void qla_get_quick_stats(qla_host_t *ha);
76 static int qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode);
77 static int qla_get_cam_search_mode(qla_host_t *ha);
79 static void ql_minidump_free(qla_host_t *ha);
83 qla_sysctl_get_drvr_stats(SYSCTL_HANDLER_ARGS)
89 err = sysctl_handle_int(oidp, &ret, 0, req);
91 if (err || !req->newptr)
96 ha = (qla_host_t *)arg1;
98 for (i = 0; i < ha->hw.num_sds_rings; i++) {
100 device_printf(ha->pci_dev,
101 "%s: sds_ring[%d] = %p\n", __func__,i,
102 (void *)ha->hw.sds[i].intr_count);
104 device_printf(ha->pci_dev,
105 "%s: sds_ring[%d].spurious_intr_count = %p\n",
107 i, (void *)ha->hw.sds[i].spurious_intr_count);
109 device_printf(ha->pci_dev,
110 "%s: sds_ring[%d].rx_free = %d\n", __func__,i,
111 ha->hw.sds[i].rx_free);
114 for (i = 0; i < ha->hw.num_tx_rings; i++)
115 device_printf(ha->pci_dev,
116 "%s: tx[%d] = %p\n", __func__,i,
117 (void *)ha->tx_ring[i].count);
119 for (i = 0; i < ha->hw.num_rds_rings; i++)
120 device_printf(ha->pci_dev,
121 "%s: rds_ring[%d] = %p\n", __func__,i,
122 (void *)ha->hw.rds[i].count);
124 device_printf(ha->pci_dev, "%s: lro_pkt_count = %p\n", __func__,
125 (void *)ha->lro_pkt_count);
127 device_printf(ha->pci_dev, "%s: lro_bytes = %p\n", __func__,
128 (void *)ha->lro_bytes);
130 #ifdef QL_ENABLE_ISCSI_TLV
131 device_printf(ha->pci_dev, "%s: iscsi_pkts = %p\n", __func__,
132 (void *)ha->hw.iscsi_pkt_count);
133 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
140 qla_sysctl_get_quick_stats(SYSCTL_HANDLER_ARGS)
145 err = sysctl_handle_int(oidp, &ret, 0, req);
147 if (err || !req->newptr)
151 ha = (qla_host_t *)arg1;
152 qla_get_quick_stats(ha);
160 qla_stop_pegs(qla_host_t *ha)
164 ql_rdwr_indreg32(ha, Q8_CRB_PEG_0, &val, 0);
165 ql_rdwr_indreg32(ha, Q8_CRB_PEG_1, &val, 0);
166 ql_rdwr_indreg32(ha, Q8_CRB_PEG_2, &val, 0);
167 ql_rdwr_indreg32(ha, Q8_CRB_PEG_3, &val, 0);
168 ql_rdwr_indreg32(ha, Q8_CRB_PEG_4, &val, 0);
169 device_printf(ha->pci_dev, "%s PEGS HALTED!!!!!\n", __func__);
173 qla_sysctl_stop_pegs(SYSCTL_HANDLER_ARGS)
178 err = sysctl_handle_int(oidp, &ret, 0, req);
181 if (err || !req->newptr)
185 ha = (qla_host_t *)arg1;
186 (void)QLA_LOCK(ha, __func__, 0);
188 QLA_UNLOCK(ha, __func__);
193 #endif /* #ifdef QL_DBG */
196 qla_validate_set_port_cfg_bit(uint32_t bits)
198 if ((bits & 0xF) > 1)
201 if (((bits >> 4) & 0xF) > 2)
204 if (((bits >> 8) & 0xF) > 2)
211 qla_sysctl_port_cfg(SYSCTL_HANDLER_ARGS)
217 err = sysctl_handle_int(oidp, &ret, 0, req);
219 if (err || !req->newptr)
222 if ((qla_validate_set_port_cfg_bit((uint32_t)ret) == 0)) {
224 ha = (qla_host_t *)arg1;
226 err = qla_get_port_config(ha, &cfg_bits);
229 goto qla_sysctl_set_port_cfg_exit;
232 cfg_bits |= Q8_PORT_CFG_BITS_DCBX_ENABLE;
234 cfg_bits &= ~Q8_PORT_CFG_BITS_DCBX_ENABLE;
238 cfg_bits &= ~Q8_PORT_CFG_BITS_PAUSE_CFG_MASK;
240 if ((ret & 0xF) == 0) {
241 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_DISABLED;
242 } else if ((ret & 0xF) == 1){
243 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_STD;
245 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_PPM;
249 cfg_bits &= ~Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK;
252 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV;
253 } else if (ret == 1){
254 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT;
256 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_RCV;
259 err = qla_set_port_config(ha, cfg_bits);
261 ha = (qla_host_t *)arg1;
263 err = qla_get_port_config(ha, &cfg_bits);
266 qla_sysctl_set_port_cfg_exit:
271 qla_sysctl_set_cam_search_mode(SYSCTL_HANDLER_ARGS)
276 err = sysctl_handle_int(oidp, &ret, 0, req);
278 if (err || !req->newptr)
281 ha = (qla_host_t *)arg1;
283 if ((ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL) ||
284 (ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO)) {
285 err = qla_set_cam_search_mode(ha, (uint32_t)ret);
287 device_printf(ha->pci_dev, "%s: ret = %d\n", __func__, ret);
294 qla_sysctl_get_cam_search_mode(SYSCTL_HANDLER_ARGS)
299 err = sysctl_handle_int(oidp, &ret, 0, req);
301 if (err || !req->newptr)
304 ha = (qla_host_t *)arg1;
305 err = qla_get_cam_search_mode(ha);
312 * Name: ql_hw_add_sysctls
313 * Function: Add P3Plus specific sysctls
316 ql_hw_add_sysctls(qla_host_t *ha)
322 ha->hw.num_sds_rings = MAX_SDS_RINGS;
323 ha->hw.num_rds_rings = MAX_RDS_RINGS;
324 ha->hw.num_tx_rings = NUM_TX_RINGS;
326 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
327 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
328 OID_AUTO, "num_rds_rings", CTLFLAG_RD, &ha->hw.num_rds_rings,
329 ha->hw.num_rds_rings, "Number of Rcv Descriptor Rings");
331 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
332 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
333 OID_AUTO, "num_sds_rings", CTLFLAG_RD, &ha->hw.num_sds_rings,
334 ha->hw.num_sds_rings, "Number of Status Descriptor Rings");
336 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
337 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
338 OID_AUTO, "num_tx_rings", CTLFLAG_RD, &ha->hw.num_tx_rings,
339 ha->hw.num_tx_rings, "Number of Transmit Rings");
341 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
342 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
343 OID_AUTO, "tx_ring_index", CTLFLAG_RW, &ha->txr_idx,
344 ha->txr_idx, "Tx Ring Used");
346 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
347 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
348 OID_AUTO, "drvr_stats", CTLTYPE_INT | CTLFLAG_RW,
350 qla_sysctl_get_drvr_stats, "I", "Driver Maintained Statistics");
352 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
353 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
354 OID_AUTO, "quick_stats", CTLTYPE_INT | CTLFLAG_RW,
356 qla_sysctl_get_quick_stats, "I", "Quick Statistics");
358 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
359 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
360 OID_AUTO, "max_tx_segs", CTLFLAG_RD, &ha->hw.max_tx_segs,
361 ha->hw.max_tx_segs, "Max # of Segments in a non-TSO pkt");
363 ha->hw.sds_cidx_thres = 32;
364 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
365 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
366 OID_AUTO, "sds_cidx_thres", CTLFLAG_RW, &ha->hw.sds_cidx_thres,
367 ha->hw.sds_cidx_thres,
368 "Number of SDS entries to process before updating"
369 " SDS Ring Consumer Index");
371 ha->hw.rds_pidx_thres = 32;
372 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
373 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
374 OID_AUTO, "rds_pidx_thres", CTLFLAG_RW, &ha->hw.rds_pidx_thres,
375 ha->hw.rds_pidx_thres,
376 "Number of Rcv Rings Entries to post before updating"
377 " RDS Ring Producer Index");
379 ha->hw.rcv_intr_coalesce = (3 << 16) | 256;
380 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
381 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
382 OID_AUTO, "rcv_intr_coalesce", CTLFLAG_RW,
383 &ha->hw.rcv_intr_coalesce,
384 ha->hw.rcv_intr_coalesce,
385 "Rcv Intr Coalescing Parameters\n"
386 "\tbits 15:0 max packets\n"
387 "\tbits 31:16 max micro-seconds to wait\n"
389 "\tifconfig <if> down && ifconfig <if> up\n"
390 "\tto take effect \n");
392 ha->hw.xmt_intr_coalesce = (64 << 16) | 64;
393 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
394 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
395 OID_AUTO, "xmt_intr_coalesce", CTLFLAG_RW,
396 &ha->hw.xmt_intr_coalesce,
397 ha->hw.xmt_intr_coalesce,
398 "Xmt Intr Coalescing Parameters\n"
399 "\tbits 15:0 max packets\n"
400 "\tbits 31:16 max micro-seconds to wait\n"
402 "\tifconfig <if> down && ifconfig <if> up\n"
403 "\tto take effect \n");
405 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
406 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
407 OID_AUTO, "port_cfg", CTLTYPE_INT | CTLFLAG_RW,
409 qla_sysctl_port_cfg, "I",
410 "Set Port Configuration if values below "
411 "otherwise Get Port Configuration\n"
412 "\tBits 0-3 ; 1 = DCBX Enable; 0 = DCBX Disable\n"
413 "\tBits 4-7 : 0 = no pause; 1 = std ; 2 = ppm \n"
414 "\tBits 8-11: std pause cfg; 0 = xmt and rcv;"
415 " 1 = xmt only; 2 = rcv only;\n"
418 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
419 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
420 OID_AUTO, "set_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW,
422 qla_sysctl_set_cam_search_mode, "I",
423 "Set CAM Search Mode"
424 "\t 1 = search mode internal\n"
425 "\t 2 = search mode auto\n");
427 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
428 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
429 OID_AUTO, "get_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW,
431 qla_sysctl_get_cam_search_mode, "I",
432 "Get CAM Search Mode"
433 "\t 1 = search mode internal\n"
434 "\t 2 = search mode auto\n");
436 ha->hw.enable_9kb = 1;
438 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
439 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
440 OID_AUTO, "enable_9kb", CTLFLAG_RW, &ha->hw.enable_9kb,
441 ha->hw.enable_9kb, "Enable 9Kbyte Buffers when MTU = 9000");
443 ha->hw.mdump_active = 0;
444 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
445 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
446 OID_AUTO, "minidump_active", CTLFLAG_RW, &ha->hw.mdump_active,
448 "Minidump retrieval is Active");
450 ha->hw.mdump_done = 0;
451 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
452 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
453 OID_AUTO, "mdump_done", CTLFLAG_RW,
454 &ha->hw.mdump_done, ha->hw.mdump_done,
455 "Minidump has been done and available for retrieval");
457 ha->hw.mdump_capture_mask = 0xF;
458 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
459 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
460 OID_AUTO, "minidump_capture_mask", CTLFLAG_RW,
461 &ha->hw.mdump_capture_mask, ha->hw.mdump_capture_mask,
462 "Minidump capture mask");
466 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
467 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
468 OID_AUTO, "err_inject",
469 CTLFLAG_RW, &ha->err_inject, ha->err_inject,
470 "Error to be injected\n"
471 "\t\t\t 0: No Errors\n"
472 "\t\t\t 1: rcv: rxb struct invalid\n"
473 "\t\t\t 2: rcv: mp == NULL\n"
474 "\t\t\t 3: lro: rxb struct invalid\n"
475 "\t\t\t 4: lro: mp == NULL\n"
476 "\t\t\t 5: rcv: num handles invalid\n"
477 "\t\t\t 6: reg: indirect reg rd_wr failure\n"
478 "\t\t\t 7: ocm: offchip memory rd_wr failure\n"
479 "\t\t\t 8: mbx: mailbox command failure\n"
480 "\t\t\t 9: heartbeat failure\n"
481 "\t\t\t A: temperature failure\n"
482 "\t\t\t 11: m_getcl or m_getjcl failure\n" );
484 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
485 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
486 OID_AUTO, "peg_stop", CTLTYPE_INT | CTLFLAG_RW,
488 qla_sysctl_stop_pegs, "I", "Peg Stop");
490 #endif /* #ifdef QL_DBG */
492 ha->hw.user_pri_nic = 0;
493 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
494 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
495 OID_AUTO, "user_pri_nic", CTLFLAG_RW, &ha->hw.user_pri_nic,
497 "VLAN Tag User Priority for Normal Ethernet Packets");
499 ha->hw.user_pri_iscsi = 4;
500 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
501 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
502 OID_AUTO, "user_pri_iscsi", CTLFLAG_RW, &ha->hw.user_pri_iscsi,
503 ha->hw.user_pri_iscsi,
504 "VLAN Tag User Priority for iSCSI Packets");
509 ql_hw_link_status(qla_host_t *ha)
511 device_printf(ha->pci_dev, "cable_oui\t\t 0x%08x\n", ha->hw.cable_oui);
513 if (ha->hw.link_up) {
514 device_printf(ha->pci_dev, "link Up\n");
516 device_printf(ha->pci_dev, "link Down\n");
519 if (ha->hw.flags.fduplex) {
520 device_printf(ha->pci_dev, "Full Duplex\n");
522 device_printf(ha->pci_dev, "Half Duplex\n");
525 if (ha->hw.flags.autoneg) {
526 device_printf(ha->pci_dev, "Auto Negotiation Enabled\n");
528 device_printf(ha->pci_dev, "Auto Negotiation Disabled\n");
531 switch (ha->hw.link_speed) {
533 device_printf(ha->pci_dev, "link speed\t\t 10Gps\n");
537 device_printf(ha->pci_dev, "link speed\t\t 1Gps\n");
541 device_printf(ha->pci_dev, "link speed\t\t 100Mbps\n");
545 device_printf(ha->pci_dev, "link speed\t\t Unknown\n");
549 switch (ha->hw.module_type) {
552 device_printf(ha->pci_dev, "Module Type 10GBase-LRM\n");
556 device_printf(ha->pci_dev, "Module Type 10GBase-LR\n");
560 device_printf(ha->pci_dev, "Module Type 10GBase-SR\n");
564 device_printf(ha->pci_dev,
565 "Module Type 10GE Passive Copper(Compliant)[%d m]\n",
566 ha->hw.cable_length);
570 device_printf(ha->pci_dev, "Module Type 10GE Active"
571 " Limiting Copper(Compliant)[%d m]\n",
572 ha->hw.cable_length);
576 device_printf(ha->pci_dev,
577 "Module Type 10GE Passive Copper"
578 " (Legacy, Best Effort)[%d m]\n",
579 ha->hw.cable_length);
583 device_printf(ha->pci_dev, "Module Type 1000Base-SX\n");
587 device_printf(ha->pci_dev, "Module Type 1000Base-LX\n");
591 device_printf(ha->pci_dev, "Module Type 1000Base-CX\n");
595 device_printf(ha->pci_dev, "Module Type 1000Base-T\n");
599 device_printf(ha->pci_dev, "Module Type 1GE Passive Copper"
600 "(Legacy, Best Effort)\n");
604 device_printf(ha->pci_dev, "Unknown Module Type 0x%x\n",
609 if (ha->hw.link_faults == 1)
610 device_printf(ha->pci_dev, "SFP Power Fault\n");
615 * Function: Frees the DMA'able memory allocated in ql_alloc_dma()
618 ql_free_dma(qla_host_t *ha)
622 if (ha->hw.dma_buf.flags.sds_ring) {
623 for (i = 0; i < ha->hw.num_sds_rings; i++) {
624 ql_free_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i]);
626 ha->hw.dma_buf.flags.sds_ring = 0;
629 if (ha->hw.dma_buf.flags.rds_ring) {
630 for (i = 0; i < ha->hw.num_rds_rings; i++) {
631 ql_free_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i]);
633 ha->hw.dma_buf.flags.rds_ring = 0;
636 if (ha->hw.dma_buf.flags.tx_ring) {
637 ql_free_dmabuf(ha, &ha->hw.dma_buf.tx_ring);
638 ha->hw.dma_buf.flags.tx_ring = 0;
640 ql_minidump_free(ha);
645 * Function: Allocates DMA'able memory for Tx/Rx Rings, Tx/Rx Contexts.
648 ql_alloc_dma(qla_host_t *ha)
651 uint32_t i, j, size, tx_ring_size;
653 qla_hw_tx_cntxt_t *tx_cntxt;
659 QL_DPRINT2(ha, (dev, "%s: enter\n", __func__));
663 * Allocate Transmit Ring
665 tx_ring_size = (sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS);
666 size = (tx_ring_size * ha->hw.num_tx_rings);
668 hw->dma_buf.tx_ring.alignment = 8;
669 hw->dma_buf.tx_ring.size = size + PAGE_SIZE;
671 if (ql_alloc_dmabuf(ha, &hw->dma_buf.tx_ring)) {
672 device_printf(dev, "%s: tx ring alloc failed\n", __func__);
673 goto ql_alloc_dma_exit;
676 vaddr = (uint8_t *)hw->dma_buf.tx_ring.dma_b;
677 paddr = hw->dma_buf.tx_ring.dma_addr;
679 for (i = 0; i < ha->hw.num_tx_rings; i++) {
680 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
682 tx_cntxt->tx_ring_base = (q80_tx_cmd_t *)vaddr;
683 tx_cntxt->tx_ring_paddr = paddr;
685 vaddr += tx_ring_size;
686 paddr += tx_ring_size;
689 for (i = 0; i < ha->hw.num_tx_rings; i++) {
690 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
692 tx_cntxt->tx_cons = (uint32_t *)vaddr;
693 tx_cntxt->tx_cons_paddr = paddr;
695 vaddr += sizeof (uint32_t);
696 paddr += sizeof (uint32_t);
699 ha->hw.dma_buf.flags.tx_ring = 1;
701 QL_DPRINT2(ha, (dev, "%s: tx_ring phys %p virt %p\n",
702 __func__, (void *)(hw->dma_buf.tx_ring.dma_addr),
703 hw->dma_buf.tx_ring.dma_b));
705 * Allocate Receive Descriptor Rings
708 for (i = 0; i < hw->num_rds_rings; i++) {
710 hw->dma_buf.rds_ring[i].alignment = 8;
711 hw->dma_buf.rds_ring[i].size =
712 (sizeof(q80_recv_desc_t)) * NUM_RX_DESCRIPTORS;
714 if (ql_alloc_dmabuf(ha, &hw->dma_buf.rds_ring[i])) {
715 device_printf(dev, "%s: rds ring[%d] alloc failed\n",
718 for (j = 0; j < i; j++)
719 ql_free_dmabuf(ha, &hw->dma_buf.rds_ring[j]);
721 goto ql_alloc_dma_exit;
723 QL_DPRINT4(ha, (dev, "%s: rx_ring[%d] phys %p virt %p\n",
724 __func__, i, (void *)(hw->dma_buf.rds_ring[i].dma_addr),
725 hw->dma_buf.rds_ring[i].dma_b));
728 hw->dma_buf.flags.rds_ring = 1;
731 * Allocate Status Descriptor Rings
734 for (i = 0; i < hw->num_sds_rings; i++) {
735 hw->dma_buf.sds_ring[i].alignment = 8;
736 hw->dma_buf.sds_ring[i].size =
737 (sizeof(q80_stat_desc_t)) * NUM_STATUS_DESCRIPTORS;
739 if (ql_alloc_dmabuf(ha, &hw->dma_buf.sds_ring[i])) {
740 device_printf(dev, "%s: sds ring alloc failed\n",
743 for (j = 0; j < i; j++)
744 ql_free_dmabuf(ha, &hw->dma_buf.sds_ring[j]);
746 goto ql_alloc_dma_exit;
748 QL_DPRINT4(ha, (dev, "%s: sds_ring[%d] phys %p virt %p\n",
750 (void *)(hw->dma_buf.sds_ring[i].dma_addr),
751 hw->dma_buf.sds_ring[i].dma_b));
753 for (i = 0; i < hw->num_sds_rings; i++) {
754 hw->sds[i].sds_ring_base =
755 (q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b;
758 hw->dma_buf.flags.sds_ring = 1;
767 #define Q8_MBX_MSEC_DELAY 5000
770 qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox,
771 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause)
777 if (QL_ERR_INJECT(ha, INJCT_MBX_CMD_FAILURE)) {
779 ha->qla_initiate_recovery = 1;
780 goto exit_qla_mbx_cmd;
786 i = Q8_MBX_MSEC_DELAY;
789 data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL);
795 qla_mdelay(__func__, 1);
801 device_printf(ha->pci_dev, "%s: host_mbx_cntrl 0x%08x\n",
804 ha->qla_initiate_recovery = 1;
805 goto exit_qla_mbx_cmd;
808 for (i = 0; i < n_hmbox; i++) {
809 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox);
813 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1);
816 i = Q8_MBX_MSEC_DELAY;
818 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
820 if ((data & 0x3) == 1) {
821 data = READ_REG32(ha, Q8_FW_MBOX0);
822 if ((data & 0xF000) != 0x8000)
828 qla_mdelay(__func__, 1);
833 device_printf(ha->pci_dev, "%s: fw_mbx_cntrl 0x%08x\n",
836 ha->qla_initiate_recovery = 1;
837 goto exit_qla_mbx_cmd;
840 for (i = 0; i < n_fwmbox; i++) {
841 *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2)));
844 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
845 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
852 qla_get_nic_partition(qla_host_t *ha, uint32_t *supports_9kb,
856 device_t dev = ha->pci_dev;
858 bzero(ha->hw.mbox, (sizeof (uint32_t) * Q8_NUM_MBOX));
862 mbox[0] = Q8_MBX_GET_NIC_PARTITION | (0x2 << 16) | (0x2 << 29);
864 if (qla_mbx_cmd(ha, mbox, 2, mbox, 19, 0)) {
865 device_printf(dev, "%s: failed0\n", __func__);
870 if (supports_9kb != NULL) {
871 if (mbox[16] & 0x80) /* bit 7 of mbox 16 */
877 if (num_rcvq != NULL)
878 *num_rcvq = ((mbox[6] >> 16) & 0xFFFF);
880 if ((err != 1) && (err != 0)) {
881 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
888 qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, uint32_t num_intrs,
892 device_t dev = ha->pci_dev;
893 q80_config_intr_t *c_intr;
894 q80_config_intr_rsp_t *c_intr_rsp;
896 c_intr = (q80_config_intr_t *)ha->hw.mbox;
897 bzero(c_intr, (sizeof (q80_config_intr_t)));
899 c_intr->opcode = Q8_MBX_CONFIG_INTR;
901 c_intr->count_version = (sizeof (q80_config_intr_t) >> 2);
902 c_intr->count_version |= Q8_MBX_CMD_VERSION;
904 c_intr->nentries = num_intrs;
906 for (i = 0; i < num_intrs; i++) {
908 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_CREATE;
909 c_intr->intr[i].msix_index = start_idx + 1 + i;
911 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_DELETE;
912 c_intr->intr[i].msix_index =
913 ha->hw.intr_id[(start_idx + i)];
916 c_intr->intr[i].cmd_type |= Q8_MBX_CONFIG_INTR_TYPE_MSI_X;
919 if (qla_mbx_cmd(ha, (uint32_t *)c_intr,
920 (sizeof (q80_config_intr_t) >> 2),
921 ha->hw.mbox, (sizeof (q80_config_intr_rsp_t) >> 2), 0)) {
922 device_printf(dev, "%s: failed0\n", __func__);
926 c_intr_rsp = (q80_config_intr_rsp_t *)ha->hw.mbox;
928 err = Q8_MBX_RSP_STATUS(c_intr_rsp->regcnt_status);
931 device_printf(dev, "%s: failed1 [0x%08x, %d]\n", __func__, err,
932 c_intr_rsp->nentries);
934 for (i = 0; i < c_intr_rsp->nentries; i++) {
935 device_printf(dev, "%s: [%d]:[0x%x 0x%x 0x%x]\n",
937 c_intr_rsp->intr[i].status,
938 c_intr_rsp->intr[i].intr_id,
939 c_intr_rsp->intr[i].intr_src);
945 for (i = 0; ((i < num_intrs) && create); i++) {
946 if (!c_intr_rsp->intr[i].status) {
947 ha->hw.intr_id[(start_idx + i)] =
948 c_intr_rsp->intr[i].intr_id;
949 ha->hw.intr_src[(start_idx + i)] =
950 c_intr_rsp->intr[i].intr_src;
958 * Name: qla_config_rss
959 * Function: Configure RSS for the context/interface.
961 static const uint64_t rss_key[] = { 0xbeac01fa6a42b73bULL,
962 0x8030f20c77cb2da3ULL,
963 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
964 0x255b0ec26d5a56daULL };
967 qla_config_rss(qla_host_t *ha, uint16_t cntxt_id)
969 q80_config_rss_t *c_rss;
970 q80_config_rss_rsp_t *c_rss_rsp;
972 device_t dev = ha->pci_dev;
974 c_rss = (q80_config_rss_t *)ha->hw.mbox;
975 bzero(c_rss, (sizeof (q80_config_rss_t)));
977 c_rss->opcode = Q8_MBX_CONFIG_RSS;
979 c_rss->count_version = (sizeof (q80_config_rss_t) >> 2);
980 c_rss->count_version |= Q8_MBX_CMD_VERSION;
982 c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP |
983 Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP);
984 //c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP |
985 // Q8_MBX_RSS_HASH_TYPE_IPV6_TCP);
987 c_rss->flags = Q8_MBX_RSS_FLAGS_ENABLE_RSS;
988 c_rss->flags |= Q8_MBX_RSS_FLAGS_USE_IND_TABLE;
990 c_rss->indtbl_mask = Q8_MBX_RSS_INDTBL_MASK;
992 c_rss->indtbl_mask |= Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID;
993 c_rss->flags |= Q8_MBX_RSS_FLAGS_TYPE_CRSS;
995 c_rss->cntxt_id = cntxt_id;
997 for (i = 0; i < 5; i++) {
998 c_rss->rss_key[i] = rss_key[i];
1001 if (qla_mbx_cmd(ha, (uint32_t *)c_rss,
1002 (sizeof (q80_config_rss_t) >> 2),
1003 ha->hw.mbox, (sizeof(q80_config_rss_rsp_t) >> 2), 0)) {
1004 device_printf(dev, "%s: failed0\n", __func__);
1007 c_rss_rsp = (q80_config_rss_rsp_t *)ha->hw.mbox;
1009 err = Q8_MBX_RSP_STATUS(c_rss_rsp->regcnt_status);
1012 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1019 qla_set_rss_ind_table(qla_host_t *ha, uint32_t start_idx, uint32_t count,
1020 uint16_t cntxt_id, uint8_t *ind_table)
1022 q80_config_rss_ind_table_t *c_rss_ind;
1023 q80_config_rss_ind_table_rsp_t *c_rss_ind_rsp;
1025 device_t dev = ha->pci_dev;
1027 if ((count > Q8_RSS_IND_TBL_SIZE) ||
1028 ((start_idx + count - 1) > Q8_RSS_IND_TBL_MAX_IDX)) {
1029 device_printf(dev, "%s: illegal count [%d, %d]\n", __func__,
1034 c_rss_ind = (q80_config_rss_ind_table_t *)ha->hw.mbox;
1035 bzero(c_rss_ind, sizeof (q80_config_rss_ind_table_t));
1037 c_rss_ind->opcode = Q8_MBX_CONFIG_RSS_TABLE;
1038 c_rss_ind->count_version = (sizeof (q80_config_rss_ind_table_t) >> 2);
1039 c_rss_ind->count_version |= Q8_MBX_CMD_VERSION;
1041 c_rss_ind->start_idx = start_idx;
1042 c_rss_ind->end_idx = start_idx + count - 1;
1043 c_rss_ind->cntxt_id = cntxt_id;
1044 bcopy(ind_table, c_rss_ind->ind_table, count);
1046 if (qla_mbx_cmd(ha, (uint32_t *)c_rss_ind,
1047 (sizeof (q80_config_rss_ind_table_t) >> 2), ha->hw.mbox,
1048 (sizeof(q80_config_rss_ind_table_rsp_t) >> 2), 0)) {
1049 device_printf(dev, "%s: failed0\n", __func__);
1053 c_rss_ind_rsp = (q80_config_rss_ind_table_rsp_t *)ha->hw.mbox;
1054 err = Q8_MBX_RSP_STATUS(c_rss_ind_rsp->regcnt_status);
1057 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1064 * Name: qla_config_intr_coalesce
1065 * Function: Configure Interrupt Coalescing.
1068 qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable,
1071 q80_config_intr_coalesc_t *intrc;
1072 q80_config_intr_coalesc_rsp_t *intrc_rsp;
1074 device_t dev = ha->pci_dev;
1076 intrc = (q80_config_intr_coalesc_t *)ha->hw.mbox;
1077 bzero(intrc, (sizeof (q80_config_intr_coalesc_t)));
1079 intrc->opcode = Q8_MBX_CONFIG_INTR_COALESCE;
1080 intrc->count_version = (sizeof (q80_config_intr_coalesc_t) >> 2);
1081 intrc->count_version |= Q8_MBX_CMD_VERSION;
1084 intrc->flags = Q8_MBX_INTRC_FLAGS_RCV;
1085 intrc->max_pkts = ha->hw.rcv_intr_coalesce & 0xFFFF;
1086 intrc->max_mswait = (ha->hw.rcv_intr_coalesce >> 16) & 0xFFFF;
1088 intrc->flags = Q8_MBX_INTRC_FLAGS_XMT;
1089 intrc->max_pkts = ha->hw.xmt_intr_coalesce & 0xFFFF;
1090 intrc->max_mswait = (ha->hw.xmt_intr_coalesce >> 16) & 0xFFFF;
1093 intrc->cntxt_id = cntxt_id;
1096 intrc->flags |= Q8_MBX_INTRC_FLAGS_PERIODIC;
1097 intrc->timer_type = Q8_MBX_INTRC_TIMER_PERIODIC;
1099 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1100 intrc->sds_ring_mask |= (1 << i);
1102 intrc->ms_timeout = 1000;
1105 if (qla_mbx_cmd(ha, (uint32_t *)intrc,
1106 (sizeof (q80_config_intr_coalesc_t) >> 2),
1107 ha->hw.mbox, (sizeof(q80_config_intr_coalesc_rsp_t) >> 2), 0)) {
1108 device_printf(dev, "%s: failed0\n", __func__);
1111 intrc_rsp = (q80_config_intr_coalesc_rsp_t *)ha->hw.mbox;
1113 err = Q8_MBX_RSP_STATUS(intrc_rsp->regcnt_status);
1116 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1125 * Name: qla_config_mac_addr
1126 * Function: binds a MAC address to the context/interface.
1127 * Can be unicast, multicast or broadcast.
1130 qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint32_t add_mac,
1133 q80_config_mac_addr_t *cmac;
1134 q80_config_mac_addr_rsp_t *cmac_rsp;
1136 device_t dev = ha->pci_dev;
1138 uint8_t *mac_cpy = mac_addr;
1140 if (num_mac > Q8_MAX_MAC_ADDRS) {
1141 device_printf(dev, "%s: %s num_mac [0x%x] > Q8_MAX_MAC_ADDRS\n",
1142 __func__, (add_mac ? "Add" : "Del"), num_mac);
1146 cmac = (q80_config_mac_addr_t *)ha->hw.mbox;
1147 bzero(cmac, (sizeof (q80_config_mac_addr_t)));
1149 cmac->opcode = Q8_MBX_CONFIG_MAC_ADDR;
1150 cmac->count_version = sizeof (q80_config_mac_addr_t) >> 2;
1151 cmac->count_version |= Q8_MBX_CMD_VERSION;
1154 cmac->cmd = Q8_MBX_CMAC_CMD_ADD_MAC_ADDR;
1156 cmac->cmd = Q8_MBX_CMAC_CMD_DEL_MAC_ADDR;
1158 cmac->cmd |= Q8_MBX_CMAC_CMD_CAM_INGRESS;
1160 cmac->nmac_entries = num_mac;
1161 cmac->cntxt_id = ha->hw.rcv_cntxt_id;
1163 for (i = 0; i < num_mac; i++) {
1164 bcopy(mac_addr, cmac->mac_addr[i].addr, Q8_ETHER_ADDR_LEN);
1165 mac_addr = mac_addr + ETHER_ADDR_LEN;
1168 if (qla_mbx_cmd(ha, (uint32_t *)cmac,
1169 (sizeof (q80_config_mac_addr_t) >> 2),
1170 ha->hw.mbox, (sizeof(q80_config_mac_addr_rsp_t) >> 2), 1)) {
1171 device_printf(dev, "%s: %s failed0\n", __func__,
1172 (add_mac ? "Add" : "Del"));
1175 cmac_rsp = (q80_config_mac_addr_rsp_t *)ha->hw.mbox;
1177 err = Q8_MBX_RSP_STATUS(cmac_rsp->regcnt_status);
1180 device_printf(dev, "%s: %s failed1 [0x%08x]\n", __func__,
1181 (add_mac ? "Add" : "Del"), err);
1182 for (i = 0; i < num_mac; i++) {
1183 device_printf(dev, "%s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1184 __func__, mac_cpy[0], mac_cpy[1], mac_cpy[2],
1185 mac_cpy[3], mac_cpy[4], mac_cpy[5]);
1186 mac_cpy += ETHER_ADDR_LEN;
1196 * Name: qla_set_mac_rcv_mode
1197 * Function: Enable/Disable AllMulticast and Promiscous Modes.
1200 qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode)
1202 q80_config_mac_rcv_mode_t *rcv_mode;
1204 q80_config_mac_rcv_mode_rsp_t *rcv_mode_rsp;
1205 device_t dev = ha->pci_dev;
1207 rcv_mode = (q80_config_mac_rcv_mode_t *)ha->hw.mbox;
1208 bzero(rcv_mode, (sizeof (q80_config_mac_rcv_mode_t)));
1210 rcv_mode->opcode = Q8_MBX_CONFIG_MAC_RX_MODE;
1211 rcv_mode->count_version = sizeof (q80_config_mac_rcv_mode_t) >> 2;
1212 rcv_mode->count_version |= Q8_MBX_CMD_VERSION;
1214 rcv_mode->mode = mode;
1216 rcv_mode->cntxt_id = ha->hw.rcv_cntxt_id;
1218 if (qla_mbx_cmd(ha, (uint32_t *)rcv_mode,
1219 (sizeof (q80_config_mac_rcv_mode_t) >> 2),
1220 ha->hw.mbox, (sizeof(q80_config_mac_rcv_mode_rsp_t) >> 2), 1)) {
1221 device_printf(dev, "%s: failed0\n", __func__);
1224 rcv_mode_rsp = (q80_config_mac_rcv_mode_rsp_t *)ha->hw.mbox;
1226 err = Q8_MBX_RSP_STATUS(rcv_mode_rsp->regcnt_status);
1229 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1237 ql_set_promisc(qla_host_t *ha)
1241 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1242 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1247 qla_reset_promisc(qla_host_t *ha)
1249 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1250 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1254 ql_set_allmulti(qla_host_t *ha)
1258 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_ALL_MULTI_ENABLE;
1259 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1264 qla_reset_allmulti(qla_host_t *ha)
1266 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_ALL_MULTI_ENABLE;
1267 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1271 * Name: ql_set_max_mtu
1273 * Sets the maximum transfer unit size for the specified rcv context.
1276 ql_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id)
1279 q80_set_max_mtu_t *max_mtu;
1280 q80_set_max_mtu_rsp_t *max_mtu_rsp;
1285 max_mtu = (q80_set_max_mtu_t *)ha->hw.mbox;
1286 bzero(max_mtu, (sizeof (q80_set_max_mtu_t)));
1288 max_mtu->opcode = Q8_MBX_SET_MAX_MTU;
1289 max_mtu->count_version = (sizeof (q80_set_max_mtu_t) >> 2);
1290 max_mtu->count_version |= Q8_MBX_CMD_VERSION;
1292 max_mtu->cntxt_id = cntxt_id;
1295 if (qla_mbx_cmd(ha, (uint32_t *)max_mtu,
1296 (sizeof (q80_set_max_mtu_t) >> 2),
1297 ha->hw.mbox, (sizeof (q80_set_max_mtu_rsp_t) >> 2), 1)) {
1298 device_printf(dev, "%s: failed\n", __func__);
1302 max_mtu_rsp = (q80_set_max_mtu_rsp_t *)ha->hw.mbox;
1304 err = Q8_MBX_RSP_STATUS(max_mtu_rsp->regcnt_status);
1307 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1314 qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id)
1317 q80_link_event_t *lnk;
1318 q80_link_event_rsp_t *lnk_rsp;
1323 lnk = (q80_link_event_t *)ha->hw.mbox;
1324 bzero(lnk, (sizeof (q80_link_event_t)));
1326 lnk->opcode = Q8_MBX_LINK_EVENT_REQ;
1327 lnk->count_version = (sizeof (q80_link_event_t) >> 2);
1328 lnk->count_version |= Q8_MBX_CMD_VERSION;
1330 lnk->cntxt_id = cntxt_id;
1331 lnk->cmd = Q8_LINK_EVENT_CMD_ENABLE_ASYNC;
1333 if (qla_mbx_cmd(ha, (uint32_t *)lnk, (sizeof (q80_link_event_t) >> 2),
1334 ha->hw.mbox, (sizeof (q80_link_event_rsp_t) >> 2), 0)) {
1335 device_printf(dev, "%s: failed\n", __func__);
1339 lnk_rsp = (q80_link_event_rsp_t *)ha->hw.mbox;
1341 err = Q8_MBX_RSP_STATUS(lnk_rsp->regcnt_status);
1344 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1351 qla_config_fw_lro(qla_host_t *ha, uint16_t cntxt_id)
1354 q80_config_fw_lro_t *fw_lro;
1355 q80_config_fw_lro_rsp_t *fw_lro_rsp;
1360 fw_lro = (q80_config_fw_lro_t *)ha->hw.mbox;
1361 bzero(fw_lro, sizeof(q80_config_fw_lro_t));
1363 fw_lro->opcode = Q8_MBX_CONFIG_FW_LRO;
1364 fw_lro->count_version = (sizeof (q80_config_fw_lro_t) >> 2);
1365 fw_lro->count_version |= Q8_MBX_CMD_VERSION;
1367 fw_lro->flags |= Q8_MBX_FW_LRO_IPV4 | Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK;
1368 fw_lro->flags |= Q8_MBX_FW_LRO_IPV6 | Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK;
1370 fw_lro->cntxt_id = cntxt_id;
1372 if (qla_mbx_cmd(ha, (uint32_t *)fw_lro,
1373 (sizeof (q80_config_fw_lro_t) >> 2),
1374 ha->hw.mbox, (sizeof (q80_config_fw_lro_rsp_t) >> 2), 0)) {
1375 device_printf(dev, "%s: failed\n", __func__);
1379 fw_lro_rsp = (q80_config_fw_lro_rsp_t *)ha->hw.mbox;
1381 err = Q8_MBX_RSP_STATUS(fw_lro_rsp->regcnt_status);
1384 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1391 qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode)
1394 q80_hw_config_t *hw_config;
1395 q80_hw_config_rsp_t *hw_config_rsp;
1400 hw_config = (q80_hw_config_t *)ha->hw.mbox;
1401 bzero(hw_config, sizeof (q80_hw_config_t));
1403 hw_config->opcode = Q8_MBX_HW_CONFIG;
1404 hw_config->count_version = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT;
1405 hw_config->count_version |= Q8_MBX_CMD_VERSION;
1407 hw_config->cmd = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE;
1409 hw_config->u.set_cam_search_mode.mode = search_mode;
1411 if (qla_mbx_cmd(ha, (uint32_t *)hw_config,
1412 (sizeof (q80_hw_config_t) >> 2),
1413 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
1414 device_printf(dev, "%s: failed\n", __func__);
1417 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
1419 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status);
1422 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1429 qla_get_cam_search_mode(qla_host_t *ha)
1432 q80_hw_config_t *hw_config;
1433 q80_hw_config_rsp_t *hw_config_rsp;
1438 hw_config = (q80_hw_config_t *)ha->hw.mbox;
1439 bzero(hw_config, sizeof (q80_hw_config_t));
1441 hw_config->opcode = Q8_MBX_HW_CONFIG;
1442 hw_config->count_version = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT;
1443 hw_config->count_version |= Q8_MBX_CMD_VERSION;
1445 hw_config->cmd = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE;
1447 if (qla_mbx_cmd(ha, (uint32_t *)hw_config,
1448 (sizeof (q80_hw_config_t) >> 2),
1449 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
1450 device_printf(dev, "%s: failed\n", __func__);
1453 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
1455 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status);
1458 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1460 device_printf(dev, "%s: cam search mode [0x%08x]\n", __func__,
1461 hw_config_rsp->u.get_cam_search_mode.mode);
1470 qla_xmt_stats(qla_host_t *ha, q80_xmt_stats_t *xstat, int i)
1472 device_t dev = ha->pci_dev;
1474 if (i < ha->hw.num_tx_rings) {
1475 device_printf(dev, "%s[%d]: total_bytes\t\t%" PRIu64 "\n",
1476 __func__, i, xstat->total_bytes);
1477 device_printf(dev, "%s[%d]: total_pkts\t\t%" PRIu64 "\n",
1478 __func__, i, xstat->total_pkts);
1479 device_printf(dev, "%s[%d]: errors\t\t%" PRIu64 "\n",
1480 __func__, i, xstat->errors);
1481 device_printf(dev, "%s[%d]: pkts_dropped\t%" PRIu64 "\n",
1482 __func__, i, xstat->pkts_dropped);
1483 device_printf(dev, "%s[%d]: switch_pkts\t\t%" PRIu64 "\n",
1484 __func__, i, xstat->switch_pkts);
1485 device_printf(dev, "%s[%d]: num_buffers\t\t%" PRIu64 "\n",
1486 __func__, i, xstat->num_buffers);
1488 device_printf(dev, "%s: total_bytes\t\t\t%" PRIu64 "\n",
1489 __func__, xstat->total_bytes);
1490 device_printf(dev, "%s: total_pkts\t\t\t%" PRIu64 "\n",
1491 __func__, xstat->total_pkts);
1492 device_printf(dev, "%s: errors\t\t\t%" PRIu64 "\n",
1493 __func__, xstat->errors);
1494 device_printf(dev, "%s: pkts_dropped\t\t\t%" PRIu64 "\n",
1495 __func__, xstat->pkts_dropped);
1496 device_printf(dev, "%s: switch_pkts\t\t\t%" PRIu64 "\n",
1497 __func__, xstat->switch_pkts);
1498 device_printf(dev, "%s: num_buffers\t\t\t%" PRIu64 "\n",
1499 __func__, xstat->num_buffers);
1504 qla_rcv_stats(qla_host_t *ha, q80_rcv_stats_t *rstat)
1506 device_t dev = ha->pci_dev;
1508 device_printf(dev, "%s: total_bytes\t\t\t%" PRIu64 "\n", __func__,
1509 rstat->total_bytes);
1510 device_printf(dev, "%s: total_pkts\t\t\t%" PRIu64 "\n", __func__,
1512 device_printf(dev, "%s: lro_pkt_count\t\t%" PRIu64 "\n", __func__,
1513 rstat->lro_pkt_count);
1514 device_printf(dev, "%s: sw_pkt_count\t\t\t%" PRIu64 "\n", __func__,
1515 rstat->sw_pkt_count);
1516 device_printf(dev, "%s: ip_chksum_err\t\t%" PRIu64 "\n", __func__,
1517 rstat->ip_chksum_err);
1518 device_printf(dev, "%s: pkts_wo_acntxts\t\t%" PRIu64 "\n", __func__,
1519 rstat->pkts_wo_acntxts);
1520 device_printf(dev, "%s: pkts_dropped_no_sds_card\t%" PRIu64 "\n",
1521 __func__, rstat->pkts_dropped_no_sds_card);
1522 device_printf(dev, "%s: pkts_dropped_no_sds_host\t%" PRIu64 "\n",
1523 __func__, rstat->pkts_dropped_no_sds_host);
1524 device_printf(dev, "%s: oversized_pkts\t\t%" PRIu64 "\n", __func__,
1525 rstat->oversized_pkts);
1526 device_printf(dev, "%s: pkts_dropped_no_rds\t\t%" PRIu64 "\n",
1527 __func__, rstat->pkts_dropped_no_rds);
1528 device_printf(dev, "%s: unxpctd_mcast_pkts\t\t%" PRIu64 "\n",
1529 __func__, rstat->unxpctd_mcast_pkts);
1530 device_printf(dev, "%s: re1_fbq_error\t\t%" PRIu64 "\n", __func__,
1531 rstat->re1_fbq_error);
1532 device_printf(dev, "%s: invalid_mac_addr\t\t%" PRIu64 "\n", __func__,
1533 rstat->invalid_mac_addr);
1534 device_printf(dev, "%s: rds_prime_trys\t\t%" PRIu64 "\n", __func__,
1535 rstat->rds_prime_trys);
1536 device_printf(dev, "%s: rds_prime_success\t\t%" PRIu64 "\n", __func__,
1537 rstat->rds_prime_success);
1538 device_printf(dev, "%s: lro_flows_added\t\t%" PRIu64 "\n", __func__,
1539 rstat->lro_flows_added);
1540 device_printf(dev, "%s: lro_flows_deleted\t\t%" PRIu64 "\n", __func__,
1541 rstat->lro_flows_deleted);
1542 device_printf(dev, "%s: lro_flows_active\t\t%" PRIu64 "\n", __func__,
1543 rstat->lro_flows_active);
1544 device_printf(dev, "%s: pkts_droped_unknown\t\t%" PRIu64 "\n",
1545 __func__, rstat->pkts_droped_unknown);
1549 qla_mac_stats(qla_host_t *ha, q80_mac_stats_t *mstat)
1551 device_t dev = ha->pci_dev;
1553 device_printf(dev, "%s: xmt_frames\t\t\t%" PRIu64 "\n", __func__,
1555 device_printf(dev, "%s: xmt_bytes\t\t\t%" PRIu64 "\n", __func__,
1557 device_printf(dev, "%s: xmt_mcast_pkts\t\t%" PRIu64 "\n", __func__,
1558 mstat->xmt_mcast_pkts);
1559 device_printf(dev, "%s: xmt_bcast_pkts\t\t%" PRIu64 "\n", __func__,
1560 mstat->xmt_bcast_pkts);
1561 device_printf(dev, "%s: xmt_pause_frames\t\t%" PRIu64 "\n", __func__,
1562 mstat->xmt_pause_frames);
1563 device_printf(dev, "%s: xmt_cntrl_pkts\t\t%" PRIu64 "\n", __func__,
1564 mstat->xmt_cntrl_pkts);
1565 device_printf(dev, "%s: xmt_pkt_lt_64bytes\t\t%" PRIu64 "\n",
1566 __func__, mstat->xmt_pkt_lt_64bytes);
1567 device_printf(dev, "%s: xmt_pkt_lt_127bytes\t\t%" PRIu64 "\n",
1568 __func__, mstat->xmt_pkt_lt_127bytes);
1569 device_printf(dev, "%s: xmt_pkt_lt_255bytes\t\t%" PRIu64 "\n",
1570 __func__, mstat->xmt_pkt_lt_255bytes);
1571 device_printf(dev, "%s: xmt_pkt_lt_511bytes\t\t%" PRIu64 "\n",
1572 __func__, mstat->xmt_pkt_lt_511bytes);
1573 device_printf(dev, "%s: xmt_pkt_lt_1023bytes\t\t%" PRIu64 "\n",
1574 __func__, mstat->xmt_pkt_lt_1023bytes);
1575 device_printf(dev, "%s: xmt_pkt_lt_1518bytes\t\t%" PRIu64 "\n",
1576 __func__, mstat->xmt_pkt_lt_1518bytes);
1577 device_printf(dev, "%s: xmt_pkt_gt_1518bytes\t\t%" PRIu64 "\n",
1578 __func__, mstat->xmt_pkt_gt_1518bytes);
1580 device_printf(dev, "%s: rcv_frames\t\t\t%" PRIu64 "\n", __func__,
1582 device_printf(dev, "%s: rcv_bytes\t\t\t%" PRIu64 "\n", __func__,
1584 device_printf(dev, "%s: rcv_mcast_pkts\t\t%" PRIu64 "\n", __func__,
1585 mstat->rcv_mcast_pkts);
1586 device_printf(dev, "%s: rcv_bcast_pkts\t\t%" PRIu64 "\n", __func__,
1587 mstat->rcv_bcast_pkts);
1588 device_printf(dev, "%s: rcv_pause_frames\t\t%" PRIu64 "\n", __func__,
1589 mstat->rcv_pause_frames);
1590 device_printf(dev, "%s: rcv_cntrl_pkts\t\t%" PRIu64 "\n", __func__,
1591 mstat->rcv_cntrl_pkts);
1592 device_printf(dev, "%s: rcv_pkt_lt_64bytes\t\t%" PRIu64 "\n",
1593 __func__, mstat->rcv_pkt_lt_64bytes);
1594 device_printf(dev, "%s: rcv_pkt_lt_127bytes\t\t%" PRIu64 "\n",
1595 __func__, mstat->rcv_pkt_lt_127bytes);
1596 device_printf(dev, "%s: rcv_pkt_lt_255bytes\t\t%" PRIu64 "\n",
1597 __func__, mstat->rcv_pkt_lt_255bytes);
1598 device_printf(dev, "%s: rcv_pkt_lt_511bytes\t\t%" PRIu64 "\n",
1599 __func__, mstat->rcv_pkt_lt_511bytes);
1600 device_printf(dev, "%s: rcv_pkt_lt_1023bytes\t\t%" PRIu64 "\n",
1601 __func__, mstat->rcv_pkt_lt_1023bytes);
1602 device_printf(dev, "%s: rcv_pkt_lt_1518bytes\t\t%" PRIu64 "\n",
1603 __func__, mstat->rcv_pkt_lt_1518bytes);
1604 device_printf(dev, "%s: rcv_pkt_gt_1518bytes\t\t%" PRIu64 "\n",
1605 __func__, mstat->rcv_pkt_gt_1518bytes);
1607 device_printf(dev, "%s: rcv_len_error\t\t%" PRIu64 "\n", __func__,
1608 mstat->rcv_len_error);
1609 device_printf(dev, "%s: rcv_len_small\t\t%" PRIu64 "\n", __func__,
1610 mstat->rcv_len_small);
1611 device_printf(dev, "%s: rcv_len_large\t\t%" PRIu64 "\n", __func__,
1612 mstat->rcv_len_large);
1613 device_printf(dev, "%s: rcv_jabber\t\t\t%" PRIu64 "\n", __func__,
1615 device_printf(dev, "%s: rcv_dropped\t\t\t%" PRIu64 "\n", __func__,
1616 mstat->rcv_dropped);
1617 device_printf(dev, "%s: fcs_error\t\t\t%" PRIu64 "\n", __func__,
1619 device_printf(dev, "%s: align_error\t\t\t%" PRIu64 "\n", __func__,
1620 mstat->align_error);
1625 qla_get_hw_stats(qla_host_t *ha, uint32_t cmd, uint32_t rsp_size)
1628 q80_get_stats_t *stat;
1629 q80_get_stats_rsp_t *stat_rsp;
1634 stat = (q80_get_stats_t *)ha->hw.mbox;
1635 bzero(stat, (sizeof (q80_get_stats_t)));
1637 stat->opcode = Q8_MBX_GET_STATS;
1638 stat->count_version = 2;
1639 stat->count_version |= Q8_MBX_CMD_VERSION;
1643 if (qla_mbx_cmd(ha, (uint32_t *)stat, 2,
1644 ha->hw.mbox, (rsp_size >> 2), 0)) {
1645 device_printf(dev, "%s: failed\n", __func__);
1649 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
1651 err = Q8_MBX_RSP_STATUS(stat_rsp->regcnt_status);
1661 ql_get_stats(qla_host_t *ha)
1663 q80_get_stats_rsp_t *stat_rsp;
1664 q80_mac_stats_t *mstat;
1665 q80_xmt_stats_t *xstat;
1666 q80_rcv_stats_t *rstat;
1670 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
1672 * Get MAC Statistics
1674 cmd = Q8_GET_STATS_CMD_TYPE_MAC;
1675 // cmd |= Q8_GET_STATS_CMD_CLEAR;
1677 cmd |= ((ha->pci_func & 0x1) << 16);
1679 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) {
1680 mstat = (q80_mac_stats_t *)&stat_rsp->u.mac;
1681 qla_mac_stats(ha, mstat);
1683 device_printf(ha->pci_dev, "%s: mac failed [0x%08x]\n",
1684 __func__, ha->hw.mbox[0]);
1687 * Get RCV Statistics
1689 cmd = Q8_GET_STATS_CMD_RCV | Q8_GET_STATS_CMD_TYPE_CNTXT;
1690 // cmd |= Q8_GET_STATS_CMD_CLEAR;
1691 cmd |= (ha->hw.rcv_cntxt_id << 16);
1693 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) {
1694 rstat = (q80_rcv_stats_t *)&stat_rsp->u.rcv;
1695 qla_rcv_stats(ha, rstat);
1697 device_printf(ha->pci_dev, "%s: rcv failed [0x%08x]\n",
1698 __func__, ha->hw.mbox[0]);
1701 * Get XMT Statistics
1703 for (i = 0 ; i < ha->hw.num_tx_rings; i++) {
1704 cmd = Q8_GET_STATS_CMD_XMT | Q8_GET_STATS_CMD_TYPE_CNTXT;
1705 // cmd |= Q8_GET_STATS_CMD_CLEAR;
1706 cmd |= (ha->hw.tx_cntxt[i].tx_cntxt_id << 16);
1708 if (qla_get_hw_stats(ha, cmd, sizeof(q80_get_stats_rsp_t))
1710 xstat = (q80_xmt_stats_t *)&stat_rsp->u.xmt;
1711 qla_xmt_stats(ha, xstat, i);
1713 device_printf(ha->pci_dev, "%s: xmt failed [0x%08x]\n",
1714 __func__, ha->hw.mbox[0]);
1721 qla_get_quick_stats(qla_host_t *ha)
1723 q80_get_mac_rcv_xmt_stats_rsp_t *stat_rsp;
1724 q80_mac_stats_t *mstat;
1725 q80_xmt_stats_t *xstat;
1726 q80_rcv_stats_t *rstat;
1729 stat_rsp = (q80_get_mac_rcv_xmt_stats_rsp_t *)ha->hw.mbox;
1731 cmd = Q8_GET_STATS_CMD_TYPE_ALL;
1732 // cmd |= Q8_GET_STATS_CMD_CLEAR;
1734 // cmd |= ((ha->pci_func & 0x3) << 16);
1735 cmd |= (0xFFFF << 16);
1737 if (qla_get_hw_stats(ha, cmd,
1738 sizeof (q80_get_mac_rcv_xmt_stats_rsp_t)) == 0) {
1740 mstat = (q80_mac_stats_t *)&stat_rsp->mac;
1741 rstat = (q80_rcv_stats_t *)&stat_rsp->rcv;
1742 xstat = (q80_xmt_stats_t *)&stat_rsp->xmt;
1743 qla_mac_stats(ha, mstat);
1744 qla_rcv_stats(ha, rstat);
1745 qla_xmt_stats(ha, xstat, ha->hw.num_tx_rings);
1747 device_printf(ha->pci_dev, "%s: failed [0x%08x]\n",
1748 __func__, ha->hw.mbox[0]);
1755 * Function: Checks if the packet to be transmitted is a candidate for
1756 * Large TCP Segment Offload. If yes, the appropriate fields in the Tx
1757 * Ring Structure are plugged in.
1760 qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, uint8_t *hdr)
1762 struct ether_vlan_header *eh;
1763 struct ip *ip = NULL;
1764 struct ip6_hdr *ip6 = NULL;
1765 struct tcphdr *th = NULL;
1766 uint32_t ehdrlen, hdrlen, ip_hlen, tcp_hlen, tcp_opt_off;
1767 uint16_t etype, opcode, offload = 1;
1773 eh = mtod(mp, struct ether_vlan_header *);
1775 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1776 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1777 etype = ntohs(eh->evl_proto);
1779 ehdrlen = ETHER_HDR_LEN;
1780 etype = ntohs(eh->evl_encap_proto);
1788 tcp_opt_off = ehdrlen + sizeof(struct ip) +
1789 sizeof(struct tcphdr);
1791 if (mp->m_len < tcp_opt_off) {
1792 m_copydata(mp, 0, tcp_opt_off, hdr);
1793 ip = (struct ip *)(hdr + ehdrlen);
1795 ip = (struct ip *)(mp->m_data + ehdrlen);
1798 ip_hlen = ip->ip_hl << 2;
1799 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO;
1802 if ((ip->ip_p != IPPROTO_TCP) ||
1803 (ip_hlen != sizeof (struct ip))){
1804 /* IP Options are not supported */
1808 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
1812 case ETHERTYPE_IPV6:
1814 tcp_opt_off = ehdrlen + sizeof(struct ip6_hdr) +
1815 sizeof (struct tcphdr);
1817 if (mp->m_len < tcp_opt_off) {
1818 m_copydata(mp, 0, tcp_opt_off, hdr);
1819 ip6 = (struct ip6_hdr *)(hdr + ehdrlen);
1821 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1824 ip_hlen = sizeof(struct ip6_hdr);
1825 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6;
1827 if (ip6->ip6_nxt != IPPROTO_TCP) {
1828 //device_printf(dev, "%s: ipv6\n", __func__);
1831 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen);
1835 QL_DPRINT8(ha, (dev, "%s: type!=ip\n", __func__));
1843 tcp_hlen = th->th_off << 2;
1844 hdrlen = ehdrlen + ip_hlen + tcp_hlen;
1846 if (mp->m_len < hdrlen) {
1847 if (mp->m_len < tcp_opt_off) {
1848 if (tcp_hlen > sizeof(struct tcphdr)) {
1849 m_copydata(mp, tcp_opt_off,
1850 (tcp_hlen - sizeof(struct tcphdr)),
1854 m_copydata(mp, 0, hdrlen, hdr);
1858 tx_cmd->mss = mp->m_pkthdr.tso_segsz;
1860 tx_cmd->flags_opcode = opcode ;
1861 tx_cmd->tcp_hdr_off = ip_hlen + ehdrlen;
1862 tx_cmd->total_hdr_len = hdrlen;
1864 /* Check for Multicast least significant bit of MSB == 1 */
1865 if (eh->evl_dhost[0] & 0x01) {
1866 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_MULTICAST;
1869 if (mp->m_len < hdrlen) {
1870 printf("%d\n", hdrlen);
1878 * Name: qla_tx_chksum
1879 * Function: Checks if the packet to be transmitted is a candidate for
1880 * TCP/UDP Checksum offload. If yes, the appropriate fields in the Tx
1881 * Ring Structure are plugged in.
1884 qla_tx_chksum(qla_host_t *ha, struct mbuf *mp, uint32_t *op_code,
1885 uint32_t *tcp_hdr_off)
1887 struct ether_vlan_header *eh;
1889 struct ip6_hdr *ip6;
1890 uint32_t ehdrlen, ip_hlen;
1891 uint16_t etype, opcode, offload = 1;
1893 uint8_t buf[sizeof(struct ip6_hdr)];
1899 if ((mp->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) == 0)
1902 eh = mtod(mp, struct ether_vlan_header *);
1904 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1905 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1906 etype = ntohs(eh->evl_proto);
1908 ehdrlen = ETHER_HDR_LEN;
1909 etype = ntohs(eh->evl_encap_proto);
1915 ip = (struct ip *)(mp->m_data + ehdrlen);
1917 ip_hlen = sizeof (struct ip);
1919 if (mp->m_len < (ehdrlen + ip_hlen)) {
1920 m_copydata(mp, ehdrlen, sizeof(struct ip), buf);
1921 ip = (struct ip *)buf;
1924 if (ip->ip_p == IPPROTO_TCP)
1925 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM;
1926 else if (ip->ip_p == IPPROTO_UDP)
1927 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM;
1929 //device_printf(dev, "%s: ipv4\n", __func__);
1934 case ETHERTYPE_IPV6:
1935 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1937 ip_hlen = sizeof(struct ip6_hdr);
1939 if (mp->m_len < (ehdrlen + ip_hlen)) {
1940 m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr),
1942 ip6 = (struct ip6_hdr *)buf;
1945 if (ip6->ip6_nxt == IPPROTO_TCP)
1946 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6;
1947 else if (ip6->ip6_nxt == IPPROTO_UDP)
1948 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6;
1950 //device_printf(dev, "%s: ipv6\n", __func__);
1963 *tcp_hdr_off = (ip_hlen + ehdrlen);
1968 #define QLA_TX_MIN_FREE 2
1971 * Function: Transmits a packet. It first checks if the packet is a
1972 * candidate for Large TCP Segment Offload and then for UDP/TCP checksum
1973 * offload. If either of these creteria are not met, it is transmitted
1974 * as a regular ethernet frame.
1977 ql_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
1978 uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx, uint32_t iscsi_pdu)
1980 struct ether_vlan_header *eh;
1981 qla_hw_t *hw = &ha->hw;
1982 q80_tx_cmd_t *tx_cmd, tso_cmd;
1983 bus_dma_segment_t *c_seg;
1984 uint32_t num_tx_cmds, hdr_len = 0;
1985 uint32_t total_length = 0, bytes, tx_cmd_count = 0, txr_next;
1988 uint8_t *src = NULL, *dst = NULL;
1989 uint8_t frame_hdr[QL_FRAME_HDR_SIZE];
1990 uint32_t op_code = 0;
1991 uint32_t tcp_hdr_off = 0;
1996 * Always make sure there is atleast one empty slot in the tx_ring
1997 * tx_ring is considered full when there only one entry available
1999 num_tx_cmds = (nsegs + (Q8_TX_CMD_MAX_SEGMENTS - 1)) >> 2;
2001 total_length = mp->m_pkthdr.len;
2002 if (total_length > QLA_MAX_TSO_FRAME_SIZE) {
2003 device_printf(dev, "%s: total length exceeds maxlen(%d)\n",
2004 __func__, total_length);
2007 eh = mtod(mp, struct ether_vlan_header *);
2009 if (mp->m_pkthdr.csum_flags & CSUM_TSO) {
2011 bzero((void *)&tso_cmd, sizeof(q80_tx_cmd_t));
2014 ret = qla_tx_tso(ha, mp, &tso_cmd, src);
2017 /* find the additional tx_cmd descriptors required */
2019 if (mp->m_flags & M_VLANTAG)
2020 tso_cmd.total_hdr_len += ETHER_VLAN_ENCAP_LEN;
2022 hdr_len = tso_cmd.total_hdr_len;
2024 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
2025 bytes = QL_MIN(bytes, hdr_len);
2031 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
2035 hdr_len = tso_cmd.total_hdr_len;
2038 src = (uint8_t *)eh;
2042 (void)qla_tx_chksum(ha, mp, &op_code, &tcp_hdr_off);
2046 ha->hw.iscsi_pkt_count++;
2048 if (hw->tx_cntxt[txr_idx].txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) {
2049 ql_hw_tx_done_locked(ha, txr_idx);
2050 if (hw->tx_cntxt[txr_idx].txr_free <=
2051 (num_tx_cmds + QLA_TX_MIN_FREE)) {
2052 QL_DPRINT8(ha, (dev, "%s: (hw->txr_free <= "
2053 "(num_tx_cmds + QLA_TX_MIN_FREE))\n",
2059 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[tx_idx];
2061 if (!(mp->m_pkthdr.csum_flags & CSUM_TSO)) {
2063 if (nsegs > ha->hw.max_tx_segs)
2064 ha->hw.max_tx_segs = nsegs;
2066 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2069 tx_cmd->flags_opcode = op_code;
2070 tx_cmd->tcp_hdr_off = tcp_hdr_off;
2073 tx_cmd->flags_opcode = Q8_TX_CMD_OP_XMT_ETHER;
2076 bcopy(&tso_cmd, tx_cmd, sizeof(q80_tx_cmd_t));
2077 ha->tx_tso_frames++;
2080 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2081 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_VLAN_TAGGED;
2084 eh->evl_tag |= ha->hw.user_pri_iscsi << 13;
2086 } else if (mp->m_flags & M_VLANTAG) {
2088 if (hdr_len) { /* TSO */
2089 tx_cmd->flags_opcode |= (Q8_TX_CMD_FLAGS_VLAN_TAGGED |
2090 Q8_TX_CMD_FLAGS_HW_VLAN_ID);
2091 tx_cmd->tcp_hdr_off += ETHER_VLAN_ENCAP_LEN;
2093 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_HW_VLAN_ID;
2095 ha->hw_vlan_tx_frames++;
2096 tx_cmd->vlan_tci = mp->m_pkthdr.ether_vtag;
2099 tx_cmd->vlan_tci |= ha->hw.user_pri_iscsi << 13;
2100 mp->m_pkthdr.ether_vtag = tx_cmd->vlan_tci;
2105 tx_cmd->n_bufs = (uint8_t)nsegs;
2106 tx_cmd->data_len_lo = (uint8_t)(total_length & 0xFF);
2107 tx_cmd->data_len_hi = qla_host_to_le16(((uint16_t)(total_length >> 8)));
2108 tx_cmd->cntxtid = Q8_TX_CMD_PORT_CNXTID(ha->pci_func);
2113 for (i = 0; ((i < Q8_TX_CMD_MAX_SEGMENTS) && nsegs); i++) {
2117 tx_cmd->buf1_addr = c_seg->ds_addr;
2118 tx_cmd->buf1_len = c_seg->ds_len;
2122 tx_cmd->buf2_addr = c_seg->ds_addr;
2123 tx_cmd->buf2_len = c_seg->ds_len;
2127 tx_cmd->buf3_addr = c_seg->ds_addr;
2128 tx_cmd->buf3_len = c_seg->ds_len;
2132 tx_cmd->buf4_addr = c_seg->ds_addr;
2133 tx_cmd->buf4_len = c_seg->ds_len;
2141 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2142 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2143 (NUM_TX_DESCRIPTORS - 1);
2149 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2150 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2153 if (mp->m_pkthdr.csum_flags & CSUM_TSO) {
2155 /* TSO : Copy the header in the following tx cmd descriptors */
2157 txr_next = hw->tx_cntxt[txr_idx].txr_next;
2159 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2160 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2162 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
2163 bytes = QL_MIN(bytes, hdr_len);
2165 dst = (uint8_t *)tx_cmd + Q8_TX_CMD_TSO_ALIGN;
2167 if (mp->m_flags & M_VLANTAG) {
2168 /* first copy the src/dst MAC addresses */
2169 bcopy(src, dst, (ETHER_ADDR_LEN * 2));
2170 dst += (ETHER_ADDR_LEN * 2);
2171 src += (ETHER_ADDR_LEN * 2);
2173 *((uint16_t *)dst) = htons(ETHERTYPE_VLAN);
2175 *((uint16_t *)dst) = htons(mp->m_pkthdr.ether_vtag);
2178 /* bytes left in src header */
2179 hdr_len -= ((ETHER_ADDR_LEN * 2) +
2180 ETHER_VLAN_ENCAP_LEN);
2182 /* bytes left in TxCmd Entry */
2183 bytes -= ((ETHER_ADDR_LEN * 2) + ETHER_VLAN_ENCAP_LEN);
2186 bcopy(src, dst, bytes);
2190 bcopy(src, dst, bytes);
2195 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2196 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2197 (NUM_TX_DESCRIPTORS - 1);
2201 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2202 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2204 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
2206 bcopy(src, tx_cmd, bytes);
2210 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2211 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2212 (NUM_TX_DESCRIPTORS - 1);
2217 hw->tx_cntxt[txr_idx].txr_free =
2218 hw->tx_cntxt[txr_idx].txr_free - tx_cmd_count;
2220 QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->tx_cntxt[txr_idx].txr_next,\
2222 QL_DPRINT8(ha, (dev, "%s: return\n", __func__));
2229 #define Q8_CONFIG_IND_TBL_SIZE 32 /* < Q8_RSS_IND_TBL_SIZE and power of 2 */
2231 qla_config_rss_ind_table(qla_host_t *ha)
2234 uint8_t rss_ind_tbl[Q8_CONFIG_IND_TBL_SIZE];
2237 for (i = 0; i < Q8_CONFIG_IND_TBL_SIZE; i++) {
2238 rss_ind_tbl[i] = i % ha->hw.num_sds_rings;
2241 for (i = 0; i <= Q8_RSS_IND_TBL_MAX_IDX ;
2242 i = i + Q8_CONFIG_IND_TBL_SIZE) {
2244 if ((i + Q8_CONFIG_IND_TBL_SIZE) > Q8_RSS_IND_TBL_MAX_IDX) {
2245 count = Q8_RSS_IND_TBL_MAX_IDX - i + 1;
2247 count = Q8_CONFIG_IND_TBL_SIZE;
2250 if (qla_set_rss_ind_table(ha, i, count, ha->hw.rcv_cntxt_id,
2259 * Name: ql_del_hw_if
2260 * Function: Destroys the hardware specific entities corresponding to an
2261 * Ethernet Interface
2264 ql_del_hw_if(qla_host_t *ha)
2269 (void)qla_stop_nic_func(ha);
2271 qla_del_rcv_cntxt(ha);
2273 qla_del_xmt_cntxt(ha);
2275 if (ha->hw.flags.init_intr_cnxt) {
2276 for (i = 0; i < ha->hw.num_sds_rings; ) {
2278 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2279 num_msix = Q8_MAX_INTR_VECTORS;
2281 num_msix = ha->hw.num_sds_rings - i;
2282 qla_config_intr_cntxt(ha, i, num_msix, 0);
2287 ha->hw.flags.init_intr_cnxt = 0;
2294 qla_confirm_9kb_enable(qla_host_t *ha)
2296 uint32_t supports_9kb = 0;
2298 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX);
2300 /* Use MSI-X vector 0; Enable Firmware Mailbox Interrupt */
2301 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2);
2302 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
2304 qla_get_nic_partition(ha, &supports_9kb, NULL);
2307 ha->hw.enable_9kb = 0;
2314 * Name: ql_init_hw_if
2315 * Function: Creates the hardware specific entities corresponding to an
2316 * Ethernet Interface - Transmit and Receive Contexts. Sets the MAC Address
2317 * corresponding to the interface. Enables LRO if allowed.
2320 ql_init_hw_if(qla_host_t *ha)
2324 uint8_t bcast_mac[6];
2330 for (i = 0; i < ha->hw.num_sds_rings; i++) {
2331 bzero(ha->hw.dma_buf.sds_ring[i].dma_b,
2332 ha->hw.dma_buf.sds_ring[i].size);
2335 for (i = 0; i < ha->hw.num_sds_rings; ) {
2337 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2338 num_msix = Q8_MAX_INTR_VECTORS;
2340 num_msix = ha->hw.num_sds_rings - i;
2342 if (qla_config_intr_cntxt(ha, i, num_msix, 1)) {
2348 for (i = 0; i < num_msix; ) {
2349 qla_config_intr_cntxt(ha, i,
2350 Q8_MAX_INTR_VECTORS, 0);
2351 i += Q8_MAX_INTR_VECTORS;
2360 ha->hw.flags.init_intr_cnxt = 1;
2363 * Create Receive Context
2365 if (qla_init_rcv_cntxt(ha)) {
2369 for (i = 0; i < ha->hw.num_rds_rings; i++) {
2370 rdesc = &ha->hw.rds[i];
2371 rdesc->rx_next = NUM_RX_DESCRIPTORS - 2;
2373 /* Update the RDS Producer Indices */
2374 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,\
2380 * Create Transmit Context
2382 if (qla_init_xmt_cntxt(ha)) {
2383 qla_del_rcv_cntxt(ha);
2386 ha->hw.max_tx_segs = 0;
2388 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 1, 1))
2391 ha->hw.flags.unicast_mac = 1;
2393 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF;
2394 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF;
2396 if (qla_config_mac_addr(ha, bcast_mac, 1, 1))
2399 ha->hw.flags.bcast_mac = 1;
2402 * program any cached multicast addresses
2404 if (qla_hw_add_all_mcast(ha))
2407 if (qla_config_rss(ha, ha->hw.rcv_cntxt_id))
2410 if (qla_config_rss_ind_table(ha))
2413 if (qla_config_intr_coalesce(ha, ha->hw.rcv_cntxt_id, 0, 1))
2416 if (qla_link_event_req(ha, ha->hw.rcv_cntxt_id))
2419 if (qla_config_fw_lro(ha, ha->hw.rcv_cntxt_id))
2422 if (qla_init_nic_func(ha))
2425 if (qla_query_fw_dcbx_caps(ha))
2428 for (i = 0; i < ha->hw.num_sds_rings; i++)
2429 QL_ENABLE_INTERRUPTS(ha, i);
2435 qla_map_sds_to_rds(qla_host_t *ha, uint32_t start_idx, uint32_t num_idx)
2437 device_t dev = ha->pci_dev;
2438 q80_rq_map_sds_to_rds_t *map_rings;
2439 q80_rsp_map_sds_to_rds_t *map_rings_rsp;
2441 qla_hw_t *hw = &ha->hw;
2443 map_rings = (q80_rq_map_sds_to_rds_t *)ha->hw.mbox;
2444 bzero(map_rings, sizeof(q80_rq_map_sds_to_rds_t));
2446 map_rings->opcode = Q8_MBX_MAP_SDS_TO_RDS;
2447 map_rings->count_version = (sizeof (q80_rq_map_sds_to_rds_t) >> 2);
2448 map_rings->count_version |= Q8_MBX_CMD_VERSION;
2450 map_rings->cntxt_id = hw->rcv_cntxt_id;
2451 map_rings->num_rings = num_idx;
2453 for (i = 0; i < num_idx; i++) {
2454 map_rings->sds_rds[i].sds_ring = i + start_idx;
2455 map_rings->sds_rds[i].rds_ring = i + start_idx;
2458 if (qla_mbx_cmd(ha, (uint32_t *)map_rings,
2459 (sizeof (q80_rq_map_sds_to_rds_t) >> 2),
2460 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
2461 device_printf(dev, "%s: failed0\n", __func__);
2465 map_rings_rsp = (q80_rsp_map_sds_to_rds_t *)ha->hw.mbox;
2467 err = Q8_MBX_RSP_STATUS(map_rings_rsp->regcnt_status);
2470 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2478 * Name: qla_init_rcv_cntxt
2479 * Function: Creates the Receive Context.
2482 qla_init_rcv_cntxt(qla_host_t *ha)
2484 q80_rq_rcv_cntxt_t *rcntxt;
2485 q80_rsp_rcv_cntxt_t *rcntxt_rsp;
2486 q80_stat_desc_t *sdesc;
2488 qla_hw_t *hw = &ha->hw;
2491 uint32_t rcntxt_sds_rings;
2492 uint32_t rcntxt_rds_rings;
2498 * Create Receive Context
2501 for (i = 0; i < hw->num_sds_rings; i++) {
2502 sdesc = (q80_stat_desc_t *)&hw->sds[i].sds_ring_base[0];
2504 for (j = 0; j < NUM_STATUS_DESCRIPTORS; j++) {
2505 sdesc->data[0] = 1ULL;
2506 sdesc->data[1] = 1ULL;
2510 rcntxt_sds_rings = hw->num_sds_rings;
2511 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS)
2512 rcntxt_sds_rings = MAX_RCNTXT_SDS_RINGS;
2514 rcntxt_rds_rings = hw->num_rds_rings;
2516 if (hw->num_rds_rings > MAX_RDS_RING_SETS)
2517 rcntxt_rds_rings = MAX_RDS_RING_SETS;
2519 rcntxt = (q80_rq_rcv_cntxt_t *)ha->hw.mbox;
2520 bzero(rcntxt, (sizeof (q80_rq_rcv_cntxt_t)));
2522 rcntxt->opcode = Q8_MBX_CREATE_RX_CNTXT;
2523 rcntxt->count_version = (sizeof (q80_rq_rcv_cntxt_t) >> 2);
2524 rcntxt->count_version |= Q8_MBX_CMD_VERSION;
2526 rcntxt->cap0 = Q8_RCV_CNTXT_CAP0_BASEFW |
2527 Q8_RCV_CNTXT_CAP0_LRO |
2528 Q8_RCV_CNTXT_CAP0_HW_LRO |
2529 Q8_RCV_CNTXT_CAP0_RSS |
2530 Q8_RCV_CNTXT_CAP0_SGL_LRO;
2532 if (ha->hw.enable_9kb)
2533 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO;
2535 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SGL_JUMBO;
2537 if (ha->hw.num_rds_rings > 1) {
2538 rcntxt->nrds_sets_rings = rcntxt_rds_rings | (1 << 5);
2539 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_MULTI_RDS;
2541 rcntxt->nrds_sets_rings = 0x1 | (1 << 5);
2543 rcntxt->nsds_rings = rcntxt_sds_rings;
2545 rcntxt->rds_producer_mode = Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE;
2547 rcntxt->rcv_vpid = 0;
2549 for (i = 0; i < rcntxt_sds_rings; i++) {
2550 rcntxt->sds[i].paddr =
2551 qla_host_to_le64(hw->dma_buf.sds_ring[i].dma_addr);
2552 rcntxt->sds[i].size =
2553 qla_host_to_le32(NUM_STATUS_DESCRIPTORS);
2554 rcntxt->sds[i].intr_id = qla_host_to_le16(hw->intr_id[i]);
2555 rcntxt->sds[i].intr_src_bit = qla_host_to_le16(0);
2558 for (i = 0; i < rcntxt_rds_rings; i++) {
2559 rcntxt->rds[i].paddr_std =
2560 qla_host_to_le64(hw->dma_buf.rds_ring[i].dma_addr);
2562 if (ha->hw.enable_9kb)
2563 rcntxt->rds[i].std_bsize =
2564 qla_host_to_le64(MJUM9BYTES);
2566 rcntxt->rds[i].std_bsize = qla_host_to_le64(MCLBYTES);
2568 rcntxt->rds[i].std_nentries =
2569 qla_host_to_le32(NUM_RX_DESCRIPTORS);
2572 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt,
2573 (sizeof (q80_rq_rcv_cntxt_t) >> 2),
2574 ha->hw.mbox, (sizeof(q80_rsp_rcv_cntxt_t) >> 2), 0)) {
2575 device_printf(dev, "%s: failed0\n", __func__);
2579 rcntxt_rsp = (q80_rsp_rcv_cntxt_t *)ha->hw.mbox;
2581 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status);
2584 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2588 for (i = 0; i < rcntxt_sds_rings; i++) {
2589 hw->sds[i].sds_consumer = rcntxt_rsp->sds_cons[i];
2592 for (i = 0; i < rcntxt_rds_rings; i++) {
2593 hw->rds[i].prod_std = rcntxt_rsp->rds[i].prod_std;
2596 hw->rcv_cntxt_id = rcntxt_rsp->cntxt_id;
2598 ha->hw.flags.init_rx_cnxt = 1;
2600 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) {
2602 for (i = MAX_RCNTXT_SDS_RINGS; i < hw->num_sds_rings;) {
2604 if ((i + MAX_RCNTXT_SDS_RINGS) < hw->num_sds_rings)
2605 max_idx = MAX_RCNTXT_SDS_RINGS;
2607 max_idx = hw->num_sds_rings - i;
2609 err = qla_add_rcv_rings(ha, i, max_idx);
2617 if (hw->num_rds_rings > 1) {
2619 for (i = 0; i < hw->num_rds_rings; ) {
2621 if ((i + MAX_SDS_TO_RDS_MAP) < hw->num_rds_rings)
2622 max_idx = MAX_SDS_TO_RDS_MAP;
2624 max_idx = hw->num_rds_rings - i;
2626 err = qla_map_sds_to_rds(ha, i, max_idx);
2638 qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds)
2640 device_t dev = ha->pci_dev;
2641 q80_rq_add_rcv_rings_t *add_rcv;
2642 q80_rsp_add_rcv_rings_t *add_rcv_rsp;
2644 qla_hw_t *hw = &ha->hw;
2646 add_rcv = (q80_rq_add_rcv_rings_t *)ha->hw.mbox;
2647 bzero(add_rcv, sizeof (q80_rq_add_rcv_rings_t));
2649 add_rcv->opcode = Q8_MBX_ADD_RX_RINGS;
2650 add_rcv->count_version = (sizeof (q80_rq_add_rcv_rings_t) >> 2);
2651 add_rcv->count_version |= Q8_MBX_CMD_VERSION;
2653 add_rcv->nrds_sets_rings = nsds | (1 << 5);
2654 add_rcv->nsds_rings = nsds;
2655 add_rcv->cntxt_id = hw->rcv_cntxt_id;
2657 for (i = 0; i < nsds; i++) {
2661 add_rcv->sds[i].paddr =
2662 qla_host_to_le64(hw->dma_buf.sds_ring[j].dma_addr);
2664 add_rcv->sds[i].size =
2665 qla_host_to_le32(NUM_STATUS_DESCRIPTORS);
2667 add_rcv->sds[i].intr_id = qla_host_to_le16(hw->intr_id[j]);
2668 add_rcv->sds[i].intr_src_bit = qla_host_to_le16(0);
2672 for (i = 0; (i < nsds); i++) {
2675 add_rcv->rds[i].paddr_std =
2676 qla_host_to_le64(hw->dma_buf.rds_ring[j].dma_addr);
2678 if (ha->hw.enable_9kb)
2679 add_rcv->rds[i].std_bsize =
2680 qla_host_to_le64(MJUM9BYTES);
2682 add_rcv->rds[i].std_bsize = qla_host_to_le64(MCLBYTES);
2684 add_rcv->rds[i].std_nentries =
2685 qla_host_to_le32(NUM_RX_DESCRIPTORS);
2689 if (qla_mbx_cmd(ha, (uint32_t *)add_rcv,
2690 (sizeof (q80_rq_add_rcv_rings_t) >> 2),
2691 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
2692 device_printf(dev, "%s: failed0\n", __func__);
2696 add_rcv_rsp = (q80_rsp_add_rcv_rings_t *)ha->hw.mbox;
2698 err = Q8_MBX_RSP_STATUS(add_rcv_rsp->regcnt_status);
2701 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2705 for (i = 0; i < nsds; i++) {
2706 hw->sds[(i + sds_idx)].sds_consumer = add_rcv_rsp->sds_cons[i];
2709 for (i = 0; i < nsds; i++) {
2710 hw->rds[(i + sds_idx)].prod_std = add_rcv_rsp->rds[i].prod_std;
2717 * Name: qla_del_rcv_cntxt
2718 * Function: Destroys the Receive Context.
2721 qla_del_rcv_cntxt(qla_host_t *ha)
2723 device_t dev = ha->pci_dev;
2724 q80_rcv_cntxt_destroy_t *rcntxt;
2725 q80_rcv_cntxt_destroy_rsp_t *rcntxt_rsp;
2727 uint8_t bcast_mac[6];
2729 if (!ha->hw.flags.init_rx_cnxt)
2732 if (qla_hw_del_all_mcast(ha))
2735 if (ha->hw.flags.bcast_mac) {
2737 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF;
2738 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF;
2740 if (qla_config_mac_addr(ha, bcast_mac, 0, 1))
2742 ha->hw.flags.bcast_mac = 0;
2746 if (ha->hw.flags.unicast_mac) {
2747 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 0, 1))
2749 ha->hw.flags.unicast_mac = 0;
2752 rcntxt = (q80_rcv_cntxt_destroy_t *)ha->hw.mbox;
2753 bzero(rcntxt, (sizeof (q80_rcv_cntxt_destroy_t)));
2755 rcntxt->opcode = Q8_MBX_DESTROY_RX_CNTXT;
2756 rcntxt->count_version = (sizeof (q80_rcv_cntxt_destroy_t) >> 2);
2757 rcntxt->count_version |= Q8_MBX_CMD_VERSION;
2759 rcntxt->cntxt_id = ha->hw.rcv_cntxt_id;
2761 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt,
2762 (sizeof (q80_rcv_cntxt_destroy_t) >> 2),
2763 ha->hw.mbox, (sizeof(q80_rcv_cntxt_destroy_rsp_t) >> 2), 0)) {
2764 device_printf(dev, "%s: failed0\n", __func__);
2767 rcntxt_rsp = (q80_rcv_cntxt_destroy_rsp_t *)ha->hw.mbox;
2769 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status);
2772 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2775 ha->hw.flags.init_rx_cnxt = 0;
2780 * Name: qla_init_xmt_cntxt
2781 * Function: Creates the Transmit Context.
2784 qla_init_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx)
2787 qla_hw_t *hw = &ha->hw;
2788 q80_rq_tx_cntxt_t *tcntxt;
2789 q80_rsp_tx_cntxt_t *tcntxt_rsp;
2791 qla_hw_tx_cntxt_t *hw_tx_cntxt;
2794 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
2799 * Create Transmit Context
2801 tcntxt = (q80_rq_tx_cntxt_t *)ha->hw.mbox;
2802 bzero(tcntxt, (sizeof (q80_rq_tx_cntxt_t)));
2804 tcntxt->opcode = Q8_MBX_CREATE_TX_CNTXT;
2805 tcntxt->count_version = (sizeof (q80_rq_tx_cntxt_t) >> 2);
2806 tcntxt->count_version |= Q8_MBX_CMD_VERSION;
2810 #ifdef QL_ENABLE_ISCSI_TLV
2812 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO |
2813 Q8_TX_CNTXT_CAP0_TC;
2815 if (txr_idx >= (ha->hw.num_tx_rings >> 1)) {
2816 tcntxt->traffic_class = 1;
2819 intr_idx = txr_idx % (ha->hw.num_tx_rings >> 1);
2822 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO;
2824 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
2826 tcntxt->ntx_rings = 1;
2828 tcntxt->tx_ring[0].paddr =
2829 qla_host_to_le64(hw_tx_cntxt->tx_ring_paddr);
2830 tcntxt->tx_ring[0].tx_consumer =
2831 qla_host_to_le64(hw_tx_cntxt->tx_cons_paddr);
2832 tcntxt->tx_ring[0].nentries = qla_host_to_le16(NUM_TX_DESCRIPTORS);
2834 tcntxt->tx_ring[0].intr_id = qla_host_to_le16(hw->intr_id[intr_idx]);
2835 tcntxt->tx_ring[0].intr_src_bit = qla_host_to_le16(0);
2837 hw_tx_cntxt->txr_free = NUM_TX_DESCRIPTORS;
2838 hw_tx_cntxt->txr_next = hw_tx_cntxt->txr_comp = 0;
2840 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt,
2841 (sizeof (q80_rq_tx_cntxt_t) >> 2),
2843 (sizeof(q80_rsp_tx_cntxt_t) >> 2), 0)) {
2844 device_printf(dev, "%s: failed0\n", __func__);
2847 tcntxt_rsp = (q80_rsp_tx_cntxt_t *)ha->hw.mbox;
2849 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status);
2852 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2856 hw_tx_cntxt->tx_prod_reg = tcntxt_rsp->tx_ring[0].prod_index;
2857 hw_tx_cntxt->tx_cntxt_id = tcntxt_rsp->tx_ring[0].cntxt_id;
2859 if (qla_config_intr_coalesce(ha, hw_tx_cntxt->tx_cntxt_id, 0, 0))
2867 * Name: qla_del_xmt_cntxt
2868 * Function: Destroys the Transmit Context.
2871 qla_del_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx)
2873 device_t dev = ha->pci_dev;
2874 q80_tx_cntxt_destroy_t *tcntxt;
2875 q80_tx_cntxt_destroy_rsp_t *tcntxt_rsp;
2878 tcntxt = (q80_tx_cntxt_destroy_t *)ha->hw.mbox;
2879 bzero(tcntxt, (sizeof (q80_tx_cntxt_destroy_t)));
2881 tcntxt->opcode = Q8_MBX_DESTROY_TX_CNTXT;
2882 tcntxt->count_version = (sizeof (q80_tx_cntxt_destroy_t) >> 2);
2883 tcntxt->count_version |= Q8_MBX_CMD_VERSION;
2885 tcntxt->cntxt_id = ha->hw.tx_cntxt[txr_idx].tx_cntxt_id;
2887 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt,
2888 (sizeof (q80_tx_cntxt_destroy_t) >> 2),
2889 ha->hw.mbox, (sizeof (q80_tx_cntxt_destroy_rsp_t) >> 2), 0)) {
2890 device_printf(dev, "%s: failed0\n", __func__);
2893 tcntxt_rsp = (q80_tx_cntxt_destroy_rsp_t *)ha->hw.mbox;
2895 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status);
2898 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2905 qla_del_xmt_cntxt(qla_host_t *ha)
2909 if (!ha->hw.flags.init_tx_cnxt)
2912 for (i = 0; i < ha->hw.num_tx_rings; i++) {
2913 if (qla_del_xmt_cntxt_i(ha, i))
2916 ha->hw.flags.init_tx_cnxt = 0;
2920 qla_init_xmt_cntxt(qla_host_t *ha)
2924 for (i = 0; i < ha->hw.num_tx_rings; i++) {
2925 if (qla_init_xmt_cntxt_i(ha, i) != 0) {
2926 for (j = 0; j < i; j++)
2927 qla_del_xmt_cntxt_i(ha, j);
2931 ha->hw.flags.init_tx_cnxt = 1;
2936 qla_hw_all_mcast(qla_host_t *ha, uint32_t add_mcast)
2942 nmcast = ha->hw.nmcast;
2944 QL_DPRINT2(ha, (ha->pci_dev,
2945 "%s:[0x%x] enter nmcast = %d \n", __func__, add_mcast, nmcast));
2947 mcast = ha->hw.mac_addr_arr;
2948 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
2950 for (i = 0 ; ((i < Q8_MAX_NUM_MULTICAST_ADDRS) && nmcast); i++) {
2951 if ((ha->hw.mcast[i].addr[0] != 0) ||
2952 (ha->hw.mcast[i].addr[1] != 0) ||
2953 (ha->hw.mcast[i].addr[2] != 0) ||
2954 (ha->hw.mcast[i].addr[3] != 0) ||
2955 (ha->hw.mcast[i].addr[4] != 0) ||
2956 (ha->hw.mcast[i].addr[5] != 0)) {
2958 bcopy(ha->hw.mcast[i].addr, mcast, ETHER_ADDR_LEN);
2959 mcast = mcast + ETHER_ADDR_LEN;
2962 if (count == Q8_MAX_MAC_ADDRS) {
2963 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
2964 add_mcast, count)) {
2965 device_printf(ha->pci_dev,
2966 "%s: failed\n", __func__);
2971 mcast = ha->hw.mac_addr_arr;
2973 (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
2981 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mcast,
2983 device_printf(ha->pci_dev, "%s: failed\n", __func__);
2987 QL_DPRINT2(ha, (ha->pci_dev,
2988 "%s:[0x%x] exit nmcast = %d \n", __func__, add_mcast, nmcast));
2994 qla_hw_add_all_mcast(qla_host_t *ha)
2998 ret = qla_hw_all_mcast(ha, 1);
3004 qla_hw_del_all_mcast(qla_host_t *ha)
3008 ret = qla_hw_all_mcast(ha, 0);
3010 bzero(ha->hw.mcast, (sizeof (qla_mcast_t) * Q8_MAX_NUM_MULTICAST_ADDRS));
3017 qla_hw_mac_addr_present(qla_host_t *ha, uint8_t *mta)
3021 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3022 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0)
3023 return (0); /* its been already added */
3029 qla_hw_add_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast)
3033 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3035 if ((ha->hw.mcast[i].addr[0] == 0) &&
3036 (ha->hw.mcast[i].addr[1] == 0) &&
3037 (ha->hw.mcast[i].addr[2] == 0) &&
3038 (ha->hw.mcast[i].addr[3] == 0) &&
3039 (ha->hw.mcast[i].addr[4] == 0) &&
3040 (ha->hw.mcast[i].addr[5] == 0)) {
3042 bcopy(mta, ha->hw.mcast[i].addr, Q8_MAC_ADDR_LEN);
3045 mta = mta + ETHER_ADDR_LEN;
3057 qla_hw_del_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast)
3061 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3062 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) {
3064 ha->hw.mcast[i].addr[0] = 0;
3065 ha->hw.mcast[i].addr[1] = 0;
3066 ha->hw.mcast[i].addr[2] = 0;
3067 ha->hw.mcast[i].addr[3] = 0;
3068 ha->hw.mcast[i].addr[4] = 0;
3069 ha->hw.mcast[i].addr[5] = 0;
3073 mta = mta + ETHER_ADDR_LEN;
3084 * Name: ql_hw_set_multi
3085 * Function: Sets the Multicast Addresses provided by the host O.S into the
3086 * hardware (for the given interface)
3089 ql_hw_set_multi(qla_host_t *ha, uint8_t *mcast_addr, uint32_t mcnt,
3092 uint8_t *mta = mcast_addr;
3098 mcast = ha->hw.mac_addr_arr;
3099 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3101 for (i = 0; i < mcnt; i++) {
3102 if (mta[0] || mta[1] || mta[2] || mta[3] || mta[4] || mta[5]) {
3104 if (qla_hw_mac_addr_present(ha, mta) != 0) {
3105 bcopy(mta, mcast, ETHER_ADDR_LEN);
3106 mcast = mcast + ETHER_ADDR_LEN;
3110 if (qla_hw_mac_addr_present(ha, mta) == 0) {
3111 bcopy(mta, mcast, ETHER_ADDR_LEN);
3112 mcast = mcast + ETHER_ADDR_LEN;
3117 if (count == Q8_MAX_MAC_ADDRS) {
3118 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
3120 device_printf(ha->pci_dev, "%s: failed\n",
3126 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr,
3129 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr,
3134 mcast = ha->hw.mac_addr_arr;
3135 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3138 mta += Q8_MAC_ADDR_LEN;
3142 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mac,
3144 device_printf(ha->pci_dev, "%s: failed\n", __func__);
3148 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, count);
3150 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, count);
3158 * Name: ql_hw_tx_done_locked
3159 * Function: Handle Transmit Completions
3162 ql_hw_tx_done_locked(qla_host_t *ha, uint32_t txr_idx)
3165 qla_hw_t *hw = &ha->hw;
3166 uint32_t comp_idx, comp_count = 0;
3167 qla_hw_tx_cntxt_t *hw_tx_cntxt;
3169 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
3171 /* retrieve index of last entry in tx ring completed */
3172 comp_idx = qla_le32_to_host(*(hw_tx_cntxt->tx_cons));
3174 while (comp_idx != hw_tx_cntxt->txr_comp) {
3176 txb = &ha->tx_ring[txr_idx].tx_buf[hw_tx_cntxt->txr_comp];
3178 hw_tx_cntxt->txr_comp++;
3179 if (hw_tx_cntxt->txr_comp == NUM_TX_DESCRIPTORS)
3180 hw_tx_cntxt->txr_comp = 0;
3185 ha->ifp->if_opackets++;
3187 bus_dmamap_sync(ha->tx_tag, txb->map,
3188 BUS_DMASYNC_POSTWRITE);
3189 bus_dmamap_unload(ha->tx_tag, txb->map);
3190 m_freem(txb->m_head);
3196 hw_tx_cntxt->txr_free += comp_count;
3201 ql_update_link_state(qla_host_t *ha)
3203 uint32_t link_state;
3204 uint32_t prev_link_state;
3206 if (!(ha->ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3210 link_state = READ_REG32(ha, Q8_LINK_STATE);
3212 prev_link_state = ha->hw.link_up;
3214 if (ha->pci_func == 0)
3215 ha->hw.link_up = (((link_state & 0xF) == 1)? 1 : 0);
3217 ha->hw.link_up = ((((link_state >> 4)& 0xF) == 1)? 1 : 0);
3219 if (prev_link_state != ha->hw.link_up) {
3220 if (ha->hw.link_up) {
3221 if_link_state_change(ha->ifp, LINK_STATE_UP);
3223 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
3230 ql_hw_stop_rcv(qla_host_t *ha)
3232 int i, done, count = 100;
3234 ha->flags.stop_rcv = 1;
3238 for (i = 0; i < ha->hw.num_sds_rings; i++) {
3239 if (ha->hw.sds[i].rcv_active)
3245 qla_mdelay(__func__, 10);
3249 device_printf(ha->pci_dev, "%s: Counter expired.\n", __func__);
3255 ql_hw_check_health(qla_host_t *ha)
3259 ha->hw.health_count++;
3261 if (ha->hw.health_count < 1000)
3264 ha->hw.health_count = 0;
3266 val = READ_REG32(ha, Q8_ASIC_TEMPERATURE);
3268 if (((val & 0xFFFF) == 2) || ((val & 0xFFFF) == 3) ||
3269 (QL_ERR_INJECT(ha, INJCT_TEMPERATURE_FAILURE))) {
3270 device_printf(ha->pci_dev, "%s: Temperature Alert [0x%08x]\n",
3275 val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT);
3277 if ((val != ha->hw.hbeat_value) &&
3278 (!(QL_ERR_INJECT(ha, INJCT_HEARTBEAT_FAILURE)))) {
3279 ha->hw.hbeat_value = val;
3282 device_printf(ha->pci_dev, "%s: Heartbeat Failue [0x%08x]\n",
3289 qla_init_nic_func(qla_host_t *ha)
3292 q80_init_nic_func_t *init_nic;
3293 q80_init_nic_func_rsp_t *init_nic_rsp;
3298 init_nic = (q80_init_nic_func_t *)ha->hw.mbox;
3299 bzero(init_nic, sizeof(q80_init_nic_func_t));
3301 init_nic->opcode = Q8_MBX_INIT_NIC_FUNC;
3302 init_nic->count_version = (sizeof (q80_init_nic_func_t) >> 2);
3303 init_nic->count_version |= Q8_MBX_CMD_VERSION;
3305 init_nic->options = Q8_INIT_NIC_REG_DCBX_CHNG_AEN;
3306 init_nic->options |= Q8_INIT_NIC_REG_SFP_CHNG_AEN;
3307 init_nic->options |= Q8_INIT_NIC_REG_IDC_AEN;
3309 //qla_dump_buf8(ha, __func__, init_nic, sizeof (q80_init_nic_func_t));
3310 if (qla_mbx_cmd(ha, (uint32_t *)init_nic,
3311 (sizeof (q80_init_nic_func_t) >> 2),
3312 ha->hw.mbox, (sizeof (q80_init_nic_func_rsp_t) >> 2), 0)) {
3313 device_printf(dev, "%s: failed\n", __func__);
3317 init_nic_rsp = (q80_init_nic_func_rsp_t *)ha->hw.mbox;
3318 // qla_dump_buf8(ha, __func__, init_nic_rsp, sizeof (q80_init_nic_func_rsp_t));
3320 err = Q8_MBX_RSP_STATUS(init_nic_rsp->regcnt_status);
3323 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3330 qla_stop_nic_func(qla_host_t *ha)
3333 q80_stop_nic_func_t *stop_nic;
3334 q80_stop_nic_func_rsp_t *stop_nic_rsp;
3339 stop_nic = (q80_stop_nic_func_t *)ha->hw.mbox;
3340 bzero(stop_nic, sizeof(q80_stop_nic_func_t));
3342 stop_nic->opcode = Q8_MBX_STOP_NIC_FUNC;
3343 stop_nic->count_version = (sizeof (q80_stop_nic_func_t) >> 2);
3344 stop_nic->count_version |= Q8_MBX_CMD_VERSION;
3346 stop_nic->options = Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN;
3347 stop_nic->options |= Q8_STOP_NIC_DEREG_SFP_CHNG_AEN;
3349 //qla_dump_buf8(ha, __func__, stop_nic, sizeof (q80_stop_nic_func_t));
3350 if (qla_mbx_cmd(ha, (uint32_t *)stop_nic,
3351 (sizeof (q80_stop_nic_func_t) >> 2),
3352 ha->hw.mbox, (sizeof (q80_stop_nic_func_rsp_t) >> 2), 0)) {
3353 device_printf(dev, "%s: failed\n", __func__);
3357 stop_nic_rsp = (q80_stop_nic_func_rsp_t *)ha->hw.mbox;
3358 //qla_dump_buf8(ha, __func__, stop_nic_rsp, sizeof (q80_stop_nic_func_rsp_ t));
3360 err = Q8_MBX_RSP_STATUS(stop_nic_rsp->regcnt_status);
3363 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3370 qla_query_fw_dcbx_caps(qla_host_t *ha)
3373 q80_query_fw_dcbx_caps_t *fw_dcbx;
3374 q80_query_fw_dcbx_caps_rsp_t *fw_dcbx_rsp;
3379 fw_dcbx = (q80_query_fw_dcbx_caps_t *)ha->hw.mbox;
3380 bzero(fw_dcbx, sizeof(q80_query_fw_dcbx_caps_t));
3382 fw_dcbx->opcode = Q8_MBX_GET_FW_DCBX_CAPS;
3383 fw_dcbx->count_version = (sizeof (q80_query_fw_dcbx_caps_t) >> 2);
3384 fw_dcbx->count_version |= Q8_MBX_CMD_VERSION;
3386 ql_dump_buf8(ha, __func__, fw_dcbx, sizeof (q80_query_fw_dcbx_caps_t));
3387 if (qla_mbx_cmd(ha, (uint32_t *)fw_dcbx,
3388 (sizeof (q80_query_fw_dcbx_caps_t) >> 2),
3389 ha->hw.mbox, (sizeof (q80_query_fw_dcbx_caps_rsp_t) >> 2), 0)) {
3390 device_printf(dev, "%s: failed\n", __func__);
3394 fw_dcbx_rsp = (q80_query_fw_dcbx_caps_rsp_t *)ha->hw.mbox;
3395 ql_dump_buf8(ha, __func__, fw_dcbx_rsp,
3396 sizeof (q80_query_fw_dcbx_caps_rsp_t));
3398 err = Q8_MBX_RSP_STATUS(fw_dcbx_rsp->regcnt_status);
3401 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3408 qla_idc_ack(qla_host_t *ha, uint32_t aen_mb1, uint32_t aen_mb2,
3409 uint32_t aen_mb3, uint32_t aen_mb4)
3412 q80_idc_ack_t *idc_ack;
3413 q80_idc_ack_rsp_t *idc_ack_rsp;
3419 idc_ack = (q80_idc_ack_t *)ha->hw.mbox;
3420 bzero(idc_ack, sizeof(q80_idc_ack_t));
3422 idc_ack->opcode = Q8_MBX_IDC_ACK;
3423 idc_ack->count_version = (sizeof (q80_idc_ack_t) >> 2);
3424 idc_ack->count_version |= Q8_MBX_CMD_VERSION;
3426 idc_ack->aen_mb1 = aen_mb1;
3427 idc_ack->aen_mb2 = aen_mb2;
3428 idc_ack->aen_mb3 = aen_mb3;
3429 idc_ack->aen_mb4 = aen_mb4;
3431 ha->hw.imd_compl= 0;
3433 if (qla_mbx_cmd(ha, (uint32_t *)idc_ack,
3434 (sizeof (q80_idc_ack_t) >> 2),
3435 ha->hw.mbox, (sizeof (q80_idc_ack_rsp_t) >> 2), 0)) {
3436 device_printf(dev, "%s: failed\n", __func__);
3440 idc_ack_rsp = (q80_idc_ack_rsp_t *)ha->hw.mbox;
3442 err = Q8_MBX_RSP_STATUS(idc_ack_rsp->regcnt_status);
3445 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3449 while (count && !ha->hw.imd_compl) {
3450 qla_mdelay(__func__, 100);
3457 device_printf(dev, "%s: count %d\n", __func__, count);
3463 qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits)
3466 q80_set_port_cfg_t *pcfg;
3467 q80_set_port_cfg_rsp_t *pfg_rsp;
3473 pcfg = (q80_set_port_cfg_t *)ha->hw.mbox;
3474 bzero(pcfg, sizeof(q80_set_port_cfg_t));
3476 pcfg->opcode = Q8_MBX_SET_PORT_CONFIG;
3477 pcfg->count_version = (sizeof (q80_set_port_cfg_t) >> 2);
3478 pcfg->count_version |= Q8_MBX_CMD_VERSION;
3480 pcfg->cfg_bits = cfg_bits;
3482 device_printf(dev, "%s: cfg_bits"
3483 " [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]"
3484 " [0x%x, 0x%x, 0x%x]\n", __func__,
3485 ((cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
3486 ((cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
3487 ((cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0));
3489 ha->hw.imd_compl= 0;
3491 if (qla_mbx_cmd(ha, (uint32_t *)pcfg,
3492 (sizeof (q80_set_port_cfg_t) >> 2),
3493 ha->hw.mbox, (sizeof (q80_set_port_cfg_rsp_t) >> 2), 0)) {
3494 device_printf(dev, "%s: failed\n", __func__);
3498 pfg_rsp = (q80_set_port_cfg_rsp_t *)ha->hw.mbox;
3500 err = Q8_MBX_RSP_STATUS(pfg_rsp->regcnt_status);
3502 if (err == Q8_MBX_RSP_IDC_INTRMD_RSP) {
3503 while (count && !ha->hw.imd_compl) {
3504 qla_mdelay(__func__, 100);
3508 device_printf(dev, "%s: count %d\n", __func__, count);
3515 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3524 qla_get_minidump_tmplt_size(qla_host_t *ha, uint32_t *size)
3527 device_t dev = ha->pci_dev;
3528 q80_config_md_templ_size_t *md_size;
3529 q80_config_md_templ_size_rsp_t *md_size_rsp;
3531 #ifndef QL_LDFLASH_FW
3533 ql_minidump_template_hdr_t *hdr;
3535 hdr = (ql_minidump_template_hdr_t *)ql83xx_minidump;
3536 *size = hdr->size_of_template;
3539 #endif /* #ifdef QL_LDFLASH_FW */
3541 md_size = (q80_config_md_templ_size_t *) ha->hw.mbox;
3542 bzero(md_size, sizeof(q80_config_md_templ_size_t));
3544 md_size->opcode = Q8_MBX_GET_MINIDUMP_TMPLT_SIZE;
3545 md_size->count_version = (sizeof (q80_config_md_templ_size_t) >> 2);
3546 md_size->count_version |= Q8_MBX_CMD_VERSION;
3548 if (qla_mbx_cmd(ha, (uint32_t *) md_size,
3549 (sizeof(q80_config_md_templ_size_t) >> 2), ha->hw.mbox,
3550 (sizeof(q80_config_md_templ_size_rsp_t) >> 2), 0)) {
3552 device_printf(dev, "%s: failed\n", __func__);
3557 md_size_rsp = (q80_config_md_templ_size_rsp_t *) ha->hw.mbox;
3559 err = Q8_MBX_RSP_STATUS(md_size_rsp->regcnt_status);
3562 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3566 *size = md_size_rsp->templ_size;
3572 qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits)
3575 q80_get_port_cfg_t *pcfg;
3576 q80_get_port_cfg_rsp_t *pcfg_rsp;
3581 pcfg = (q80_get_port_cfg_t *)ha->hw.mbox;
3582 bzero(pcfg, sizeof(q80_get_port_cfg_t));
3584 pcfg->opcode = Q8_MBX_GET_PORT_CONFIG;
3585 pcfg->count_version = (sizeof (q80_get_port_cfg_t) >> 2);
3586 pcfg->count_version |= Q8_MBX_CMD_VERSION;
3588 if (qla_mbx_cmd(ha, (uint32_t *)pcfg,
3589 (sizeof (q80_get_port_cfg_t) >> 2),
3590 ha->hw.mbox, (sizeof (q80_get_port_cfg_rsp_t) >> 2), 0)) {
3591 device_printf(dev, "%s: failed\n", __func__);
3595 pcfg_rsp = (q80_get_port_cfg_rsp_t *)ha->hw.mbox;
3597 err = Q8_MBX_RSP_STATUS(pcfg_rsp->regcnt_status);
3600 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3604 device_printf(dev, "%s: [cfg_bits, port type]"
3605 " [0x%08x, 0x%02x] [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]"
3606 " [0x%x, 0x%x, 0x%x]\n", __func__,
3607 pcfg_rsp->cfg_bits, pcfg_rsp->phys_port_type,
3608 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
3609 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
3610 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0)
3613 *cfg_bits = pcfg_rsp->cfg_bits;
3619 ql_iscsi_pdu(qla_host_t *ha, struct mbuf *mp)
3621 struct ether_vlan_header *eh;
3623 struct ip *ip = NULL;
3624 struct ip6_hdr *ip6 = NULL;
3625 struct tcphdr *th = NULL;
3628 uint8_t buf[sizeof(struct ip6_hdr)];
3630 eh = mtod(mp, struct ether_vlan_header *);
3632 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3633 hdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3634 etype = ntohs(eh->evl_proto);
3636 hdrlen = ETHER_HDR_LEN;
3637 etype = ntohs(eh->evl_encap_proto);
3640 if (etype == ETHERTYPE_IP) {
3642 offset = (hdrlen + sizeof (struct ip));
3644 if (mp->m_len >= offset) {
3645 ip = (struct ip *)(mp->m_data + hdrlen);
3647 m_copydata(mp, hdrlen, sizeof (struct ip), buf);
3648 ip = (struct ip *)buf;
3651 if (ip->ip_p == IPPROTO_TCP) {
3653 hdrlen += ip->ip_hl << 2;
3654 offset = hdrlen + 4;
3656 if (mp->m_len >= offset) {
3657 th = (struct tcphdr *)(mp->m_data + hdrlen);;
3659 m_copydata(mp, hdrlen, 4, buf);
3660 th = (struct tcphdr *)buf;
3664 } else if (etype == ETHERTYPE_IPV6) {
3666 offset = (hdrlen + sizeof (struct ip6_hdr));
3668 if (mp->m_len >= offset) {
3669 ip6 = (struct ip6_hdr *)(mp->m_data + hdrlen);
3671 m_copydata(mp, hdrlen, sizeof (struct ip6_hdr), buf);
3672 ip6 = (struct ip6_hdr *)buf;
3675 if (ip6->ip6_nxt == IPPROTO_TCP) {
3677 hdrlen += sizeof(struct ip6_hdr);
3678 offset = hdrlen + 4;
3680 if (mp->m_len >= offset) {
3681 th = (struct tcphdr *)(mp->m_data + hdrlen);;
3683 m_copydata(mp, hdrlen, 4, buf);
3684 th = (struct tcphdr *)buf;
3690 if ((th->th_sport == htons(3260)) ||
3691 (th->th_dport == htons(3260)))
3698 qla_hw_async_event(qla_host_t *ha)
3700 switch (ha->hw.aen_mb0) {
3702 (void)qla_idc_ack(ha, ha->hw.aen_mb1, ha->hw.aen_mb2,
3703 ha->hw.aen_mb3, ha->hw.aen_mb4);
3714 #ifdef QL_LDFLASH_FW
3716 ql_get_minidump_template(qla_host_t *ha)
3719 device_t dev = ha->pci_dev;
3720 q80_config_md_templ_cmd_t *md_templ;
3721 q80_config_md_templ_cmd_rsp_t *md_templ_rsp;
3723 md_templ = (q80_config_md_templ_cmd_t *) ha->hw.mbox;
3724 bzero(md_templ, (sizeof (q80_config_md_templ_cmd_t)));
3726 md_templ->opcode = Q8_MBX_GET_MINIDUMP_TMPLT;
3727 md_templ->count_version = ( sizeof(q80_config_md_templ_cmd_t) >> 2);
3728 md_templ->count_version |= Q8_MBX_CMD_VERSION;
3730 md_templ->buf_addr = ha->hw.dma_buf.minidump.dma_addr;
3731 md_templ->buff_size = ha->hw.dma_buf.minidump.size;
3733 if (qla_mbx_cmd(ha, (uint32_t *) md_templ,
3734 (sizeof(q80_config_md_templ_cmd_t) >> 2),
3736 (sizeof(q80_config_md_templ_cmd_rsp_t) >> 2), 0)) {
3738 device_printf(dev, "%s: failed\n", __func__);
3743 md_templ_rsp = (q80_config_md_templ_cmd_rsp_t *) ha->hw.mbox;
3745 err = Q8_MBX_RSP_STATUS(md_templ_rsp->regcnt_status);
3748 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3755 #endif /* #ifdef QL_LDFLASH_FW */
3758 * Minidump related functionality
3761 static int ql_parse_template(qla_host_t *ha);
3763 static uint32_t ql_rdcrb(qla_host_t *ha,
3764 ql_minidump_entry_rdcrb_t *crb_entry,
3765 uint32_t * data_buff);
3767 static uint32_t ql_pollrd(qla_host_t *ha,
3768 ql_minidump_entry_pollrd_t *entry,
3769 uint32_t * data_buff);
3771 static uint32_t ql_pollrd_modify_write(qla_host_t *ha,
3772 ql_minidump_entry_rd_modify_wr_with_poll_t *entry,
3773 uint32_t *data_buff);
3775 static uint32_t ql_L2Cache(qla_host_t *ha,
3776 ql_minidump_entry_cache_t *cacheEntry,
3777 uint32_t * data_buff);
3779 static uint32_t ql_L1Cache(qla_host_t *ha,
3780 ql_minidump_entry_cache_t *cacheEntry,
3781 uint32_t *data_buff);
3783 static uint32_t ql_rdocm(qla_host_t *ha,
3784 ql_minidump_entry_rdocm_t *ocmEntry,
3785 uint32_t *data_buff);
3787 static uint32_t ql_rdmem(qla_host_t *ha,
3788 ql_minidump_entry_rdmem_t *mem_entry,
3789 uint32_t *data_buff);
3791 static uint32_t ql_rdrom(qla_host_t *ha,
3792 ql_minidump_entry_rdrom_t *romEntry,
3793 uint32_t *data_buff);
3795 static uint32_t ql_rdmux(qla_host_t *ha,
3796 ql_minidump_entry_mux_t *muxEntry,
3797 uint32_t *data_buff);
3799 static uint32_t ql_rdmux2(qla_host_t *ha,
3800 ql_minidump_entry_mux2_t *muxEntry,
3801 uint32_t *data_buff);
3803 static uint32_t ql_rdqueue(qla_host_t *ha,
3804 ql_minidump_entry_queue_t *queueEntry,
3805 uint32_t *data_buff);
3807 static uint32_t ql_cntrl(qla_host_t *ha,
3808 ql_minidump_template_hdr_t *template_hdr,
3809 ql_minidump_entry_cntrl_t *crbEntry);
3813 ql_minidump_size(qla_host_t *ha)
3817 ql_minidump_template_hdr_t *hdr;
3819 hdr = (ql_minidump_template_hdr_t *)ha->hw.dma_buf.minidump.dma_b;
3823 for (k = 1; k < QL_DBG_CAP_SIZE_ARRAY_LEN; k++) {
3824 if (i & ha->hw.mdump_capture_mask)
3825 size += hdr->capture_size_array[k];
3832 ql_free_minidump_buffer(qla_host_t *ha)
3834 if (ha->hw.mdump_buffer != NULL) {
3835 free(ha->hw.mdump_buffer, M_QLA83XXBUF);
3836 ha->hw.mdump_buffer = NULL;
3837 ha->hw.mdump_buffer_size = 0;
3843 ql_alloc_minidump_buffer(qla_host_t *ha)
3845 ha->hw.mdump_buffer_size = ql_minidump_size(ha);
3847 if (!ha->hw.mdump_buffer_size)
3850 ha->hw.mdump_buffer = malloc(ha->hw.mdump_buffer_size, M_QLA83XXBUF,
3853 if (ha->hw.mdump_buffer == NULL)
3860 ql_free_minidump_template_buffer(qla_host_t *ha)
3862 if (ha->hw.mdump_template != NULL) {
3863 free(ha->hw.mdump_template, M_QLA83XXBUF);
3864 ha->hw.mdump_template = NULL;
3865 ha->hw.mdump_template_size = 0;
3871 ql_alloc_minidump_template_buffer(qla_host_t *ha)
3873 ha->hw.mdump_template_size = ha->hw.dma_buf.minidump.size;
3875 ha->hw.mdump_template = malloc(ha->hw.mdump_template_size,
3876 M_QLA83XXBUF, M_NOWAIT);
3878 if (ha->hw.mdump_template == NULL)
3885 ql_alloc_minidump_buffers(qla_host_t *ha)
3889 ret = ql_alloc_minidump_template_buffer(ha);
3894 ret = ql_alloc_minidump_buffer(ha);
3897 ql_free_minidump_template_buffer(ha);
3904 ql_validate_minidump_checksum(qla_host_t *ha)
3908 uint32_t *template_buff;
3910 count = ha->hw.dma_buf.minidump.size / sizeof (uint32_t);
3911 template_buff = ha->hw.dma_buf.minidump.dma_b;
3913 while (count-- > 0) {
3914 sum += *template_buff++;
3918 sum = (sum & 0xFFFFFFFF) + (sum >> 32);
3925 ql_minidump_init(qla_host_t *ha)
3928 uint32_t template_size = 0;
3929 device_t dev = ha->pci_dev;
3932 * Get Minidump Template Size
3934 ret = qla_get_minidump_tmplt_size(ha, &template_size);
3936 if (ret || (template_size == 0)) {
3937 device_printf(dev, "%s: failed [%d, %d]\n", __func__, ret,
3943 * Allocate Memory for Minidump Template
3946 ha->hw.dma_buf.minidump.alignment = 8;
3947 ha->hw.dma_buf.minidump.size = template_size;
3949 #ifdef QL_LDFLASH_FW
3950 if (ql_alloc_dmabuf(ha, &ha->hw.dma_buf.minidump)) {
3952 device_printf(dev, "%s: minidump dma alloc failed\n", __func__);
3956 ha->hw.dma_buf.flags.minidump = 1;
3959 * Retrieve Minidump Template
3961 ret = ql_get_minidump_template(ha);
3963 ha->hw.dma_buf.minidump.dma_b = ql83xx_minidump;
3965 #endif /* #ifdef QL_LDFLASH_FW */
3969 ret = ql_validate_minidump_checksum(ha);
3973 ret = ql_alloc_minidump_buffers(ha);
3976 ha->hw.mdump_init = 1;
3979 "%s: ql_alloc_minidump_buffers"
3980 " failed\n", __func__);
3982 device_printf(dev, "%s: ql_validate_minidump_checksum"
3983 " failed\n", __func__);
3986 device_printf(dev, "%s: ql_get_minidump_template failed\n",
3991 ql_minidump_free(ha);
3997 ql_minidump_free(qla_host_t *ha)
3999 ha->hw.mdump_init = 0;
4000 if (ha->hw.dma_buf.flags.minidump) {
4001 ha->hw.dma_buf.flags.minidump = 0;
4002 ql_free_dmabuf(ha, &ha->hw.dma_buf.minidump);
4005 ql_free_minidump_template_buffer(ha);
4006 ql_free_minidump_buffer(ha);
4012 ql_minidump(qla_host_t *ha)
4014 if (!ha->hw.mdump_init)
4017 if (ha->hw.mdump_done)
4020 ha->hw.mdump_start_seq_index = ql_stop_sequence(ha);
4022 bzero(ha->hw.mdump_buffer, ha->hw.mdump_buffer_size);
4023 bzero(ha->hw.mdump_template, ha->hw.mdump_template_size);
4025 bcopy(ha->hw.dma_buf.minidump.dma_b, ha->hw.mdump_template,
4026 ha->hw.mdump_template_size);
4028 ql_parse_template(ha);
4030 ql_start_sequence(ha, ha->hw.mdump_start_seq_index);
4032 ha->hw.mdump_done = 1;
4042 ql_entry_err_chk(ql_minidump_entry_t *entry, uint32_t esize)
4044 if (esize != entry->hdr.entry_capture_size) {
4045 entry->hdr.entry_capture_size = esize;
4046 entry->hdr.driver_flags |= QL_DBG_SIZE_ERR_FLAG;
4053 ql_parse_template(qla_host_t *ha)
4055 uint32_t num_of_entries, buff_level, e_cnt, esize;
4056 uint32_t end_cnt, rv = 0;
4057 char *dump_buff, *dbuff;
4058 int sane_start = 0, sane_end = 0;
4059 ql_minidump_template_hdr_t *template_hdr;
4060 ql_minidump_entry_t *entry;
4061 uint32_t capture_mask;
4064 /* Setup parameters */
4065 template_hdr = (ql_minidump_template_hdr_t *)ha->hw.mdump_template;
4067 if (template_hdr->entry_type == TLHDR)
4070 dump_buff = (char *) ha->hw.mdump_buffer;
4072 num_of_entries = template_hdr->num_of_entries;
4074 entry = (ql_minidump_entry_t *) ((char *)template_hdr
4075 + template_hdr->first_entry_offset );
4077 template_hdr->saved_state_array[QL_OCM0_ADDR_INDX] =
4078 template_hdr->ocm_window_array[ha->pci_func];
4079 template_hdr->saved_state_array[QL_PCIE_FUNC_INDX] = ha->pci_func;
4081 capture_mask = ha->hw.mdump_capture_mask;
4082 dump_size = ha->hw.mdump_buffer_size;
4084 template_hdr->driver_capture_mask = capture_mask;
4086 QL_DPRINT80(ha, (ha->pci_dev,
4087 "%s: sane_start = %d num_of_entries = %d "
4088 "capture_mask = 0x%x dump_size = %d \n",
4089 __func__, sane_start, num_of_entries, capture_mask, dump_size));
4091 for (buff_level = 0, e_cnt = 0; e_cnt < num_of_entries; e_cnt++) {
4094 * If the capture_mask of the entry does not match capture mask
4095 * skip the entry after marking the driver_flags indicator.
4098 if (!(entry->hdr.entry_capture_mask & capture_mask)) {
4100 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4101 entry = (ql_minidump_entry_t *) ((char *) entry
4102 + entry->hdr.entry_size);
4107 * This is ONLY needed in implementations where
4108 * the capture buffer allocated is too small to capture
4109 * all of the required entries for a given capture mask.
4110 * We need to empty the buffer contents to a file
4111 * if possible, before processing the next entry
4112 * If the buff_full_flag is set, no further capture will happen
4113 * and all remaining non-control entries will be skipped.
4115 if (entry->hdr.entry_capture_size != 0) {
4116 if ((buff_level + entry->hdr.entry_capture_size) >
4118 /* Try to recover by emptying buffer to file */
4119 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4120 entry = (ql_minidump_entry_t *) ((char *) entry
4121 + entry->hdr.entry_size);
4127 * Decode the entry type and process it accordingly
4130 switch (entry->hdr.entry_type) {
4135 if (sane_end == 0) {
4142 dbuff = dump_buff + buff_level;
4143 esize = ql_rdcrb(ha, (void *)entry, (void *)dbuff);
4144 ql_entry_err_chk(entry, esize);
4145 buff_level += esize;
4149 dbuff = dump_buff + buff_level;
4150 esize = ql_pollrd(ha, (void *)entry, (void *)dbuff);
4151 ql_entry_err_chk(entry, esize);
4152 buff_level += esize;
4156 dbuff = dump_buff + buff_level;
4157 esize = ql_pollrd_modify_write(ha, (void *)entry,
4159 ql_entry_err_chk(entry, esize);
4160 buff_level += esize;
4167 dbuff = dump_buff + buff_level;
4168 esize = ql_L2Cache(ha, (void *)entry, (void *)dbuff);
4170 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4172 ql_entry_err_chk(entry, esize);
4173 buff_level += esize;
4179 dbuff = dump_buff + buff_level;
4180 esize = ql_L1Cache(ha, (void *)entry, (void *)dbuff);
4181 ql_entry_err_chk(entry, esize);
4182 buff_level += esize;
4186 dbuff = dump_buff + buff_level;
4187 esize = ql_rdocm(ha, (void *)entry, (void *)dbuff);
4188 ql_entry_err_chk(entry, esize);
4189 buff_level += esize;
4193 dbuff = dump_buff + buff_level;
4194 esize = ql_rdmem(ha, (void *)entry, (void *)dbuff);
4195 ql_entry_err_chk(entry, esize);
4196 buff_level += esize;
4201 dbuff = dump_buff + buff_level;
4202 esize = ql_rdrom(ha, (void *)entry, (void *)dbuff);
4203 ql_entry_err_chk(entry, esize);
4204 buff_level += esize;
4208 dbuff = dump_buff + buff_level;
4209 esize = ql_rdmux(ha, (void *)entry, (void *)dbuff);
4210 ql_entry_err_chk(entry, esize);
4211 buff_level += esize;
4215 dbuff = dump_buff + buff_level;
4216 esize = ql_rdmux2(ha, (void *)entry, (void *)dbuff);
4217 ql_entry_err_chk(entry, esize);
4218 buff_level += esize;
4222 dbuff = dump_buff + buff_level;
4223 esize = ql_rdqueue(ha, (void *)entry, (void *)dbuff);
4224 ql_entry_err_chk(entry, esize);
4225 buff_level += esize;
4229 if ((rv = ql_cntrl(ha, template_hdr, (void *)entry))) {
4230 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4234 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4237 /* next entry in the template */
4238 entry = (ql_minidump_entry_t *) ((char *) entry
4239 + entry->hdr.entry_size);
4242 if (!sane_start || (sane_end > 1)) {
4243 device_printf(ha->pci_dev,
4244 "\n%s: Template configuration error. Check Template\n",
4248 QL_DPRINT80(ha, (ha->pci_dev, "%s: Minidump num of entries = %d\n",
4249 __func__, template_hdr->num_of_entries));
4255 * Read CRB operation.
4258 ql_rdcrb(qla_host_t *ha, ql_minidump_entry_rdcrb_t * crb_entry,
4259 uint32_t * data_buff)
4263 uint32_t op_count, addr, stride, value = 0;
4265 addr = crb_entry->addr;
4266 op_count = crb_entry->op_count;
4267 stride = crb_entry->addr_stride;
4269 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
4271 ret = ql_rdwr_indreg32(ha, addr, &value, 1);
4276 *data_buff++ = addr;
4277 *data_buff++ = value;
4278 addr = addr + stride;
4282 * for testing purpose we return amount of data written
4284 return (op_count * (2 * sizeof(uint32_t)));
4292 ql_L2Cache(qla_host_t *ha, ql_minidump_entry_cache_t *cacheEntry,
4293 uint32_t * data_buff)
4299 uint32_t read_value;
4300 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr, cntl_value_w;
4301 uint32_t tag_value, read_cnt;
4302 volatile uint8_t cntl_value_r;
4306 loop_cnt = cacheEntry->op_count;
4308 read_addr = cacheEntry->read_addr;
4309 cntrl_addr = cacheEntry->control_addr;
4310 cntl_value_w = (uint32_t) cacheEntry->write_value;
4312 tag_reg_addr = cacheEntry->tag_reg_addr;
4314 tag_value = cacheEntry->init_tag_value;
4315 read_cnt = cacheEntry->read_addr_cnt;
4317 for (i = 0; i < loop_cnt; i++) {
4319 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0);
4323 if (cacheEntry->write_value != 0) {
4325 ret = ql_rdwr_indreg32(ha, cntrl_addr,
4331 if (cacheEntry->poll_mask != 0) {
4333 timeout = cacheEntry->poll_wait;
4335 ret = ql_rdwr_indreg32(ha, cntrl_addr, &data, 1);
4339 cntl_value_r = (uint8_t)data;
4341 while ((cntl_value_r & cacheEntry->poll_mask) != 0) {
4344 qla_mdelay(__func__, 1);
4349 ret = ql_rdwr_indreg32(ha, cntrl_addr,
4354 cntl_value_r = (uint8_t)data;
4357 /* Report timeout error.
4358 * core dump capture failed
4359 * Skip remaining entries.
4360 * Write buffer out to file
4361 * Use driver specific fields in template header
4362 * to report this error.
4369 for (k = 0; k < read_cnt; k++) {
4371 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4375 *data_buff++ = read_value;
4376 addr += cacheEntry->read_addr_stride;
4379 tag_value += cacheEntry->tag_value_stride;
4382 return (read_cnt * loop_cnt * sizeof(uint32_t));
4390 ql_L1Cache(qla_host_t *ha,
4391 ql_minidump_entry_cache_t *cacheEntry,
4392 uint32_t *data_buff)
4398 uint32_t read_value;
4399 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr;
4400 uint32_t tag_value, read_cnt;
4401 uint32_t cntl_value_w;
4403 loop_cnt = cacheEntry->op_count;
4405 read_addr = cacheEntry->read_addr;
4406 cntrl_addr = cacheEntry->control_addr;
4407 cntl_value_w = (uint32_t) cacheEntry->write_value;
4409 tag_reg_addr = cacheEntry->tag_reg_addr;
4411 tag_value = cacheEntry->init_tag_value;
4412 read_cnt = cacheEntry->read_addr_cnt;
4414 for (i = 0; i < loop_cnt; i++) {
4416 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0);
4420 ret = ql_rdwr_indreg32(ha, cntrl_addr, &cntl_value_w, 0);
4425 for (k = 0; k < read_cnt; k++) {
4427 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4431 *data_buff++ = read_value;
4432 addr += cacheEntry->read_addr_stride;
4435 tag_value += cacheEntry->tag_value_stride;
4438 return (read_cnt * loop_cnt * sizeof(uint32_t));
4442 * Reading OCM memory
4446 ql_rdocm(qla_host_t *ha,
4447 ql_minidump_entry_rdocm_t *ocmEntry,
4448 uint32_t *data_buff)
4451 volatile uint32_t addr;
4452 volatile uint32_t value;
4454 addr = ocmEntry->read_addr;
4455 loop_cnt = ocmEntry->op_count;
4457 for (i = 0; i < loop_cnt; i++) {
4458 value = READ_REG32(ha, addr);
4459 *data_buff++ = value;
4460 addr += ocmEntry->read_addr_stride;
4462 return (loop_cnt * sizeof(value));
4470 ql_rdmem(qla_host_t *ha,
4471 ql_minidump_entry_rdmem_t *mem_entry,
4472 uint32_t *data_buff)
4476 volatile uint32_t addr;
4477 q80_offchip_mem_val_t val;
4479 addr = mem_entry->read_addr;
4481 /* size in bytes / 16 */
4482 loop_cnt = mem_entry->read_data_size / (sizeof(uint32_t) * 4);
4484 for (i = 0; i < loop_cnt; i++) {
4486 ret = ql_rdwr_offchip_mem(ha, (addr & 0x0ffffffff), &val, 1);
4490 *data_buff++ = val.data_lo;
4491 *data_buff++ = val.data_hi;
4492 *data_buff++ = val.data_ulo;
4493 *data_buff++ = val.data_uhi;
4495 addr += (sizeof(uint32_t) * 4);
4498 return (loop_cnt * (sizeof(uint32_t) * 4));
4506 ql_rdrom(qla_host_t *ha,
4507 ql_minidump_entry_rdrom_t *romEntry,
4508 uint32_t *data_buff)
4515 addr = romEntry->read_addr;
4516 loop_cnt = romEntry->read_data_size; /* This is size in bytes */
4517 loop_cnt /= sizeof(value);
4519 for (i = 0; i < loop_cnt; i++) {
4521 ret = ql_rd_flash32(ha, addr, &value);
4525 *data_buff++ = value;
4526 addr += sizeof(value);
4529 return (loop_cnt * sizeof(value));
4537 ql_rdmux(qla_host_t *ha,
4538 ql_minidump_entry_mux_t *muxEntry,
4539 uint32_t *data_buff)
4543 uint32_t read_value, sel_value;
4544 uint32_t read_addr, select_addr;
4546 select_addr = muxEntry->select_addr;
4547 sel_value = muxEntry->select_value;
4548 read_addr = muxEntry->read_addr;
4550 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) {
4552 ret = ql_rdwr_indreg32(ha, select_addr, &sel_value, 0);
4556 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
4560 *data_buff++ = sel_value;
4561 *data_buff++ = read_value;
4563 sel_value += muxEntry->select_value_stride;
4566 return (loop_cnt * (2 * sizeof(uint32_t)));
4570 ql_rdmux2(qla_host_t *ha,
4571 ql_minidump_entry_mux2_t *muxEntry,
4572 uint32_t *data_buff)
4577 uint32_t select_addr_1, select_addr_2;
4578 uint32_t select_value_1, select_value_2;
4579 uint32_t select_value_count, select_value_mask;
4580 uint32_t read_addr, read_value;
4582 select_addr_1 = muxEntry->select_addr_1;
4583 select_addr_2 = muxEntry->select_addr_2;
4584 select_value_1 = muxEntry->select_value_1;
4585 select_value_2 = muxEntry->select_value_2;
4586 select_value_count = muxEntry->select_value_count;
4587 select_value_mask = muxEntry->select_value_mask;
4589 read_addr = muxEntry->read_addr;
4591 for (loop_cnt = 0; loop_cnt < muxEntry->select_value_count;
4594 uint32_t temp_sel_val;
4596 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_1, 0);
4600 temp_sel_val = select_value_1 & select_value_mask;
4602 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0);
4606 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
4610 *data_buff++ = temp_sel_val;
4611 *data_buff++ = read_value;
4613 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_2, 0);
4617 temp_sel_val = select_value_2 & select_value_mask;
4619 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0);
4623 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
4627 *data_buff++ = temp_sel_val;
4628 *data_buff++ = read_value;
4630 select_value_1 += muxEntry->select_value_stride;
4631 select_value_2 += muxEntry->select_value_stride;
4634 return (loop_cnt * (4 * sizeof(uint32_t)));
4638 * Handling Queue State Reads.
4642 ql_rdqueue(qla_host_t *ha,
4643 ql_minidump_entry_queue_t *queueEntry,
4644 uint32_t *data_buff)
4648 uint32_t read_value;
4649 uint32_t read_addr, read_stride, select_addr;
4650 uint32_t queue_id, read_cnt;
4652 read_cnt = queueEntry->read_addr_cnt;
4653 read_stride = queueEntry->read_addr_stride;
4654 select_addr = queueEntry->select_addr;
4656 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count;
4659 ret = ql_rdwr_indreg32(ha, select_addr, &queue_id, 0);
4663 read_addr = queueEntry->read_addr;
4665 for (k = 0; k < read_cnt; k++) {
4667 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
4671 *data_buff++ = read_value;
4672 read_addr += read_stride;
4675 queue_id += queueEntry->queue_id_stride;
4678 return (loop_cnt * (read_cnt * sizeof(uint32_t)));
4682 * Handling control entries.
4686 ql_cntrl(qla_host_t *ha,
4687 ql_minidump_template_hdr_t *template_hdr,
4688 ql_minidump_entry_cntrl_t *crbEntry)
4692 uint32_t opcode, read_value, addr, entry_addr;
4695 entry_addr = crbEntry->addr;
4697 for (count = 0; count < crbEntry->op_count; count++) {
4698 opcode = crbEntry->opcode;
4700 if (opcode & QL_DBG_OPCODE_WR) {
4702 ret = ql_rdwr_indreg32(ha, entry_addr,
4703 &crbEntry->value_1, 0);
4707 opcode &= ~QL_DBG_OPCODE_WR;
4710 if (opcode & QL_DBG_OPCODE_RW) {
4712 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
4716 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
4720 opcode &= ~QL_DBG_OPCODE_RW;
4723 if (opcode & QL_DBG_OPCODE_AND) {
4725 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
4729 read_value &= crbEntry->value_2;
4730 opcode &= ~QL_DBG_OPCODE_AND;
4732 if (opcode & QL_DBG_OPCODE_OR) {
4733 read_value |= crbEntry->value_3;
4734 opcode &= ~QL_DBG_OPCODE_OR;
4737 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
4742 if (opcode & QL_DBG_OPCODE_OR) {
4744 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
4748 read_value |= crbEntry->value_3;
4750 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
4754 opcode &= ~QL_DBG_OPCODE_OR;
4757 if (opcode & QL_DBG_OPCODE_POLL) {
4759 opcode &= ~QL_DBG_OPCODE_POLL;
4760 timeout = crbEntry->poll_timeout;
4763 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4767 while ((read_value & crbEntry->value_2)
4768 != crbEntry->value_1) {
4771 qla_mdelay(__func__, 1);
4776 ret = ql_rdwr_indreg32(ha, addr,
4784 * Report timeout error.
4785 * core dump capture failed
4786 * Skip remaining entries.
4787 * Write buffer out to file
4788 * Use driver specific fields in template header
4789 * to report this error.
4795 if (opcode & QL_DBG_OPCODE_RDSTATE) {
4797 * decide which address to use.
4799 if (crbEntry->state_index_a) {
4800 addr = template_hdr->saved_state_array[
4801 crbEntry-> state_index_a];
4806 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4810 template_hdr->saved_state_array[crbEntry->state_index_v]
4812 opcode &= ~QL_DBG_OPCODE_RDSTATE;
4815 if (opcode & QL_DBG_OPCODE_WRSTATE) {
4817 * decide which value to use.
4819 if (crbEntry->state_index_v) {
4820 read_value = template_hdr->saved_state_array[
4821 crbEntry->state_index_v];
4823 read_value = crbEntry->value_1;
4826 * decide which address to use.
4828 if (crbEntry->state_index_a) {
4829 addr = template_hdr->saved_state_array[
4830 crbEntry-> state_index_a];
4835 ret = ql_rdwr_indreg32(ha, addr, &read_value, 0);
4839 opcode &= ~QL_DBG_OPCODE_WRSTATE;
4842 if (opcode & QL_DBG_OPCODE_MDSTATE) {
4843 /* Read value from saved state using index */
4844 read_value = template_hdr->saved_state_array[
4845 crbEntry->state_index_v];
4847 read_value <<= crbEntry->shl; /*Shift left operation */
4848 read_value >>= crbEntry->shr; /*Shift right operation */
4850 if (crbEntry->value_2) {
4851 /* check if AND mask is provided */
4852 read_value &= crbEntry->value_2;
4855 read_value |= crbEntry->value_3; /* OR operation */
4856 read_value += crbEntry->value_1; /* increment op */
4858 /* Write value back to state area. */
4860 template_hdr->saved_state_array[crbEntry->state_index_v]
4862 opcode &= ~QL_DBG_OPCODE_MDSTATE;
4865 entry_addr += crbEntry->addr_stride;
4872 * Handling rd poll entry.
4876 ql_pollrd(qla_host_t *ha, ql_minidump_entry_pollrd_t *entry,
4877 uint32_t *data_buff)
4881 uint32_t op_count, select_addr, select_value_stride, select_value;
4882 uint32_t read_addr, poll, mask, data_size, data;
4883 uint32_t wait_count = 0;
4885 select_addr = entry->select_addr;
4886 read_addr = entry->read_addr;
4887 select_value = entry->select_value;
4888 select_value_stride = entry->select_value_stride;
4889 op_count = entry->op_count;
4892 data_size = entry->data_size;
4894 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
4896 ret = ql_rdwr_indreg32(ha, select_addr, &select_value, 0);
4902 while (wait_count < poll) {
4906 ret = ql_rdwr_indreg32(ha, select_addr, &temp, 1);
4910 if ( (temp & mask) != 0 ) {
4916 if (wait_count == poll) {
4917 device_printf(ha->pci_dev,
4918 "%s: Error in processing entry\n", __func__);
4919 device_printf(ha->pci_dev,
4920 "%s: wait_count <0x%x> poll <0x%x>\n",
4921 __func__, wait_count, poll);
4925 ret = ql_rdwr_indreg32(ha, read_addr, &data, 1);
4929 *data_buff++ = select_value;
4930 *data_buff++ = data;
4931 select_value = select_value + select_value_stride;
4935 * for testing purpose we return amount of data written
4937 return (loop_cnt * (2 * sizeof(uint32_t)));
4942 * Handling rd modify write poll entry.
4946 ql_pollrd_modify_write(qla_host_t *ha,
4947 ql_minidump_entry_rd_modify_wr_with_poll_t *entry,
4948 uint32_t *data_buff)
4951 uint32_t addr_1, addr_2, value_1, value_2, data;
4952 uint32_t poll, mask, data_size, modify_mask;
4953 uint32_t wait_count = 0;
4955 addr_1 = entry->addr_1;
4956 addr_2 = entry->addr_2;
4957 value_1 = entry->value_1;
4958 value_2 = entry->value_2;
4962 modify_mask = entry->modify_mask;
4963 data_size = entry->data_size;
4966 ret = ql_rdwr_indreg32(ha, addr_1, &value_1, 0);
4971 while (wait_count < poll) {
4975 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1);
4979 if ( (temp & mask) != 0 ) {
4985 if (wait_count == poll) {
4986 device_printf(ha->pci_dev, "%s Error in processing entry\n",
4990 ret = ql_rdwr_indreg32(ha, addr_2, &data, 1);
4994 data = (data & modify_mask);
4996 ret = ql_rdwr_indreg32(ha, addr_2, &data, 0);
5000 ret = ql_rdwr_indreg32(ha, addr_1, &value_2, 0);
5006 while (wait_count < poll) {
5010 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1);
5014 if ( (temp & mask) != 0 ) {
5019 *data_buff++ = addr_2;
5020 *data_buff++ = data;
5024 * for testing purpose we return amount of data written
5026 return (2 * sizeof(uint32_t));