2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #include "efx_types.h"
41 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
43 (_etp)->et_stat[_stat]++; \
44 _NOTE(CONSTANTCONDITION) \
47 #define EFX_TX_QSTAT_INCR(_etp, _stat)
50 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
52 static __checkReturn int
60 static __checkReturn int
61 falconsiena_tx_qcreate(
63 __in unsigned int index,
64 __in unsigned int label,
65 __in efsys_mem_t *esmp,
71 __out unsigned int *addedp);
74 falconsiena_tx_qdestroy(
77 static __checkReturn int
80 __in_ecount(n) efx_buffer_t *eb,
82 __in unsigned int completed,
83 __inout unsigned int *addedp);
88 __in unsigned int added,
89 __in unsigned int pushed);
91 static __checkReturn int
94 __in unsigned int ns);
96 static __checkReturn int
97 falconsiena_tx_qflush(
101 falconsiena_tx_qenable(
102 __in efx_txq_t *etp);
105 falconsiena_tx_qdesc_post(
107 __in_ecount(n) efx_desc_t *ed,
109 __in unsigned int completed,
110 __inout unsigned int *addedp);
113 falconsiena_tx_qdesc_dma_create(
115 __in efsys_dma_addr_t addr,
118 __out efx_desc_t *edp);
122 falconsiena_tx_qstats_update(
124 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
127 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
131 static efx_tx_ops_t __efx_tx_falcon_ops = {
132 falconsiena_tx_init, /* etxo_init */
133 falconsiena_tx_fini, /* etxo_fini */
134 falconsiena_tx_qcreate, /* etxo_qcreate */
135 falconsiena_tx_qdestroy, /* etxo_qdestroy */
136 falconsiena_tx_qpost, /* etxo_qpost */
137 falconsiena_tx_qpush, /* etxo_qpush */
138 falconsiena_tx_qpace, /* etxo_qpace */
139 falconsiena_tx_qflush, /* etxo_qflush */
140 falconsiena_tx_qenable, /* etxo_qenable */
141 NULL, /* etxo_qpio_enable */
142 NULL, /* etxo_qpio_disable */
143 NULL, /* etxo_qpio_write */
144 NULL, /* etxo_qpio_post */
145 falconsiena_tx_qdesc_post, /* etxo_qdesc_post */
146 falconsiena_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */
147 NULL, /* etxo_qdesc_tso_create */
148 NULL, /* etxo_qdesc_vlantci_create */
150 falconsiena_tx_qstats_update, /* etxo_qstats_update */
153 #endif /* EFSYS_OPT_FALCON */
156 static efx_tx_ops_t __efx_tx_siena_ops = {
157 falconsiena_tx_init, /* etxo_init */
158 falconsiena_tx_fini, /* etxo_fini */
159 falconsiena_tx_qcreate, /* etxo_qcreate */
160 falconsiena_tx_qdestroy, /* etxo_qdestroy */
161 falconsiena_tx_qpost, /* etxo_qpost */
162 falconsiena_tx_qpush, /* etxo_qpush */
163 falconsiena_tx_qpace, /* etxo_qpace */
164 falconsiena_tx_qflush, /* etxo_qflush */
165 falconsiena_tx_qenable, /* etxo_qenable */
166 NULL, /* etxo_qpio_enable */
167 NULL, /* etxo_qpio_disable */
168 NULL, /* etxo_qpio_write */
169 NULL, /* etxo_qpio_post */
170 falconsiena_tx_qdesc_post, /* etxo_qdesc_post */
171 falconsiena_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */
172 NULL, /* etxo_qdesc_tso_create */
173 NULL, /* etxo_qdesc_vlantci_create */
175 falconsiena_tx_qstats_update, /* etxo_qstats_update */
178 #endif /* EFSYS_OPT_SIENA */
180 #if EFSYS_OPT_HUNTINGTON
181 static efx_tx_ops_t __efx_tx_hunt_ops = {
182 hunt_tx_init, /* etxo_init */
183 hunt_tx_fini, /* etxo_fini */
184 hunt_tx_qcreate, /* etxo_qcreate */
185 hunt_tx_qdestroy, /* etxo_qdestroy */
186 hunt_tx_qpost, /* etxo_qpost */
187 hunt_tx_qpush, /* etxo_qpush */
188 hunt_tx_qpace, /* etxo_qpace */
189 hunt_tx_qflush, /* etxo_qflush */
190 hunt_tx_qenable, /* etxo_qenable */
191 hunt_tx_qpio_enable, /* etxo_qpio_enable */
192 hunt_tx_qpio_disable, /* etxo_qpio_disable */
193 hunt_tx_qpio_write, /* etxo_qpio_write */
194 hunt_tx_qpio_post, /* etxo_qpio_post */
195 hunt_tx_qdesc_post, /* etxo_qdesc_post */
196 hunt_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */
197 hunt_tx_qdesc_tso_create, /* etxo_qdesc_tso_create */
198 hunt_tx_qdesc_vlantci_create, /* etxo_qdesc_vlantci_create */
200 hunt_tx_qstats_update, /* etxo_qstats_update */
203 #endif /* EFSYS_OPT_HUNTINGTON */
212 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
213 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
215 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
220 if (enp->en_mod_flags & EFX_MOD_TX) {
225 switch (enp->en_family) {
227 case EFX_FAMILY_FALCON:
228 etxop = (efx_tx_ops_t *)&__efx_tx_falcon_ops;
230 #endif /* EFSYS_OPT_FALCON */
233 case EFX_FAMILY_SIENA:
234 etxop = (efx_tx_ops_t *)&__efx_tx_siena_ops;
236 #endif /* EFSYS_OPT_SIENA */
238 #if EFSYS_OPT_HUNTINGTON
239 case EFX_FAMILY_HUNTINGTON:
240 etxop = (efx_tx_ops_t *)&__efx_tx_hunt_ops;
242 #endif /* EFSYS_OPT_HUNTINGTON */
250 EFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0);
252 if ((rc = etxop->etxo_init(enp)) != 0)
255 enp->en_etxop = etxop;
256 enp->en_mod_flags |= EFX_MOD_TX;
266 EFSYS_PROBE1(fail1, int, rc);
268 enp->en_etxop = NULL;
269 enp->en_mod_flags &= ~EFX_MOD_TX;
277 efx_tx_ops_t *etxop = enp->en_etxop;
279 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
280 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
281 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX);
282 EFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0);
284 etxop->etxo_fini(enp);
286 enp->en_etxop = NULL;
287 enp->en_mod_flags &= ~EFX_MOD_TX;
293 __in unsigned int index,
294 __in unsigned int label,
295 __in efsys_mem_t *esmp,
300 __deref_out efx_txq_t **etpp,
301 __out unsigned int *addedp)
303 efx_tx_ops_t *etxop = enp->en_etxop;
304 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
308 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
309 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX);
311 EFSYS_ASSERT3U(enp->en_tx_qcount + 1, <, encp->enc_txq_limit);
313 /* Allocate an TXQ object */
314 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_txq_t), etp);
321 etp->et_magic = EFX_TXQ_MAGIC;
323 etp->et_index = index;
324 etp->et_mask = n - 1;
327 /* Initial descriptor index may be modified by etxo_qcreate */
330 if ((rc = etxop->etxo_qcreate(enp, index, label, esmp,
331 n, id, flags, eep, etp, addedp)) != 0)
341 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp);
343 EFSYS_PROBE1(fail1, int, rc);
351 efx_nic_t *enp = etp->et_enp;
352 efx_tx_ops_t *etxop = enp->en_etxop;
354 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
356 EFSYS_ASSERT(enp->en_tx_qcount != 0);
359 etxop->etxo_qdestroy(etp);
361 /* Free the TXQ object */
362 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp);
368 __in_ecount(n) efx_buffer_t *eb,
370 __in unsigned int completed,
371 __inout unsigned int *addedp)
373 efx_nic_t *enp = etp->et_enp;
374 efx_tx_ops_t *etxop = enp->en_etxop;
377 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
379 if ((rc = etxop->etxo_qpost(etp, eb,
380 n, completed, addedp)) != 0)
386 EFSYS_PROBE1(fail1, int, rc);
393 __in unsigned int added,
394 __in unsigned int pushed)
396 efx_nic_t *enp = etp->et_enp;
397 efx_tx_ops_t *etxop = enp->en_etxop;
399 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
401 etxop->etxo_qpush(etp, added, pushed);
407 __in unsigned int ns)
409 efx_nic_t *enp = etp->et_enp;
410 efx_tx_ops_t *etxop = enp->en_etxop;
413 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
415 if ((rc = etxop->etxo_qpace(etp, ns)) != 0)
421 EFSYS_PROBE1(fail1, int, rc);
429 efx_nic_t *enp = etp->et_enp;
430 efx_tx_ops_t *etxop = enp->en_etxop;
433 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
435 if ((rc = etxop->etxo_qflush(etp)) != 0)
441 EFSYS_PROBE1(fail1, int, rc);
449 efx_nic_t *enp = etp->et_enp;
450 efx_tx_ops_t *etxop = enp->en_etxop;
452 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
454 etxop->etxo_qenable(etp);
461 efx_nic_t *enp = etp->et_enp;
462 efx_tx_ops_t *etxop = enp->en_etxop;
465 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
467 if (~enp->en_features & EFX_FEATURE_PIO_BUFFERS) {
471 if (etxop->etxo_qpio_enable == NULL) {
475 if ((rc = etxop->etxo_qpio_enable(etp)) != 0)
485 EFSYS_PROBE1(fail1, int, rc);
493 efx_nic_t *enp = etp->et_enp;
494 efx_tx_ops_t *etxop = enp->en_etxop;
496 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
498 if (etxop->etxo_qpio_disable != NULL)
499 etxop->etxo_qpio_disable(etp);
505 __in_ecount(buf_length) uint8_t *buffer,
506 __in size_t buf_length,
507 __in size_t pio_buf_offset)
509 efx_nic_t *enp = etp->et_enp;
510 efx_tx_ops_t *etxop = enp->en_etxop;
513 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
515 if (etxop->etxo_qpio_write != NULL) {
516 if ((rc = etxop->etxo_qpio_write(etp, buffer, buf_length,
517 pio_buf_offset)) != 0)
525 EFSYS_PROBE1(fail1, int, rc);
532 __in size_t pkt_length,
533 __in unsigned int completed,
534 __inout unsigned int *addedp)
536 efx_nic_t *enp = etp->et_enp;
537 efx_tx_ops_t *etxop = enp->en_etxop;
540 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
542 if (etxop->etxo_qpio_post != NULL) {
543 if ((rc = etxop->etxo_qpio_post(etp, pkt_length, completed,
552 EFSYS_PROBE1(fail1, int, rc);
559 __in_ecount(n) efx_desc_t *ed,
561 __in unsigned int completed,
562 __inout unsigned int *addedp)
564 efx_nic_t *enp = etp->et_enp;
565 efx_tx_ops_t *etxop = enp->en_etxop;
568 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
570 if ((rc = etxop->etxo_qdesc_post(etp, ed,
571 n, completed, addedp)) != 0)
577 EFSYS_PROBE1(fail1, int, rc);
582 efx_tx_qdesc_dma_create(
584 __in efsys_dma_addr_t addr,
587 __out efx_desc_t *edp)
589 efx_nic_t *enp = etp->et_enp;
590 efx_tx_ops_t *etxop = enp->en_etxop;
592 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
593 EFSYS_ASSERT(etxop->etxo_qdesc_dma_create != NULL);
595 etxop->etxo_qdesc_dma_create(etp, addr, size, eop, edp);
599 efx_tx_qdesc_tso_create(
601 __in uint16_t ipv4_id,
602 __in uint32_t tcp_seq,
603 __in uint8_t tcp_flags,
604 __out efx_desc_t *edp)
606 efx_nic_t *enp = etp->et_enp;
607 efx_tx_ops_t *etxop = enp->en_etxop;
609 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
610 EFSYS_ASSERT(etxop->etxo_qdesc_tso_create != NULL);
612 etxop->etxo_qdesc_tso_create(etp, ipv4_id, tcp_seq, tcp_flags, edp);
616 efx_tx_qdesc_vlantci_create(
619 __out efx_desc_t *edp)
621 efx_nic_t *enp = etp->et_enp;
622 efx_tx_ops_t *etxop = enp->en_etxop;
624 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
625 EFSYS_ASSERT(etxop->etxo_qdesc_vlantci_create != NULL);
627 etxop->etxo_qdesc_vlantci_create(etp, tci, edp);
633 efx_tx_qstats_update(
635 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
637 efx_nic_t *enp = etp->et_enp;
638 efx_tx_ops_t *etxop = enp->en_etxop;
640 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
642 etxop->etxo_qstats_update(etp, stat);
647 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
649 static __checkReturn int
656 * Disable the timer-based TX DMA backoff and allow TX DMA to be
657 * controlled by the RX FIFO fill level (although always allow a
660 EFX_BAR_READO(enp, FR_AZ_TX_RESERVED_REG, &oword);
661 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_RX_SPACER, 0xfe);
662 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_RX_SPACER_EN, 1);
663 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
664 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PUSH_EN, 0);
665 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DIS_NON_IP_EV, 1);
666 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PREF_THRESHOLD, 2);
667 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
670 * Filter all packets less than 14 bytes to avoid parsing
673 EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
674 EFX_BAR_WRITEO(enp, FR_AZ_TX_RESERVED_REG, &oword);
677 * Do not set TX_NO_EOP_DISC_EN, since it limits packets to 16
678 * descriptors (which is bad).
680 EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword);
681 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
682 EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword);
687 #define EFX_TX_DESC(_etp, _addr, _size, _eop, _added) \
693 id = (_added)++ & (_etp)->et_mask; \
694 offset = id * sizeof (efx_qword_t); \
696 EFSYS_PROBE5(tx_post, unsigned int, (_etp)->et_index, \
697 unsigned int, id, efsys_dma_addr_t, (_addr), \
698 size_t, (_size), boolean_t, (_eop)); \
700 EFX_POPULATE_QWORD_4(qword, \
701 FSF_AZ_TX_KER_CONT, (_eop) ? 0 : 1, \
702 FSF_AZ_TX_KER_BYTE_COUNT, (uint32_t)(_size), \
703 FSF_AZ_TX_KER_BUF_ADDR_DW0, \
704 (uint32_t)((_addr) & 0xffffffff), \
705 FSF_AZ_TX_KER_BUF_ADDR_DW1, \
706 (uint32_t)((_addr) >> 32)); \
707 EFSYS_MEM_WRITEQ((_etp)->et_esmp, offset, &qword); \
709 _NOTE(CONSTANTCONDITION) \
712 static __checkReturn int
713 falconsiena_tx_qpost(
715 __in_ecount(n) efx_buffer_t *eb,
717 __in unsigned int completed,
718 __inout unsigned int *addedp)
720 unsigned int added = *addedp;
724 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1))
727 for (i = 0; i < n; i++) {
728 efx_buffer_t *ebp = &eb[i];
729 efsys_dma_addr_t start = ebp->eb_addr;
730 size_t size = ebp->eb_size;
731 efsys_dma_addr_t end = start + size;
733 /* Fragments must not span 4k boundaries. */
734 EFSYS_ASSERT(P2ROUNDUP(start + 1, 4096) >= end);
736 EFX_TX_DESC(etp, start, size, ebp->eb_eop, added);
739 EFX_TX_QSTAT_INCR(etp, TX_POST);
745 EFSYS_PROBE1(fail1, int, rc);
751 falconsiena_tx_qpush(
753 __in unsigned int added,
754 __in unsigned int pushed)
756 efx_nic_t *enp = etp->et_enp;
761 /* Push the populated descriptors out */
762 wptr = added & etp->et_mask;
764 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DESC_WPTR, wptr);
766 /* Only write the third DWORD */
767 EFX_POPULATE_DWORD_1(dword,
768 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
770 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
771 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
772 wptr, pushed & etp->et_mask);
773 EFSYS_PIO_WRITE_BARRIER();
774 EFX_BAR_TBL_WRITED3(enp, FR_BZ_TX_DESC_UPD_REGP0,
775 etp->et_index, &dword, B_FALSE);
778 #define EFX_MAX_PACE_VALUE 20
779 #define EFX_TX_PACE_CLOCK_BASE 104
781 static __checkReturn int
782 falconsiena_tx_qpace(
784 __in unsigned int ns)
786 efx_nic_t *enp = etp->et_enp;
787 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
789 unsigned int pace_val;
790 unsigned int timer_period;
797 * The pace_val to write into the table is s.t
798 * ns <= timer_period * (2 ^ pace_val)
800 timer_period = EFX_TX_PACE_CLOCK_BASE / encp->enc_clk_mult;
801 for (pace_val = 1; pace_val <= EFX_MAX_PACE_VALUE; pace_val++) {
802 if ((timer_period << pace_val) >= ns)
806 if (pace_val > EFX_MAX_PACE_VALUE) {
811 /* Update the pacing table */
812 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_PACE, pace_val);
813 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_PACE_TBL, etp->et_index,
819 EFSYS_PROBE1(fail1, int, rc);
824 static __checkReturn int
825 falconsiena_tx_qflush(
828 efx_nic_t *enp = etp->et_enp;
832 efx_tx_qpace(etp, 0);
834 label = etp->et_index;
836 /* Flush the queue */
837 EFX_POPULATE_OWORD_2(oword, FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
838 FRF_AZ_TX_FLUSH_DESCQ, label);
839 EFX_BAR_WRITEO(enp, FR_AZ_TX_FLUSH_DESCQ_REG, &oword);
845 falconsiena_tx_qenable(
848 efx_nic_t *enp = etp->et_enp;
851 EFX_BAR_TBL_READO(enp, FR_AZ_TX_DESC_PTR_TBL,
852 etp->et_index, &oword, B_TRUE);
854 EFSYS_PROBE5(tx_descq_ptr, unsigned int, etp->et_index,
855 uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_3),
856 uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_2),
857 uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_1),
858 uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_0));
860 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DC_HW_RPTR, 0);
861 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DESCQ_HW_RPTR, 0);
862 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DESCQ_EN, 1);
864 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL,
865 etp->et_index, &oword, B_TRUE);
868 static __checkReturn int
869 falconsiena_tx_qcreate(
871 __in unsigned int index,
872 __in unsigned int label,
873 __in efsys_mem_t *esmp,
879 __out unsigned int *addedp)
881 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
886 EFX_STATIC_ASSERT(EFX_EV_TX_NLABELS ==
887 (1 << FRF_AZ_TX_DESCQ_LABEL_WIDTH));
888 EFSYS_ASSERT3U(label, <, EFX_EV_TX_NLABELS);
890 EFSYS_ASSERT(ISP2(EFX_TXQ_MAXNDESCS(encp)));
891 EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS));
893 if (!ISP2(n) || (n < EFX_TXQ_MINNDESCS) || (n > EFX_EVQ_MAXNEVS)) {
897 if (index >= encp->enc_txq_limit) {
902 (1 << size) <= (EFX_TXQ_MAXNDESCS(encp) / EFX_TXQ_MINNDESCS);
904 if ((1 << size) == (int)(n / EFX_TXQ_MINNDESCS))
906 if (id + (1 << size) >= encp->enc_buftbl_limit) {
911 /* Set up the new descriptor queue */
912 EFX_POPULATE_OWORD_6(oword,
913 FRF_AZ_TX_DESCQ_BUF_BASE_ID, id,
914 FRF_AZ_TX_DESCQ_EVQ_ID, eep->ee_index,
915 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
916 FRF_AZ_TX_DESCQ_LABEL, label,
917 FRF_AZ_TX_DESCQ_SIZE, size,
918 FRF_AZ_TX_DESCQ_TYPE, 0);
920 EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_NON_IP_DROP_DIS, 1);
921 EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_IP_CHKSM_DIS,
922 (flags & EFX_CKSUM_IPV4) ? 0 : 1);
923 EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_TCP_CHKSM_DIS,
924 (flags & EFX_CKSUM_TCPUDP) ? 0 : 1);
926 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL,
927 etp->et_index, &oword, B_TRUE);
936 EFSYS_PROBE1(fail1, int, rc);
942 falconsiena_tx_qdesc_post(
944 __in_ecount(n) efx_desc_t *ed,
946 __in unsigned int completed,
947 __inout unsigned int *addedp)
949 unsigned int added = *addedp;
953 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
958 for (i = 0; i < n; i++) {
959 efx_desc_t *edp = &ed[i];
963 id = added++ & etp->et_mask;
964 offset = id * sizeof (efx_desc_t);
966 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
969 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
970 unsigned int, added, unsigned int, n);
972 EFX_TX_QSTAT_INCR(etp, TX_POST);
978 EFSYS_PROBE1(fail1, int, rc);
983 falconsiena_tx_qdesc_dma_create(
985 __in efsys_dma_addr_t addr,
988 __out efx_desc_t *edp)
990 /* Fragments must not span 4k boundaries. */
991 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
993 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
994 efsys_dma_addr_t, addr,
995 size_t, size, boolean_t, eop);
997 EFX_POPULATE_QWORD_4(edp->ed_eq,
998 FSF_AZ_TX_KER_CONT, eop ? 0 : 1,
999 FSF_AZ_TX_KER_BYTE_COUNT, (uint32_t)size,
1000 FSF_AZ_TX_KER_BUF_ADDR_DW0,
1001 (uint32_t)(addr & 0xffffffff),
1002 FSF_AZ_TX_KER_BUF_ADDR_DW1,
1003 (uint32_t)(addr >> 32));
1006 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
1008 #if EFSYS_OPT_QSTATS
1010 /* START MKCONFIG GENERATED EfxTransmitQueueStatNamesBlock 9d8d26a0a5e2c453 */
1011 static const char *__efx_tx_qstat_name[] = {
1015 /* END MKCONFIG GENERATED EfxTransmitQueueStatNamesBlock */
1019 __in efx_nic_t *enp,
1020 __in unsigned int id)
1022 _NOTE(ARGUNUSED(enp))
1023 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1024 EFSYS_ASSERT3U(id, <, TX_NQSTATS);
1026 return (__efx_tx_qstat_name[id]);
1028 #endif /* EFSYS_OPT_NAMES */
1029 #endif /* EFSYS_OPT_QSTATS */
1031 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
1033 #if EFSYS_OPT_QSTATS
1035 falconsiena_tx_qstats_update(
1036 __in efx_txq_t *etp,
1037 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
1041 for (id = 0; id < TX_NQSTATS; id++) {
1042 efsys_stat_t *essp = &stat[id];
1044 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
1045 etp->et_stat[id] = 0;
1048 #endif /* EFSYS_OPT_QSTATS */
1051 falconsiena_tx_qdestroy(
1052 __in efx_txq_t *etp)
1054 efx_nic_t *enp = etp->et_enp;
1057 /* Purge descriptor queue */
1058 EFX_ZERO_OWORD(oword);
1060 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL,
1061 etp->et_index, &oword, B_TRUE);
1065 falconsiena_tx_fini(
1066 __in efx_nic_t *enp)
1068 _NOTE(ARGUNUSED(enp))
1071 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */