sys/dev/ti/if_ti.c

   1 /*-
   2  * Copyright (c) 1997, 1998, 1999
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
  35  * Manuals, sample driver and firmware source kits are available
  36  * from http://www.alteon.com/support/openkits.
  37  *
  38  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  39  * Electrical Engineering Department
  40  * Columbia University, New York City
  41  */
  42
  43 /*
  44  * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
  45  * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
  46  * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
  47  * Tigon supports hardware IP, TCP and UCP checksumming, multicast
  48  * filtering and jumbo (9014 byte) frames. The hardware is largely
  49  * controlled by firmware, which must be loaded into the NIC during
  50  * initialization.
  51  *
  52  * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
  53  * revision, which supports new features such as extended commands,
  54  * extended jumbo receive ring desciptors and a mini receive ring.
  55  *
  56  * Alteon Networks is to be commended for releasing such a vast amount
  57  * of development material for the Tigon NIC without requiring an NDA
  58  * (although they really should have done it a long time ago). With
  59  * any luck, the other vendors will finally wise up and follow Alteon's
  60  * stellar example.
  61  *
  62  * The firmware for the Tigon 1 and 2 NICs is compiled directly into
  63  * this driver by #including it as a C header file. This bloats the
  64  * driver somewhat, but it's the easiest method considering that the
  65  * driver code and firmware code need to be kept in sync. The source
  66  * for the firmware is not provided with the FreeBSD distribution since
  67  * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
  68  *
  69  * The following people deserve special thanks:
  70  * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
  71  *   for testing
  72  * - Raymond Lee of Netgear, for providing a pair of Netgear
  73  *   GA620 Tigon 2 boards for testing
  74  * - Ulf Zimmermann, for bringing the GA260 to my attention and
  75  *   convincing me to write this driver.
  76  * - Andrew Gallatin for providing FreeBSD/Alpha support.
  77  */
  78
  79 #include <sys/cdefs.h>
  80 __FBSDID("$FreeBSD$");
  81
  82 #include "opt_ti.h"
  83
  84 #include <sys/param.h>
  85 #include <sys/systm.h>
  86 #include <sys/sockio.h>
  87 #include <sys/mbuf.h>
  88 #include <sys/malloc.h>
  89 #include <sys/kernel.h>
  90 #include <sys/module.h>
  91 #include <sys/socket.h>
  92 #include <sys/queue.h>
  93 #include <sys/conf.h>
  94 #include <sys/sf_buf.h>
  95
  96 #include <net/if.h>
  97 #include <net/if_arp.h>
  98 #include <net/ethernet.h>
  99 #include <net/if_dl.h>
 100 #include <net/if_media.h>
 101 #include <net/if_types.h>
 102 #include <net/if_vlan_var.h>
 103
 104 #include <net/bpf.h>
 105
 106 #include <netinet/in_systm.h>
 107 #include <netinet/in.h>
 108 #include <netinet/ip.h>
 109
 110 #include <machine/bus.h>
 111 #include <machine/resource.h>
 112 #include <sys/bus.h>
 113 #include <sys/rman.h>
 114
 115 /* #define TI_PRIVATE_JUMBOS */
 116 #ifndef TI_PRIVATE_JUMBOS
 117 #include <vm/vm.h>
 118 #include <vm/vm_page.h>
 119 #endif
 120
 121 #include <dev/pci/pcireg.h>
 122 #include <dev/pci/pcivar.h>
 123
 124 #include <sys/tiio.h>
 125 #include <dev/ti/if_tireg.h>
 126 #include <dev/ti/ti_fw.h>
 127 #include <dev/ti/ti_fw2.h>
 128
 129 #define TI_CSUM_FEATURES        (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
 130 /*
 131  * We can only turn on header splitting if we're using extended receive
 132  * BDs.
 133  */
 134 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
 135 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
 136 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
 137
 138 typedef enum {
 139         TI_SWAP_HTON,
 140         TI_SWAP_NTOH
 141 } ti_swap_type;
 142
 143
 144 /*
 145  * Various supported device vendors/types and their names.
 146  */
 147
 148 static const struct ti_type const ti_devs[] = {
 149         { ALT_VENDORID, ALT_DEVICEID_ACENIC,
 150                 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
 151         { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
 152                 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
 153         { TC_VENDORID,  TC_DEVICEID_3C985,
 154                 "3Com 3c985-SX Gigabit Ethernet" },
 155         { NG_VENDORID, NG_DEVICEID_GA620,
 156                 "Netgear GA620 1000baseSX Gigabit Ethernet" },
 157         { NG_VENDORID, NG_DEVICEID_GA620T,
 158                 "Netgear GA620 1000baseT Gigabit Ethernet" },
 159         { SGI_VENDORID, SGI_DEVICEID_TIGON,
 160                 "Silicon Graphics Gigabit Ethernet" },
 161         { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
 162                 "Farallon PN9000SX Gigabit Ethernet" },
 163         { 0, 0, NULL }
 164 };
 165
 166
 167 static  d_open_t        ti_open;
 168 static  d_close_t       ti_close;
 169 static  d_ioctl_t       ti_ioctl2;
 170
 171 static struct cdevsw ti_cdevsw = {
 172         .d_version =    D_VERSION,
 173         .d_flags =      0,
 174         .d_open =       ti_open,
 175         .d_close =      ti_close,
 176         .d_ioctl =      ti_ioctl2,
 177         .d_name =       "ti",
 178 };
 179
 180 static int ti_probe(device_t);
 181 static int ti_attach(device_t);
 182 static int ti_detach(device_t);
 183 static void ti_txeof(struct ti_softc *);
 184 static void ti_rxeof(struct ti_softc *);
 185
 186 static void ti_stats_update(struct ti_softc *);
 187 static int ti_encap(struct ti_softc *, struct mbuf **);
 188
 189 static void ti_intr(void *);
 190 static void ti_start(struct ifnet *);
 191 static void ti_start_locked(struct ifnet *);
 192 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
 193 static void ti_init(void *);
 194 static void ti_init_locked(void *);
 195 static void ti_init2(struct ti_softc *);
 196 static void ti_stop(struct ti_softc *);
 197 static void ti_watchdog(void *);
 198 static int ti_shutdown(device_t);
 199 static int ti_ifmedia_upd(struct ifnet *);
 200 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 201
 202 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
 203 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
 204 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
 205
 206 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
 207 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
 208 static void ti_setmulti(struct ti_softc *);
 209
 210 static void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *);
 211 static void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, void *);
 212 static void ti_mem_zero(struct ti_softc *, u_int32_t, u_int32_t);
 213 static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int);
 214 static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t,
 215                 int, int, int);
 216 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
 217 static void ti_loadfw(struct ti_softc *);
 218 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
 219 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
 220 static void ti_handle_events(struct ti_softc *);
 221 static int ti_alloc_dmamaps(struct ti_softc *);
 222 static void ti_free_dmamaps(struct ti_softc *);
 223 static int ti_alloc_jumbo_mem(struct ti_softc *);
 224 #ifdef TI_PRIVATE_JUMBOS
 225 static void *ti_jalloc(struct ti_softc *);
 226 static void ti_jfree(void *, void *);
 227 #endif /* TI_PRIVATE_JUMBOS */
 228 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
 229 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
 230 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
 231 static int ti_init_rx_ring_std(struct ti_softc *);
 232 static void ti_free_rx_ring_std(struct ti_softc *);
 233 static int ti_init_rx_ring_jumbo(struct ti_softc *);
 234 static void ti_free_rx_ring_jumbo(struct ti_softc *);
 235 static int ti_init_rx_ring_mini(struct ti_softc *);
 236 static void ti_free_rx_ring_mini(struct ti_softc *);
 237 static void ti_free_tx_ring(struct ti_softc *);
 238 static int ti_init_tx_ring(struct ti_softc *);
 239
 240 static int ti_64bitslot_war(struct ti_softc *);
 241 static int ti_chipinit(struct ti_softc *);
 242 static int ti_gibinit(struct ti_softc *);
 243
 244 #ifdef TI_JUMBO_HDRSPLIT
 245 static __inline void ti_hdr_split       (struct mbuf *top, int hdr_len,
 246                                              int pkt_len, int idx);
 247 #endif /* TI_JUMBO_HDRSPLIT */
 248
 249 static device_method_t ti_methods[] = {
 250         /* Device interface */
 251         DEVMETHOD(device_probe,         ti_probe),
 252         DEVMETHOD(device_attach,        ti_attach),
 253         DEVMETHOD(device_detach,        ti_detach),
 254         DEVMETHOD(device_shutdown,      ti_shutdown),
 255         { 0, 0 }
 256 };
 257
 258 static driver_t ti_driver = {
 259         "ti",
 260         ti_methods,
 261         sizeof(struct ti_softc)
 262 };
 263
 264 static devclass_t ti_devclass;
 265
 266 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
 267 MODULE_DEPEND(ti, pci, 1, 1, 1);
 268 MODULE_DEPEND(ti, ether, 1, 1, 1);
 269
 270 /*
 271  * Send an instruction or address to the EEPROM, check for ACK.
 272  */
 273 static u_int32_t ti_eeprom_putbyte(sc, byte)
 274         struct ti_softc         *sc;
 275         int                     byte;
 276 {
 277         int                     i, ack = 0;
 278
 279         /*
 280          * Make sure we're in TX mode.
 281          */
 282         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
 283
 284         /*
 285          * Feed in each bit and stobe the clock.
 286          */
 287         for (i = 0x80; i; i >>= 1) {
 288                 if (byte & i) {
 289                         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
 290                 } else {
 291                         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
 292                 }
 293                 DELAY(1);
 294                 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 295                 DELAY(1);
 296                 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 297         }
 298
 299         /*
 300          * Turn off TX mode.
 301          */
 302         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
 303
 304         /*
 305          * Check for ack.
 306          */
 307         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 308         ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
 309         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 310
 311         return (ack);
 312 }
 313
 314 /*
 315  * Read a byte of data stored in the EEPROM at address 'addr.'
 316  * We have to send two address bytes since the EEPROM can hold
 317  * more than 256 bytes of data.
 318  */
 319 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
 320         struct ti_softc         *sc;
 321         int                     addr;
 322         u_int8_t                *dest;
 323 {
 324         int                     i;
 325         u_int8_t                byte = 0;
 326
 327         EEPROM_START;
 328
 329         /*
 330          * Send write control code to EEPROM.
 331          */
 332         if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
 333                 device_printf(sc->ti_dev,
 334                     "failed to send write command, status: %x\n",
 335                     CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
 336                 return (1);
 337         }
 338
 339         /*
 340          * Send first byte of address of byte we want to read.
 341          */
 342         if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
 343                 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
 344                     CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
 345                 return (1);
 346         }
 347         /*
 348          * Send second byte address of byte we want to read.
 349          */
 350         if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
 351                 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
 352                     CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
 353                 return (1);
 354         }
 355
 356         EEPROM_STOP;
 357         EEPROM_START;
 358         /*
 359          * Send read control code to EEPROM.
 360          */
 361         if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
 362                 device_printf(sc->ti_dev,
 363                     "failed to send read command, status: %x\n",
 364                     CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
 365                 return (1);
 366         }
 367
 368         /*
 369          * Start reading bits from EEPROM.
 370          */
 371         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
 372         for (i = 0x80; i; i >>= 1) {
 373                 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 374                 DELAY(1);
 375                 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
 376                         byte |= i;
 377                 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 378                 DELAY(1);
 379         }
 380
 381         EEPROM_STOP;
 382
 383         /*
 384          * No ACK generated for read, so just return byte.
 385          */
 386
 387         *dest = byte;
 388
 389         return (0);
 390 }
 391
 392 /*
 393  * Read a sequence of bytes from the EEPROM.
 394  */
 395 static int
 396 ti_read_eeprom(sc, dest, off, cnt)
 397         struct ti_softc         *sc;
 398         caddr_t                 dest;
 399         int                     off;
 400         int                     cnt;
 401 {
 402         int                     err = 0, i;
 403         u_int8_t                byte = 0;
 404
 405         for (i = 0; i < cnt; i++) {
 406                 err = ti_eeprom_getbyte(sc, off + i, &byte);
 407                 if (err)
 408                         break;
 409                 *(dest + i) = byte;
 410         }
 411
 412         return (err ? 1 : 0);
 413 }
 414
 415 /*
 416  * NIC memory read function.
 417  * Can be used to copy data from NIC local memory.
 418  */
 419 static void
 420 ti_mem_read(sc, addr, len, buf)
 421         struct ti_softc         *sc;
 422         u_int32_t               addr, len;
 423         void                    *buf;
 424 {
 425         int                     segptr, segsize, cnt;
 426         char                    *ptr;
 427
 428         segptr = addr;
 429         cnt = len;
 430         ptr = buf;
 431
 432         while (cnt) {
 433                 if (cnt < TI_WINLEN)
 434                         segsize = cnt;
 435                 else
 436                         segsize = TI_WINLEN - (segptr % TI_WINLEN);
 437                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
 438                 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
 439                     TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr,
 440                     segsize / 4);
 441                 ptr += segsize;
 442                 segptr += segsize;
 443                 cnt -= segsize;
 444         }
 445 }
 446
 447
 448 /*
 449  * NIC memory write function.
 450  * Can be used to copy data into NIC local memory.
 451  */
 452 static void
 453 ti_mem_write(sc, addr, len, buf)
 454         struct ti_softc         *sc;
 455         u_int32_t               addr, len;
 456         void                    *buf;
 457 {
 458         int                     segptr, segsize, cnt;
 459         char                    *ptr;
 460
 461         segptr = addr;
 462         cnt = len;
 463         ptr = buf;
 464
 465         while (cnt) {
 466                 if (cnt < TI_WINLEN)
 467                         segsize = cnt;
 468                 else
 469                         segsize = TI_WINLEN - (segptr % TI_WINLEN);
 470                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
 471                 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
 472                     TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr,
 473                     segsize / 4);
 474                 ptr += segsize;
 475                 segptr += segsize;
 476                 cnt -= segsize;
 477         }
 478 }
 479
 480 /*
 481  * NIC memory read function.
 482  * Can be used to clear a section of NIC local memory.
 483  */
 484 static void
 485 ti_mem_zero(sc, addr, len)
 486         struct ti_softc         *sc;
 487         u_int32_t               addr, len;
 488 {
 489         int                     segptr, segsize, cnt;
 490
 491         segptr = addr;
 492         cnt = len;
 493
 494         while (cnt) {
 495                 if (cnt < TI_WINLEN)
 496                         segsize = cnt;
 497                 else
 498                         segsize = TI_WINLEN - (segptr % TI_WINLEN);
 499                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
 500                 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
 501                     TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
 502                 segptr += segsize;
 503                 cnt -= segsize;
 504         }
 505 }
 506
 507 static int
 508 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata)
 509         struct ti_softc         *sc;
 510         u_int32_t               tigon_addr, len;
 511         caddr_t                 buf;
 512         int                     useraddr, readdata;
 513 {
 514         int             segptr, segsize, cnt;
 515         caddr_t         ptr;
 516         u_int32_t       origwin;
 517         u_int8_t        tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
 518         int             resid, segresid;
 519         int             first_pass;
 520
 521         TI_LOCK_ASSERT(sc);
 522
 523         /*
 524          * At the moment, we don't handle non-aligned cases, we just bail.
 525          * If this proves to be a problem, it will be fixed.
 526          */
 527         if ((readdata == 0)
 528          && (tigon_addr & 0x3)) {
 529                 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
 530                     "word-aligned\n", __func__, tigon_addr);
 531                 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
 532                     "yet supported\n", __func__);
 533                 return (EINVAL);
 534         }
 535
 536         segptr = tigon_addr & ~0x3;
 537         segresid = tigon_addr - segptr;
 538
 539         /*
 540          * This is the non-aligned amount left over that we'll need to
 541          * copy.
 542          */
 543         resid = len & 0x3;
 544
 545         /* Add in the left over amount at the front of the buffer */
 546         resid += segresid;
 547
 548         cnt = len & ~0x3;
 549         /*
 550          * If resid + segresid is >= 4, add multiples of 4 to the count and
 551          * decrease the residual by that much.
 552          */
 553         cnt += resid & ~0x3;
 554         resid -= resid & ~0x3;
 555
 556         ptr = buf;
 557
 558         first_pass = 1;
 559
 560         /*
 561          * Save the old window base value.
 562          */
 563         origwin = CSR_READ_4(sc, TI_WINBASE);
 564
 565         while (cnt) {
 566                 bus_size_t ti_offset;
 567
 568                 if (cnt < TI_WINLEN)
 569                         segsize = cnt;
 570                 else
 571                         segsize = TI_WINLEN - (segptr % TI_WINLEN);
 572                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
 573
 574                 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
 575
 576                 if (readdata) {
 577
 578                         bus_space_read_region_4(sc->ti_btag,
 579                                                 sc->ti_bhandle, ti_offset,
 580                                                 (u_int32_t *)tmparray,
 581                                                 segsize >> 2);
 582                         if (useraddr) {
 583                                 /*
 584                                  * Yeah, this is a little on the kludgy
 585                                  * side, but at least this code is only
 586                                  * used for debugging.
 587                                  */
 588                                 ti_bcopy_swap(tmparray, tmparray2, segsize,
 589                                               TI_SWAP_NTOH);
 590
 591                                 TI_UNLOCK(sc);
 592                                 if (first_pass) {
 593                                         copyout(&tmparray2[segresid], ptr,
 594                                                 segsize - segresid);
 595                                         first_pass = 0;
 596                                 } else
 597                                         copyout(tmparray2, ptr, segsize);
 598                                 TI_LOCK(sc);
 599                         } else {
 600                                 if (first_pass) {
 601
 602                                         ti_bcopy_swap(tmparray, tmparray2,
 603                                                       segsize, TI_SWAP_NTOH);
 604                                         TI_UNLOCK(sc);
 605                                         bcopy(&tmparray2[segresid], ptr,
 606                                               segsize - segresid);
 607                                         TI_LOCK(sc);
 608                                         first_pass = 0;
 609                                 } else
 610                                         ti_bcopy_swap(tmparray, ptr, segsize,
 611                                                       TI_SWAP_NTOH);
 612                         }
 613
 614                 } else {
 615                         if (useraddr) {
 616                                 TI_UNLOCK(sc);
 617                                 copyin(ptr, tmparray2, segsize);
 618                                 TI_LOCK(sc);
 619                                 ti_bcopy_swap(tmparray2, tmparray, segsize,
 620                                               TI_SWAP_HTON);
 621                         } else
 622                                 ti_bcopy_swap(ptr, tmparray, segsize,
 623                                               TI_SWAP_HTON);
 624
 625                         bus_space_write_region_4(sc->ti_btag,
 626                                                  sc->ti_bhandle, ti_offset,
 627                                                  (u_int32_t *)tmparray,
 628                                                  segsize >> 2);
 629                 }
 630                 segptr += segsize;
 631                 ptr += segsize;
 632                 cnt -= segsize;
 633         }
 634
 635         /*
 636          * Handle leftover, non-word-aligned bytes.
 637          */
 638         if (resid != 0) {
 639                 u_int32_t       tmpval, tmpval2;
 640                 bus_size_t      ti_offset;
 641
 642                 /*
 643                  * Set the segment pointer.
 644                  */
 645                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
 646
 647                 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
 648
 649                 /*
 650                  * First, grab whatever is in our source/destination.
 651                  * We'll obviously need this for reads, but also for
 652                  * writes, since we'll be doing read/modify/write.
 653                  */
 654                 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
 655                                         ti_offset, &tmpval, 1);
 656
 657                 /*
 658                  * Next, translate this from little-endian to big-endian
 659                  * (at least on i386 boxes).
 660                  */
 661                 tmpval2 = ntohl(tmpval);
 662
 663                 if (readdata) {
 664                         /*
 665                          * If we're reading, just copy the leftover number
 666                          * of bytes from the host byte order buffer to
 667                          * the user's buffer.
 668                          */
 669                         if (useraddr) {
 670                                 TI_UNLOCK(sc);
 671                                 copyout(&tmpval2, ptr, resid);
 672                                 TI_LOCK(sc);
 673                         } else
 674                                 bcopy(&tmpval2, ptr, resid);
 675                 } else {
 676                         /*
 677                          * If we're writing, first copy the bytes to be
 678                          * written into the network byte order buffer,
 679                          * leaving the rest of the buffer with whatever was
 680                          * originally in there.  Then, swap the bytes
 681                          * around into host order and write them out.
 682                          *
 683                          * XXX KDM the read side of this has been verified
 684                          * to work, but the write side of it has not been
 685                          * verified.  So user beware.
 686                          */
 687                         if (useraddr) {
 688                                 TI_UNLOCK(sc);
 689                                 copyin(ptr, &tmpval2, resid);
 690                                 TI_LOCK(sc);
 691                         } else
 692                                 bcopy(ptr, &tmpval2, resid);
 693
 694                         tmpval = htonl(tmpval2);
 695
 696                         bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
 697                                                  ti_offset, &tmpval, 1);
 698                 }
 699         }
 700
 701         CSR_WRITE_4(sc, TI_WINBASE, origwin);
 702
 703         return (0);
 704 }
 705
 706 static int
 707 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu)
 708         struct ti_softc         *sc;
 709         u_int32_t               tigon_addr, len;
 710         caddr_t                 buf;
 711         int                     useraddr, readdata;
 712         int                     cpu;
 713 {
 714         u_int32_t       segptr;
 715         int             cnt;
 716         u_int32_t       tmpval, tmpval2;
 717         caddr_t         ptr;
 718
 719         TI_LOCK_ASSERT(sc);
 720
 721         /*
 722          * At the moment, we don't handle non-aligned cases, we just bail.
 723          * If this proves to be a problem, it will be fixed.
 724          */
 725         if (tigon_addr & 0x3) {
 726                 device_printf(sc->ti_dev, "%s: tigon address %#x "
 727                     "isn't word-aligned\n", __func__, tigon_addr);
 728                 return (EINVAL);
 729         }
 730
 731         if (len & 0x3) {
 732                 device_printf(sc->ti_dev, "%s: transfer length %d "
 733                     "isn't word-aligned\n", __func__, len);
 734                 return (EINVAL);
 735         }
 736
 737         segptr = tigon_addr;
 738         cnt = len;
 739         ptr = buf;
 740
 741         while (cnt) {
 742                 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
 743
 744                 if (readdata) {
 745                         tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
 746
 747                         tmpval = ntohl(tmpval2);
 748
 749                         /*
 750                          * Note:  I've used this debugging interface
 751                          * extensively with Alteon's 12.3.15 firmware,
 752                          * compiled with GCC 2.7.2.1 and binutils 2.9.1.
 753                          *
 754                          * When you compile the firmware without
 755                          * optimization, which is necessary sometimes in
 756                          * order to properly step through it, you sometimes
 757                          * read out a bogus value of 0xc0017c instead of
 758                          * whatever was supposed to be in that scratchpad
 759                          * location.  That value is on the stack somewhere,
 760                          * but I've never been able to figure out what was
 761                          * causing the problem.
 762                          *
 763                          * The address seems to pop up in random places,
 764                          * often not in the same place on two subsequent
 765                          * reads.
 766                          *
 767                          * In any case, the underlying data doesn't seem
 768                          * to be affected, just the value read out.
 769                          *
 770                          * KDM, 3/7/2000
 771                          */
 772
 773                         if (tmpval2 == 0xc0017c)
 774                                 device_printf(sc->ti_dev, "found 0xc0017c at "
 775                                     "%#x (tmpval2)\n", segptr);
 776
 777                         if (tmpval == 0xc0017c)
 778                                 device_printf(sc->ti_dev, "found 0xc0017c at "
 779                                     "%#x (tmpval)\n", segptr);
 780
 781                         if (useraddr)
 782                                 copyout(&tmpval, ptr, 4);
 783                         else
 784                                 bcopy(&tmpval, ptr, 4);
 785                 } else {
 786                         if (useraddr)
 787                                 copyin(ptr, &tmpval2, 4);
 788                         else
 789                                 bcopy(ptr, &tmpval2, 4);
 790
 791                         tmpval = htonl(tmpval2);
 792
 793                         CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
 794                 }
 795
 796                 cnt -= 4;
 797                 segptr += 4;
 798                 ptr += 4;
 799         }
 800
 801         return (0);
 802 }
 803
 804 static int
 805 ti_bcopy_swap(src, dst, len, swap_type)
 806         const void      *src;
 807         void            *dst;
 808         size_t          len;
 809         ti_swap_type    swap_type;
 810 {
 811         const u_int8_t *tmpsrc;
 812         u_int8_t *tmpdst;
 813         size_t tmplen;
 814
 815         if (len & 0x3) {
 816                 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
 817                        len);
 818                 return (-1);
 819         }
 820
 821         tmpsrc = src;
 822         tmpdst = dst;
 823         tmplen = len;
 824
 825         while (tmplen) {
 826                 if (swap_type == TI_SWAP_NTOH)
 827                         *(u_int32_t *)tmpdst =
 828                                 ntohl(*(const u_int32_t *)tmpsrc);
 829                 else
 830                         *(u_int32_t *)tmpdst =
 831                                 htonl(*(const u_int32_t *)tmpsrc);
 832
 833                 tmpsrc += 4;
 834                 tmpdst += 4;
 835                 tmplen -= 4;
 836         }
 837
 838         return (0);
 839 }
 840
 841 /*
 842  * Load firmware image into the NIC. Check that the firmware revision
 843  * is acceptable and see if we want the firmware for the Tigon 1 or
 844  * Tigon 2.
 845  */
 846 static void
 847 ti_loadfw(sc)
 848         struct ti_softc         *sc;
 849 {
 850
 851         TI_LOCK_ASSERT(sc);
 852
 853         switch (sc->ti_hwrev) {
 854         case TI_HWREV_TIGON:
 855                 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
 856                     tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
 857                     tigonFwReleaseFix != TI_FIRMWARE_FIX) {
 858                         device_printf(sc->ti_dev, "firmware revision mismatch; "
 859                             "want %d.%d.%d, got %d.%d.%d\n",
 860                             TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
 861                             TI_FIRMWARE_FIX, tigonFwReleaseMajor,
 862                             tigonFwReleaseMinor, tigonFwReleaseFix);
 863                         return;
 864                 }
 865                 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
 866                 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
 867                 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
 868                     tigonFwRodata);
 869                 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
 870                 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
 871                 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
 872                 break;
 873         case TI_HWREV_TIGON_II:
 874                 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
 875                     tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
 876                     tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
 877                         device_printf(sc->ti_dev, "firmware revision mismatch; "
 878                             "want %d.%d.%d, got %d.%d.%d\n",
 879                             TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
 880                             TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
 881                             tigon2FwReleaseMinor, tigon2FwReleaseFix);
 882                         return;
 883                 }
 884                 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
 885                     tigon2FwText);
 886                 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
 887                     tigon2FwData);
 888                 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
 889                     tigon2FwRodata);
 890                 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
 891                 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
 892                 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
 893                 break;
 894         default:
 895                 device_printf(sc->ti_dev,
 896                     "can't load firmware: unknown hardware rev\n");
 897                 break;
 898         }
 899 }
 900
 901 /*
 902  * Send the NIC a command via the command ring.
 903  */
 904 static void
 905 ti_cmd(sc, cmd)
 906         struct ti_softc         *sc;
 907         struct ti_cmd_desc      *cmd;
 908 {
 909         int                     index;
 910
 911         index = sc->ti_cmd_saved_prodidx;
 912         CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
 913         TI_INC(index, TI_CMD_RING_CNT);
 914         CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
 915         sc->ti_cmd_saved_prodidx = index;
 916 }
 917
 918 /*
 919  * Send the NIC an extended command. The 'len' parameter specifies the
 920  * number of command slots to include after the initial command.
 921  */
 922 static void
 923 ti_cmd_ext(sc, cmd, arg, len)
 924         struct ti_softc         *sc;
 925         struct ti_cmd_desc      *cmd;
 926         caddr_t                 arg;
 927         int                     len;
 928 {
 929         int                     index;
 930         int                     i;
 931
 932         index = sc->ti_cmd_saved_prodidx;
 933         CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
 934         TI_INC(index, TI_CMD_RING_CNT);
 935         for (i = 0; i < len; i++) {
 936                 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
 937                     *(u_int32_t *)(&arg[i * 4]));
 938                 TI_INC(index, TI_CMD_RING_CNT);
 939         }
 940         CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
 941         sc->ti_cmd_saved_prodidx = index;
 942 }
 943
 944 /*
 945  * Handle events that have triggered interrupts.
 946  */
 947 static void
 948 ti_handle_events(sc)
 949         struct ti_softc         *sc;
 950 {
 951         struct ti_event_desc    *e;
 952
 953         if (sc->ti_rdata->ti_event_ring == NULL)
 954                 return;
 955
 956         while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
 957                 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
 958                 switch (TI_EVENT_EVENT(e)) {
 959                 case TI_EV_LINKSTAT_CHANGED:
 960                         sc->ti_linkstat = TI_EVENT_CODE(e);
 961                         if (sc->ti_linkstat == TI_EV_CODE_LINK_UP)
 962                                 device_printf(sc->ti_dev, "10/100 link up\n");
 963                         else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
 964                                 device_printf(sc->ti_dev, "gigabit link up\n");
 965                         else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
 966                                 device_printf(sc->ti_dev, "link down\n");
 967                         break;
 968                 case TI_EV_ERROR:
 969                         if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
 970                                 device_printf(sc->ti_dev, "invalid command\n");
 971                         else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
 972                                 device_printf(sc->ti_dev, "unknown command\n");
 973                         else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
 974                                 device_printf(sc->ti_dev, "bad config data\n");
 975                         break;
 976                 case TI_EV_FIRMWARE_UP:
 977                         ti_init2(sc);
 978                         break;
 979                 case TI_EV_STATS_UPDATED:
 980                         ti_stats_update(sc);
 981                         break;
 982                 case TI_EV_RESET_JUMBO_RING:
 983                 case TI_EV_MCAST_UPDATED:
 984                         /* Who cares. */
 985                         break;
 986                 default:
 987                         device_printf(sc->ti_dev, "unknown event: %d\n",
 988                             TI_EVENT_EVENT(e));
 989                         break;
 990                 }
 991                 /* Advance the consumer index. */
 992                 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
 993                 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
 994         }
 995 }
 996
 997 static int
 998 ti_alloc_dmamaps(struct ti_softc *sc)
 999 {
1000         int i;
1001
1002         for (i = 0; i < TI_TX_RING_CNT; i++) {
1003                 sc->ti_cdata.ti_txdesc[i].tx_m = NULL;
1004                 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
1005                 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0,
1006                                       &sc->ti_cdata.ti_txdesc[i].tx_dmamap))
1007                         return (ENOBUFS);
1008         }
1009         for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1010                 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
1011                                       &sc->ti_cdata.ti_rx_std_maps[i]))
1012                         return (ENOBUFS);
1013         }
1014
1015         for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1016                 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0,
1017                                       &sc->ti_cdata.ti_rx_jumbo_maps[i]))
1018                         return (ENOBUFS);
1019         }
1020         for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1021                 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
1022                                       &sc->ti_cdata.ti_rx_mini_maps[i]))
1023                         return (ENOBUFS);
1024         }
1025
1026         return (0);
1027 }
1028
1029 static void
1030 ti_free_dmamaps(struct ti_softc *sc)
1031 {
1032         int i;
1033
1034         if (sc->ti_mbuftx_dmat)
1035                 for (i = 0; i < TI_TX_RING_CNT; i++)
1036                         if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1037                                 bus_dmamap_destroy(sc->ti_mbuftx_dmat,
1038                                     sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1039                                 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
1040                         }
1041
1042         if (sc->ti_mbufrx_dmat)
1043                 for (i = 0; i < TI_STD_RX_RING_CNT; i++)
1044                         if (sc->ti_cdata.ti_rx_std_maps[i]) {
1045                                 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1046                                     sc->ti_cdata.ti_rx_std_maps[i]);
1047                                 sc->ti_cdata.ti_rx_std_maps[i] = 0;
1048                         }
1049
1050         if (sc->ti_jumbo_dmat)
1051                 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++)
1052                         if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1053                                 bus_dmamap_destroy(sc->ti_jumbo_dmat,
1054                                     sc->ti_cdata.ti_rx_jumbo_maps[i]);
1055                                 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0;
1056                         }
1057         if (sc->ti_mbufrx_dmat)
1058                 for (i = 0; i < TI_MINI_RX_RING_CNT; i++)
1059                         if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1060                                 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1061                                     sc->ti_cdata.ti_rx_mini_maps[i]);
1062                                 sc->ti_cdata.ti_rx_mini_maps[i] = 0;
1063                         }
1064 }
1065
1066 #ifdef TI_PRIVATE_JUMBOS
1067
1068 /*
1069  * Memory management for the jumbo receive ring is a pain in the
1070  * butt. We need to allocate at least 9018 bytes of space per frame,
1071  * _and_ it has to be contiguous (unless you use the extended
1072  * jumbo descriptor format). Using malloc() all the time won't
1073  * work: malloc() allocates memory in powers of two, which means we
1074  * would end up wasting a considerable amount of space by allocating
1075  * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
1076  * to do our own memory management.
1077  *
1078  * The driver needs to allocate a contiguous chunk of memory at boot
1079  * time. We then chop this up ourselves into 9K pieces and use them
1080  * as external mbuf storage.
1081  *
1082  * One issue here is how much memory to allocate. The jumbo ring has
1083  * 256 slots in it, but at 9K per slot than can consume over 2MB of
1084  * RAM. This is a bit much, especially considering we also need
1085  * RAM for the standard ring and mini ring (on the Tigon 2). To
1086  * save space, we only actually allocate enough memory for 64 slots
1087  * by default, which works out to between 500 and 600K. This can
1088  * be tuned by changing a #define in if_tireg.h.
1089  */
1090
1091 static int
1092 ti_alloc_jumbo_mem(sc)
1093         struct ti_softc         *sc;
1094 {
1095         caddr_t                 ptr;
1096         int                     i;
1097         struct ti_jpool_entry   *entry;
1098
1099         /*
1100          * Grab a big chunk o' storage.  Since we are chopping this pool up
1101          * into ~9k chunks, there doesn't appear to be a need to use page
1102          * alignment.
1103          */
1104         if (bus_dma_tag_create(sc->ti_parent_dmat,      /* parent */
1105                                 1, 0,                   /* algnmnt, boundary */
1106                                 BUS_SPACE_MAXADDR,      /* lowaddr */
1107                                 BUS_SPACE_MAXADDR,      /* highaddr */
1108                                 NULL, NULL,             /* filter, filterarg */
1109                                 TI_JMEM,                /* maxsize */
1110                                 1,                      /* nsegments */
1111                                 TI_JMEM,                /* maxsegsize */
1112                                 0,                      /* flags */
1113                                 NULL, NULL,             /* lockfunc, lockarg */
1114                                 &sc->ti_jumbo_dmat) != 0) {
1115                 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1116                 return (ENOBUFS);
1117         }
1118
1119         if (bus_dmamem_alloc(sc->ti_jumbo_dmat,
1120                              (void**)&sc->ti_cdata.ti_jumbo_buf,
1121                              BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
1122                              &sc->ti_jumbo_dmamap) != 0) {
1123                 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n");
1124                 return (ENOBUFS);
1125         }
1126
1127         SLIST_INIT(&sc->ti_jfree_listhead);
1128         SLIST_INIT(&sc->ti_jinuse_listhead);
1129
1130         /*
1131          * Now divide it up into 9K pieces and save the addresses
1132          * in an array.
1133          */
1134         ptr = sc->ti_cdata.ti_jumbo_buf;
1135         for (i = 0; i < TI_JSLOTS; i++) {
1136                 sc->ti_cdata.ti_jslots[i] = ptr;
1137                 ptr += TI_JLEN;
1138                 entry = malloc(sizeof(struct ti_jpool_entry),
1139                                M_DEVBUF, M_NOWAIT);
1140                 if (entry == NULL) {
1141                         device_printf(sc->ti_dev, "no memory for jumbo "
1142                             "buffer queue!\n");
1143                         return (ENOBUFS);
1144                 }
1145                 entry->slot = i;
1146                 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1147         }
1148
1149         return (0);
1150 }
1151
1152 /*
1153  * Allocate a jumbo buffer.
1154  */
1155 static void *ti_jalloc(sc)
1156         struct ti_softc         *sc;
1157 {
1158         struct ti_jpool_entry   *entry;
1159
1160         entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1161
1162         if (entry == NULL) {
1163                 device_printf(sc->ti_dev, "no free jumbo buffers\n");
1164                 return (NULL);
1165         }
1166
1167         SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1168         SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1169         return (sc->ti_cdata.ti_jslots[entry->slot]);
1170 }
1171
1172 /*
1173  * Release a jumbo buffer.
1174  */
1175 static void
1176 ti_jfree(buf, args)
1177         void                    *buf;
1178         void                    *args;
1179 {
1180         struct ti_softc         *sc;
1181         int                     i;
1182         struct ti_jpool_entry   *entry;
1183
1184         /* Extract the softc struct pointer. */
1185         sc = (struct ti_softc *)args;
1186
1187         if (sc == NULL)
1188                 panic("ti_jfree: didn't get softc pointer!");
1189
1190         /* calculate the slot this buffer belongs to */
1191         i = ((vm_offset_t)buf
1192              - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1193
1194         if ((i < 0) || (i >= TI_JSLOTS))
1195                 panic("ti_jfree: asked to free buffer that we don't manage!");
1196
1197         entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1198         if (entry == NULL)
1199                 panic("ti_jfree: buffer not in use!");
1200         entry->slot = i;
1201         SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1202         SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1203 }
1204
1205 #else
1206
1207 static int
1208 ti_alloc_jumbo_mem(sc)
1209         struct ti_softc         *sc;
1210 {
1211
1212         /*
1213          * The VM system will take care of providing aligned pages.  Alignment
1214          * is set to 1 here so that busdma resources won't be wasted.
1215          */
1216         if (bus_dma_tag_create(sc->ti_parent_dmat,      /* parent */
1217                                 1, 0,                   /* algnmnt, boundary */
1218                                 BUS_SPACE_MAXADDR,      /* lowaddr */
1219                                 BUS_SPACE_MAXADDR,      /* highaddr */
1220                                 NULL, NULL,             /* filter, filterarg */
1221                                 PAGE_SIZE * 4 /*XXX*/,  /* maxsize */
1222                                 4,                      /* nsegments */
1223                                 PAGE_SIZE,              /* maxsegsize */
1224                                 0,                      /* flags */
1225                                 NULL, NULL,             /* lockfunc, lockarg */
1226                                 &sc->ti_jumbo_dmat) != 0) {
1227                 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1228                 return (ENOBUFS);
1229         }
1230
1231         return (0);
1232 }
1233
1234 #endif /* TI_PRIVATE_JUMBOS */
1235
1236 /*
1237  * Intialize a standard receive ring descriptor.
1238  */
1239 static int
1240 ti_newbuf_std(sc, i, m)
1241         struct ti_softc         *sc;
1242         int                     i;
1243         struct mbuf             *m;
1244 {
1245         bus_dmamap_t            map;
1246         bus_dma_segment_t       segs;
1247         struct mbuf             *m_new = NULL;
1248         struct ti_rx_desc       *r;
1249         int                     nsegs;
1250
1251         nsegs = 0;
1252         if (m == NULL) {
1253                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1254                 if (m_new == NULL)
1255                         return (ENOBUFS);
1256
1257                 MCLGET(m_new, M_DONTWAIT);
1258                 if (!(m_new->m_flags & M_EXT)) {
1259                         m_freem(m_new);
1260                         return (ENOBUFS);
1261                 }
1262                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1263         } else {
1264                 m_new = m;
1265                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1266                 m_new->m_data = m_new->m_ext.ext_buf;
1267         }
1268
1269         m_adj(m_new, ETHER_ALIGN);
1270         sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1271         r = &sc->ti_rdata->ti_rx_std_ring[i];
1272         map = sc->ti_cdata.ti_rx_std_maps[i];
1273         if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1274                                     &nsegs, 0))
1275                 return (ENOBUFS);
1276         if (nsegs != 1)
1277                 return (ENOBUFS);
1278         ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1279         r->ti_len = segs.ds_len;
1280         r->ti_type = TI_BDTYPE_RECV_BD;
1281         r->ti_flags = 0;
1282         if (sc->ti_ifp->if_hwassist)
1283                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1284         r->ti_idx = i;
1285
1286         bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1287         return (0);
1288 }
1289
1290 /*
1291  * Intialize a mini receive ring descriptor. This only applies to
1292  * the Tigon 2.
1293  */
1294 static int
1295 ti_newbuf_mini(sc, i, m)
1296         struct ti_softc         *sc;
1297         int                     i;
1298         struct mbuf             *m;
1299 {
1300         bus_dma_segment_t       segs;
1301         bus_dmamap_t            map;
1302         struct mbuf             *m_new = NULL;
1303         struct ti_rx_desc       *r;
1304         int                     nsegs;
1305
1306         nsegs = 0;
1307         if (m == NULL) {
1308                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1309                 if (m_new == NULL) {
1310                         return (ENOBUFS);
1311                 }
1312                 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1313         } else {
1314                 m_new = m;
1315                 m_new->m_data = m_new->m_pktdat;
1316                 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1317         }
1318
1319         m_adj(m_new, ETHER_ALIGN);
1320         r = &sc->ti_rdata->ti_rx_mini_ring[i];
1321         sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1322         map = sc->ti_cdata.ti_rx_mini_maps[i];
1323         if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1324                                     &nsegs, 0))
1325                 return (ENOBUFS);
1326         if (nsegs != 1)
1327                 return (ENOBUFS);
1328         ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1329         r->ti_len = segs.ds_len;
1330         r->ti_type = TI_BDTYPE_RECV_BD;
1331         r->ti_flags = TI_BDFLAG_MINI_RING;
1332         if (sc->ti_ifp->if_hwassist)
1333                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1334         r->ti_idx = i;
1335
1336         bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1337         return (0);
1338 }
1339
1340 #ifdef TI_PRIVATE_JUMBOS
1341
1342 /*
1343  * Initialize a jumbo receive ring descriptor. This allocates
1344  * a jumbo buffer from the pool managed internally by the driver.
1345  */
1346 static int
1347 ti_newbuf_jumbo(sc, i, m)
1348         struct ti_softc         *sc;
1349         int                     i;
1350         struct mbuf             *m;
1351 {
1352         bus_dmamap_t            map;
1353         struct mbuf             *m_new = NULL;
1354         struct ti_rx_desc       *r;
1355         int                     nsegs;
1356         bus_dma_segment_t       segs;
1357
1358         if (m == NULL) {
1359                 caddr_t                 *buf = NULL;
1360
1361                 /* Allocate the mbuf. */
1362                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1363                 if (m_new == NULL) {
1364                         return (ENOBUFS);
1365                 }
1366
1367                 /* Allocate the jumbo buffer */
1368                 buf = ti_jalloc(sc);
1369                 if (buf == NULL) {
1370                         m_freem(m_new);
1371                         device_printf(sc->ti_dev, "jumbo allocation failed "
1372                             "-- packet dropped!\n");
1373                         return (ENOBUFS);
1374                 }
1375
1376                 /* Attach the buffer to the mbuf. */
1377                 m_new->m_data = (void *) buf;
1378                 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1379                 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
1380                     (struct ti_softc *)sc, 0, EXT_NET_DRV);
1381         } else {
1382                 m_new = m;
1383                 m_new->m_data = m_new->m_ext.ext_buf;
1384                 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1385         }
1386
1387         m_adj(m_new, ETHER_ALIGN);
1388         /* Set up the descriptor. */
1389         r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1390         sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1391         map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1392         if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs,
1393                                     &nsegs, 0))
1394                 return (ENOBUFS);
1395         if (nsegs != 1)
1396                 return (ENOBUFS);
1397         ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1398         r->ti_len = segs.ds_len;
1399         r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1400         r->ti_flags = TI_BDFLAG_JUMBO_RING;
1401         if (sc->ti_ifp->if_hwassist)
1402                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1403         r->ti_idx = i;
1404
1405         bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1406         return (0);
1407 }
1408
1409 #else
1410
1411 #if (PAGE_SIZE == 4096)
1412 #define NPAYLOAD 2
1413 #else
1414 #define NPAYLOAD 1
1415 #endif
1416
1417 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1418 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1419 #define NFS_HDR_LEN (UDP_HDR_LEN)
1420 static int HDR_LEN =  TCP_HDR_LEN;
1421
1422
1423 /*
1424  * Initialize a jumbo receive ring descriptor. This allocates
1425  * a jumbo buffer from the pool managed internally by the driver.
1426  */
1427 static int
1428 ti_newbuf_jumbo(sc, idx, m_old)
1429         struct ti_softc         *sc;
1430         int                     idx;
1431         struct mbuf             *m_old;
1432 {
1433         bus_dmamap_t            map;
1434         struct mbuf             *cur, *m_new = NULL;
1435         struct mbuf             *m[3] = {NULL, NULL, NULL};
1436         struct ti_rx_desc_ext   *r;
1437         vm_page_t               frame;
1438         static int              color;
1439                                 /* 1 extra buf to make nobufs easy*/
1440         struct sf_buf           *sf[3] = {NULL, NULL, NULL};
1441         int                     i;
1442         bus_dma_segment_t       segs[4];
1443         int                     nsegs;
1444
1445         if (m_old != NULL) {
1446                 m_new = m_old;
1447                 cur = m_old->m_next;
1448                 for (i = 0; i <= NPAYLOAD; i++){
1449                         m[i] = cur;
1450                         cur = cur->m_next;
1451                 }
1452         } else {
1453                 /* Allocate the mbufs. */
1454                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1455                 if (m_new == NULL) {
1456                         device_printf(sc->ti_dev, "mbuf allocation failed "
1457                             "-- packet dropped!\n");
1458                         goto nobufs;
1459                 }
1460                 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1461                 if (m[NPAYLOAD] == NULL) {
1462                         device_printf(sc->ti_dev, "cluster mbuf allocation "
1463                             "failed -- packet dropped!\n");
1464                         goto nobufs;
1465                 }
1466                 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1467                 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1468                         device_printf(sc->ti_dev, "mbuf allocation failed "
1469                             "-- packet dropped!\n");
1470                         goto nobufs;
1471                 }
1472                 m[NPAYLOAD]->m_len = MCLBYTES;
1473
1474                 for (i = 0; i < NPAYLOAD; i++){
1475                         MGET(m[i], M_DONTWAIT, MT_DATA);
1476                         if (m[i] == NULL) {
1477                                 device_printf(sc->ti_dev, "mbuf allocation "
1478                                     "failed -- packet dropped!\n");
1479                                 goto nobufs;
1480                         }
1481                         frame = vm_page_alloc(NULL, color++,
1482                             VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1483                             VM_ALLOC_WIRED);
1484                         if (frame == NULL) {
1485                                 device_printf(sc->ti_dev, "buffer allocation "
1486                                     "failed -- packet dropped!\n");
1487                                 printf("      index %d page %d\n", idx, i);
1488                                 goto nobufs;
1489                         }
1490                         sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1491                         if (sf[i] == NULL) {
1492                                 vm_page_lock_queues();
1493                                 vm_page_unwire(frame, 0);
1494                                 vm_page_free(frame);
1495                                 vm_page_unlock_queues();
1496                                 device_printf(sc->ti_dev, "buffer allocation "
1497                                     "failed -- packet dropped!\n");
1498                                 printf("      index %d page %d\n", idx, i);
1499                                 goto nobufs;
1500                         }
1501                 }
1502                 for (i = 0; i < NPAYLOAD; i++){
1503                 /* Attach the buffer to the mbuf. */
1504                         m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1505                         m[i]->m_len = PAGE_SIZE;
1506                         MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1507                             sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1508                             0, EXT_DISPOSABLE);
1509                         m[i]->m_next = m[i+1];
1510                 }
1511                 /* link the buffers to the header */
1512                 m_new->m_next = m[0];
1513                 m_new->m_data += ETHER_ALIGN;
1514                 if (sc->ti_hdrsplit)
1515                         m_new->m_len = MHLEN - ETHER_ALIGN;
1516                 else
1517                         m_new->m_len = HDR_LEN;
1518                 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1519         }
1520
1521         /* Set up the descriptor. */
1522         r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1523         sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1524         map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1525         if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs,
1526                                     &nsegs, 0))
1527                 return (ENOBUFS);
1528         if ((nsegs < 1) || (nsegs > 4))
1529                 return (ENOBUFS);
1530         ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1531         r->ti_len0 = m_new->m_len;
1532
1533         ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1534         r->ti_len1 = PAGE_SIZE;
1535
1536         ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1537         r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1538
1539         if (PAGE_SIZE == 4096) {
1540                 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1541                 r->ti_len3 = MCLBYTES;
1542         } else {
1543                 r->ti_len3 = 0;
1544         }
1545         r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1546
1547         r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1548
1549         if (sc->ti_ifp->if_hwassist)
1550                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1551
1552         r->ti_idx = idx;
1553
1554         bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1555         return (0);
1556
1557 nobufs:
1558
1559         /*
1560          * Warning! :
1561          * This can only be called before the mbufs are strung together.
1562          * If the mbufs are strung together, m_freem() will free the chain,
1563          * so that the later mbufs will be freed multiple times.
1564          */
1565         if (m_new)
1566                 m_freem(m_new);
1567
1568         for (i = 0; i < 3; i++) {
1569                 if (m[i])
1570                         m_freem(m[i]);
1571                 if (sf[i])
1572                         sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1573         }
1574         return (ENOBUFS);
1575 }
1576 #endif
1577
1578
1579
1580 /*
1581  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1582  * that's 1MB or memory, which is a lot. For now, we fill only the first
1583  * 256 ring entries and hope that our CPU is fast enough to keep up with
1584  * the NIC.
1585  */
1586 static int
1587 ti_init_rx_ring_std(sc)
1588         struct ti_softc         *sc;
1589 {
1590         int                     i;
1591         struct ti_cmd_desc      cmd;
1592
1593         for (i = 0; i < TI_SSLOTS; i++) {
1594                 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1595                         return (ENOBUFS);
1596         };
1597
1598         TI_UPDATE_STDPROD(sc, i - 1);
1599         sc->ti_std = i - 1;
1600
1601         return (0);
1602 }
1603
1604 static void
1605 ti_free_rx_ring_std(sc)
1606         struct ti_softc         *sc;
1607 {
1608         bus_dmamap_t            map;
1609         int                     i;
1610
1611         for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1612                 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1613                         map = sc->ti_cdata.ti_rx_std_maps[i];
1614                         bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1615                             BUS_DMASYNC_POSTREAD);
1616                         bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1617                         m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1618                         sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1619                 }
1620                 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1621                     sizeof(struct ti_rx_desc));
1622         }
1623 }
1624
1625 static int
1626 ti_init_rx_ring_jumbo(sc)
1627         struct ti_softc         *sc;
1628 {
1629         int                     i;
1630         struct ti_cmd_desc      cmd;
1631
1632         for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1633                 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1634                         return (ENOBUFS);
1635         };
1636
1637         TI_UPDATE_JUMBOPROD(sc, i - 1);
1638         sc->ti_jumbo = i - 1;
1639
1640         return (0);
1641 }
1642
1643 static void
1644 ti_free_rx_ring_jumbo(sc)
1645         struct ti_softc         *sc;
1646 {
1647         bus_dmamap_t            map;
1648         int                     i;
1649
1650         for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1651                 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1652                         map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1653                         bus_dmamap_sync(sc->ti_jumbo_dmat, map,
1654                             BUS_DMASYNC_POSTREAD);
1655                         bus_dmamap_unload(sc->ti_jumbo_dmat, map);
1656                         m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1657                         sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1658                 }
1659                 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1660                     sizeof(struct ti_rx_desc));
1661         }
1662 }
1663
1664 static int
1665 ti_init_rx_ring_mini(sc)
1666         struct ti_softc         *sc;
1667 {
1668         int                     i;
1669
1670         for (i = 0; i < TI_MSLOTS; i++) {
1671                 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1672                         return (ENOBUFS);
1673         };
1674
1675         TI_UPDATE_MINIPROD(sc, i - 1);
1676         sc->ti_mini = i - 1;
1677
1678         return (0);
1679 }
1680
1681 static void
1682 ti_free_rx_ring_mini(sc)
1683         struct ti_softc         *sc;
1684 {
1685         bus_dmamap_t            map;
1686         int                     i;
1687
1688         for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1689                 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1690                         map = sc->ti_cdata.ti_rx_mini_maps[i];
1691                         bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1692                             BUS_DMASYNC_POSTREAD);
1693                         bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1694                         m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1695                         sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1696                 }
1697                 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1698                     sizeof(struct ti_rx_desc));
1699         }
1700 }
1701
1702 static void
1703 ti_free_tx_ring(sc)
1704         struct ti_softc         *sc;
1705 {
1706         struct ti_txdesc        *txd;
1707         int                     i;
1708
1709         if (sc->ti_rdata->ti_tx_ring == NULL)
1710                 return;
1711
1712         for (i = 0; i < TI_TX_RING_CNT; i++) {
1713                 txd = &sc->ti_cdata.ti_txdesc[i];
1714                 if (txd->tx_m != NULL) {
1715                         bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
1716                             BUS_DMASYNC_POSTWRITE);
1717                         bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
1718                         m_freem(txd->tx_m);
1719                         txd->tx_m = NULL;
1720                 }
1721                 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1722                     sizeof(struct ti_tx_desc));
1723         }
1724 }
1725
1726 static int
1727 ti_init_tx_ring(sc)
1728         struct ti_softc         *sc;
1729 {
1730         struct ti_txdesc        *txd;
1731         int                     i;
1732
1733         STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1734         STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1735         for (i = 0; i < TI_TX_RING_CNT; i++) {
1736                 txd = &sc->ti_cdata.ti_txdesc[i];
1737                 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1738         }
1739         sc->ti_txcnt = 0;
1740         sc->ti_tx_saved_considx = 0;
1741         sc->ti_tx_saved_prodidx = 0;
1742         CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1743         return (0);
1744 }
1745
1746 /*
1747  * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1748  * but we have to support the old way too so that Tigon 1 cards will
1749  * work.
1750  */
1751 static void
1752 ti_add_mcast(sc, addr)
1753         struct ti_softc         *sc;
1754         struct ether_addr       *addr;
1755 {
1756         struct ti_cmd_desc      cmd;
1757         u_int16_t               *m;
1758         u_int32_t               ext[2] = {0, 0};
1759
1760         m = (u_int16_t *)&addr->octet[0];
1761
1762         switch (sc->ti_hwrev) {
1763         case TI_HWREV_TIGON:
1764                 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1765                 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1766                 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1767                 break;
1768         case TI_HWREV_TIGON_II:
1769                 ext[0] = htons(m[0]);
1770                 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1771                 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1772                 break;
1773         default:
1774                 device_printf(sc->ti_dev, "unknown hwrev\n");
1775                 break;
1776         }
1777 }
1778
1779 static void
1780 ti_del_mcast(sc, addr)
1781         struct ti_softc         *sc;
1782         struct ether_addr       *addr;
1783 {
1784         struct ti_cmd_desc      cmd;
1785         u_int16_t               *m;
1786         u_int32_t               ext[2] = {0, 0};
1787
1788         m = (u_int16_t *)&addr->octet[0];
1789
1790         switch (sc->ti_hwrev) {
1791         case TI_HWREV_TIGON:
1792                 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1793                 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1794                 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1795                 break;
1796         case TI_HWREV_TIGON_II:
1797                 ext[0] = htons(m[0]);
1798                 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1799                 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1800                 break;
1801         default:
1802                 device_printf(sc->ti_dev, "unknown hwrev\n");
1803                 break;
1804         }
1805 }
1806
1807 /*
1808  * Configure the Tigon's multicast address filter.
1809  *
1810  * The actual multicast table management is a bit of a pain, thanks to
1811  * slight brain damage on the part of both Alteon and us. With our
1812  * multicast code, we are only alerted when the multicast address table
1813  * changes and at that point we only have the current list of addresses:
1814  * we only know the current state, not the previous state, so we don't
1815  * actually know what addresses were removed or added. The firmware has
1816  * state, but we can't get our grubby mits on it, and there is no 'delete
1817  * all multicast addresses' command. Hence, we have to maintain our own
1818  * state so we know what addresses have been programmed into the NIC at
1819  * any given time.
1820  */
1821 static void
1822 ti_setmulti(sc)
1823         struct ti_softc         *sc;
1824 {
1825         struct ifnet            *ifp;
1826         struct ifmultiaddr      *ifma;
1827         struct ti_cmd_desc      cmd;
1828         struct ti_mc_entry      *mc;
1829         u_int32_t               intrs;
1830
1831         TI_LOCK_ASSERT(sc);
1832
1833         ifp = sc->ti_ifp;
1834
1835         if (ifp->if_flags & IFF_ALLMULTI) {
1836                 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1837                 return;
1838         } else {
1839                 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1840         }
1841
1842         /* Disable interrupts. */
1843         intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1844         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1845
1846         /* First, zot all the existing filters. */
1847         while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1848                 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1849                 ti_del_mcast(sc, &mc->mc_addr);
1850                 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1851                 free(mc, M_DEVBUF);
1852         }
1853
1854         /* Now program new ones. */
1855         if_maddr_rlock(ifp);
1856         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1857                 if (ifma->ifma_addr->sa_family != AF_LINK)
1858                         continue;
1859                 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1860                 if (mc == NULL) {
1861                         device_printf(sc->ti_dev,
1862                             "no memory for mcast filter entry\n");
1863                         continue;
1864                 }
1865                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1866                     (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1867                 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1868                 ti_add_mcast(sc, &mc->mc_addr);
1869         }
1870         if_maddr_runlock(ifp);
1871
1872         /* Re-enable interrupts. */
1873         CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1874 }
1875
1876 /*
1877  * Check to see if the BIOS has configured us for a 64 bit slot when
1878  * we aren't actually in one. If we detect this condition, we can work
1879  * around it on the Tigon 2 by setting a bit in the PCI state register,
1880  * but for the Tigon 1 we must give up and abort the interface attach.
1881  */
1882 static int ti_64bitslot_war(sc)
1883         struct ti_softc         *sc;
1884 {
1885         if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1886                 CSR_WRITE_4(sc, 0x600, 0);
1887                 CSR_WRITE_4(sc, 0x604, 0);
1888                 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1889                 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1890                         if (sc->ti_hwrev == TI_HWREV_TIGON)
1891                                 return (EINVAL);
1892                         else {
1893                                 TI_SETBIT(sc, TI_PCI_STATE,
1894                                     TI_PCISTATE_32BIT_BUS);
1895                                 return (0);
1896                         }
1897                 }
1898         }
1899
1900         return (0);
1901 }
1902
1903 /*
1904  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1905  * self-test results.
1906  */
1907 static int
1908 ti_chipinit(sc)
1909         struct ti_softc         *sc;
1910 {
1911         u_int32_t               cacheline;
1912         u_int32_t               pci_writemax = 0;
1913         u_int32_t               hdrsplit;
1914
1915         /* Initialize link to down state. */
1916         sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1917
1918         if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM)
1919                 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
1920         else
1921                 sc->ti_ifp->if_hwassist = 0;
1922
1923         /* Set endianness before we access any non-PCI registers. */
1924 #if 0 && BYTE_ORDER == BIG_ENDIAN
1925         CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1926             TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1927 #else
1928         CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1929             TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1930 #endif
1931
1932         /* Check the ROM failed bit to see if self-tests passed. */
1933         if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1934                 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
1935                 return (ENODEV);
1936         }
1937
1938         /* Halt the CPU. */
1939         TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1940
1941         /* Figure out the hardware revision. */
1942         switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1943         case TI_REV_TIGON_I:
1944                 sc->ti_hwrev = TI_HWREV_TIGON;
1945                 break;
1946         case TI_REV_TIGON_II:
1947                 sc->ti_hwrev = TI_HWREV_TIGON_II;
1948                 break;
1949         default:
1950                 device_printf(sc->ti_dev, "unsupported chip revision\n");
1951                 return (ENODEV);
1952         }
1953
1954         /* Do special setup for Tigon 2. */
1955         if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1956                 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1957                 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1958                 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1959         }
1960
1961         /*
1962          * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1963          * can't do header splitting.
1964          */
1965 #ifdef TI_JUMBO_HDRSPLIT
1966         if (sc->ti_hwrev != TI_HWREV_TIGON)
1967                 sc->ti_hdrsplit = 1;
1968         else
1969                 device_printf(sc->ti_dev,
1970                     "can't do header splitting on a Tigon I board\n");
1971 #endif /* TI_JUMBO_HDRSPLIT */
1972
1973         /* Set up the PCI state register. */
1974         CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1975         if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1976                 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1977         }
1978
1979         /* Clear the read/write max DMA parameters. */
1980         TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1981             TI_PCISTATE_READ_MAXDMA));
1982
1983         /* Get cache line size. */
1984         cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1985
1986         /*
1987          * If the system has set enabled the PCI memory write
1988          * and invalidate command in the command register, set
1989          * the write max parameter accordingly. This is necessary
1990          * to use MWI with the Tigon 2.
1991          */
1992         if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1993                 switch (cacheline) {
1994                 case 1:
1995                 case 4:
1996                 case 8:
1997                 case 16:
1998                 case 32:
1999                 case 64:
2000                         break;
2001                 default:
2002                 /* Disable PCI memory write and invalidate. */
2003                         if (bootverbose)
2004                                 device_printf(sc->ti_dev, "cache line size %d"
2005                                     " not supported; disabling PCI MWI\n",
2006                                     cacheline);
2007                         CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
2008                             TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
2009                         break;
2010                 }
2011         }
2012
2013         TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
2014
2015         /* This sets the min dma param all the way up (0xff). */
2016         TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
2017
2018         if (sc->ti_hdrsplit)
2019                 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
2020         else
2021                 hdrsplit = 0;
2022
2023         /* Configure DMA variables. */
2024 #if BYTE_ORDER == BIG_ENDIAN
2025         CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
2026             TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
2027             TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
2028             TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
2029 #else /* BYTE_ORDER */
2030         CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
2031             TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
2032             TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
2033 #endif /* BYTE_ORDER */
2034
2035         /*
2036          * Only allow 1 DMA channel to be active at a time.
2037          * I don't think this is a good idea, but without it
2038          * the firmware racks up lots of nicDmaReadRingFull
2039          * errors.  This is not compatible with hardware checksums.
2040          */
2041         if (sc->ti_ifp->if_hwassist == 0)
2042                 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
2043
2044         /* Recommended settings from Tigon manual. */
2045         CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
2046         CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
2047
2048         if (ti_64bitslot_war(sc)) {
2049                 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
2050                     "but we aren't");
2051                 return (EINVAL);
2052         }
2053
2054         return (0);
2055 }
2056
2057 /*
2058  * Initialize the general information block and firmware, and
2059  * start the CPU(s) running.
2060  */
2061 static int
2062 ti_gibinit(sc)
2063         struct ti_softc         *sc;
2064 {
2065         struct ti_rcb           *rcb;
2066         int                     i;
2067         struct ifnet            *ifp;
2068         uint32_t                rdphys;
2069
2070         TI_LOCK_ASSERT(sc);
2071
2072         ifp = sc->ti_ifp;
2073         rdphys = sc->ti_rdata_phys;
2074
2075         /* Disable interrupts for now. */
2076         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2077
2078         /*
2079          * Tell the chip where to find the general information block.
2080          * While this struct could go into >4GB memory, we allocate it in a
2081          * single slab with the other descriptors, and those don't seem to
2082          * support being located in a 64-bit region.
2083          */
2084         CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
2085         CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
2086
2087         /* Load the firmware into SRAM. */
2088         ti_loadfw(sc);
2089
2090         /* Set up the contents of the general info and ring control blocks. */
2091
2092         /* Set up the event ring and producer pointer. */
2093         rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
2094
2095         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
2096         rcb->ti_flags = 0;
2097         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
2098             rdphys + TI_RD_OFF(ti_ev_prodidx_r);
2099         sc->ti_ev_prodidx.ti_idx = 0;
2100         CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2101         sc->ti_ev_saved_considx = 0;
2102
2103         /* Set up the command ring and producer mailbox. */
2104         rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
2105
2106         TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
2107         rcb->ti_flags = 0;
2108         rcb->ti_max_len = 0;
2109         for (i = 0; i < TI_CMD_RING_CNT; i++) {
2110                 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2111         }
2112         CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2113         CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2114         sc->ti_cmd_saved_prodidx = 0;
2115
2116         /*
2117          * Assign the address of the stats refresh buffer.
2118          * We re-use the current stats buffer for this to
2119          * conserve memory.
2120          */
2121         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
2122             rdphys + TI_RD_OFF(ti_info.ti_stats);
2123
2124         /* Set up the standard receive ring. */
2125         rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
2126         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
2127         rcb->ti_max_len = TI_FRAMELEN;
2128         rcb->ti_flags = 0;
2129         if (sc->ti_ifp->if_hwassist)
2130                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2131                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2132         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2133
2134         /* Set up the jumbo receive ring. */
2135         rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
2136         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
2137
2138 #ifdef TI_PRIVATE_JUMBOS
2139         rcb->ti_max_len = TI_JUMBO_FRAMELEN;
2140         rcb->ti_flags = 0;
2141 #else
2142         rcb->ti_max_len = PAGE_SIZE;
2143         rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2144 #endif
2145         if (sc->ti_ifp->if_hwassist)
2146                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2147                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2148         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2149
2150         /*
2151          * Set up the mini ring. Only activated on the
2152          * Tigon 2 but the slot in the config block is
2153          * still there on the Tigon 1.
2154          */
2155         rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
2156         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
2157         rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2158         if (sc->ti_hwrev == TI_HWREV_TIGON)
2159                 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2160         else
2161                 rcb->ti_flags = 0;
2162         if (sc->ti_ifp->if_hwassist)
2163                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2164                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2165         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2166
2167         /*
2168          * Set up the receive return ring.
2169          */
2170         rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
2171         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
2172         rcb->ti_flags = 0;
2173         rcb->ti_max_len = TI_RETURN_RING_CNT;
2174         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
2175             rdphys + TI_RD_OFF(ti_return_prodidx_r);
2176
2177         /*
2178          * Set up the tx ring. Note: for the Tigon 2, we have the option
2179          * of putting the transmit ring in the host's address space and
2180          * letting the chip DMA it instead of leaving the ring in the NIC's
2181          * memory and accessing it through the shared memory region. We
2182          * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2183          * so we have to revert to the shared memory scheme if we detect
2184          * a Tigon 1 chip.
2185          */
2186         CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2187         bzero((char *)sc->ti_rdata->ti_tx_ring,
2188             TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
2189         rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
2190         if (sc->ti_hwrev == TI_HWREV_TIGON)
2191                 rcb->ti_flags = 0;
2192         else
2193                 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2194         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2195         if (sc->ti_ifp->if_hwassist)
2196                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2197                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2198         rcb->ti_max_len = TI_TX_RING_CNT;
2199         if (sc->ti_hwrev == TI_HWREV_TIGON)
2200                 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
2201         else
2202                 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
2203         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
2204             rdphys + TI_RD_OFF(ti_tx_considx_r);
2205
2206         bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2207             BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2208
2209         /* Set up tuneables */
2210 #if 0
2211         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2212                 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2213                     (sc->ti_rx_coal_ticks / 10));
2214         else
2215 #endif
2216                 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2217         CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2218         CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2219         CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2220         CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2221         CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2222
2223         /* Turn interrupts on. */
2224         CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2225         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2226
2227         /* Start CPU. */
2228         TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2229
2230         return (0);
2231 }
2232
2233 static void
2234 ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2235 {
2236         struct ti_softc *sc;
2237
2238         sc = arg;
2239         if (error || nseg != 1)
2240                 return;
2241
2242         /*
2243          * All of the Tigon data structures need to live at <4GB.  This
2244          * cast is fine since busdma was told about this constraint.
2245          */
2246         sc->ti_rdata_phys = segs[0].ds_addr;
2247         return;
2248 }
2249
2250 /*
2251  * Probe for a Tigon chip. Check the PCI vendor and device IDs
2252  * against our list and return its name if we find a match.
2253  */
2254 static int
2255 ti_probe(dev)
2256         device_t                dev;
2257 {
2258         const struct ti_type    *t;
2259
2260         t = ti_devs;
2261
2262         while (t->ti_name != NULL) {
2263                 if ((pci_get_vendor(dev) == t->ti_vid) &&
2264                     (pci_get_device(dev) == t->ti_did)) {
2265                         device_set_desc(dev, t->ti_name);
2266                         return (BUS_PROBE_DEFAULT);
2267                 }
2268                 t++;
2269         }
2270
2271         return (ENXIO);
2272 }
2273
2274 static int
2275 ti_attach(dev)
2276         device_t                dev;
2277 {
2278         struct ifnet            *ifp;
2279         struct ti_softc         *sc;
2280         int                     error = 0, rid;
2281         u_char                  eaddr[6];
2282
2283         sc = device_get_softc(dev);
2284         sc->ti_unit = device_get_unit(dev);
2285         sc->ti_dev = dev;
2286
2287         mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2288             MTX_DEF);
2289         callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2290         ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2291         ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2292         if (ifp == NULL) {
2293                 device_printf(dev, "can not if_alloc()\n");
2294                 error = ENOSPC;
2295                 goto fail;
2296         }
2297         sc->ti_ifp->if_capabilities = IFCAP_HWCSUM |
2298             IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2299         sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2300
2301         /*
2302          * Map control/status registers.
2303          */
2304         pci_enable_busmaster(dev);
2305
2306         rid = TI_PCI_LOMEM;
2307         sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2308             RF_ACTIVE);
2309
2310         if (sc->ti_res == NULL) {
2311                 device_printf(dev, "couldn't map memory\n");
2312                 error = ENXIO;
2313                 goto fail;
2314         }
2315
2316         sc->ti_btag = rman_get_bustag(sc->ti_res);
2317         sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2318
2319         /* Allocate interrupt */
2320         rid = 0;
2321
2322         sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2323             RF_SHAREABLE | RF_ACTIVE);
2324
2325         if (sc->ti_irq == NULL) {
2326                 device_printf(dev, "couldn't map interrupt\n");
2327                 error = ENXIO;
2328                 goto fail;
2329         }
2330
2331         if (ti_chipinit(sc)) {
2332                 device_printf(dev, "chip initialization failed\n");
2333                 error = ENXIO;
2334                 goto fail;
2335         }
2336
2337         /* Zero out the NIC's on-board SRAM. */
2338         ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2339
2340         /* Init again -- zeroing memory may have clobbered some registers. */
2341         if (ti_chipinit(sc)) {
2342                 device_printf(dev, "chip initialization failed\n");
2343                 error = ENXIO;
2344                 goto fail;
2345         }
2346
2347         /*
2348          * Get station address from the EEPROM. Note: the manual states
2349          * that the MAC address is at offset 0x8c, however the data is
2350          * stored as two longwords (since that's how it's loaded into
2351          * the NIC). This means the MAC address is actually preceded
2352          * by two zero bytes. We need to skip over those.
2353          */
2354         if (ti_read_eeprom(sc, eaddr,
2355                                 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2356                 device_printf(dev, "failed to read station address\n");
2357                 error = ENXIO;
2358                 goto fail;
2359         }
2360
2361         /* Allocate the general information block and ring buffers. */
2362         if (bus_dma_tag_create(bus_get_dma_tag(dev),    /* parent */
2363                                 1, 0,                   /* algnmnt, boundary */
2364                                 BUS_SPACE_MAXADDR,      /* lowaddr */
2365                                 BUS_SPACE_MAXADDR,      /* highaddr */
2366                                 NULL, NULL,             /* filter, filterarg */
2367                                 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2368                                 0,                      /* nsegments */
2369                                 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2370                                 0,                      /* flags */
2371                                 NULL, NULL,             /* lockfunc, lockarg */
2372                                 &sc->ti_parent_dmat) != 0) {
2373                 device_printf(dev, "Failed to allocate parent dmat\n");
2374                 error = ENOMEM;
2375                 goto fail;
2376         }
2377
2378         if (bus_dma_tag_create(sc->ti_parent_dmat,      /* parent */
2379                                 PAGE_SIZE, 0,           /* algnmnt, boundary */
2380                                 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2381                                 BUS_SPACE_MAXADDR,      /* highaddr */
2382                                 NULL, NULL,             /* filter, filterarg */
2383                                 sizeof(struct ti_ring_data),    /* maxsize */
2384                                 1,                      /* nsegments */
2385                                 sizeof(struct ti_ring_data),    /* maxsegsize */
2386                                 0,                      /* flags */
2387                                 NULL, NULL,             /* lockfunc, lockarg */
2388                                 &sc->ti_rdata_dmat) != 0) {
2389                 device_printf(dev, "Failed to allocate rdata dmat\n");
2390                 error = ENOMEM;
2391                 goto fail;
2392         }
2393
2394         if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2395                              BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
2396                              &sc->ti_rdata_dmamap) != 0) {
2397                 device_printf(dev, "Failed to allocate rdata memory\n");
2398                 error = ENOMEM;
2399                 goto fail;
2400         }
2401
2402         if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2403                             sc->ti_rdata, sizeof(struct ti_ring_data),
2404                             ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2405                 device_printf(dev, "Failed to load rdata segments\n");
2406                 error = ENOMEM;
2407                 goto fail;
2408         }
2409
2410         bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2411
2412         /* Try to allocate memory for jumbo buffers. */
2413         if (ti_alloc_jumbo_mem(sc)) {
2414                 device_printf(dev, "jumbo buffer allocation failed\n");
2415                 error = ENXIO;
2416                 goto fail;
2417         }
2418
2419         if (bus_dma_tag_create(sc->ti_parent_dmat,      /* parent */
2420                                 1, 0,                   /* algnmnt, boundary */
2421                                 BUS_SPACE_MAXADDR,      /* lowaddr */
2422                                 BUS_SPACE_MAXADDR,      /* highaddr */
2423                                 NULL, NULL,             /* filter, filterarg */
2424                                 MCLBYTES * TI_MAXTXSEGS,/* maxsize */
2425                                 TI_MAXTXSEGS,           /* nsegments */
2426                                 MCLBYTES,               /* maxsegsize */
2427                                 0,                      /* flags */
2428                                 NULL, NULL,             /* lockfunc, lockarg */
2429                                 &sc->ti_mbuftx_dmat) != 0) {
2430                 device_printf(dev, "Failed to allocate rdata dmat\n");
2431                 error = ENOMEM;
2432                 goto fail;
2433         }
2434
2435         if (bus_dma_tag_create(sc->ti_parent_dmat,      /* parent */
2436                                 1, 0,                   /* algnmnt, boundary */
2437                                 BUS_SPACE_MAXADDR,      /* lowaddr */
2438                                 BUS_SPACE_MAXADDR,      /* highaddr */
2439                                 NULL, NULL,             /* filter, filterarg */
2440                                 MCLBYTES,               /* maxsize */
2441                                 1,                      /* nsegments */
2442                                 MCLBYTES,               /* maxsegsize */
2443                                 0,                      /* flags */
2444                                 NULL, NULL,             /* lockfunc, lockarg */
2445                                 &sc->ti_mbufrx_dmat) != 0) {
2446                 device_printf(dev, "Failed to allocate rdata dmat\n");
2447                 error = ENOMEM;
2448                 goto fail;
2449         }
2450
2451         if (ti_alloc_dmamaps(sc)) {
2452                 device_printf(dev, "dma map creation failed\n");
2453                 error = ENXIO;
2454                 goto fail;
2455         }
2456
2457         /*
2458          * We really need a better way to tell a 1000baseTX card
2459          * from a 1000baseSX one, since in theory there could be
2460          * OEMed 1000baseTX cards from lame vendors who aren't
2461          * clever enough to change the PCI ID. For the moment
2462          * though, the AceNIC is the only copper card available.
2463          */
2464         if (pci_get_vendor(dev) == ALT_VENDORID &&
2465             pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2466                 sc->ti_copper = 1;
2467         /* Ok, it's not the only copper card available. */
2468         if (pci_get_vendor(dev) == NG_VENDORID &&
2469             pci_get_device(dev) == NG_DEVICEID_GA620T)
2470                 sc->ti_copper = 1;
2471
2472         /* Set default tuneable values. */
2473         sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2474 #if 0
2475         sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2476 #endif
2477         sc->ti_rx_coal_ticks = 170;
2478         sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2479         sc->ti_rx_max_coal_bds = 64;
2480 #if 0
2481         sc->ti_tx_max_coal_bds = 128;
2482 #endif
2483         sc->ti_tx_max_coal_bds = 32;
2484         sc->ti_tx_buf_ratio = 21;
2485
2486         /* Set up ifnet structure */
2487         ifp->if_softc = sc;
2488         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2489         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2490         ifp->if_ioctl = ti_ioctl;
2491         ifp->if_start = ti_start;
2492         ifp->if_init = ti_init;
2493         ifp->if_baudrate = 1000000000;
2494         ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
2495
2496         /* Set up ifmedia support. */
2497         if (sc->ti_copper) {
2498                 /*
2499                  * Copper cards allow manual 10/100 mode selection,
2500                  * but not manual 1000baseTX mode selection. Why?
2501                  * Becuase currently there's no way to specify the
2502                  * master/slave setting through the firmware interface,
2503                  * so Alteon decided to just bag it and handle it
2504                  * via autonegotiation.
2505                  */
2506                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2507                 ifmedia_add(&sc->ifmedia,
2508                     IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2509                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2510                 ifmedia_add(&sc->ifmedia,
2511                     IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2512                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2513                 ifmedia_add(&sc->ifmedia,
2514                     IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2515         } else {
2516                 /* Fiber cards don't support 10/100 modes. */
2517                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2518                 ifmedia_add(&sc->ifmedia,
2519                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2520         }
2521         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2522         ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2523
2524         /*
2525          * We're assuming here that card initialization is a sequential
2526          * thing.  If it isn't, multiple cards probing at the same time
2527          * could stomp on the list of softcs here.
2528          */
2529
2530         /* Register the device */
2531         sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
2532                            0600, "ti%d", sc->ti_unit);
2533         sc->dev->si_drv1 = sc;
2534
2535         /*
2536          * Call MI attach routine.
2537          */
2538         ether_ifattach(ifp, eaddr);
2539
2540         /* Hook interrupt last to avoid having to lock softc */
2541         error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2542            NULL, ti_intr, sc, &sc->ti_intrhand);
2543
2544         if (error) {
2545                 device_printf(dev, "couldn't set up irq\n");
2546                 goto fail;
2547         }
2548
2549 fail:
2550         if (error)
2551                 ti_detach(dev);
2552
2553         return (error);
2554 }
2555
2556 /*
2557  * Shutdown hardware and free up resources. This can be called any
2558  * time after the mutex has been initialized. It is called in both
2559  * the error case in attach and the normal detach case so it needs
2560  * to be careful about only freeing resources that have actually been
2561  * allocated.
2562  */
2563 static int
2564 ti_detach(dev)
2565         device_t                dev;
2566 {
2567         struct ti_softc         *sc;
2568         struct ifnet            *ifp;
2569
2570         sc = device_get_softc(dev);
2571         if (sc->dev)
2572                 destroy_dev(sc->dev);
2573         KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2574         ifp = sc->ti_ifp;
2575         if (device_is_attached(dev)) {
2576                 ether_ifdetach(ifp);
2577                 TI_LOCK(sc);
2578                 ti_stop(sc);
2579                 TI_UNLOCK(sc);
2580         }
2581
2582         /* These should only be active if attach succeeded */
2583         callout_drain(&sc->ti_watchdog);
2584         bus_generic_detach(dev);
2585         ti_free_dmamaps(sc);
2586         ifmedia_removeall(&sc->ifmedia);
2587
2588 #ifdef TI_PRIVATE_JUMBOS
2589         if (sc->ti_cdata.ti_jumbo_buf)
2590                 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf,
2591                     sc->ti_jumbo_dmamap);
2592 #endif
2593         if (sc->ti_jumbo_dmat)
2594                 bus_dma_tag_destroy(sc->ti_jumbo_dmat);
2595         if (sc->ti_mbuftx_dmat)
2596                 bus_dma_tag_destroy(sc->ti_mbuftx_dmat);
2597         if (sc->ti_mbufrx_dmat)
2598                 bus_dma_tag_destroy(sc->ti_mbufrx_dmat);
2599         if (sc->ti_rdata)
2600                 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2601                                 sc->ti_rdata_dmamap);
2602         if (sc->ti_rdata_dmat)
2603                 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2604         if (sc->ti_parent_dmat)
2605                 bus_dma_tag_destroy(sc->ti_parent_dmat);
2606         if (sc->ti_intrhand)
2607                 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2608         if (sc->ti_irq)
2609                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2610         if (sc->ti_res) {
2611                 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2612                     sc->ti_res);
2613         }
2614         if (ifp)
2615                 if_free(ifp);
2616
2617         mtx_destroy(&sc->ti_mtx);
2618
2619         return (0);
2620 }
2621
2622 #ifdef TI_JUMBO_HDRSPLIT
2623 /*
2624  * If hdr_len is 0, that means that header splitting wasn't done on
2625  * this packet for some reason.  The two most likely reasons are that
2626  * the protocol isn't a supported protocol for splitting, or this
2627  * packet had a fragment offset that wasn't 0.
2628  *
2629  * The header length, if it is non-zero, will always be the length of
2630  * the headers on the packet, but that length could be longer than the
2631  * first mbuf.  So we take the minimum of the two as the actual
2632  * length.
2633  */
2634 static __inline void
2635 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2636 {
2637         int i = 0;
2638         int lengths[4] = {0, 0, 0, 0};
2639         struct mbuf *m, *mp;
2640
2641         if (hdr_len != 0)
2642                 top->m_len = min(hdr_len, top->m_len);
2643         pkt_len -= top->m_len;
2644         lengths[i++] = top->m_len;
2645
2646         mp = top;
2647         for (m = top->m_next; m && pkt_len; m = m->m_next) {
2648                 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2649                 pkt_len -= m->m_len;
2650                 lengths[i++] = m->m_len;
2651                 mp = m;
2652         }
2653
2654 #if 0
2655         if (hdr_len != 0)
2656                 printf("got split packet: ");
2657         else
2658                 printf("got non-split packet: ");
2659
2660         printf("%d,%d,%d,%d = %d\n", lengths[0],
2661             lengths[1], lengths[2], lengths[3],
2662             lengths[0] + lengths[1] + lengths[2] +
2663             lengths[3]);
2664 #endif
2665
2666         if (pkt_len)
2667                 panic("header splitting didn't");
2668
2669         if (m) {
2670                 m_freem(m);
2671                 mp->m_next = NULL;
2672
2673         }
2674         if (mp->m_next != NULL)
2675                 panic("ti_hdr_split: last mbuf in chain should be null");
2676 }
2677 #endif /* TI_JUMBO_HDRSPLIT */
2678
2679 /*
2680  * Frame reception handling. This is called if there's a frame
2681  * on the receive return list.
2682  *
2683  * Note: we have to be able to handle three possibilities here:
2684  * 1) the frame is from the mini receive ring (can only happen)
2685  *    on Tigon 2 boards)
2686  * 2) the frame is from the jumbo recieve ring
2687  * 3) the frame is from the standard receive ring
2688  */
2689
2690 static void
2691 ti_rxeof(sc)
2692         struct ti_softc         *sc;
2693 {
2694         bus_dmamap_t            map;
2695         struct ifnet            *ifp;
2696         struct ti_cmd_desc      cmd;
2697
2698         TI_LOCK_ASSERT(sc);
2699
2700         ifp = sc->ti_ifp;
2701
2702         while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2703                 struct ti_rx_desc       *cur_rx;
2704                 u_int32_t               rxidx;
2705                 struct mbuf             *m = NULL;
2706                 u_int16_t               vlan_tag = 0;
2707                 int                     have_tag = 0;
2708
2709                 cur_rx =
2710                     &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2711                 rxidx = cur_rx->ti_idx;
2712                 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2713
2714                 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2715                         have_tag = 1;
2716                         vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2717                 }
2718
2719                 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2720
2721                         TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2722                         m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2723                         sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2724                         map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2725                         bus_dmamap_sync(sc->ti_jumbo_dmat, map,
2726                             BUS_DMASYNC_POSTREAD);
2727                         bus_dmamap_unload(sc->ti_jumbo_dmat, map);
2728                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2729                                 ifp->if_ierrors++;
2730                                 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2731                                 continue;
2732                         }
2733                         if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2734                                 ifp->if_ierrors++;
2735                                 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2736                                 continue;
2737                         }
2738 #ifdef TI_PRIVATE_JUMBOS
2739                         m->m_len = cur_rx->ti_len;
2740 #else /* TI_PRIVATE_JUMBOS */
2741 #ifdef TI_JUMBO_HDRSPLIT
2742                         if (sc->ti_hdrsplit)
2743                                 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2744                                              cur_rx->ti_len, rxidx);
2745                         else
2746 #endif /* TI_JUMBO_HDRSPLIT */
2747                         m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2748 #endif /* TI_PRIVATE_JUMBOS */
2749                 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2750                         TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2751                         m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2752                         sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2753                         map = sc->ti_cdata.ti_rx_mini_maps[rxidx];
2754                         bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2755                             BUS_DMASYNC_POSTREAD);
2756                         bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2757                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2758                                 ifp->if_ierrors++;
2759                                 ti_newbuf_mini(sc, sc->ti_mini, m);
2760                                 continue;
2761                         }
2762                         if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2763                                 ifp->if_ierrors++;
2764                                 ti_newbuf_mini(sc, sc->ti_mini, m);
2765                                 continue;
2766                         }
2767                         m->m_len = cur_rx->ti_len;
2768                 } else {
2769                         TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2770                         m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2771                         sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2772                         map = sc->ti_cdata.ti_rx_std_maps[rxidx];
2773                         bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2774                             BUS_DMASYNC_POSTREAD);
2775                         bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2776                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2777                                 ifp->if_ierrors++;
2778                                 ti_newbuf_std(sc, sc->ti_std, m);
2779                                 continue;
2780                         }
2781                         if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2782                                 ifp->if_ierrors++;
2783                                 ti_newbuf_std(sc, sc->ti_std, m);
2784                                 continue;
2785                         }
2786                         m->m_len = cur_rx->ti_len;
2787                 }
2788
2789                 m->m_pkthdr.len = cur_rx->ti_len;
2790                 ifp->if_ipackets++;
2791                 m->m_pkthdr.rcvif = ifp;
2792
2793                 if (ifp->if_hwassist) {
2794                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2795                             CSUM_DATA_VALID;
2796                         if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2797                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2798                         m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2799                 }
2800
2801                 /*
2802                  * If we received a packet with a vlan tag,
2803                  * tag it before passing the packet upward.
2804                  */
2805                 if (have_tag) {
2806                         m->m_pkthdr.ether_vtag = vlan_tag;
2807                         m->m_flags |= M_VLANTAG;
2808                 }
2809                 TI_UNLOCK(sc);
2810                 (*ifp->if_input)(ifp, m);
2811                 TI_LOCK(sc);
2812         }
2813
2814         /* Only necessary on the Tigon 1. */
2815         if (sc->ti_hwrev == TI_HWREV_TIGON)
2816                 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2817                     sc->ti_rx_saved_considx);
2818
2819         TI_UPDATE_STDPROD(sc, sc->ti_std);
2820         TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2821         TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2822 }
2823
2824 static void
2825 ti_txeof(sc)
2826         struct ti_softc         *sc;
2827 {
2828         struct ti_txdesc        *txd;
2829         struct ti_tx_desc       txdesc;
2830         struct ti_tx_desc       *cur_tx = NULL;
2831         struct ifnet            *ifp;
2832         int                     idx;
2833
2834         ifp = sc->ti_ifp;
2835
2836         txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2837         if (txd == NULL)
2838                 return;
2839         /*
2840          * Go through our tx ring and free mbufs for those
2841          * frames that have been sent.
2842          */
2843         for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2844             TI_INC(idx, TI_TX_RING_CNT)) {
2845                 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2846                         ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2847                             sizeof(txdesc), &txdesc);
2848                         cur_tx = &txdesc;
2849                 } else
2850                         cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2851                 sc->ti_txcnt--;
2852                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2853                 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2854                         continue;
2855                 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2856                     BUS_DMASYNC_POSTWRITE);
2857                 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2858
2859                 ifp->if_opackets++;
2860                 m_freem(txd->tx_m);
2861                 txd->tx_m = NULL;
2862                 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2863                 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2864                 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2865         }
2866         sc->ti_tx_saved_considx = idx;
2867
2868         sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0;
2869 }
2870
2871 static void
2872 ti_intr(xsc)
2873         void                    *xsc;
2874 {
2875         struct ti_softc         *sc;
2876         struct ifnet            *ifp;
2877
2878         sc = xsc;
2879         TI_LOCK(sc);
2880         ifp = sc->ti_ifp;
2881
2882 /*#ifdef notdef*/
2883         /* Avoid this for now -- checking this register is expensive. */
2884         /* Make sure this is really our interrupt. */
2885         if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2886                 TI_UNLOCK(sc);
2887                 return;
2888         }
2889 /*#endif*/
2890
2891         /* Ack interrupt and stop others from occuring. */
2892         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2893
2894         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2895                 /* Check RX return ring producer/consumer */
2896                 ti_rxeof(sc);
2897
2898                 /* Check TX ring producer/consumer */
2899                 ti_txeof(sc);
2900         }
2901
2902         ti_handle_events(sc);
2903
2904         /* Re-enable interrupts. */
2905         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2906
2907         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2908             ifp->if_snd.ifq_head != NULL)
2909                 ti_start_locked(ifp);
2910
2911         TI_UNLOCK(sc);
2912 }
2913
2914 static void
2915 ti_stats_update(sc)
2916         struct ti_softc         *sc;
2917 {
2918         struct ifnet            *ifp;
2919
2920         ifp = sc->ti_ifp;
2921
2922         bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2923             BUS_DMASYNC_POSTREAD);
2924
2925         ifp->if_collisions +=
2926            (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2927            sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2928            sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2929            sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2930            ifp->if_collisions;
2931
2932         bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2933             BUS_DMASYNC_PREREAD);
2934 }
2935
2936 /*
2937  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2938  * pointers to descriptors.
2939  */
2940 static int
2941 ti_encap(sc, m_head)
2942         struct ti_softc         *sc;
2943         struct mbuf             **m_head;
2944 {
2945         struct ti_txdesc        *txd;
2946         struct ti_tx_desc       *f;
2947         struct ti_tx_desc       txdesc;
2948         struct mbuf             *m;
2949         bus_dma_segment_t       txsegs[TI_MAXTXSEGS];
2950         u_int16_t               csum_flags;
2951         int                     error, frag, i, nseg;
2952
2953         if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
2954                 return (ENOBUFS);
2955
2956         error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2957             *m_head, txsegs, &nseg, 0);
2958         if (error == EFBIG) {
2959                 m = m_defrag(*m_head, M_DONTWAIT);
2960                 if (m == NULL) {
2961                         m_freem(*m_head);
2962                         *m_head = NULL;
2963                         return (ENOMEM);
2964                 }
2965                 *m_head = m;
2966                 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat,
2967                     txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2968                 if (error) {
2969                         m_freem(*m_head);
2970                         *m_head = NULL;
2971                         return (error);
2972                 }
2973         } else if (error != 0)
2974                 return (error);
2975         if (nseg == 0) {
2976                 m_freem(*m_head);
2977                 *m_head = NULL;
2978                 return (EIO);
2979         }
2980
2981         if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
2982                 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2983                 return (ENOBUFS);
2984         }
2985
2986         m = *m_head;
2987         csum_flags = 0;
2988         if (m->m_pkthdr.csum_flags) {
2989                 if (m->m_pkthdr.csum_flags & CSUM_IP)
2990                         csum_flags |= TI_BDFLAG_IP_CKSUM;
2991                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2992                         csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2993                 if (m->m_flags & M_LASTFRAG)
2994                         csum_flags |= TI_BDFLAG_IP_FRAG_END;
2995                 else if (m->m_flags & M_FRAG)
2996                         csum_flags |= TI_BDFLAG_IP_FRAG;
2997         }
2998
2999         bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
3000             BUS_DMASYNC_PREWRITE);
3001         bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
3002             BUS_DMASYNC_PREWRITE);
3003
3004         frag = sc->ti_tx_saved_prodidx;
3005         for (i = 0; i < nseg; i++) {
3006                 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3007                         bzero(&txdesc, sizeof(txdesc));
3008                         f = &txdesc;
3009                 } else
3010                         f = &sc->ti_rdata->ti_tx_ring[frag];
3011                 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
3012                 f->ti_len = txsegs[i].ds_len;
3013                 f->ti_flags = csum_flags;
3014                 if (m->m_flags & M_VLANTAG) {
3015                         f->ti_flags |= TI_BDFLAG_VLAN_TAG;
3016                         f->ti_vlan_tag = m->m_pkthdr.ether_vtag & 0xfff;
3017                 } else {
3018                         f->ti_vlan_tag = 0;
3019                 }
3020
3021                 if (sc->ti_hwrev == TI_HWREV_TIGON)
3022                         ti_mem_write(sc, TI_TX_RING_BASE + frag *
3023                             sizeof(txdesc), sizeof(txdesc), &txdesc);
3024                 TI_INC(frag, TI_TX_RING_CNT);
3025         }
3026
3027         sc->ti_tx_saved_prodidx = frag;
3028         /* set TI_BDFLAG_END on the last descriptor */
3029         frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
3030         if (sc->ti_hwrev == TI_HWREV_TIGON) {
3031                 txdesc.ti_flags |= TI_BDFLAG_END;
3032                 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
3033                     sizeof(txdesc), &txdesc);
3034         } else
3035                 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
3036
3037         STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
3038         STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
3039         txd->tx_m = m;
3040         sc->ti_txcnt += nseg;
3041
3042         return (0);
3043 }
3044
3045 static void
3046 ti_start(ifp)
3047         struct ifnet            *ifp;
3048 {
3049         struct ti_softc         *sc;
3050
3051         sc = ifp->if_softc;
3052         TI_LOCK(sc);
3053         ti_start_locked(ifp);
3054         TI_UNLOCK(sc);
3055 }
3056
3057 /*
3058  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3059  * to the mbuf data regions directly in the transmit descriptors.
3060  */
3061 static void
3062 ti_start_locked(ifp)
3063         struct ifnet            *ifp;
3064 {
3065         struct ti_softc         *sc;
3066         struct mbuf             *m_head = NULL;
3067         int                     enq = 0;
3068
3069         sc = ifp->if_softc;
3070
3071         for (; ifp->if_snd.ifq_head != NULL &&
3072             sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3073                 IF_DEQUEUE(&ifp->if_snd, m_head);
3074                 if (m_head == NULL)
3075                         break;
3076
3077                 /*
3078                  * XXX
3079                  * safety overkill.  If this is a fragmented packet chain
3080                  * with delayed TCP/UDP checksums, then only encapsulate
3081                  * it if we have enough descriptors to handle the entire
3082                  * chain at once.
3083                  * (paranoia -- may not actually be needed)
3084                  */
3085                 if (m_head->m_flags & M_FIRSTFRAG &&
3086                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3087                         if ((TI_TX_RING_CNT - sc->ti_txcnt) <
3088                             m_head->m_pkthdr.csum_data + 16) {
3089                                 IF_PREPEND(&ifp->if_snd, m_head);
3090                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3091                                 break;
3092                         }
3093                 }
3094
3095                 /*
3096                  * Pack the data into the transmit ring. If we
3097                  * don't have room, set the OACTIVE flag and wait
3098                  * for the NIC to drain the ring.
3099                  */
3100                 if (ti_encap(sc, &m_head)) {
3101                         if (m_head == NULL)
3102                                 break;
3103                         IF_PREPEND(&ifp->if_snd, m_head);
3104                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3105                         break;
3106                 }
3107
3108                 enq++;
3109                 /*
3110                  * If there's a BPF listener, bounce a copy of this frame
3111                  * to him.
3112                  */
3113                 ETHER_BPF_MTAP(ifp, m_head);
3114         }
3115
3116         if (enq > 0) {
3117                 /* Transmit */
3118                 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3119
3120                 /*
3121                  * Set a timeout in case the chip goes out to lunch.
3122                  */
3123                 sc->ti_timer = 5;
3124         }
3125 }
3126
3127 static void
3128 ti_init(xsc)
3129         void                    *xsc;
3130 {
3131         struct ti_softc         *sc;
3132
3133         sc = xsc;
3134         TI_LOCK(sc);
3135         ti_init_locked(sc);
3136         TI_UNLOCK(sc);
3137 }
3138
3139 static void
3140 ti_init_locked(xsc)
3141         void                    *xsc;
3142 {
3143         struct ti_softc         *sc = xsc;
3144
3145         /* Cancel pending I/O and flush buffers. */
3146         ti_stop(sc);
3147
3148         /* Init the gen info block, ring control blocks and firmware. */
3149         if (ti_gibinit(sc)) {
3150                 device_printf(sc->ti_dev, "initialization failure\n");
3151                 return;
3152         }
3153 }
3154
3155 static void ti_init2(sc)
3156         struct ti_softc         *sc;
3157 {
3158         struct ti_cmd_desc      cmd;
3159         struct ifnet            *ifp;
3160         u_int8_t                *ea;
3161         struct ifmedia          *ifm;
3162         int                     tmp;
3163
3164         TI_LOCK_ASSERT(sc);
3165
3166         ifp = sc->ti_ifp;
3167
3168         /* Specify MTU and interface index. */
3169         CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
3170         CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3171             ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3172         TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3173
3174         /* Load our MAC address. */
3175         ea = IF_LLADDR(sc->ti_ifp);
3176         CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3177         CSR_WRITE_4(sc, TI_GCR_PAR1,
3178             (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3179         TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3180
3181         /* Enable or disable promiscuous mode as needed. */
3182         if (ifp->if_flags & IFF_PROMISC) {
3183                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3184         } else {
3185                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3186         }
3187
3188         /* Program multicast filter. */
3189         ti_setmulti(sc);
3190
3191         /*
3192          * If this is a Tigon 1, we should tell the
3193          * firmware to use software packet filtering.
3194          */
3195         if (sc->ti_hwrev == TI_HWREV_TIGON) {
3196                 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3197         }
3198
3199         /* Init RX ring. */
3200         ti_init_rx_ring_std(sc);
3201
3202         /* Init jumbo RX ring. */
3203         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3204                 ti_init_rx_ring_jumbo(sc);
3205
3206         /*
3207          * If this is a Tigon 2, we can also configure the
3208          * mini ring.
3209          */
3210         if (sc->ti_hwrev == TI_HWREV_TIGON_II)
3211                 ti_init_rx_ring_mini(sc);
3212
3213         CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3214         sc->ti_rx_saved_considx = 0;
3215
3216         /* Init TX ring. */
3217         ti_init_tx_ring(sc);
3218
3219         /* Tell firmware we're alive. */
3220         TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3221
3222         /* Enable host interrupts. */
3223         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3224
3225         ifp->if_drv_flags |= IFF_DRV_RUNNING;
3226         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3227         callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3228
3229         /*
3230          * Make sure to set media properly. We have to do this
3231          * here since we have to issue commands in order to set
3232          * the link negotiation and we can't issue commands until
3233          * the firmware is running.
3234          */
3235         ifm = &sc->ifmedia;
3236         tmp = ifm->ifm_media;
3237         ifm->ifm_media = ifm->ifm_cur->ifm_media;
3238         ti_ifmedia_upd(ifp);
3239         ifm->ifm_media = tmp;
3240 }
3241
3242 /*
3243  * Set media options.
3244  */
3245 static int
3246 ti_ifmedia_upd(ifp)
3247         struct ifnet            *ifp;
3248 {
3249         struct ti_softc         *sc;
3250         struct ifmedia          *ifm;
3251         struct ti_cmd_desc      cmd;
3252         u_int32_t               flowctl;
3253
3254         sc = ifp->if_softc;
3255         ifm = &sc->ifmedia;
3256
3257         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3258                 return (EINVAL);
3259
3260         flowctl = 0;
3261
3262         switch (IFM_SUBTYPE(ifm->ifm_media)) {
3263         case IFM_AUTO:
3264                 /*
3265                  * Transmit flow control doesn't work on the Tigon 1.
3266                  */
3267                 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3268
3269                 /*
3270                  * Transmit flow control can also cause problems on the
3271                  * Tigon 2, apparantly with both the copper and fiber
3272                  * boards.  The symptom is that the interface will just
3273                  * hang.  This was reproduced with Alteon 180 switches.
3274                  */
3275 #if 0
3276                 if (sc->ti_hwrev != TI_HWREV_TIGON)
3277                         flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3278 #endif
3279
3280                 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3281                     TI_GLNK_FULL_DUPLEX| flowctl |
3282                     TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3283
3284                 flowctl = TI_LNK_RX_FLOWCTL_Y;
3285 #if 0
3286                 if (sc->ti_hwrev != TI_HWREV_TIGON)
3287                         flowctl |= TI_LNK_TX_FLOWCTL_Y;
3288 #endif
3289
3290                 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3291                     TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3292                     TI_LNK_AUTONEGENB|TI_LNK_ENB);
3293                 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3294                     TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3295                 break;
3296         case IFM_1000_SX:
3297         case IFM_1000_T:
3298                 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3299 #if 0
3300                 if (sc->ti_hwrev != TI_HWREV_TIGON)
3301                         flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3302 #endif
3303
3304                 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3305                     flowctl |TI_GLNK_ENB);
3306                 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3307                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3308                         TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3309                 }
3310                 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3311                     TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3312                 break;
3313         case IFM_100_FX:
3314         case IFM_10_FL:
3315         case IFM_100_TX:
3316         case IFM_10_T:
3317                 flowctl = TI_LNK_RX_FLOWCTL_Y;
3318 #if 0
3319                 if (sc->ti_hwrev != TI_HWREV_TIGON)
3320                         flowctl |= TI_LNK_TX_FLOWCTL_Y;
3321 #endif
3322
3323                 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3324                 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3325                 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3326                     IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3327                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3328                 } else {
3329                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3330                 }
3331                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3332                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3333                 } else {
3334                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3335                 }
3336                 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3337                     TI_CMD_CODE_NEGOTIATE_10_100, 0);
3338                 break;
3339         }
3340
3341         return (0);
3342 }
3343
3344 /*
3345  * Report current media status.
3346  */
3347 static void
3348 ti_ifmedia_sts(ifp, ifmr)
3349         struct ifnet            *ifp;
3350         struct ifmediareq       *ifmr;
3351 {
3352         struct ti_softc         *sc;
3353         u_int32_t               media = 0;
3354
3355         sc = ifp->if_softc;
3356
3357         ifmr->ifm_status = IFM_AVALID;
3358         ifmr->ifm_active = IFM_ETHER;
3359
3360         if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
3361                 return;
3362
3363         ifmr->ifm_status |= IFM_ACTIVE;
3364
3365         if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3366                 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3367                 if (sc->ti_copper)
3368                         ifmr->ifm_active |= IFM_1000_T;
3369                 else
3370                         ifmr->ifm_active |= IFM_1000_SX;
3371                 if (media & TI_GLNK_FULL_DUPLEX)
3372                         ifmr->ifm_active |= IFM_FDX;
3373                 else
3374                         ifmr->ifm_active |= IFM_HDX;
3375         } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3376                 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3377                 if (sc->ti_copper) {
3378                         if (media & TI_LNK_100MB)
3379                                 ifmr->ifm_active |= IFM_100_TX;
3380                         if (media & TI_LNK_10MB)
3381                                 ifmr->ifm_active |= IFM_10_T;
3382                 } else {
3383                         if (media & TI_LNK_100MB)
3384                                 ifmr->ifm_active |= IFM_100_FX;
3385                         if (media & TI_LNK_10MB)
3386                                 ifmr->ifm_active |= IFM_10_FL;
3387                 }
3388                 if (media & TI_LNK_FULL_DUPLEX)
3389                         ifmr->ifm_active |= IFM_FDX;
3390                 if (media & TI_LNK_HALF_DUPLEX)
3391                         ifmr->ifm_active |= IFM_HDX;
3392         }
3393 }
3394
3395 static int
3396 ti_ioctl(ifp, command, data)
3397         struct ifnet            *ifp;
3398         u_long                  command;
3399         caddr_t                 data;
3400 {
3401         struct ti_softc         *sc = ifp->if_softc;
3402         struct ifreq            *ifr = (struct ifreq *) data;
3403         int                     mask, error = 0;
3404         struct ti_cmd_desc      cmd;
3405
3406         switch (command) {
3407         case SIOCSIFMTU:
3408                 TI_LOCK(sc);
3409                 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3410                         error = EINVAL;
3411                 else {
3412                         ifp->if_mtu = ifr->ifr_mtu;
3413                         ti_init_locked(sc);
3414                 }
3415                 TI_UNLOCK(sc);
3416                 break;
3417         case SIOCSIFFLAGS:
3418                 TI_LOCK(sc);
3419                 if (ifp->if_flags & IFF_UP) {
3420                         /*
3421                          * If only the state of the PROMISC flag changed,
3422                          * then just use the 'set promisc mode' command
3423                          * instead of reinitializing the entire NIC. Doing
3424                          * a full re-init means reloading the firmware and
3425                          * waiting for it to start up, which may take a
3426                          * second or two.
3427                          */
3428                         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3429                             ifp->if_flags & IFF_PROMISC &&
3430                             !(sc->ti_if_flags & IFF_PROMISC)) {
3431                                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3432                                     TI_CMD_CODE_PROMISC_ENB, 0);
3433                         } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3434                             !(ifp->if_flags & IFF_PROMISC) &&
3435                             sc->ti_if_flags & IFF_PROMISC) {
3436                                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3437                                     TI_CMD_CODE_PROMISC_DIS, 0);
3438                         } else
3439                                 ti_init_locked(sc);
3440                 } else {
3441                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3442                                 ti_stop(sc);
3443                         }
3444                 }
3445                 sc->ti_if_flags = ifp->if_flags;
3446                 TI_UNLOCK(sc);
3447                 break;
3448         case SIOCADDMULTI:
3449         case SIOCDELMULTI:
3450                 TI_LOCK(sc);
3451                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3452                         ti_setmulti(sc);
3453                 TI_UNLOCK(sc);
3454                 break;
3455         case SIOCSIFMEDIA:
3456         case SIOCGIFMEDIA:
3457                 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3458                 break;
3459         case SIOCSIFCAP:
3460                 TI_LOCK(sc);
3461                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3462                 if (mask & IFCAP_HWCSUM) {
3463                         if (IFCAP_HWCSUM & ifp->if_capenable)
3464                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
3465                         else
3466                                 ifp->if_capenable |= IFCAP_HWCSUM;
3467                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3468                                 ti_init_locked(sc);
3469                 }
3470                 TI_UNLOCK(sc);
3471                 break;
3472         default:
3473                 error = ether_ioctl(ifp, command, data);
3474                 break;
3475         }
3476
3477         return (error);
3478 }
3479
3480 static int
3481 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3482 {
3483         struct ti_softc *sc;
3484
3485         sc = dev->si_drv1;
3486         if (sc == NULL)
3487                 return (ENODEV);
3488
3489         TI_LOCK(sc);
3490         sc->ti_flags |= TI_FLAG_DEBUGING;
3491         TI_UNLOCK(sc);
3492
3493         return (0);
3494 }
3495
3496 static int
3497 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3498 {
3499         struct ti_softc *sc;
3500
3501         sc = dev->si_drv1;
3502         if (sc == NULL)
3503                 return (ENODEV);
3504
3505         TI_LOCK(sc);
3506         sc->ti_flags &= ~TI_FLAG_DEBUGING;
3507         TI_UNLOCK(sc);
3508
3509         return (0);
3510 }
3511
3512 /*
3513  * This ioctl routine goes along with the Tigon character device.
3514  */
3515 static int
3516 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3517     struct thread *td)
3518 {
3519         int error;
3520         struct ti_softc *sc;
3521
3522         sc = dev->si_drv1;
3523         if (sc == NULL)
3524                 return (ENODEV);
3525
3526         error = 0;
3527
3528         switch (cmd) {
3529         case TIIOCGETSTATS:
3530         {
3531                 struct ti_stats *outstats;
3532
3533                 outstats = (struct ti_stats *)addr;
3534
3535                 TI_LOCK(sc);
3536                 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3537                       sizeof(struct ti_stats));
3538                 TI_UNLOCK(sc);
3539                 break;
3540         }
3541         case TIIOCGETPARAMS:
3542         {
3543                 struct ti_params        *params;
3544
3545                 params = (struct ti_params *)addr;
3546
3547                 TI_LOCK(sc);
3548                 params->ti_stat_ticks = sc->ti_stat_ticks;
3549                 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3550                 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3551                 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3552                 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3553                 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3554                 params->param_mask = TI_PARAM_ALL;
3555                 TI_UNLOCK(sc);
3556
3557                 error = 0;
3558
3559                 break;
3560         }
3561         case TIIOCSETPARAMS:
3562         {
3563                 struct ti_params *params;
3564
3565                 params = (struct ti_params *)addr;
3566
3567                 TI_LOCK(sc);
3568                 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3569                         sc->ti_stat_ticks = params->ti_stat_ticks;
3570                         CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3571                 }
3572
3573                 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3574                         sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3575                         CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3576                                     sc->ti_rx_coal_ticks);
3577                 }
3578
3579                 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3580                         sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3581                         CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3582                                     sc->ti_tx_coal_ticks);
3583                 }
3584
3585                 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3586                         sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3587                         CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3588                                     sc->ti_rx_max_coal_bds);
3589                 }
3590
3591                 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3592                         sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3593                         CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3594                                     sc->ti_tx_max_coal_bds);
3595                 }
3596
3597                 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3598                         sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3599                         CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3600                                     sc->ti_tx_buf_ratio);
3601                 }
3602                 TI_UNLOCK(sc);
3603
3604                 error = 0;
3605
3606                 break;
3607         }
3608         case TIIOCSETTRACE: {
3609                 ti_trace_type   trace_type;
3610
3611                 trace_type = *(ti_trace_type *)addr;
3612
3613                 /*
3614                  * Set tracing to whatever the user asked for.  Setting
3615                  * this register to 0 should have the effect of disabling
3616                  * tracing.
3617                  */
3618                 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3619
3620                 error = 0;
3621
3622                 break;
3623         }
3624         case TIIOCGETTRACE: {
3625                 struct ti_trace_buf     *trace_buf;
3626                 u_int32_t               trace_start, cur_trace_ptr, trace_len;
3627
3628                 trace_buf = (struct ti_trace_buf *)addr;
3629
3630                 TI_LOCK(sc);
3631                 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3632                 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3633                 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3634
3635 #if 0
3636                 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3637                        "trace_len = %d\n", trace_start,
3638                        cur_trace_ptr, trace_len);
3639                 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3640                        trace_buf->buf_len);
3641 #endif
3642
3643                 error = ti_copy_mem(sc, trace_start, min(trace_len,
3644                                     trace_buf->buf_len),
3645                                     (caddr_t)trace_buf->buf, 1, 1);
3646
3647                 if (error == 0) {
3648                         trace_buf->fill_len = min(trace_len,
3649                                                   trace_buf->buf_len);
3650                         if (cur_trace_ptr < trace_start)
3651                                 trace_buf->cur_trace_ptr =
3652                                         trace_start - cur_trace_ptr;
3653                         else
3654                                 trace_buf->cur_trace_ptr =
3655                                         cur_trace_ptr - trace_start;
3656                 } else
3657                         trace_buf->fill_len = 0;
3658                 TI_UNLOCK(sc);
3659
3660                 break;
3661         }
3662
3663         /*
3664          * For debugging, five ioctls are needed:
3665          * ALT_ATTACH
3666          * ALT_READ_TG_REG
3667          * ALT_WRITE_TG_REG
3668          * ALT_READ_TG_MEM
3669          * ALT_WRITE_TG_MEM
3670          */
3671         case ALT_ATTACH:
3672                 /*
3673                  * From what I can tell, Alteon's Solaris Tigon driver
3674                  * only has one character device, so you have to attach
3675                  * to the Tigon board you're interested in.  This seems
3676                  * like a not-so-good way to do things, since unless you
3677                  * subsequently specify the unit number of the device
3678                  * you're interested in every ioctl, you'll only be
3679                  * able to debug one board at a time.
3680                  */
3681                 error = 0;
3682                 break;
3683         case ALT_READ_TG_MEM:
3684         case ALT_WRITE_TG_MEM:
3685         {
3686                 struct tg_mem *mem_param;
3687                 u_int32_t sram_end, scratch_end;
3688
3689                 mem_param = (struct tg_mem *)addr;
3690
3691                 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3692                         sram_end = TI_END_SRAM_I;
3693                         scratch_end = TI_END_SCRATCH_I;
3694                 } else {
3695                         sram_end = TI_END_SRAM_II;
3696                         scratch_end = TI_END_SCRATCH_II;
3697                 }
3698
3699                 /*
3700                  * For now, we'll only handle accessing regular SRAM,
3701                  * nothing else.
3702                  */
3703                 TI_LOCK(sc);
3704                 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3705                  && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3706                         /*
3707                          * In this instance, we always copy to/from user
3708                          * space, so the user space argument is set to 1.
3709                          */
3710                         error = ti_copy_mem(sc, mem_param->tgAddr,
3711                                             mem_param->len,
3712                                             mem_param->userAddr, 1,
3713                                             (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3714                 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3715                         && (mem_param->tgAddr <= scratch_end)) {
3716                         error = ti_copy_scratch(sc, mem_param->tgAddr,
3717                                                 mem_param->len,
3718                                                 mem_param->userAddr, 1,
3719                                                 (cmd == ALT_READ_TG_MEM) ?
3720                                                 1 : 0, TI_PROCESSOR_A);
3721                 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3722                         && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3723                         if (sc->ti_hwrev == TI_HWREV_TIGON) {
3724                                 if_printf(sc->ti_ifp,
3725                                     "invalid memory range for Tigon I\n");
3726                                 error = EINVAL;
3727                                 break;
3728                         }
3729                         error = ti_copy_scratch(sc, mem_param->tgAddr -
3730                                                 TI_SCRATCH_DEBUG_OFF,
3731                                                 mem_param->len,
3732                                                 mem_param->userAddr, 1,
3733                                                 (cmd == ALT_READ_TG_MEM) ?
3734                                                 1 : 0, TI_PROCESSOR_B);
3735                 } else {
3736                         if_printf(sc->ti_ifp, "memory address %#x len %d is "
3737                                 "out of supported range\n",
3738                                 mem_param->tgAddr, mem_param->len);
3739                         error = EINVAL;
3740                 }
3741                 TI_UNLOCK(sc);
3742
3743                 break;
3744         }
3745         case ALT_READ_TG_REG:
3746         case ALT_WRITE_TG_REG:
3747         {
3748                 struct tg_reg   *regs;
3749                 u_int32_t       tmpval;
3750
3751                 regs = (struct tg_reg *)addr;
3752
3753                 /*
3754                  * Make sure the address in question isn't out of range.
3755                  */
3756                 if (regs->addr > TI_REG_MAX) {
3757                         error = EINVAL;
3758                         break;
3759                 }
3760                 TI_LOCK(sc);
3761                 if (cmd == ALT_READ_TG_REG) {
3762                         bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3763                                                 regs->addr, &tmpval, 1);
3764                         regs->data = ntohl(tmpval);
3765 #if 0
3766                         if ((regs->addr == TI_CPU_STATE)
3767                          || (regs->addr == TI_CPU_CTL_B)) {
3768                                 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3769                                        regs->addr, tmpval);
3770                         }
3771 #endif
3772                 } else {
3773                         tmpval = htonl(regs->data);
3774                         bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3775                                                  regs->addr, &tmpval, 1);
3776                 }
3777                 TI_UNLOCK(sc);
3778
3779                 break;
3780         }
3781         default:
3782                 error = ENOTTY;
3783                 break;
3784         }
3785         return (error);
3786 }
3787
3788 static void
3789 ti_watchdog(void *arg)
3790 {
3791         struct ti_softc         *sc;
3792         struct ifnet            *ifp;
3793
3794         sc = arg;
3795         TI_LOCK_ASSERT(sc);
3796         callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3797         if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3798                 return;
3799
3800         /*
3801          * When we're debugging, the chip is often stopped for long periods
3802          * of time, and that would normally cause the watchdog timer to fire.
3803          * Since that impedes debugging, we don't want to do that.
3804          */
3805         if (sc->ti_flags & TI_FLAG_DEBUGING)
3806                 return;
3807
3808         ifp = sc->ti_ifp;
3809         if_printf(ifp, "watchdog timeout -- resetting\n");
3810         ti_stop(sc);
3811         ti_init_locked(sc);
3812
3813         ifp->if_oerrors++;
3814 }
3815
3816 /*
3817  * Stop the adapter and free any mbufs allocated to the
3818  * RX and TX lists.
3819  */
3820 static void
3821 ti_stop(sc)
3822         struct ti_softc         *sc;
3823 {
3824         struct ifnet            *ifp;
3825         struct ti_cmd_desc      cmd;
3826
3827         TI_LOCK_ASSERT(sc);
3828
3829         ifp = sc->ti_ifp;
3830
3831         /* Disable host interrupts. */
3832         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3833         /*
3834          * Tell firmware we're shutting down.
3835          */
3836         TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3837
3838         /* Halt and reinitialize. */
3839         if (ti_chipinit(sc) != 0)
3840                 return;
3841         ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3842         if (ti_chipinit(sc) != 0)
3843                 return;
3844
3845         /* Free the RX lists. */
3846         ti_free_rx_ring_std(sc);
3847
3848         /* Free jumbo RX list. */
3849         ti_free_rx_ring_jumbo(sc);
3850
3851         /* Free mini RX list. */
3852         ti_free_rx_ring_mini(sc);
3853
3854         /* Free TX buffers. */
3855         ti_free_tx_ring(sc);
3856
3857         sc->ti_ev_prodidx.ti_idx = 0;
3858         sc->ti_return_prodidx.ti_idx = 0;
3859         sc->ti_tx_considx.ti_idx = 0;
3860         sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3861
3862         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3863         callout_stop(&sc->ti_watchdog);
3864 }
3865
3866 /*
3867  * Stop all chip I/O so that the kernel's probe routines don't
3868  * get confused by errant DMAs when rebooting.
3869  */
3870 static int
3871 ti_shutdown(dev)
3872         device_t                dev;
3873 {
3874         struct ti_softc         *sc;
3875
3876         sc = device_get_softc(dev);
3877         TI_LOCK(sc);
3878         ti_chipinit(sc);
3879         TI_UNLOCK(sc);
3880
3881         return (0);
3882 }