2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
94 #include <sys/sf_buf.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
102 #include <net/if_vlan_var.h>
106 #include <netinet/in_systm.h>
107 #include <netinet/in.h>
108 #include <netinet/ip.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 /* #define TI_PRIVATE_JUMBOS */
116 #ifndef TI_PRIVATE_JUMBOS
118 #include <vm/vm_page.h>
121 #include <dev/pci/pcireg.h>
122 #include <dev/pci/pcivar.h>
124 #include <sys/tiio.h>
125 #include <dev/ti/if_tireg.h>
126 #include <dev/ti/ti_fw.h>
127 #include <dev/ti/ti_fw2.h>
129 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
131 * We can only turn on header splitting if we're using extended receive
134 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
135 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
136 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
144 * Various supported device vendors/types and their names.
147 static const struct ti_type const ti_devs[] = {
148 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
149 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
150 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
151 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
152 { TC_VENDORID, TC_DEVICEID_3C985,
153 "3Com 3c985-SX Gigabit Ethernet" },
154 { NG_VENDORID, NG_DEVICEID_GA620,
155 "Netgear GA620 1000baseSX Gigabit Ethernet" },
156 { NG_VENDORID, NG_DEVICEID_GA620T,
157 "Netgear GA620 1000baseT Gigabit Ethernet" },
158 { SGI_VENDORID, SGI_DEVICEID_TIGON,
159 "Silicon Graphics Gigabit Ethernet" },
160 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
161 "Farallon PN9000SX Gigabit Ethernet" },
166 static d_open_t ti_open;
167 static d_close_t ti_close;
168 static d_ioctl_t ti_ioctl2;
170 static struct cdevsw ti_cdevsw = {
171 .d_version = D_VERSION,
175 .d_ioctl = ti_ioctl2,
179 static int ti_probe(device_t);
180 static int ti_attach(device_t);
181 static int ti_detach(device_t);
182 static void ti_txeof(struct ti_softc *);
183 static void ti_rxeof(struct ti_softc *);
185 static void ti_stats_update(struct ti_softc *);
186 static int ti_encap(struct ti_softc *, struct mbuf **);
188 static void ti_intr(void *);
189 static void ti_start(struct ifnet *);
190 static void ti_start_locked(struct ifnet *);
191 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
192 static void ti_init(void *);
193 static void ti_init_locked(void *);
194 static void ti_init2(struct ti_softc *);
195 static void ti_stop(struct ti_softc *);
196 static void ti_watchdog(void *);
197 static int ti_shutdown(device_t);
198 static int ti_ifmedia_upd(struct ifnet *);
199 static int ti_ifmedia_upd_locked(struct ti_softc *);
200 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
202 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
203 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
204 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
206 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
207 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
208 static void ti_setmulti(struct ti_softc *);
210 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
211 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
212 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
213 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
215 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
217 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
218 static void ti_loadfw(struct ti_softc *);
219 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
220 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
221 static void ti_handle_events(struct ti_softc *);
222 static int ti_alloc_dmamaps(struct ti_softc *);
223 static void ti_free_dmamaps(struct ti_softc *);
224 static int ti_alloc_jumbo_mem(struct ti_softc *);
225 #ifdef TI_PRIVATE_JUMBOS
226 static void *ti_jalloc(struct ti_softc *);
227 static void ti_jfree(void *, void *);
228 #endif /* TI_PRIVATE_JUMBOS */
229 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
230 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
231 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
232 static int ti_init_rx_ring_std(struct ti_softc *);
233 static void ti_free_rx_ring_std(struct ti_softc *);
234 static int ti_init_rx_ring_jumbo(struct ti_softc *);
235 static void ti_free_rx_ring_jumbo(struct ti_softc *);
236 static int ti_init_rx_ring_mini(struct ti_softc *);
237 static void ti_free_rx_ring_mini(struct ti_softc *);
238 static void ti_free_tx_ring(struct ti_softc *);
239 static int ti_init_tx_ring(struct ti_softc *);
241 static int ti_64bitslot_war(struct ti_softc *);
242 static int ti_chipinit(struct ti_softc *);
243 static int ti_gibinit(struct ti_softc *);
245 #ifdef TI_JUMBO_HDRSPLIT
246 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
248 #endif /* TI_JUMBO_HDRSPLIT */
250 static device_method_t ti_methods[] = {
251 /* Device interface */
252 DEVMETHOD(device_probe, ti_probe),
253 DEVMETHOD(device_attach, ti_attach),
254 DEVMETHOD(device_detach, ti_detach),
255 DEVMETHOD(device_shutdown, ti_shutdown),
259 static driver_t ti_driver = {
262 sizeof(struct ti_softc)
265 static devclass_t ti_devclass;
267 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
268 MODULE_DEPEND(ti, pci, 1, 1, 1);
269 MODULE_DEPEND(ti, ether, 1, 1, 1);
272 * Send an instruction or address to the EEPROM, check for ACK.
275 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
280 * Make sure we're in TX mode.
282 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
285 * Feed in each bit and stobe the clock.
287 for (i = 0x80; i; i >>= 1) {
289 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
291 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
296 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
307 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
308 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
315 * Read a byte of data stored in the EEPROM at address 'addr.'
316 * We have to send two address bytes since the EEPROM can hold
317 * more than 256 bytes of data.
320 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
328 * Send write control code to EEPROM.
330 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
331 device_printf(sc->ti_dev,
332 "failed to send write command, status: %x\n",
333 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
338 * Send first byte of address of byte we want to read.
340 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
341 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
342 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
346 * Send second byte address of byte we want to read.
348 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
349 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
350 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
357 * Send read control code to EEPROM.
359 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
360 device_printf(sc->ti_dev,
361 "failed to send read command, status: %x\n",
362 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
367 * Start reading bits from EEPROM.
369 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
370 for (i = 0x80; i; i >>= 1) {
371 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
373 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
375 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
382 * No ACK generated for read, so just return byte.
391 * Read a sequence of bytes from the EEPROM.
394 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
399 for (i = 0; i < cnt; i++) {
400 err = ti_eeprom_getbyte(sc, off + i, &byte);
406 return (err ? 1 : 0);
410 * NIC memory read function.
411 * Can be used to copy data from NIC local memory.
414 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
416 int segptr, segsize, cnt;
427 segsize = TI_WINLEN - (segptr % TI_WINLEN);
428 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
429 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
430 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
440 * NIC memory write function.
441 * Can be used to copy data into NIC local memory.
444 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
446 int segptr, segsize, cnt;
457 segsize = TI_WINLEN - (segptr % TI_WINLEN);
458 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
459 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
460 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
469 * NIC memory read function.
470 * Can be used to clear a section of NIC local memory.
473 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
475 int segptr, segsize, cnt;
484 segsize = TI_WINLEN - (segptr % TI_WINLEN);
485 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
486 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
487 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
494 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
495 caddr_t buf, int useraddr, int readdata)
497 int segptr, segsize, cnt;
500 uint8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
507 * At the moment, we don't handle non-aligned cases, we just bail.
508 * If this proves to be a problem, it will be fixed.
511 && (tigon_addr & 0x3)) {
512 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
513 "word-aligned\n", __func__, tigon_addr);
514 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
515 "yet supported\n", __func__);
519 segptr = tigon_addr & ~0x3;
520 segresid = tigon_addr - segptr;
523 * This is the non-aligned amount left over that we'll need to
528 /* Add in the left over amount at the front of the buffer */
533 * If resid + segresid is >= 4, add multiples of 4 to the count and
534 * decrease the residual by that much.
537 resid -= resid & ~0x3;
544 * Save the old window base value.
546 origwin = CSR_READ_4(sc, TI_WINBASE);
549 bus_size_t ti_offset;
554 segsize = TI_WINLEN - (segptr % TI_WINLEN);
555 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
557 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
561 bus_space_read_region_4(sc->ti_btag,
562 sc->ti_bhandle, ti_offset,
563 (uint32_t *)tmparray,
567 * Yeah, this is a little on the kludgy
568 * side, but at least this code is only
569 * used for debugging.
571 ti_bcopy_swap(tmparray, tmparray2, segsize,
576 copyout(&tmparray2[segresid], ptr,
580 copyout(tmparray2, ptr, segsize);
585 ti_bcopy_swap(tmparray, tmparray2,
586 segsize, TI_SWAP_NTOH);
588 bcopy(&tmparray2[segresid], ptr,
593 ti_bcopy_swap(tmparray, ptr, segsize,
600 copyin(ptr, tmparray2, segsize);
602 ti_bcopy_swap(tmparray2, tmparray, segsize,
605 ti_bcopy_swap(ptr, tmparray, segsize,
608 bus_space_write_region_4(sc->ti_btag,
609 sc->ti_bhandle, ti_offset,
610 (uint32_t *)tmparray,
619 * Handle leftover, non-word-aligned bytes.
622 uint32_t tmpval, tmpval2;
623 bus_size_t ti_offset;
626 * Set the segment pointer.
628 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
630 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
633 * First, grab whatever is in our source/destination.
634 * We'll obviously need this for reads, but also for
635 * writes, since we'll be doing read/modify/write.
637 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
638 ti_offset, &tmpval, 1);
641 * Next, translate this from little-endian to big-endian
642 * (at least on i386 boxes).
644 tmpval2 = ntohl(tmpval);
648 * If we're reading, just copy the leftover number
649 * of bytes from the host byte order buffer to
654 copyout(&tmpval2, ptr, resid);
657 bcopy(&tmpval2, ptr, resid);
660 * If we're writing, first copy the bytes to be
661 * written into the network byte order buffer,
662 * leaving the rest of the buffer with whatever was
663 * originally in there. Then, swap the bytes
664 * around into host order and write them out.
666 * XXX KDM the read side of this has been verified
667 * to work, but the write side of it has not been
668 * verified. So user beware.
672 copyin(ptr, &tmpval2, resid);
675 bcopy(ptr, &tmpval2, resid);
677 tmpval = htonl(tmpval2);
679 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
680 ti_offset, &tmpval, 1);
684 CSR_WRITE_4(sc, TI_WINBASE, origwin);
690 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
691 caddr_t buf, int useraddr, int readdata, int cpu)
695 uint32_t tmpval, tmpval2;
701 * At the moment, we don't handle non-aligned cases, we just bail.
702 * If this proves to be a problem, it will be fixed.
704 if (tigon_addr & 0x3) {
705 device_printf(sc->ti_dev, "%s: tigon address %#x "
706 "isn't word-aligned\n", __func__, tigon_addr);
711 device_printf(sc->ti_dev, "%s: transfer length %d "
712 "isn't word-aligned\n", __func__, len);
721 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
724 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
726 tmpval = ntohl(tmpval2);
729 * Note: I've used this debugging interface
730 * extensively with Alteon's 12.3.15 firmware,
731 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
733 * When you compile the firmware without
734 * optimization, which is necessary sometimes in
735 * order to properly step through it, you sometimes
736 * read out a bogus value of 0xc0017c instead of
737 * whatever was supposed to be in that scratchpad
738 * location. That value is on the stack somewhere,
739 * but I've never been able to figure out what was
740 * causing the problem.
742 * The address seems to pop up in random places,
743 * often not in the same place on two subsequent
746 * In any case, the underlying data doesn't seem
747 * to be affected, just the value read out.
752 if (tmpval2 == 0xc0017c)
753 device_printf(sc->ti_dev, "found 0xc0017c at "
754 "%#x (tmpval2)\n", segptr);
756 if (tmpval == 0xc0017c)
757 device_printf(sc->ti_dev, "found 0xc0017c at "
758 "%#x (tmpval)\n", segptr);
761 copyout(&tmpval, ptr, 4);
763 bcopy(&tmpval, ptr, 4);
766 copyin(ptr, &tmpval2, 4);
768 bcopy(ptr, &tmpval2, 4);
770 tmpval = htonl(tmpval2);
772 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
784 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
786 const uint8_t *tmpsrc;
791 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
801 if (swap_type == TI_SWAP_NTOH)
802 *(uint32_t *)tmpdst =
803 ntohl(*(const uint32_t *)tmpsrc);
805 *(uint32_t *)tmpdst =
806 htonl(*(const uint32_t *)tmpsrc);
817 * Load firmware image into the NIC. Check that the firmware revision
818 * is acceptable and see if we want the firmware for the Tigon 1 or
822 ti_loadfw(struct ti_softc *sc)
827 switch (sc->ti_hwrev) {
829 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
830 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
831 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
832 device_printf(sc->ti_dev, "firmware revision mismatch; "
833 "want %d.%d.%d, got %d.%d.%d\n",
834 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
835 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
836 tigonFwReleaseMinor, tigonFwReleaseFix);
839 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
840 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
841 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
843 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
844 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
845 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
847 case TI_HWREV_TIGON_II:
848 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
849 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
850 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
851 device_printf(sc->ti_dev, "firmware revision mismatch; "
852 "want %d.%d.%d, got %d.%d.%d\n",
853 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
854 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
855 tigon2FwReleaseMinor, tigon2FwReleaseFix);
858 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
860 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
862 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
864 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
865 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
866 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
869 device_printf(sc->ti_dev,
870 "can't load firmware: unknown hardware rev\n");
876 * Send the NIC a command via the command ring.
879 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
883 index = sc->ti_cmd_saved_prodidx;
884 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
885 TI_INC(index, TI_CMD_RING_CNT);
886 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
887 sc->ti_cmd_saved_prodidx = index;
891 * Send the NIC an extended command. The 'len' parameter specifies the
892 * number of command slots to include after the initial command.
895 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
900 index = sc->ti_cmd_saved_prodidx;
901 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
902 TI_INC(index, TI_CMD_RING_CNT);
903 for (i = 0; i < len; i++) {
904 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
905 *(uint32_t *)(&arg[i * 4]));
906 TI_INC(index, TI_CMD_RING_CNT);
908 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
909 sc->ti_cmd_saved_prodidx = index;
913 * Handle events that have triggered interrupts.
916 ti_handle_events(struct ti_softc *sc)
918 struct ti_event_desc *e;
920 if (sc->ti_rdata->ti_event_ring == NULL)
923 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
924 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
925 switch (TI_EVENT_EVENT(e)) {
926 case TI_EV_LINKSTAT_CHANGED:
927 sc->ti_linkstat = TI_EVENT_CODE(e);
928 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
930 sc->ti_ifp->if_baudrate = IF_Mbps(100);
932 device_printf(sc->ti_dev,
934 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
935 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
936 sc->ti_ifp->if_baudrate = IF_Gbps(1UL);
938 device_printf(sc->ti_dev,
939 "gigabit link up\n");
940 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
941 if_link_state_change(sc->ti_ifp,
943 sc->ti_ifp->if_baudrate = 0;
945 device_printf(sc->ti_dev,
950 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
951 device_printf(sc->ti_dev, "invalid command\n");
952 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
953 device_printf(sc->ti_dev, "unknown command\n");
954 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
955 device_printf(sc->ti_dev, "bad config data\n");
957 case TI_EV_FIRMWARE_UP:
960 case TI_EV_STATS_UPDATED:
963 case TI_EV_RESET_JUMBO_RING:
964 case TI_EV_MCAST_UPDATED:
968 device_printf(sc->ti_dev, "unknown event: %d\n",
972 /* Advance the consumer index. */
973 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
974 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
979 ti_alloc_dmamaps(struct ti_softc *sc)
983 for (i = 0; i < TI_TX_RING_CNT; i++) {
984 sc->ti_cdata.ti_txdesc[i].tx_m = NULL;
985 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
986 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0,
987 &sc->ti_cdata.ti_txdesc[i].tx_dmamap))
990 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
991 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
992 &sc->ti_cdata.ti_rx_std_maps[i]))
996 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
997 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0,
998 &sc->ti_cdata.ti_rx_jumbo_maps[i]))
1001 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1002 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
1003 &sc->ti_cdata.ti_rx_mini_maps[i]))
1011 ti_free_dmamaps(struct ti_softc *sc)
1015 if (sc->ti_mbuftx_dmat)
1016 for (i = 0; i < TI_TX_RING_CNT; i++)
1017 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1018 bus_dmamap_destroy(sc->ti_mbuftx_dmat,
1019 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1020 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
1023 if (sc->ti_mbufrx_dmat)
1024 for (i = 0; i < TI_STD_RX_RING_CNT; i++)
1025 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1026 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1027 sc->ti_cdata.ti_rx_std_maps[i]);
1028 sc->ti_cdata.ti_rx_std_maps[i] = 0;
1031 if (sc->ti_jumbo_dmat)
1032 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++)
1033 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1034 bus_dmamap_destroy(sc->ti_jumbo_dmat,
1035 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1036 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0;
1038 if (sc->ti_mbufrx_dmat)
1039 for (i = 0; i < TI_MINI_RX_RING_CNT; i++)
1040 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1041 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1042 sc->ti_cdata.ti_rx_mini_maps[i]);
1043 sc->ti_cdata.ti_rx_mini_maps[i] = 0;
1047 #ifdef TI_PRIVATE_JUMBOS
1050 * Memory management for the jumbo receive ring is a pain in the
1051 * butt. We need to allocate at least 9018 bytes of space per frame,
1052 * _and_ it has to be contiguous (unless you use the extended
1053 * jumbo descriptor format). Using malloc() all the time won't
1054 * work: malloc() allocates memory in powers of two, which means we
1055 * would end up wasting a considerable amount of space by allocating
1056 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
1057 * to do our own memory management.
1059 * The driver needs to allocate a contiguous chunk of memory at boot
1060 * time. We then chop this up ourselves into 9K pieces and use them
1061 * as external mbuf storage.
1063 * One issue here is how much memory to allocate. The jumbo ring has
1064 * 256 slots in it, but at 9K per slot than can consume over 2MB of
1065 * RAM. This is a bit much, especially considering we also need
1066 * RAM for the standard ring and mini ring (on the Tigon 2). To
1067 * save space, we only actually allocate enough memory for 64 slots
1068 * by default, which works out to between 500 and 600K. This can
1069 * be tuned by changing a #define in if_tireg.h.
1073 ti_alloc_jumbo_mem(struct ti_softc *sc)
1075 struct ti_jpool_entry *entry;
1080 * Grab a big chunk o' storage. Since we are chopping this pool up
1081 * into ~9k chunks, there doesn't appear to be a need to use page
1084 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1085 1, 0, /* algnmnt, boundary */
1086 BUS_SPACE_MAXADDR, /* lowaddr */
1087 BUS_SPACE_MAXADDR, /* highaddr */
1088 NULL, NULL, /* filter, filterarg */
1089 TI_JMEM, /* maxsize */
1091 TI_JMEM, /* maxsegsize */
1093 NULL, NULL, /* lockfunc, lockarg */
1094 &sc->ti_jumbo_dmat) != 0) {
1095 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1099 if (bus_dmamem_alloc(sc->ti_jumbo_dmat,
1100 (void**)&sc->ti_cdata.ti_jumbo_buf,
1101 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
1102 &sc->ti_jumbo_dmamap) != 0) {
1103 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n");
1107 SLIST_INIT(&sc->ti_jfree_listhead);
1108 SLIST_INIT(&sc->ti_jinuse_listhead);
1111 * Now divide it up into 9K pieces and save the addresses
1114 ptr = sc->ti_cdata.ti_jumbo_buf;
1115 for (i = 0; i < TI_JSLOTS; i++) {
1116 sc->ti_cdata.ti_jslots[i] = ptr;
1118 entry = malloc(sizeof(struct ti_jpool_entry),
1119 M_DEVBUF, M_NOWAIT);
1120 if (entry == NULL) {
1121 device_printf(sc->ti_dev, "no memory for jumbo "
1126 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1133 * Allocate a jumbo buffer.
1135 static void *ti_jalloc(struct ti_softc *sc)
1137 struct ti_jpool_entry *entry;
1139 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1141 if (entry == NULL) {
1142 device_printf(sc->ti_dev, "no free jumbo buffers\n");
1146 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1147 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1148 return (sc->ti_cdata.ti_jslots[entry->slot]);
1152 * Release a jumbo buffer.
1155 ti_jfree(void *buf, void *args)
1157 struct ti_softc *sc;
1159 struct ti_jpool_entry *entry;
1161 /* Extract the softc struct pointer. */
1162 sc = (struct ti_softc *)args;
1165 panic("ti_jfree: didn't get softc pointer!");
1167 /* calculate the slot this buffer belongs to */
1168 i = ((vm_offset_t)buf
1169 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1171 if ((i < 0) || (i >= TI_JSLOTS))
1172 panic("ti_jfree: asked to free buffer that we don't manage!");
1174 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1176 panic("ti_jfree: buffer not in use!");
1178 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1179 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1185 ti_alloc_jumbo_mem(struct ti_softc *sc)
1189 * The VM system will take care of providing aligned pages. Alignment
1190 * is set to 1 here so that busdma resources won't be wasted.
1192 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1193 1, 0, /* algnmnt, boundary */
1194 BUS_SPACE_MAXADDR, /* lowaddr */
1195 BUS_SPACE_MAXADDR, /* highaddr */
1196 NULL, NULL, /* filter, filterarg */
1197 PAGE_SIZE * 4 /*XXX*/, /* maxsize */
1199 PAGE_SIZE, /* maxsegsize */
1201 NULL, NULL, /* lockfunc, lockarg */
1202 &sc->ti_jumbo_dmat) != 0) {
1203 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1210 #endif /* TI_PRIVATE_JUMBOS */
1213 * Intialize a standard receive ring descriptor.
1216 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m)
1219 bus_dma_segment_t segs;
1220 struct mbuf *m_new = NULL;
1221 struct ti_rx_desc *r;
1226 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1230 MCLGET(m_new, M_DONTWAIT);
1231 if (!(m_new->m_flags & M_EXT)) {
1235 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1238 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1239 m_new->m_data = m_new->m_ext.ext_buf;
1242 m_adj(m_new, ETHER_ALIGN);
1243 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1244 r = &sc->ti_rdata->ti_rx_std_ring[i];
1245 map = sc->ti_cdata.ti_rx_std_maps[i];
1246 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1251 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1252 r->ti_len = segs.ds_len;
1253 r->ti_type = TI_BDTYPE_RECV_BD;
1255 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1256 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1259 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1264 * Intialize a mini receive ring descriptor. This only applies to
1268 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m)
1270 bus_dma_segment_t segs;
1272 struct mbuf *m_new = NULL;
1273 struct ti_rx_desc *r;
1278 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1279 if (m_new == NULL) {
1282 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1285 m_new->m_data = m_new->m_pktdat;
1286 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1289 m_adj(m_new, ETHER_ALIGN);
1290 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1291 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1292 map = sc->ti_cdata.ti_rx_mini_maps[i];
1293 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1298 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1299 r->ti_len = segs.ds_len;
1300 r->ti_type = TI_BDTYPE_RECV_BD;
1301 r->ti_flags = TI_BDFLAG_MINI_RING;
1302 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1303 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1306 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1310 #ifdef TI_PRIVATE_JUMBOS
1313 * Initialize a jumbo receive ring descriptor. This allocates
1314 * a jumbo buffer from the pool managed internally by the driver.
1317 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
1320 struct mbuf *m_new = NULL;
1321 struct ti_rx_desc *r;
1323 bus_dma_segment_t segs;
1326 caddr_t *buf = NULL;
1328 /* Allocate the mbuf. */
1329 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1330 if (m_new == NULL) {
1334 /* Allocate the jumbo buffer */
1335 buf = ti_jalloc(sc);
1338 device_printf(sc->ti_dev, "jumbo allocation failed "
1339 "-- packet dropped!\n");
1343 /* Attach the buffer to the mbuf. */
1344 m_new->m_data = (void *) buf;
1345 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1346 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, buf,
1347 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1350 m_new->m_data = m_new->m_ext.ext_buf;
1351 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1354 m_adj(m_new, ETHER_ALIGN);
1355 /* Set up the descriptor. */
1356 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1357 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1358 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1359 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs,
1364 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1365 r->ti_len = segs.ds_len;
1366 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1367 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1368 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1369 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1372 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1378 #if (PAGE_SIZE == 4096)
1384 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1385 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1386 #define NFS_HDR_LEN (UDP_HDR_LEN)
1387 static int HDR_LEN = TCP_HDR_LEN;
1390 * Initialize a jumbo receive ring descriptor. This allocates
1391 * a jumbo buffer from the pool managed internally by the driver.
1394 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1397 struct mbuf *cur, *m_new = NULL;
1398 struct mbuf *m[3] = {NULL, NULL, NULL};
1399 struct ti_rx_desc_ext *r;
1402 /* 1 extra buf to make nobufs easy*/
1403 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1405 bus_dma_segment_t segs[4];
1408 if (m_old != NULL) {
1410 cur = m_old->m_next;
1411 for (i = 0; i <= NPAYLOAD; i++){
1416 /* Allocate the mbufs. */
1417 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1418 if (m_new == NULL) {
1419 device_printf(sc->ti_dev, "mbuf allocation failed "
1420 "-- packet dropped!\n");
1423 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1424 if (m[NPAYLOAD] == NULL) {
1425 device_printf(sc->ti_dev, "cluster mbuf allocation "
1426 "failed -- packet dropped!\n");
1429 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1430 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1431 device_printf(sc->ti_dev, "mbuf allocation failed "
1432 "-- packet dropped!\n");
1435 m[NPAYLOAD]->m_len = MCLBYTES;
1437 for (i = 0; i < NPAYLOAD; i++){
1438 MGET(m[i], M_DONTWAIT, MT_DATA);
1440 device_printf(sc->ti_dev, "mbuf allocation "
1441 "failed -- packet dropped!\n");
1444 frame = vm_page_alloc(NULL, color++,
1445 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1447 if (frame == NULL) {
1448 device_printf(sc->ti_dev, "buffer allocation "
1449 "failed -- packet dropped!\n");
1450 printf(" index %d page %d\n", idx, i);
1453 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1454 if (sf[i] == NULL) {
1455 vm_page_lock_queues();
1456 vm_page_unwire(frame, 0);
1457 vm_page_free(frame);
1458 vm_page_unlock_queues();
1459 device_printf(sc->ti_dev, "buffer allocation "
1460 "failed -- packet dropped!\n");
1461 printf(" index %d page %d\n", idx, i);
1465 for (i = 0; i < NPAYLOAD; i++){
1466 /* Attach the buffer to the mbuf. */
1467 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1468 m[i]->m_len = PAGE_SIZE;
1469 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1470 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1472 m[i]->m_next = m[i+1];
1474 /* link the buffers to the header */
1475 m_new->m_next = m[0];
1476 m_new->m_data += ETHER_ALIGN;
1477 if (sc->ti_hdrsplit)
1478 m_new->m_len = MHLEN - ETHER_ALIGN;
1480 m_new->m_len = HDR_LEN;
1481 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1484 /* Set up the descriptor. */
1485 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1486 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1487 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1488 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs,
1491 if ((nsegs < 1) || (nsegs > 4))
1493 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1494 r->ti_len0 = m_new->m_len;
1496 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1497 r->ti_len1 = PAGE_SIZE;
1499 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1500 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1502 if (PAGE_SIZE == 4096) {
1503 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1504 r->ti_len3 = MCLBYTES;
1508 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1510 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1512 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1513 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1517 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1524 * This can only be called before the mbufs are strung together.
1525 * If the mbufs are strung together, m_freem() will free the chain,
1526 * so that the later mbufs will be freed multiple times.
1531 for (i = 0; i < 3; i++) {
1535 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1542 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1543 * that's 1MB or memory, which is a lot. For now, we fill only the first
1544 * 256 ring entries and hope that our CPU is fast enough to keep up with
1548 ti_init_rx_ring_std(struct ti_softc *sc)
1551 struct ti_cmd_desc cmd;
1553 for (i = 0; i < TI_SSLOTS; i++) {
1554 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1558 TI_UPDATE_STDPROD(sc, i - 1);
1565 ti_free_rx_ring_std(struct ti_softc *sc)
1570 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1571 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1572 map = sc->ti_cdata.ti_rx_std_maps[i];
1573 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1574 BUS_DMASYNC_POSTREAD);
1575 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1576 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1577 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1579 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1580 sizeof(struct ti_rx_desc));
1585 ti_init_rx_ring_jumbo(struct ti_softc *sc)
1587 struct ti_cmd_desc cmd;
1590 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1591 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1595 TI_UPDATE_JUMBOPROD(sc, i - 1);
1596 sc->ti_jumbo = i - 1;
1602 ti_free_rx_ring_jumbo(struct ti_softc *sc)
1607 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1608 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1609 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1610 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
1611 BUS_DMASYNC_POSTREAD);
1612 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
1613 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1614 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1616 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1617 sizeof(struct ti_rx_desc));
1622 ti_init_rx_ring_mini(struct ti_softc *sc)
1626 for (i = 0; i < TI_MSLOTS; i++) {
1627 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1631 TI_UPDATE_MINIPROD(sc, i - 1);
1632 sc->ti_mini = i - 1;
1638 ti_free_rx_ring_mini(struct ti_softc *sc)
1643 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1644 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1645 map = sc->ti_cdata.ti_rx_mini_maps[i];
1646 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1647 BUS_DMASYNC_POSTREAD);
1648 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1649 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1650 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1652 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1653 sizeof(struct ti_rx_desc));
1658 ti_free_tx_ring(struct ti_softc *sc)
1660 struct ti_txdesc *txd;
1663 if (sc->ti_rdata->ti_tx_ring == NULL)
1666 for (i = 0; i < TI_TX_RING_CNT; i++) {
1667 txd = &sc->ti_cdata.ti_txdesc[i];
1668 if (txd->tx_m != NULL) {
1669 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
1670 BUS_DMASYNC_POSTWRITE);
1671 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
1675 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1676 sizeof(struct ti_tx_desc));
1681 ti_init_tx_ring(struct ti_softc *sc)
1683 struct ti_txdesc *txd;
1686 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1687 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1688 for (i = 0; i < TI_TX_RING_CNT; i++) {
1689 txd = &sc->ti_cdata.ti_txdesc[i];
1690 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1693 sc->ti_tx_saved_considx = 0;
1694 sc->ti_tx_saved_prodidx = 0;
1695 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1700 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1701 * but we have to support the old way too so that Tigon 1 cards will
1705 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1707 struct ti_cmd_desc cmd;
1709 uint32_t ext[2] = {0, 0};
1711 m = (uint16_t *)&addr->octet[0];
1713 switch (sc->ti_hwrev) {
1714 case TI_HWREV_TIGON:
1715 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1716 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1717 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1719 case TI_HWREV_TIGON_II:
1720 ext[0] = htons(m[0]);
1721 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1722 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1725 device_printf(sc->ti_dev, "unknown hwrev\n");
1731 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1733 struct ti_cmd_desc cmd;
1735 uint32_t ext[2] = {0, 0};
1737 m = (uint16_t *)&addr->octet[0];
1739 switch (sc->ti_hwrev) {
1740 case TI_HWREV_TIGON:
1741 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1742 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1743 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1745 case TI_HWREV_TIGON_II:
1746 ext[0] = htons(m[0]);
1747 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1748 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1751 device_printf(sc->ti_dev, "unknown hwrev\n");
1757 * Configure the Tigon's multicast address filter.
1759 * The actual multicast table management is a bit of a pain, thanks to
1760 * slight brain damage on the part of both Alteon and us. With our
1761 * multicast code, we are only alerted when the multicast address table
1762 * changes and at that point we only have the current list of addresses:
1763 * we only know the current state, not the previous state, so we don't
1764 * actually know what addresses were removed or added. The firmware has
1765 * state, but we can't get our grubby mits on it, and there is no 'delete
1766 * all multicast addresses' command. Hence, we have to maintain our own
1767 * state so we know what addresses have been programmed into the NIC at
1771 ti_setmulti(struct ti_softc *sc)
1774 struct ifmultiaddr *ifma;
1775 struct ti_cmd_desc cmd;
1776 struct ti_mc_entry *mc;
1783 if (ifp->if_flags & IFF_ALLMULTI) {
1784 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1787 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1790 /* Disable interrupts. */
1791 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1792 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1794 /* First, zot all the existing filters. */
1795 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1796 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1797 ti_del_mcast(sc, &mc->mc_addr);
1798 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1802 /* Now program new ones. */
1803 if_maddr_rlock(ifp);
1804 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1805 if (ifma->ifma_addr->sa_family != AF_LINK)
1807 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1809 device_printf(sc->ti_dev,
1810 "no memory for mcast filter entry\n");
1813 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1814 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1815 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1816 ti_add_mcast(sc, &mc->mc_addr);
1818 if_maddr_runlock(ifp);
1820 /* Re-enable interrupts. */
1821 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1825 * Check to see if the BIOS has configured us for a 64 bit slot when
1826 * we aren't actually in one. If we detect this condition, we can work
1827 * around it on the Tigon 2 by setting a bit in the PCI state register,
1828 * but for the Tigon 1 we must give up and abort the interface attach.
1830 static int ti_64bitslot_war(struct ti_softc *sc)
1833 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1834 CSR_WRITE_4(sc, 0x600, 0);
1835 CSR_WRITE_4(sc, 0x604, 0);
1836 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1837 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1838 if (sc->ti_hwrev == TI_HWREV_TIGON)
1841 TI_SETBIT(sc, TI_PCI_STATE,
1842 TI_PCISTATE_32BIT_BUS);
1852 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1853 * self-test results.
1856 ti_chipinit(struct ti_softc *sc)
1859 uint32_t pci_writemax = 0;
1862 /* Initialize link to down state. */
1863 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1865 /* Set endianness before we access any non-PCI registers. */
1866 #if 0 && BYTE_ORDER == BIG_ENDIAN
1867 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1868 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1870 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1871 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1874 /* Check the ROM failed bit to see if self-tests passed. */
1875 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1876 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
1881 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1883 /* Figure out the hardware revision. */
1884 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1885 case TI_REV_TIGON_I:
1886 sc->ti_hwrev = TI_HWREV_TIGON;
1888 case TI_REV_TIGON_II:
1889 sc->ti_hwrev = TI_HWREV_TIGON_II;
1892 device_printf(sc->ti_dev, "unsupported chip revision\n");
1896 /* Do special setup for Tigon 2. */
1897 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1898 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1899 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1900 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1904 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1905 * can't do header splitting.
1907 #ifdef TI_JUMBO_HDRSPLIT
1908 if (sc->ti_hwrev != TI_HWREV_TIGON)
1909 sc->ti_hdrsplit = 1;
1911 device_printf(sc->ti_dev,
1912 "can't do header splitting on a Tigon I board\n");
1913 #endif /* TI_JUMBO_HDRSPLIT */
1915 /* Set up the PCI state register. */
1916 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1917 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1918 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1921 /* Clear the read/write max DMA parameters. */
1922 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1923 TI_PCISTATE_READ_MAXDMA));
1925 /* Get cache line size. */
1926 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1929 * If the system has set enabled the PCI memory write
1930 * and invalidate command in the command register, set
1931 * the write max parameter accordingly. This is necessary
1932 * to use MWI with the Tigon 2.
1934 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1935 switch (cacheline) {
1944 /* Disable PCI memory write and invalidate. */
1946 device_printf(sc->ti_dev, "cache line size %d"
1947 " not supported; disabling PCI MWI\n",
1949 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1950 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1955 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1957 /* This sets the min dma param all the way up (0xff). */
1958 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1960 if (sc->ti_hdrsplit)
1961 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1965 /* Configure DMA variables. */
1966 #if BYTE_ORDER == BIG_ENDIAN
1967 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1968 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1969 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1970 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1971 #else /* BYTE_ORDER */
1972 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1973 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1974 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1975 #endif /* BYTE_ORDER */
1978 * Only allow 1 DMA channel to be active at a time.
1979 * I don't think this is a good idea, but without it
1980 * the firmware racks up lots of nicDmaReadRingFull
1981 * errors. This is not compatible with hardware checksums.
1983 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0)
1984 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1986 /* Recommended settings from Tigon manual. */
1987 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1988 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1990 if (ti_64bitslot_war(sc)) {
1991 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
2000 * Initialize the general information block and firmware, and
2001 * start the CPU(s) running.
2004 ti_gibinit(struct ti_softc *sc)
2014 rdphys = sc->ti_rdata_phys;
2016 /* Disable interrupts for now. */
2017 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2020 * Tell the chip where to find the general information block.
2021 * While this struct could go into >4GB memory, we allocate it in a
2022 * single slab with the other descriptors, and those don't seem to
2023 * support being located in a 64-bit region.
2025 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
2026 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
2028 /* Load the firmware into SRAM. */
2031 /* Set up the contents of the general info and ring control blocks. */
2033 /* Set up the event ring and producer pointer. */
2034 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
2036 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
2038 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
2039 rdphys + TI_RD_OFF(ti_ev_prodidx_r);
2040 sc->ti_ev_prodidx.ti_idx = 0;
2041 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2042 sc->ti_ev_saved_considx = 0;
2044 /* Set up the command ring and producer mailbox. */
2045 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
2047 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
2049 rcb->ti_max_len = 0;
2050 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2051 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2053 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2054 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2055 sc->ti_cmd_saved_prodidx = 0;
2058 * Assign the address of the stats refresh buffer.
2059 * We re-use the current stats buffer for this to
2062 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
2063 rdphys + TI_RD_OFF(ti_info.ti_stats);
2065 /* Set up the standard receive ring. */
2066 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
2067 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
2068 rcb->ti_max_len = TI_FRAMELEN;
2070 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2071 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2072 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2073 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2074 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2076 /* Set up the jumbo receive ring. */
2077 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
2078 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
2080 #ifdef TI_PRIVATE_JUMBOS
2081 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
2084 rcb->ti_max_len = PAGE_SIZE;
2085 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2087 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2088 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2089 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2090 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2091 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2094 * Set up the mini ring. Only activated on the
2095 * Tigon 2 but the slot in the config block is
2096 * still there on the Tigon 1.
2098 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
2099 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
2100 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2101 if (sc->ti_hwrev == TI_HWREV_TIGON)
2102 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2105 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2106 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2107 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2108 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2109 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2112 * Set up the receive return ring.
2114 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
2115 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
2117 rcb->ti_max_len = TI_RETURN_RING_CNT;
2118 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
2119 rdphys + TI_RD_OFF(ti_return_prodidx_r);
2122 * Set up the tx ring. Note: for the Tigon 2, we have the option
2123 * of putting the transmit ring in the host's address space and
2124 * letting the chip DMA it instead of leaving the ring in the NIC's
2125 * memory and accessing it through the shared memory region. We
2126 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2127 * so we have to revert to the shared memory scheme if we detect
2130 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2131 bzero((char *)sc->ti_rdata->ti_tx_ring,
2132 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
2133 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
2134 if (sc->ti_hwrev == TI_HWREV_TIGON)
2137 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2138 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2139 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2140 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM)
2141 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2142 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2143 rcb->ti_max_len = TI_TX_RING_CNT;
2144 if (sc->ti_hwrev == TI_HWREV_TIGON)
2145 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
2147 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
2148 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
2149 rdphys + TI_RD_OFF(ti_tx_considx_r);
2151 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2152 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2154 /* Set up tuneables */
2156 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2157 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2158 (sc->ti_rx_coal_ticks / 10));
2161 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2162 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2163 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2164 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2165 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2166 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2168 /* Turn interrupts on. */
2169 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2170 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2173 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2179 ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2181 struct ti_softc *sc;
2184 if (error || nseg != 1)
2188 * All of the Tigon data structures need to live at <4GB. This
2189 * cast is fine since busdma was told about this constraint.
2191 sc->ti_rdata_phys = segs[0].ds_addr;
2196 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2197 * against our list and return its name if we find a match.
2200 ti_probe(device_t dev)
2202 const struct ti_type *t;
2206 while (t->ti_name != NULL) {
2207 if ((pci_get_vendor(dev) == t->ti_vid) &&
2208 (pci_get_device(dev) == t->ti_did)) {
2209 device_set_desc(dev, t->ti_name);
2210 return (BUS_PROBE_DEFAULT);
2219 ti_attach(device_t dev)
2222 struct ti_softc *sc;
2226 sc = device_get_softc(dev);
2227 sc->ti_unit = device_get_unit(dev);
2230 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2232 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2233 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2234 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2236 device_printf(dev, "can not if_alloc()\n");
2240 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
2241 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
2242 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2245 * Map control/status registers.
2247 pci_enable_busmaster(dev);
2250 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2253 if (sc->ti_res == NULL) {
2254 device_printf(dev, "couldn't map memory\n");
2259 sc->ti_btag = rman_get_bustag(sc->ti_res);
2260 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2262 /* Allocate interrupt */
2265 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2266 RF_SHAREABLE | RF_ACTIVE);
2268 if (sc->ti_irq == NULL) {
2269 device_printf(dev, "couldn't map interrupt\n");
2274 if (ti_chipinit(sc)) {
2275 device_printf(dev, "chip initialization failed\n");
2280 /* Zero out the NIC's on-board SRAM. */
2281 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2283 /* Init again -- zeroing memory may have clobbered some registers. */
2284 if (ti_chipinit(sc)) {
2285 device_printf(dev, "chip initialization failed\n");
2291 * Get station address from the EEPROM. Note: the manual states
2292 * that the MAC address is at offset 0x8c, however the data is
2293 * stored as two longwords (since that's how it's loaded into
2294 * the NIC). This means the MAC address is actually preceded
2295 * by two zero bytes. We need to skip over those.
2297 if (ti_read_eeprom(sc, eaddr,
2298 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2299 device_printf(dev, "failed to read station address\n");
2304 /* Allocate the general information block and ring buffers. */
2305 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
2306 1, 0, /* algnmnt, boundary */
2307 BUS_SPACE_MAXADDR, /* lowaddr */
2308 BUS_SPACE_MAXADDR, /* highaddr */
2309 NULL, NULL, /* filter, filterarg */
2310 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2312 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2314 NULL, NULL, /* lockfunc, lockarg */
2315 &sc->ti_parent_dmat) != 0) {
2316 device_printf(dev, "Failed to allocate parent dmat\n");
2321 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2322 PAGE_SIZE, 0, /* algnmnt, boundary */
2323 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2324 BUS_SPACE_MAXADDR, /* highaddr */
2325 NULL, NULL, /* filter, filterarg */
2326 sizeof(struct ti_ring_data), /* maxsize */
2328 sizeof(struct ti_ring_data), /* maxsegsize */
2330 NULL, NULL, /* lockfunc, lockarg */
2331 &sc->ti_rdata_dmat) != 0) {
2332 device_printf(dev, "Failed to allocate rdata dmat\n");
2337 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2338 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
2339 &sc->ti_rdata_dmamap) != 0) {
2340 device_printf(dev, "Failed to allocate rdata memory\n");
2345 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2346 sc->ti_rdata, sizeof(struct ti_ring_data),
2347 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2348 device_printf(dev, "Failed to load rdata segments\n");
2353 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2355 /* Try to allocate memory for jumbo buffers. */
2356 if (ti_alloc_jumbo_mem(sc)) {
2357 device_printf(dev, "jumbo buffer allocation failed\n");
2362 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2363 1, 0, /* algnmnt, boundary */
2364 BUS_SPACE_MAXADDR, /* lowaddr */
2365 BUS_SPACE_MAXADDR, /* highaddr */
2366 NULL, NULL, /* filter, filterarg */
2367 MCLBYTES * TI_MAXTXSEGS,/* maxsize */
2368 TI_MAXTXSEGS, /* nsegments */
2369 MCLBYTES, /* maxsegsize */
2371 NULL, NULL, /* lockfunc, lockarg */
2372 &sc->ti_mbuftx_dmat) != 0) {
2373 device_printf(dev, "Failed to allocate rdata dmat\n");
2378 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2379 1, 0, /* algnmnt, boundary */
2380 BUS_SPACE_MAXADDR, /* lowaddr */
2381 BUS_SPACE_MAXADDR, /* highaddr */
2382 NULL, NULL, /* filter, filterarg */
2383 MCLBYTES, /* maxsize */
2385 MCLBYTES, /* maxsegsize */
2387 NULL, NULL, /* lockfunc, lockarg */
2388 &sc->ti_mbufrx_dmat) != 0) {
2389 device_printf(dev, "Failed to allocate rdata dmat\n");
2394 if (ti_alloc_dmamaps(sc)) {
2395 device_printf(dev, "dma map creation failed\n");
2401 * We really need a better way to tell a 1000baseTX card
2402 * from a 1000baseSX one, since in theory there could be
2403 * OEMed 1000baseTX cards from lame vendors who aren't
2404 * clever enough to change the PCI ID. For the moment
2405 * though, the AceNIC is the only copper card available.
2407 if (pci_get_vendor(dev) == ALT_VENDORID &&
2408 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2410 /* Ok, it's not the only copper card available. */
2411 if (pci_get_vendor(dev) == NG_VENDORID &&
2412 pci_get_device(dev) == NG_DEVICEID_GA620T)
2415 /* Set default tuneable values. */
2416 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2418 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2420 sc->ti_rx_coal_ticks = 170;
2421 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2422 sc->ti_rx_max_coal_bds = 64;
2424 sc->ti_tx_max_coal_bds = 128;
2426 sc->ti_tx_max_coal_bds = 32;
2427 sc->ti_tx_buf_ratio = 21;
2429 /* Set up ifnet structure */
2431 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2432 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2433 ifp->if_ioctl = ti_ioctl;
2434 ifp->if_start = ti_start;
2435 ifp->if_init = ti_init;
2436 ifp->if_baudrate = IF_Gbps(1UL);
2437 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1;
2438 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2439 IFQ_SET_READY(&ifp->if_snd);
2441 /* Set up ifmedia support. */
2442 if (sc->ti_copper) {
2444 * Copper cards allow manual 10/100 mode selection,
2445 * but not manual 1000baseTX mode selection. Why?
2446 * Becuase currently there's no way to specify the
2447 * master/slave setting through the firmware interface,
2448 * so Alteon decided to just bag it and handle it
2449 * via autonegotiation.
2451 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2452 ifmedia_add(&sc->ifmedia,
2453 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2454 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2455 ifmedia_add(&sc->ifmedia,
2456 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2457 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2458 ifmedia_add(&sc->ifmedia,
2459 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2461 /* Fiber cards don't support 10/100 modes. */
2462 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2463 ifmedia_add(&sc->ifmedia,
2464 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2466 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2467 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2470 * We're assuming here that card initialization is a sequential
2471 * thing. If it isn't, multiple cards probing at the same time
2472 * could stomp on the list of softcs here.
2475 /* Register the device */
2476 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
2477 0600, "ti%d", sc->ti_unit);
2478 sc->dev->si_drv1 = sc;
2481 * Call MI attach routine.
2483 ether_ifattach(ifp, eaddr);
2485 /* VLAN capability setup. */
2486 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM |
2487 IFCAP_VLAN_HWTAGGING;
2488 ifp->if_capenable = ifp->if_capabilities;
2489 /* Tell the upper layer we support VLAN over-sized frames. */
2490 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2492 /* Driver supports link state tracking. */
2493 ifp->if_capabilities |= IFCAP_LINKSTATE;
2494 ifp->if_capenable |= IFCAP_LINKSTATE;
2496 /* Hook interrupt last to avoid having to lock softc */
2497 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2498 NULL, ti_intr, sc, &sc->ti_intrhand);
2501 device_printf(dev, "couldn't set up irq\n");
2513 * Shutdown hardware and free up resources. This can be called any
2514 * time after the mutex has been initialized. It is called in both
2515 * the error case in attach and the normal detach case so it needs
2516 * to be careful about only freeing resources that have actually been
2520 ti_detach(device_t dev)
2522 struct ti_softc *sc;
2525 sc = device_get_softc(dev);
2527 destroy_dev(sc->dev);
2528 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2530 if (device_is_attached(dev)) {
2531 ether_ifdetach(ifp);
2537 /* These should only be active if attach succeeded */
2538 callout_drain(&sc->ti_watchdog);
2539 bus_generic_detach(dev);
2540 ti_free_dmamaps(sc);
2541 ifmedia_removeall(&sc->ifmedia);
2543 #ifdef TI_PRIVATE_JUMBOS
2544 if (sc->ti_cdata.ti_jumbo_buf)
2545 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf,
2546 sc->ti_jumbo_dmamap);
2548 if (sc->ti_jumbo_dmat)
2549 bus_dma_tag_destroy(sc->ti_jumbo_dmat);
2550 if (sc->ti_mbuftx_dmat)
2551 bus_dma_tag_destroy(sc->ti_mbuftx_dmat);
2552 if (sc->ti_mbufrx_dmat)
2553 bus_dma_tag_destroy(sc->ti_mbufrx_dmat);
2554 if (sc->ti_rdata && sc->ti_rdata_dmamap)
2555 bus_dmamap_unload(sc->ti_rdata_dmat, sc->ti_rdata_dmamap);
2557 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2558 sc->ti_rdata_dmamap);
2559 if (sc->ti_rdata_dmat)
2560 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2561 if (sc->ti_parent_dmat)
2562 bus_dma_tag_destroy(sc->ti_parent_dmat);
2563 if (sc->ti_intrhand)
2564 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2566 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2568 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2574 mtx_destroy(&sc->ti_mtx);
2579 #ifdef TI_JUMBO_HDRSPLIT
2581 * If hdr_len is 0, that means that header splitting wasn't done on
2582 * this packet for some reason. The two most likely reasons are that
2583 * the protocol isn't a supported protocol for splitting, or this
2584 * packet had a fragment offset that wasn't 0.
2586 * The header length, if it is non-zero, will always be the length of
2587 * the headers on the packet, but that length could be longer than the
2588 * first mbuf. So we take the minimum of the two as the actual
2591 static __inline void
2592 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2595 int lengths[4] = {0, 0, 0, 0};
2596 struct mbuf *m, *mp;
2599 top->m_len = min(hdr_len, top->m_len);
2600 pkt_len -= top->m_len;
2601 lengths[i++] = top->m_len;
2604 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2605 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2606 pkt_len -= m->m_len;
2607 lengths[i++] = m->m_len;
2613 printf("got split packet: ");
2615 printf("got non-split packet: ");
2617 printf("%d,%d,%d,%d = %d\n", lengths[0],
2618 lengths[1], lengths[2], lengths[3],
2619 lengths[0] + lengths[1] + lengths[2] +
2624 panic("header splitting didn't");
2631 if (mp->m_next != NULL)
2632 panic("ti_hdr_split: last mbuf in chain should be null");
2634 #endif /* TI_JUMBO_HDRSPLIT */
2637 * Frame reception handling. This is called if there's a frame
2638 * on the receive return list.
2640 * Note: we have to be able to handle three possibilities here:
2641 * 1) the frame is from the mini receive ring (can only happen)
2642 * on Tigon 2 boards)
2643 * 2) the frame is from the jumbo recieve ring
2644 * 3) the frame is from the standard receive ring
2648 ti_rxeof(struct ti_softc *sc)
2652 struct ti_cmd_desc cmd;
2658 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2659 struct ti_rx_desc *cur_rx;
2660 struct mbuf *m = NULL;
2662 uint16_t vlan_tag = 0;
2666 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2667 rxidx = cur_rx->ti_idx;
2668 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2670 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2672 vlan_tag = cur_rx->ti_vlan_tag;
2675 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2677 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2678 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2679 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2680 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2681 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
2682 BUS_DMASYNC_POSTREAD);
2683 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
2684 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2686 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2689 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2691 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2694 #ifdef TI_PRIVATE_JUMBOS
2695 m->m_len = cur_rx->ti_len;
2696 #else /* TI_PRIVATE_JUMBOS */
2697 #ifdef TI_JUMBO_HDRSPLIT
2698 if (sc->ti_hdrsplit)
2699 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2700 cur_rx->ti_len, rxidx);
2702 #endif /* TI_JUMBO_HDRSPLIT */
2703 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2704 #endif /* TI_PRIVATE_JUMBOS */
2705 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2706 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2707 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2708 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2709 map = sc->ti_cdata.ti_rx_mini_maps[rxidx];
2710 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2711 BUS_DMASYNC_POSTREAD);
2712 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2713 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2715 ti_newbuf_mini(sc, sc->ti_mini, m);
2718 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2720 ti_newbuf_mini(sc, sc->ti_mini, m);
2723 m->m_len = cur_rx->ti_len;
2725 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2726 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2727 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2728 map = sc->ti_cdata.ti_rx_std_maps[rxidx];
2729 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2730 BUS_DMASYNC_POSTREAD);
2731 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2732 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2734 ti_newbuf_std(sc, sc->ti_std, m);
2737 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2739 ti_newbuf_std(sc, sc->ti_std, m);
2742 m->m_len = cur_rx->ti_len;
2745 m->m_pkthdr.len = cur_rx->ti_len;
2747 m->m_pkthdr.rcvif = ifp;
2749 if (ifp->if_capenable & IFCAP_RXCSUM) {
2750 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) {
2751 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2752 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2753 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2755 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) {
2756 m->m_pkthdr.csum_data =
2757 cur_rx->ti_tcp_udp_cksum;
2758 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2763 * If we received a packet with a vlan tag,
2764 * tag it before passing the packet upward.
2767 m->m_pkthdr.ether_vtag = vlan_tag;
2768 m->m_flags |= M_VLANTAG;
2771 (*ifp->if_input)(ifp, m);
2775 /* Only necessary on the Tigon 1. */
2776 if (sc->ti_hwrev == TI_HWREV_TIGON)
2777 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2778 sc->ti_rx_saved_considx);
2780 TI_UPDATE_STDPROD(sc, sc->ti_std);
2781 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2782 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2786 ti_txeof(struct ti_softc *sc)
2788 struct ti_txdesc *txd;
2789 struct ti_tx_desc txdesc;
2790 struct ti_tx_desc *cur_tx = NULL;
2796 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2800 * Go through our tx ring and free mbufs for those
2801 * frames that have been sent.
2803 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2804 TI_INC(idx, TI_TX_RING_CNT)) {
2805 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2806 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2807 sizeof(txdesc), &txdesc);
2810 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2812 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2813 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2815 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2816 BUS_DMASYNC_POSTWRITE);
2817 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2822 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2823 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2824 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2826 sc->ti_tx_saved_considx = idx;
2828 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0;
2834 struct ti_softc *sc;
2842 /* Avoid this for now -- checking this register is expensive. */
2843 /* Make sure this is really our interrupt. */
2844 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2850 /* Ack interrupt and stop others from occuring. */
2851 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2853 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2854 /* Check RX return ring producer/consumer */
2857 /* Check TX ring producer/consumer */
2861 ti_handle_events(sc);
2863 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2864 /* Re-enable interrupts. */
2865 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2866 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2867 ti_start_locked(ifp);
2874 ti_stats_update(struct ti_softc *sc)
2880 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2881 BUS_DMASYNC_POSTREAD);
2883 ifp->if_collisions +=
2884 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2885 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2886 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2887 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2890 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2891 BUS_DMASYNC_PREREAD);
2895 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2896 * pointers to descriptors.
2899 ti_encap(struct ti_softc *sc, struct mbuf **m_head)
2901 struct ti_txdesc *txd;
2902 struct ti_tx_desc *f;
2903 struct ti_tx_desc txdesc;
2905 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
2906 uint16_t csum_flags;
2907 int error, frag, i, nseg;
2909 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
2912 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2913 *m_head, txsegs, &nseg, 0);
2914 if (error == EFBIG) {
2915 m = m_defrag(*m_head, M_DONTWAIT);
2922 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat,
2923 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2929 } else if (error != 0)
2937 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
2938 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2944 if (m->m_pkthdr.csum_flags) {
2945 if (m->m_pkthdr.csum_flags & CSUM_IP)
2946 csum_flags |= TI_BDFLAG_IP_CKSUM;
2947 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2948 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2949 if (m->m_flags & M_LASTFRAG)
2950 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2951 else if (m->m_flags & M_FRAG)
2952 csum_flags |= TI_BDFLAG_IP_FRAG;
2955 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2956 BUS_DMASYNC_PREWRITE);
2957 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2958 BUS_DMASYNC_PREWRITE);
2960 frag = sc->ti_tx_saved_prodidx;
2961 for (i = 0; i < nseg; i++) {
2962 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2963 bzero(&txdesc, sizeof(txdesc));
2966 f = &sc->ti_rdata->ti_tx_ring[frag];
2967 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
2968 f->ti_len = txsegs[i].ds_len;
2969 f->ti_flags = csum_flags;
2970 if (m->m_flags & M_VLANTAG) {
2971 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2972 f->ti_vlan_tag = m->m_pkthdr.ether_vtag;
2977 if (sc->ti_hwrev == TI_HWREV_TIGON)
2978 ti_mem_write(sc, TI_TX_RING_BASE + frag *
2979 sizeof(txdesc), sizeof(txdesc), &txdesc);
2980 TI_INC(frag, TI_TX_RING_CNT);
2983 sc->ti_tx_saved_prodidx = frag;
2984 /* set TI_BDFLAG_END on the last descriptor */
2985 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
2986 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2987 txdesc.ti_flags |= TI_BDFLAG_END;
2988 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
2989 sizeof(txdesc), &txdesc);
2991 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
2993 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
2994 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
2996 sc->ti_txcnt += nseg;
3002 ti_start(struct ifnet *ifp)
3004 struct ti_softc *sc;
3008 ti_start_locked(ifp);
3013 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3014 * to the mbuf data regions directly in the transmit descriptors.
3017 ti_start_locked(struct ifnet *ifp)
3019 struct ti_softc *sc;
3020 struct mbuf *m_head = NULL;
3025 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
3026 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3027 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3033 * safety overkill. If this is a fragmented packet chain
3034 * with delayed TCP/UDP checksums, then only encapsulate
3035 * it if we have enough descriptors to handle the entire
3037 * (paranoia -- may not actually be needed)
3039 if (m_head->m_flags & M_FIRSTFRAG &&
3040 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3041 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
3042 m_head->m_pkthdr.csum_data + 16) {
3043 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3044 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3050 * Pack the data into the transmit ring. If we
3051 * don't have room, set the OACTIVE flag and wait
3052 * for the NIC to drain the ring.
3054 if (ti_encap(sc, &m_head)) {
3057 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3058 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3064 * If there's a BPF listener, bounce a copy of this frame
3067 ETHER_BPF_MTAP(ifp, m_head);
3072 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3075 * Set a timeout in case the chip goes out to lunch.
3084 struct ti_softc *sc;
3093 ti_init_locked(void *xsc)
3095 struct ti_softc *sc = xsc;
3097 /* Cancel pending I/O and flush buffers. */
3100 /* Init the gen info block, ring control blocks and firmware. */
3101 if (ti_gibinit(sc)) {
3102 device_printf(sc->ti_dev, "initialization failure\n");
3107 static void ti_init2(struct ti_softc *sc)
3109 struct ti_cmd_desc cmd;
3112 struct ifmedia *ifm;
3119 /* Specify MTU and interface index. */
3120 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
3121 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3122 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3123 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3125 /* Load our MAC address. */
3126 ea = IF_LLADDR(sc->ti_ifp);
3127 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3128 CSR_WRITE_4(sc, TI_GCR_PAR1,
3129 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3130 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3132 /* Enable or disable promiscuous mode as needed. */
3133 if (ifp->if_flags & IFF_PROMISC) {
3134 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3136 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3139 /* Program multicast filter. */
3143 * If this is a Tigon 1, we should tell the
3144 * firmware to use software packet filtering.
3146 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3147 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3151 ti_init_rx_ring_std(sc);
3153 /* Init jumbo RX ring. */
3154 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3155 ti_init_rx_ring_jumbo(sc);
3158 * If this is a Tigon 2, we can also configure the
3161 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
3162 ti_init_rx_ring_mini(sc);
3164 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3165 sc->ti_rx_saved_considx = 0;
3168 ti_init_tx_ring(sc);
3170 /* Tell firmware we're alive. */
3171 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3173 /* Enable host interrupts. */
3174 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3176 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3177 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3178 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3181 * Make sure to set media properly. We have to do this
3182 * here since we have to issue commands in order to set
3183 * the link negotiation and we can't issue commands until
3184 * the firmware is running.
3187 tmp = ifm->ifm_media;
3188 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3189 ti_ifmedia_upd_locked(sc);
3190 ifm->ifm_media = tmp;
3194 * Set media options.
3197 ti_ifmedia_upd(struct ifnet *ifp)
3199 struct ti_softc *sc;
3204 error = ti_ifmedia_upd(ifp);
3211 ti_ifmedia_upd_locked(struct ti_softc *sc)
3213 struct ifmedia *ifm;
3214 struct ti_cmd_desc cmd;
3219 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3224 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3227 * Transmit flow control doesn't work on the Tigon 1.
3229 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3232 * Transmit flow control can also cause problems on the
3233 * Tigon 2, apparantly with both the copper and fiber
3234 * boards. The symptom is that the interface will just
3235 * hang. This was reproduced with Alteon 180 switches.
3238 if (sc->ti_hwrev != TI_HWREV_TIGON)
3239 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3242 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3243 TI_GLNK_FULL_DUPLEX| flowctl |
3244 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3246 flowctl = TI_LNK_RX_FLOWCTL_Y;
3248 if (sc->ti_hwrev != TI_HWREV_TIGON)
3249 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3252 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3253 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3254 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3255 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3256 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3260 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3262 if (sc->ti_hwrev != TI_HWREV_TIGON)
3263 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3266 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3267 flowctl |TI_GLNK_ENB);
3268 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3269 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3270 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3272 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3273 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3279 flowctl = TI_LNK_RX_FLOWCTL_Y;
3281 if (sc->ti_hwrev != TI_HWREV_TIGON)
3282 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3285 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3286 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3287 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3288 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3289 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3291 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3293 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3294 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3296 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3298 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3299 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3307 * Report current media status.
3310 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3312 struct ti_softc *sc;
3319 ifmr->ifm_status = IFM_AVALID;
3320 ifmr->ifm_active = IFM_ETHER;
3322 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
3327 ifmr->ifm_status |= IFM_ACTIVE;
3329 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3330 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3332 ifmr->ifm_active |= IFM_1000_T;
3334 ifmr->ifm_active |= IFM_1000_SX;
3335 if (media & TI_GLNK_FULL_DUPLEX)
3336 ifmr->ifm_active |= IFM_FDX;
3338 ifmr->ifm_active |= IFM_HDX;
3339 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3340 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3341 if (sc->ti_copper) {
3342 if (media & TI_LNK_100MB)
3343 ifmr->ifm_active |= IFM_100_TX;
3344 if (media & TI_LNK_10MB)
3345 ifmr->ifm_active |= IFM_10_T;
3347 if (media & TI_LNK_100MB)
3348 ifmr->ifm_active |= IFM_100_FX;
3349 if (media & TI_LNK_10MB)
3350 ifmr->ifm_active |= IFM_10_FL;
3352 if (media & TI_LNK_FULL_DUPLEX)
3353 ifmr->ifm_active |= IFM_FDX;
3354 if (media & TI_LNK_HALF_DUPLEX)
3355 ifmr->ifm_active |= IFM_HDX;
3361 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3363 struct ti_softc *sc = ifp->if_softc;
3364 struct ifreq *ifr = (struct ifreq *) data;
3365 struct ti_cmd_desc cmd;
3366 int mask, error = 0;
3371 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3374 ifp->if_mtu = ifr->ifr_mtu;
3381 if (ifp->if_flags & IFF_UP) {
3383 * If only the state of the PROMISC flag changed,
3384 * then just use the 'set promisc mode' command
3385 * instead of reinitializing the entire NIC. Doing
3386 * a full re-init means reloading the firmware and
3387 * waiting for it to start up, which may take a
3390 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3391 ifp->if_flags & IFF_PROMISC &&
3392 !(sc->ti_if_flags & IFF_PROMISC)) {
3393 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3394 TI_CMD_CODE_PROMISC_ENB, 0);
3395 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3396 !(ifp->if_flags & IFF_PROMISC) &&
3397 sc->ti_if_flags & IFF_PROMISC) {
3398 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3399 TI_CMD_CODE_PROMISC_DIS, 0);
3403 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3407 sc->ti_if_flags = ifp->if_flags;
3413 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3419 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3423 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3424 if ((mask & IFCAP_TXCSUM) != 0 &&
3425 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3426 ifp->if_capenable ^= IFCAP_TXCSUM;
3427 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3428 ifp->if_hwassist |= TI_CSUM_FEATURES;
3430 ifp->if_hwassist &= ~TI_CSUM_FEATURES;
3432 if ((mask & IFCAP_RXCSUM) != 0 &&
3433 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3434 ifp->if_capenable ^= IFCAP_RXCSUM;
3435 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3436 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0)
3437 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3438 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3439 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
3440 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
3441 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM |
3442 IFCAP_VLAN_HWTAGGING)) != 0) {
3443 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3444 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3449 VLAN_CAPABILITIES(ifp);
3452 error = ether_ioctl(ifp, command, data);
3460 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3462 struct ti_softc *sc;
3469 sc->ti_flags |= TI_FLAG_DEBUGING;
3476 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3478 struct ti_softc *sc;
3485 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3492 * This ioctl routine goes along with the Tigon character device.
3495 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3498 struct ti_softc *sc;
3510 struct ti_stats *outstats;
3512 outstats = (struct ti_stats *)addr;
3515 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3516 sizeof(struct ti_stats));
3520 case TIIOCGETPARAMS:
3522 struct ti_params *params;
3524 params = (struct ti_params *)addr;
3527 params->ti_stat_ticks = sc->ti_stat_ticks;
3528 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3529 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3530 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3531 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3532 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3533 params->param_mask = TI_PARAM_ALL;
3540 case TIIOCSETPARAMS:
3542 struct ti_params *params;
3544 params = (struct ti_params *)addr;
3547 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3548 sc->ti_stat_ticks = params->ti_stat_ticks;
3549 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3552 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3553 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3554 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3555 sc->ti_rx_coal_ticks);
3558 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3559 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3560 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3561 sc->ti_tx_coal_ticks);
3564 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3565 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3566 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3567 sc->ti_rx_max_coal_bds);
3570 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3571 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3572 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3573 sc->ti_tx_max_coal_bds);
3576 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3577 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3578 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3579 sc->ti_tx_buf_ratio);
3587 case TIIOCSETTRACE: {
3588 ti_trace_type trace_type;
3590 trace_type = *(ti_trace_type *)addr;
3593 * Set tracing to whatever the user asked for. Setting
3594 * this register to 0 should have the effect of disabling
3597 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3603 case TIIOCGETTRACE: {
3604 struct ti_trace_buf *trace_buf;
3605 uint32_t trace_start, cur_trace_ptr, trace_len;
3607 trace_buf = (struct ti_trace_buf *)addr;
3610 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3611 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3612 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3615 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3616 "trace_len = %d\n", trace_start,
3617 cur_trace_ptr, trace_len);
3618 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3619 trace_buf->buf_len);
3622 error = ti_copy_mem(sc, trace_start, min(trace_len,
3623 trace_buf->buf_len),
3624 (caddr_t)trace_buf->buf, 1, 1);
3627 trace_buf->fill_len = min(trace_len,
3628 trace_buf->buf_len);
3629 if (cur_trace_ptr < trace_start)
3630 trace_buf->cur_trace_ptr =
3631 trace_start - cur_trace_ptr;
3633 trace_buf->cur_trace_ptr =
3634 cur_trace_ptr - trace_start;
3636 trace_buf->fill_len = 0;
3643 * For debugging, five ioctls are needed:
3652 * From what I can tell, Alteon's Solaris Tigon driver
3653 * only has one character device, so you have to attach
3654 * to the Tigon board you're interested in. This seems
3655 * like a not-so-good way to do things, since unless you
3656 * subsequently specify the unit number of the device
3657 * you're interested in every ioctl, you'll only be
3658 * able to debug one board at a time.
3662 case ALT_READ_TG_MEM:
3663 case ALT_WRITE_TG_MEM:
3665 struct tg_mem *mem_param;
3666 uint32_t sram_end, scratch_end;
3668 mem_param = (struct tg_mem *)addr;
3670 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3671 sram_end = TI_END_SRAM_I;
3672 scratch_end = TI_END_SCRATCH_I;
3674 sram_end = TI_END_SRAM_II;
3675 scratch_end = TI_END_SCRATCH_II;
3679 * For now, we'll only handle accessing regular SRAM,
3683 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3684 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3686 * In this instance, we always copy to/from user
3687 * space, so the user space argument is set to 1.
3689 error = ti_copy_mem(sc, mem_param->tgAddr,
3691 mem_param->userAddr, 1,
3692 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3693 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3694 && (mem_param->tgAddr <= scratch_end)) {
3695 error = ti_copy_scratch(sc, mem_param->tgAddr,
3697 mem_param->userAddr, 1,
3698 (cmd == ALT_READ_TG_MEM) ?
3699 1 : 0, TI_PROCESSOR_A);
3700 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3701 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3702 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3703 if_printf(sc->ti_ifp,
3704 "invalid memory range for Tigon I\n");
3708 error = ti_copy_scratch(sc, mem_param->tgAddr -
3709 TI_SCRATCH_DEBUG_OFF,
3711 mem_param->userAddr, 1,
3712 (cmd == ALT_READ_TG_MEM) ?
3713 1 : 0, TI_PROCESSOR_B);
3715 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3716 "out of supported range\n",
3717 mem_param->tgAddr, mem_param->len);
3724 case ALT_READ_TG_REG:
3725 case ALT_WRITE_TG_REG:
3727 struct tg_reg *regs;
3730 regs = (struct tg_reg *)addr;
3733 * Make sure the address in question isn't out of range.
3735 if (regs->addr > TI_REG_MAX) {
3740 if (cmd == ALT_READ_TG_REG) {
3741 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3742 regs->addr, &tmpval, 1);
3743 regs->data = ntohl(tmpval);
3745 if ((regs->addr == TI_CPU_STATE)
3746 || (regs->addr == TI_CPU_CTL_B)) {
3747 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3748 regs->addr, tmpval);
3752 tmpval = htonl(regs->data);
3753 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3754 regs->addr, &tmpval, 1);
3768 ti_watchdog(void *arg)
3770 struct ti_softc *sc;
3775 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3776 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3780 * When we're debugging, the chip is often stopped for long periods
3781 * of time, and that would normally cause the watchdog timer to fire.
3782 * Since that impedes debugging, we don't want to do that.
3784 if (sc->ti_flags & TI_FLAG_DEBUGING)
3788 if_printf(ifp, "watchdog timeout -- resetting\n");
3796 * Stop the adapter and free any mbufs allocated to the
3800 ti_stop(struct ti_softc *sc)
3803 struct ti_cmd_desc cmd;
3809 /* Disable host interrupts. */
3810 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3812 * Tell firmware we're shutting down.
3814 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3816 /* Halt and reinitialize. */
3817 if (ti_chipinit(sc) != 0)
3819 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3820 if (ti_chipinit(sc) != 0)
3823 /* Free the RX lists. */
3824 ti_free_rx_ring_std(sc);
3826 /* Free jumbo RX list. */
3827 ti_free_rx_ring_jumbo(sc);
3829 /* Free mini RX list. */
3830 ti_free_rx_ring_mini(sc);
3832 /* Free TX buffers. */
3833 ti_free_tx_ring(sc);
3835 sc->ti_ev_prodidx.ti_idx = 0;
3836 sc->ti_return_prodidx.ti_idx = 0;
3837 sc->ti_tx_considx.ti_idx = 0;
3838 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3840 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3841 callout_stop(&sc->ti_watchdog);
3845 * Stop all chip I/O so that the kernel's probe routines don't
3846 * get confused by errant DMAs when rebooting.
3849 ti_shutdown(device_t dev)
3851 struct ti_softc *sc;
3853 sc = device_get_softc(dev);