2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
94 #include <sys/sf_buf.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
102 #include <net/if_vlan_var.h>
106 #include <netinet/in_systm.h>
107 #include <netinet/in.h>
108 #include <netinet/ip.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 /* #define TI_PRIVATE_JUMBOS */
116 #ifndef TI_PRIVATE_JUMBOS
118 #include <vm/vm_page.h>
121 #include <dev/pci/pcireg.h>
122 #include <dev/pci/pcivar.h>
124 #include <sys/tiio.h>
125 #include <dev/ti/if_tireg.h>
126 #include <dev/ti/ti_fw.h>
127 #include <dev/ti/ti_fw2.h>
129 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
131 * We can only turn on header splitting if we're using extended receive
134 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
135 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
136 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
144 * Various supported device vendors/types and their names.
147 static const struct ti_type const ti_devs[] = {
148 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
149 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
150 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
151 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
152 { TC_VENDORID, TC_DEVICEID_3C985,
153 "3Com 3c985-SX Gigabit Ethernet" },
154 { NG_VENDORID, NG_DEVICEID_GA620,
155 "Netgear GA620 1000baseSX Gigabit Ethernet" },
156 { NG_VENDORID, NG_DEVICEID_GA620T,
157 "Netgear GA620 1000baseT Gigabit Ethernet" },
158 { SGI_VENDORID, SGI_DEVICEID_TIGON,
159 "Silicon Graphics Gigabit Ethernet" },
160 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
161 "Farallon PN9000SX Gigabit Ethernet" },
166 static d_open_t ti_open;
167 static d_close_t ti_close;
168 static d_ioctl_t ti_ioctl2;
170 static struct cdevsw ti_cdevsw = {
171 .d_version = D_VERSION,
175 .d_ioctl = ti_ioctl2,
179 static int ti_probe(device_t);
180 static int ti_attach(device_t);
181 static int ti_detach(device_t);
182 static void ti_txeof(struct ti_softc *);
183 static void ti_rxeof(struct ti_softc *);
185 static void ti_stats_update(struct ti_softc *);
186 static int ti_encap(struct ti_softc *, struct mbuf **);
188 static void ti_intr(void *);
189 static void ti_start(struct ifnet *);
190 static void ti_start_locked(struct ifnet *);
191 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
192 static void ti_init(void *);
193 static void ti_init_locked(void *);
194 static void ti_init2(struct ti_softc *);
195 static void ti_stop(struct ti_softc *);
196 static void ti_watchdog(void *);
197 static int ti_shutdown(device_t);
198 static int ti_ifmedia_upd(struct ifnet *);
199 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
201 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
202 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
203 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
205 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
206 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
207 static void ti_setmulti(struct ti_softc *);
209 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
210 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
211 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
212 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
214 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
216 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
217 static void ti_loadfw(struct ti_softc *);
218 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
219 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
220 static void ti_handle_events(struct ti_softc *);
221 static int ti_alloc_dmamaps(struct ti_softc *);
222 static void ti_free_dmamaps(struct ti_softc *);
223 static int ti_alloc_jumbo_mem(struct ti_softc *);
224 #ifdef TI_PRIVATE_JUMBOS
225 static void *ti_jalloc(struct ti_softc *);
226 static void ti_jfree(void *, void *);
227 #endif /* TI_PRIVATE_JUMBOS */
228 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
229 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
230 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
231 static int ti_init_rx_ring_std(struct ti_softc *);
232 static void ti_free_rx_ring_std(struct ti_softc *);
233 static int ti_init_rx_ring_jumbo(struct ti_softc *);
234 static void ti_free_rx_ring_jumbo(struct ti_softc *);
235 static int ti_init_rx_ring_mini(struct ti_softc *);
236 static void ti_free_rx_ring_mini(struct ti_softc *);
237 static void ti_free_tx_ring(struct ti_softc *);
238 static int ti_init_tx_ring(struct ti_softc *);
240 static int ti_64bitslot_war(struct ti_softc *);
241 static int ti_chipinit(struct ti_softc *);
242 static int ti_gibinit(struct ti_softc *);
244 #ifdef TI_JUMBO_HDRSPLIT
245 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
247 #endif /* TI_JUMBO_HDRSPLIT */
249 static device_method_t ti_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, ti_probe),
252 DEVMETHOD(device_attach, ti_attach),
253 DEVMETHOD(device_detach, ti_detach),
254 DEVMETHOD(device_shutdown, ti_shutdown),
258 static driver_t ti_driver = {
261 sizeof(struct ti_softc)
264 static devclass_t ti_devclass;
266 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
267 MODULE_DEPEND(ti, pci, 1, 1, 1);
268 MODULE_DEPEND(ti, ether, 1, 1, 1);
271 * Send an instruction or address to the EEPROM, check for ACK.
274 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
279 * Make sure we're in TX mode.
281 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
284 * Feed in each bit and stobe the clock.
286 for (i = 0x80; i; i >>= 1) {
288 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
290 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
295 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
301 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
306 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
307 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
308 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
314 * Read a byte of data stored in the EEPROM at address 'addr.'
315 * We have to send two address bytes since the EEPROM can hold
316 * more than 256 bytes of data.
319 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
327 * Send write control code to EEPROM.
329 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
330 device_printf(sc->ti_dev,
331 "failed to send write command, status: %x\n",
332 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
337 * Send first byte of address of byte we want to read.
339 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
340 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
341 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
345 * Send second byte address of byte we want to read.
347 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
348 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
349 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
356 * Send read control code to EEPROM.
358 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
359 device_printf(sc->ti_dev,
360 "failed to send read command, status: %x\n",
361 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
366 * Start reading bits from EEPROM.
368 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
369 for (i = 0x80; i; i >>= 1) {
370 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
372 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
374 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
381 * No ACK generated for read, so just return byte.
390 * Read a sequence of bytes from the EEPROM.
393 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
398 for (i = 0; i < cnt; i++) {
399 err = ti_eeprom_getbyte(sc, off + i, &byte);
405 return (err ? 1 : 0);
409 * NIC memory read function.
410 * Can be used to copy data from NIC local memory.
413 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
415 int segptr, segsize, cnt;
426 segsize = TI_WINLEN - (segptr % TI_WINLEN);
427 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
428 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
429 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
439 * NIC memory write function.
440 * Can be used to copy data into NIC local memory.
443 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
445 int segptr, segsize, cnt;
456 segsize = TI_WINLEN - (segptr % TI_WINLEN);
457 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
458 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
459 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
468 * NIC memory read function.
469 * Can be used to clear a section of NIC local memory.
472 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
474 int segptr, segsize, cnt;
483 segsize = TI_WINLEN - (segptr % TI_WINLEN);
484 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
485 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
486 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
493 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
494 caddr_t buf, int useraddr, int readdata)
496 int segptr, segsize, cnt;
499 uint8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
506 * At the moment, we don't handle non-aligned cases, we just bail.
507 * If this proves to be a problem, it will be fixed.
510 && (tigon_addr & 0x3)) {
511 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
512 "word-aligned\n", __func__, tigon_addr);
513 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
514 "yet supported\n", __func__);
518 segptr = tigon_addr & ~0x3;
519 segresid = tigon_addr - segptr;
522 * This is the non-aligned amount left over that we'll need to
527 /* Add in the left over amount at the front of the buffer */
532 * If resid + segresid is >= 4, add multiples of 4 to the count and
533 * decrease the residual by that much.
536 resid -= resid & ~0x3;
543 * Save the old window base value.
545 origwin = CSR_READ_4(sc, TI_WINBASE);
548 bus_size_t ti_offset;
553 segsize = TI_WINLEN - (segptr % TI_WINLEN);
554 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
556 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
560 bus_space_read_region_4(sc->ti_btag,
561 sc->ti_bhandle, ti_offset,
562 (uint32_t *)tmparray,
566 * Yeah, this is a little on the kludgy
567 * side, but at least this code is only
568 * used for debugging.
570 ti_bcopy_swap(tmparray, tmparray2, segsize,
575 copyout(&tmparray2[segresid], ptr,
579 copyout(tmparray2, ptr, segsize);
584 ti_bcopy_swap(tmparray, tmparray2,
585 segsize, TI_SWAP_NTOH);
587 bcopy(&tmparray2[segresid], ptr,
592 ti_bcopy_swap(tmparray, ptr, segsize,
599 copyin(ptr, tmparray2, segsize);
601 ti_bcopy_swap(tmparray2, tmparray, segsize,
604 ti_bcopy_swap(ptr, tmparray, segsize,
607 bus_space_write_region_4(sc->ti_btag,
608 sc->ti_bhandle, ti_offset,
609 (uint32_t *)tmparray,
618 * Handle leftover, non-word-aligned bytes.
621 uint32_t tmpval, tmpval2;
622 bus_size_t ti_offset;
625 * Set the segment pointer.
627 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
629 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
632 * First, grab whatever is in our source/destination.
633 * We'll obviously need this for reads, but also for
634 * writes, since we'll be doing read/modify/write.
636 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
637 ti_offset, &tmpval, 1);
640 * Next, translate this from little-endian to big-endian
641 * (at least on i386 boxes).
643 tmpval2 = ntohl(tmpval);
647 * If we're reading, just copy the leftover number
648 * of bytes from the host byte order buffer to
653 copyout(&tmpval2, ptr, resid);
656 bcopy(&tmpval2, ptr, resid);
659 * If we're writing, first copy the bytes to be
660 * written into the network byte order buffer,
661 * leaving the rest of the buffer with whatever was
662 * originally in there. Then, swap the bytes
663 * around into host order and write them out.
665 * XXX KDM the read side of this has been verified
666 * to work, but the write side of it has not been
667 * verified. So user beware.
671 copyin(ptr, &tmpval2, resid);
674 bcopy(ptr, &tmpval2, resid);
676 tmpval = htonl(tmpval2);
678 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
679 ti_offset, &tmpval, 1);
683 CSR_WRITE_4(sc, TI_WINBASE, origwin);
689 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
690 caddr_t buf, int useraddr, int readdata, int cpu)
694 uint32_t tmpval, tmpval2;
700 * At the moment, we don't handle non-aligned cases, we just bail.
701 * If this proves to be a problem, it will be fixed.
703 if (tigon_addr & 0x3) {
704 device_printf(sc->ti_dev, "%s: tigon address %#x "
705 "isn't word-aligned\n", __func__, tigon_addr);
710 device_printf(sc->ti_dev, "%s: transfer length %d "
711 "isn't word-aligned\n", __func__, len);
720 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
723 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
725 tmpval = ntohl(tmpval2);
728 * Note: I've used this debugging interface
729 * extensively with Alteon's 12.3.15 firmware,
730 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
732 * When you compile the firmware without
733 * optimization, which is necessary sometimes in
734 * order to properly step through it, you sometimes
735 * read out a bogus value of 0xc0017c instead of
736 * whatever was supposed to be in that scratchpad
737 * location. That value is on the stack somewhere,
738 * but I've never been able to figure out what was
739 * causing the problem.
741 * The address seems to pop up in random places,
742 * often not in the same place on two subsequent
745 * In any case, the underlying data doesn't seem
746 * to be affected, just the value read out.
751 if (tmpval2 == 0xc0017c)
752 device_printf(sc->ti_dev, "found 0xc0017c at "
753 "%#x (tmpval2)\n", segptr);
755 if (tmpval == 0xc0017c)
756 device_printf(sc->ti_dev, "found 0xc0017c at "
757 "%#x (tmpval)\n", segptr);
760 copyout(&tmpval, ptr, 4);
762 bcopy(&tmpval, ptr, 4);
765 copyin(ptr, &tmpval2, 4);
767 bcopy(ptr, &tmpval2, 4);
769 tmpval = htonl(tmpval2);
771 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
783 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
785 const uint8_t *tmpsrc;
790 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
800 if (swap_type == TI_SWAP_NTOH)
801 *(uint32_t *)tmpdst =
802 ntohl(*(const uint32_t *)tmpsrc);
804 *(uint32_t *)tmpdst =
805 htonl(*(const uint32_t *)tmpsrc);
816 * Load firmware image into the NIC. Check that the firmware revision
817 * is acceptable and see if we want the firmware for the Tigon 1 or
821 ti_loadfw(struct ti_softc *sc)
826 switch (sc->ti_hwrev) {
828 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
829 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
830 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
831 device_printf(sc->ti_dev, "firmware revision mismatch; "
832 "want %d.%d.%d, got %d.%d.%d\n",
833 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
834 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
835 tigonFwReleaseMinor, tigonFwReleaseFix);
838 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
839 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
840 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
842 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
843 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
844 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
846 case TI_HWREV_TIGON_II:
847 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
848 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
849 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
850 device_printf(sc->ti_dev, "firmware revision mismatch; "
851 "want %d.%d.%d, got %d.%d.%d\n",
852 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
853 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
854 tigon2FwReleaseMinor, tigon2FwReleaseFix);
857 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
859 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
861 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
863 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
864 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
865 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
868 device_printf(sc->ti_dev,
869 "can't load firmware: unknown hardware rev\n");
875 * Send the NIC a command via the command ring.
878 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
882 index = sc->ti_cmd_saved_prodidx;
883 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
884 TI_INC(index, TI_CMD_RING_CNT);
885 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
886 sc->ti_cmd_saved_prodidx = index;
890 * Send the NIC an extended command. The 'len' parameter specifies the
891 * number of command slots to include after the initial command.
894 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
899 index = sc->ti_cmd_saved_prodidx;
900 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
901 TI_INC(index, TI_CMD_RING_CNT);
902 for (i = 0; i < len; i++) {
903 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
904 *(uint32_t *)(&arg[i * 4]));
905 TI_INC(index, TI_CMD_RING_CNT);
907 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
908 sc->ti_cmd_saved_prodidx = index;
912 * Handle events that have triggered interrupts.
915 ti_handle_events(struct ti_softc *sc)
917 struct ti_event_desc *e;
919 if (sc->ti_rdata->ti_event_ring == NULL)
922 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
923 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
924 switch (TI_EVENT_EVENT(e)) {
925 case TI_EV_LINKSTAT_CHANGED:
926 sc->ti_linkstat = TI_EVENT_CODE(e);
927 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP)
928 device_printf(sc->ti_dev, "10/100 link up\n");
929 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
930 device_printf(sc->ti_dev, "gigabit link up\n");
931 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
932 device_printf(sc->ti_dev, "link down\n");
935 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
936 device_printf(sc->ti_dev, "invalid command\n");
937 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
938 device_printf(sc->ti_dev, "unknown command\n");
939 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
940 device_printf(sc->ti_dev, "bad config data\n");
942 case TI_EV_FIRMWARE_UP:
945 case TI_EV_STATS_UPDATED:
948 case TI_EV_RESET_JUMBO_RING:
949 case TI_EV_MCAST_UPDATED:
953 device_printf(sc->ti_dev, "unknown event: %d\n",
957 /* Advance the consumer index. */
958 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
959 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
964 ti_alloc_dmamaps(struct ti_softc *sc)
968 for (i = 0; i < TI_TX_RING_CNT; i++) {
969 sc->ti_cdata.ti_txdesc[i].tx_m = NULL;
970 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
971 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0,
972 &sc->ti_cdata.ti_txdesc[i].tx_dmamap))
975 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
976 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
977 &sc->ti_cdata.ti_rx_std_maps[i]))
981 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
982 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0,
983 &sc->ti_cdata.ti_rx_jumbo_maps[i]))
986 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
987 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
988 &sc->ti_cdata.ti_rx_mini_maps[i]))
996 ti_free_dmamaps(struct ti_softc *sc)
1000 if (sc->ti_mbuftx_dmat)
1001 for (i = 0; i < TI_TX_RING_CNT; i++)
1002 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1003 bus_dmamap_destroy(sc->ti_mbuftx_dmat,
1004 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1005 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
1008 if (sc->ti_mbufrx_dmat)
1009 for (i = 0; i < TI_STD_RX_RING_CNT; i++)
1010 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1011 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1012 sc->ti_cdata.ti_rx_std_maps[i]);
1013 sc->ti_cdata.ti_rx_std_maps[i] = 0;
1016 if (sc->ti_jumbo_dmat)
1017 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++)
1018 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1019 bus_dmamap_destroy(sc->ti_jumbo_dmat,
1020 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1021 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0;
1023 if (sc->ti_mbufrx_dmat)
1024 for (i = 0; i < TI_MINI_RX_RING_CNT; i++)
1025 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1026 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1027 sc->ti_cdata.ti_rx_mini_maps[i]);
1028 sc->ti_cdata.ti_rx_mini_maps[i] = 0;
1032 #ifdef TI_PRIVATE_JUMBOS
1035 * Memory management for the jumbo receive ring is a pain in the
1036 * butt. We need to allocate at least 9018 bytes of space per frame,
1037 * _and_ it has to be contiguous (unless you use the extended
1038 * jumbo descriptor format). Using malloc() all the time won't
1039 * work: malloc() allocates memory in powers of two, which means we
1040 * would end up wasting a considerable amount of space by allocating
1041 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
1042 * to do our own memory management.
1044 * The driver needs to allocate a contiguous chunk of memory at boot
1045 * time. We then chop this up ourselves into 9K pieces and use them
1046 * as external mbuf storage.
1048 * One issue here is how much memory to allocate. The jumbo ring has
1049 * 256 slots in it, but at 9K per slot than can consume over 2MB of
1050 * RAM. This is a bit much, especially considering we also need
1051 * RAM for the standard ring and mini ring (on the Tigon 2). To
1052 * save space, we only actually allocate enough memory for 64 slots
1053 * by default, which works out to between 500 and 600K. This can
1054 * be tuned by changing a #define in if_tireg.h.
1058 ti_alloc_jumbo_mem(struct ti_softc *sc)
1060 struct ti_jpool_entry *entry;
1065 * Grab a big chunk o' storage. Since we are chopping this pool up
1066 * into ~9k chunks, there doesn't appear to be a need to use page
1069 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1070 1, 0, /* algnmnt, boundary */
1071 BUS_SPACE_MAXADDR, /* lowaddr */
1072 BUS_SPACE_MAXADDR, /* highaddr */
1073 NULL, NULL, /* filter, filterarg */
1074 TI_JMEM, /* maxsize */
1076 TI_JMEM, /* maxsegsize */
1078 NULL, NULL, /* lockfunc, lockarg */
1079 &sc->ti_jumbo_dmat) != 0) {
1080 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1084 if (bus_dmamem_alloc(sc->ti_jumbo_dmat,
1085 (void**)&sc->ti_cdata.ti_jumbo_buf,
1086 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
1087 &sc->ti_jumbo_dmamap) != 0) {
1088 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n");
1092 SLIST_INIT(&sc->ti_jfree_listhead);
1093 SLIST_INIT(&sc->ti_jinuse_listhead);
1096 * Now divide it up into 9K pieces and save the addresses
1099 ptr = sc->ti_cdata.ti_jumbo_buf;
1100 for (i = 0; i < TI_JSLOTS; i++) {
1101 sc->ti_cdata.ti_jslots[i] = ptr;
1103 entry = malloc(sizeof(struct ti_jpool_entry),
1104 M_DEVBUF, M_NOWAIT);
1105 if (entry == NULL) {
1106 device_printf(sc->ti_dev, "no memory for jumbo "
1111 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1118 * Allocate a jumbo buffer.
1120 static void *ti_jalloc(struct ti_softc *sc)
1122 struct ti_jpool_entry *entry;
1124 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1126 if (entry == NULL) {
1127 device_printf(sc->ti_dev, "no free jumbo buffers\n");
1131 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1132 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1133 return (sc->ti_cdata.ti_jslots[entry->slot]);
1137 * Release a jumbo buffer.
1140 ti_jfree(void *buf, void *args)
1142 struct ti_softc *sc;
1144 struct ti_jpool_entry *entry;
1146 /* Extract the softc struct pointer. */
1147 sc = (struct ti_softc *)args;
1150 panic("ti_jfree: didn't get softc pointer!");
1152 /* calculate the slot this buffer belongs to */
1153 i = ((vm_offset_t)buf
1154 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1156 if ((i < 0) || (i >= TI_JSLOTS))
1157 panic("ti_jfree: asked to free buffer that we don't manage!");
1159 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1161 panic("ti_jfree: buffer not in use!");
1163 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1164 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1170 ti_alloc_jumbo_mem(struct ti_softc *sc)
1174 * The VM system will take care of providing aligned pages. Alignment
1175 * is set to 1 here so that busdma resources won't be wasted.
1177 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1178 1, 0, /* algnmnt, boundary */
1179 BUS_SPACE_MAXADDR, /* lowaddr */
1180 BUS_SPACE_MAXADDR, /* highaddr */
1181 NULL, NULL, /* filter, filterarg */
1182 PAGE_SIZE * 4 /*XXX*/, /* maxsize */
1184 PAGE_SIZE, /* maxsegsize */
1186 NULL, NULL, /* lockfunc, lockarg */
1187 &sc->ti_jumbo_dmat) != 0) {
1188 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1195 #endif /* TI_PRIVATE_JUMBOS */
1198 * Intialize a standard receive ring descriptor.
1201 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m)
1204 bus_dma_segment_t segs;
1205 struct mbuf *m_new = NULL;
1206 struct ti_rx_desc *r;
1211 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1215 MCLGET(m_new, M_DONTWAIT);
1216 if (!(m_new->m_flags & M_EXT)) {
1220 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1223 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1224 m_new->m_data = m_new->m_ext.ext_buf;
1227 m_adj(m_new, ETHER_ALIGN);
1228 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1229 r = &sc->ti_rdata->ti_rx_std_ring[i];
1230 map = sc->ti_cdata.ti_rx_std_maps[i];
1231 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1236 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1237 r->ti_len = segs.ds_len;
1238 r->ti_type = TI_BDTYPE_RECV_BD;
1240 if (sc->ti_ifp->if_hwassist)
1241 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1244 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1249 * Intialize a mini receive ring descriptor. This only applies to
1253 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m)
1255 bus_dma_segment_t segs;
1257 struct mbuf *m_new = NULL;
1258 struct ti_rx_desc *r;
1263 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1264 if (m_new == NULL) {
1267 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1270 m_new->m_data = m_new->m_pktdat;
1271 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1274 m_adj(m_new, ETHER_ALIGN);
1275 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1276 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1277 map = sc->ti_cdata.ti_rx_mini_maps[i];
1278 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1283 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1284 r->ti_len = segs.ds_len;
1285 r->ti_type = TI_BDTYPE_RECV_BD;
1286 r->ti_flags = TI_BDFLAG_MINI_RING;
1287 if (sc->ti_ifp->if_hwassist)
1288 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1291 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1295 #ifdef TI_PRIVATE_JUMBOS
1298 * Initialize a jumbo receive ring descriptor. This allocates
1299 * a jumbo buffer from the pool managed internally by the driver.
1302 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
1305 struct mbuf *m_new = NULL;
1306 struct ti_rx_desc *r;
1308 bus_dma_segment_t segs;
1311 caddr_t *buf = NULL;
1313 /* Allocate the mbuf. */
1314 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1315 if (m_new == NULL) {
1319 /* Allocate the jumbo buffer */
1320 buf = ti_jalloc(sc);
1323 device_printf(sc->ti_dev, "jumbo allocation failed "
1324 "-- packet dropped!\n");
1328 /* Attach the buffer to the mbuf. */
1329 m_new->m_data = (void *) buf;
1330 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1331 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, buf,
1332 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1335 m_new->m_data = m_new->m_ext.ext_buf;
1336 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1339 m_adj(m_new, ETHER_ALIGN);
1340 /* Set up the descriptor. */
1341 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1342 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1343 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1344 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs,
1349 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1350 r->ti_len = segs.ds_len;
1351 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1352 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1353 if (sc->ti_ifp->if_hwassist)
1354 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1357 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1363 #if (PAGE_SIZE == 4096)
1369 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1370 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1371 #define NFS_HDR_LEN (UDP_HDR_LEN)
1372 static int HDR_LEN = TCP_HDR_LEN;
1375 * Initialize a jumbo receive ring descriptor. This allocates
1376 * a jumbo buffer from the pool managed internally by the driver.
1379 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1382 struct mbuf *cur, *m_new = NULL;
1383 struct mbuf *m[3] = {NULL, NULL, NULL};
1384 struct ti_rx_desc_ext *r;
1387 /* 1 extra buf to make nobufs easy*/
1388 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1390 bus_dma_segment_t segs[4];
1393 if (m_old != NULL) {
1395 cur = m_old->m_next;
1396 for (i = 0; i <= NPAYLOAD; i++){
1401 /* Allocate the mbufs. */
1402 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1403 if (m_new == NULL) {
1404 device_printf(sc->ti_dev, "mbuf allocation failed "
1405 "-- packet dropped!\n");
1408 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1409 if (m[NPAYLOAD] == NULL) {
1410 device_printf(sc->ti_dev, "cluster mbuf allocation "
1411 "failed -- packet dropped!\n");
1414 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1415 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1416 device_printf(sc->ti_dev, "mbuf allocation failed "
1417 "-- packet dropped!\n");
1420 m[NPAYLOAD]->m_len = MCLBYTES;
1422 for (i = 0; i < NPAYLOAD; i++){
1423 MGET(m[i], M_DONTWAIT, MT_DATA);
1425 device_printf(sc->ti_dev, "mbuf allocation "
1426 "failed -- packet dropped!\n");
1429 frame = vm_page_alloc(NULL, color++,
1430 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1432 if (frame == NULL) {
1433 device_printf(sc->ti_dev, "buffer allocation "
1434 "failed -- packet dropped!\n");
1435 printf(" index %d page %d\n", idx, i);
1438 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1439 if (sf[i] == NULL) {
1440 vm_page_lock_queues();
1441 vm_page_unwire(frame, 0);
1442 vm_page_free(frame);
1443 vm_page_unlock_queues();
1444 device_printf(sc->ti_dev, "buffer allocation "
1445 "failed -- packet dropped!\n");
1446 printf(" index %d page %d\n", idx, i);
1450 for (i = 0; i < NPAYLOAD; i++){
1451 /* Attach the buffer to the mbuf. */
1452 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1453 m[i]->m_len = PAGE_SIZE;
1454 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1455 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1457 m[i]->m_next = m[i+1];
1459 /* link the buffers to the header */
1460 m_new->m_next = m[0];
1461 m_new->m_data += ETHER_ALIGN;
1462 if (sc->ti_hdrsplit)
1463 m_new->m_len = MHLEN - ETHER_ALIGN;
1465 m_new->m_len = HDR_LEN;
1466 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1469 /* Set up the descriptor. */
1470 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1471 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1472 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1473 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs,
1476 if ((nsegs < 1) || (nsegs > 4))
1478 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1479 r->ti_len0 = m_new->m_len;
1481 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1482 r->ti_len1 = PAGE_SIZE;
1484 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1485 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1487 if (PAGE_SIZE == 4096) {
1488 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1489 r->ti_len3 = MCLBYTES;
1493 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1495 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1497 if (sc->ti_ifp->if_hwassist)
1498 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1502 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1509 * This can only be called before the mbufs are strung together.
1510 * If the mbufs are strung together, m_freem() will free the chain,
1511 * so that the later mbufs will be freed multiple times.
1516 for (i = 0; i < 3; i++) {
1520 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1527 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1528 * that's 1MB or memory, which is a lot. For now, we fill only the first
1529 * 256 ring entries and hope that our CPU is fast enough to keep up with
1533 ti_init_rx_ring_std(struct ti_softc *sc)
1536 struct ti_cmd_desc cmd;
1538 for (i = 0; i < TI_SSLOTS; i++) {
1539 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1543 TI_UPDATE_STDPROD(sc, i - 1);
1550 ti_free_rx_ring_std(struct ti_softc *sc)
1555 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1556 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1557 map = sc->ti_cdata.ti_rx_std_maps[i];
1558 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1559 BUS_DMASYNC_POSTREAD);
1560 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1561 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1562 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1564 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1565 sizeof(struct ti_rx_desc));
1570 ti_init_rx_ring_jumbo(struct ti_softc *sc)
1572 struct ti_cmd_desc cmd;
1575 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1576 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1580 TI_UPDATE_JUMBOPROD(sc, i - 1);
1581 sc->ti_jumbo = i - 1;
1587 ti_free_rx_ring_jumbo(struct ti_softc *sc)
1592 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1593 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1594 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1595 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
1596 BUS_DMASYNC_POSTREAD);
1597 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
1598 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1599 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1601 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1602 sizeof(struct ti_rx_desc));
1607 ti_init_rx_ring_mini(struct ti_softc *sc)
1611 for (i = 0; i < TI_MSLOTS; i++) {
1612 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1616 TI_UPDATE_MINIPROD(sc, i - 1);
1617 sc->ti_mini = i - 1;
1623 ti_free_rx_ring_mini(struct ti_softc *sc)
1628 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1629 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1630 map = sc->ti_cdata.ti_rx_mini_maps[i];
1631 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1632 BUS_DMASYNC_POSTREAD);
1633 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1634 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1635 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1637 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1638 sizeof(struct ti_rx_desc));
1643 ti_free_tx_ring(struct ti_softc *sc)
1645 struct ti_txdesc *txd;
1648 if (sc->ti_rdata->ti_tx_ring == NULL)
1651 for (i = 0; i < TI_TX_RING_CNT; i++) {
1652 txd = &sc->ti_cdata.ti_txdesc[i];
1653 if (txd->tx_m != NULL) {
1654 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
1655 BUS_DMASYNC_POSTWRITE);
1656 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
1660 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1661 sizeof(struct ti_tx_desc));
1666 ti_init_tx_ring(struct ti_softc *sc)
1668 struct ti_txdesc *txd;
1671 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1672 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1673 for (i = 0; i < TI_TX_RING_CNT; i++) {
1674 txd = &sc->ti_cdata.ti_txdesc[i];
1675 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1678 sc->ti_tx_saved_considx = 0;
1679 sc->ti_tx_saved_prodidx = 0;
1680 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1685 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1686 * but we have to support the old way too so that Tigon 1 cards will
1690 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1692 struct ti_cmd_desc cmd;
1694 uint32_t ext[2] = {0, 0};
1696 m = (uint16_t *)&addr->octet[0];
1698 switch (sc->ti_hwrev) {
1699 case TI_HWREV_TIGON:
1700 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1701 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1702 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1704 case TI_HWREV_TIGON_II:
1705 ext[0] = htons(m[0]);
1706 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1707 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1710 device_printf(sc->ti_dev, "unknown hwrev\n");
1716 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1718 struct ti_cmd_desc cmd;
1720 uint32_t ext[2] = {0, 0};
1722 m = (uint16_t *)&addr->octet[0];
1724 switch (sc->ti_hwrev) {
1725 case TI_HWREV_TIGON:
1726 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1727 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1728 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1730 case TI_HWREV_TIGON_II:
1731 ext[0] = htons(m[0]);
1732 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1733 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1736 device_printf(sc->ti_dev, "unknown hwrev\n");
1742 * Configure the Tigon's multicast address filter.
1744 * The actual multicast table management is a bit of a pain, thanks to
1745 * slight brain damage on the part of both Alteon and us. With our
1746 * multicast code, we are only alerted when the multicast address table
1747 * changes and at that point we only have the current list of addresses:
1748 * we only know the current state, not the previous state, so we don't
1749 * actually know what addresses were removed or added. The firmware has
1750 * state, but we can't get our grubby mits on it, and there is no 'delete
1751 * all multicast addresses' command. Hence, we have to maintain our own
1752 * state so we know what addresses have been programmed into the NIC at
1756 ti_setmulti(struct ti_softc *sc)
1759 struct ifmultiaddr *ifma;
1760 struct ti_cmd_desc cmd;
1761 struct ti_mc_entry *mc;
1768 if (ifp->if_flags & IFF_ALLMULTI) {
1769 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1772 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1775 /* Disable interrupts. */
1776 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1777 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1779 /* First, zot all the existing filters. */
1780 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1781 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1782 ti_del_mcast(sc, &mc->mc_addr);
1783 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1787 /* Now program new ones. */
1788 if_maddr_rlock(ifp);
1789 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1790 if (ifma->ifma_addr->sa_family != AF_LINK)
1792 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1794 device_printf(sc->ti_dev,
1795 "no memory for mcast filter entry\n");
1798 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1799 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1800 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1801 ti_add_mcast(sc, &mc->mc_addr);
1803 if_maddr_runlock(ifp);
1805 /* Re-enable interrupts. */
1806 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1810 * Check to see if the BIOS has configured us for a 64 bit slot when
1811 * we aren't actually in one. If we detect this condition, we can work
1812 * around it on the Tigon 2 by setting a bit in the PCI state register,
1813 * but for the Tigon 1 we must give up and abort the interface attach.
1815 static int ti_64bitslot_war(struct ti_softc *sc)
1818 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1819 CSR_WRITE_4(sc, 0x600, 0);
1820 CSR_WRITE_4(sc, 0x604, 0);
1821 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1822 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1823 if (sc->ti_hwrev == TI_HWREV_TIGON)
1826 TI_SETBIT(sc, TI_PCI_STATE,
1827 TI_PCISTATE_32BIT_BUS);
1837 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1838 * self-test results.
1841 ti_chipinit(struct ti_softc *sc)
1844 uint32_t pci_writemax = 0;
1847 /* Initialize link to down state. */
1848 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1850 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM)
1851 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
1853 sc->ti_ifp->if_hwassist = 0;
1855 /* Set endianness before we access any non-PCI registers. */
1856 #if 0 && BYTE_ORDER == BIG_ENDIAN
1857 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1858 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1860 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1861 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1864 /* Check the ROM failed bit to see if self-tests passed. */
1865 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1866 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
1871 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1873 /* Figure out the hardware revision. */
1874 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1875 case TI_REV_TIGON_I:
1876 sc->ti_hwrev = TI_HWREV_TIGON;
1878 case TI_REV_TIGON_II:
1879 sc->ti_hwrev = TI_HWREV_TIGON_II;
1882 device_printf(sc->ti_dev, "unsupported chip revision\n");
1886 /* Do special setup for Tigon 2. */
1887 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1888 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1889 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1890 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1894 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1895 * can't do header splitting.
1897 #ifdef TI_JUMBO_HDRSPLIT
1898 if (sc->ti_hwrev != TI_HWREV_TIGON)
1899 sc->ti_hdrsplit = 1;
1901 device_printf(sc->ti_dev,
1902 "can't do header splitting on a Tigon I board\n");
1903 #endif /* TI_JUMBO_HDRSPLIT */
1905 /* Set up the PCI state register. */
1906 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1907 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1908 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1911 /* Clear the read/write max DMA parameters. */
1912 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1913 TI_PCISTATE_READ_MAXDMA));
1915 /* Get cache line size. */
1916 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1919 * If the system has set enabled the PCI memory write
1920 * and invalidate command in the command register, set
1921 * the write max parameter accordingly. This is necessary
1922 * to use MWI with the Tigon 2.
1924 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1925 switch (cacheline) {
1934 /* Disable PCI memory write and invalidate. */
1936 device_printf(sc->ti_dev, "cache line size %d"
1937 " not supported; disabling PCI MWI\n",
1939 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1940 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1945 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1947 /* This sets the min dma param all the way up (0xff). */
1948 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1950 if (sc->ti_hdrsplit)
1951 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1955 /* Configure DMA variables. */
1956 #if BYTE_ORDER == BIG_ENDIAN
1957 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1958 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1959 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1960 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1961 #else /* BYTE_ORDER */
1962 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1963 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1964 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1965 #endif /* BYTE_ORDER */
1968 * Only allow 1 DMA channel to be active at a time.
1969 * I don't think this is a good idea, but without it
1970 * the firmware racks up lots of nicDmaReadRingFull
1971 * errors. This is not compatible with hardware checksums.
1973 if (sc->ti_ifp->if_hwassist == 0)
1974 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1976 /* Recommended settings from Tigon manual. */
1977 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1978 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1980 if (ti_64bitslot_war(sc)) {
1981 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
1990 * Initialize the general information block and firmware, and
1991 * start the CPU(s) running.
1994 ti_gibinit(struct ti_softc *sc)
2004 rdphys = sc->ti_rdata_phys;
2006 /* Disable interrupts for now. */
2007 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2010 * Tell the chip where to find the general information block.
2011 * While this struct could go into >4GB memory, we allocate it in a
2012 * single slab with the other descriptors, and those don't seem to
2013 * support being located in a 64-bit region.
2015 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
2016 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
2018 /* Load the firmware into SRAM. */
2021 /* Set up the contents of the general info and ring control blocks. */
2023 /* Set up the event ring and producer pointer. */
2024 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
2026 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
2028 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
2029 rdphys + TI_RD_OFF(ti_ev_prodidx_r);
2030 sc->ti_ev_prodidx.ti_idx = 0;
2031 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2032 sc->ti_ev_saved_considx = 0;
2034 /* Set up the command ring and producer mailbox. */
2035 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
2037 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
2039 rcb->ti_max_len = 0;
2040 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2041 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2043 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2044 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2045 sc->ti_cmd_saved_prodidx = 0;
2048 * Assign the address of the stats refresh buffer.
2049 * We re-use the current stats buffer for this to
2052 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
2053 rdphys + TI_RD_OFF(ti_info.ti_stats);
2055 /* Set up the standard receive ring. */
2056 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
2057 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
2058 rcb->ti_max_len = TI_FRAMELEN;
2060 if (sc->ti_ifp->if_hwassist)
2061 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2062 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2063 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2065 /* Set up the jumbo receive ring. */
2066 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
2067 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
2069 #ifdef TI_PRIVATE_JUMBOS
2070 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
2073 rcb->ti_max_len = PAGE_SIZE;
2074 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2076 if (sc->ti_ifp->if_hwassist)
2077 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2078 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2079 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2082 * Set up the mini ring. Only activated on the
2083 * Tigon 2 but the slot in the config block is
2084 * still there on the Tigon 1.
2086 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
2087 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
2088 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2089 if (sc->ti_hwrev == TI_HWREV_TIGON)
2090 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2093 if (sc->ti_ifp->if_hwassist)
2094 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2095 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2096 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2099 * Set up the receive return ring.
2101 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
2102 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
2104 rcb->ti_max_len = TI_RETURN_RING_CNT;
2105 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
2106 rdphys + TI_RD_OFF(ti_return_prodidx_r);
2109 * Set up the tx ring. Note: for the Tigon 2, we have the option
2110 * of putting the transmit ring in the host's address space and
2111 * letting the chip DMA it instead of leaving the ring in the NIC's
2112 * memory and accessing it through the shared memory region. We
2113 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2114 * so we have to revert to the shared memory scheme if we detect
2117 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2118 bzero((char *)sc->ti_rdata->ti_tx_ring,
2119 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
2120 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
2121 if (sc->ti_hwrev == TI_HWREV_TIGON)
2124 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2125 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2126 if (sc->ti_ifp->if_hwassist)
2127 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2128 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2129 rcb->ti_max_len = TI_TX_RING_CNT;
2130 if (sc->ti_hwrev == TI_HWREV_TIGON)
2131 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
2133 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
2134 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
2135 rdphys + TI_RD_OFF(ti_tx_considx_r);
2137 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2138 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2140 /* Set up tuneables */
2142 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2143 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2144 (sc->ti_rx_coal_ticks / 10));
2147 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2148 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2149 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2150 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2151 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2152 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2154 /* Turn interrupts on. */
2155 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2156 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2159 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2165 ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2167 struct ti_softc *sc;
2170 if (error || nseg != 1)
2174 * All of the Tigon data structures need to live at <4GB. This
2175 * cast is fine since busdma was told about this constraint.
2177 sc->ti_rdata_phys = segs[0].ds_addr;
2182 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2183 * against our list and return its name if we find a match.
2186 ti_probe(device_t dev)
2188 const struct ti_type *t;
2192 while (t->ti_name != NULL) {
2193 if ((pci_get_vendor(dev) == t->ti_vid) &&
2194 (pci_get_device(dev) == t->ti_did)) {
2195 device_set_desc(dev, t->ti_name);
2196 return (BUS_PROBE_DEFAULT);
2205 ti_attach(device_t dev)
2208 struct ti_softc *sc;
2212 sc = device_get_softc(dev);
2213 sc->ti_unit = device_get_unit(dev);
2216 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2218 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2219 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2220 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2222 device_printf(dev, "can not if_alloc()\n");
2226 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM |
2227 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2228 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2231 * Map control/status registers.
2233 pci_enable_busmaster(dev);
2236 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2239 if (sc->ti_res == NULL) {
2240 device_printf(dev, "couldn't map memory\n");
2245 sc->ti_btag = rman_get_bustag(sc->ti_res);
2246 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2248 /* Allocate interrupt */
2251 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2252 RF_SHAREABLE | RF_ACTIVE);
2254 if (sc->ti_irq == NULL) {
2255 device_printf(dev, "couldn't map interrupt\n");
2260 if (ti_chipinit(sc)) {
2261 device_printf(dev, "chip initialization failed\n");
2266 /* Zero out the NIC's on-board SRAM. */
2267 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2269 /* Init again -- zeroing memory may have clobbered some registers. */
2270 if (ti_chipinit(sc)) {
2271 device_printf(dev, "chip initialization failed\n");
2277 * Get station address from the EEPROM. Note: the manual states
2278 * that the MAC address is at offset 0x8c, however the data is
2279 * stored as two longwords (since that's how it's loaded into
2280 * the NIC). This means the MAC address is actually preceded
2281 * by two zero bytes. We need to skip over those.
2283 if (ti_read_eeprom(sc, eaddr,
2284 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2285 device_printf(dev, "failed to read station address\n");
2290 /* Allocate the general information block and ring buffers. */
2291 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
2292 1, 0, /* algnmnt, boundary */
2293 BUS_SPACE_MAXADDR, /* lowaddr */
2294 BUS_SPACE_MAXADDR, /* highaddr */
2295 NULL, NULL, /* filter, filterarg */
2296 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2298 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2300 NULL, NULL, /* lockfunc, lockarg */
2301 &sc->ti_parent_dmat) != 0) {
2302 device_printf(dev, "Failed to allocate parent dmat\n");
2307 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2308 PAGE_SIZE, 0, /* algnmnt, boundary */
2309 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2310 BUS_SPACE_MAXADDR, /* highaddr */
2311 NULL, NULL, /* filter, filterarg */
2312 sizeof(struct ti_ring_data), /* maxsize */
2314 sizeof(struct ti_ring_data), /* maxsegsize */
2316 NULL, NULL, /* lockfunc, lockarg */
2317 &sc->ti_rdata_dmat) != 0) {
2318 device_printf(dev, "Failed to allocate rdata dmat\n");
2323 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2324 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
2325 &sc->ti_rdata_dmamap) != 0) {
2326 device_printf(dev, "Failed to allocate rdata memory\n");
2331 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2332 sc->ti_rdata, sizeof(struct ti_ring_data),
2333 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2334 device_printf(dev, "Failed to load rdata segments\n");
2339 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2341 /* Try to allocate memory for jumbo buffers. */
2342 if (ti_alloc_jumbo_mem(sc)) {
2343 device_printf(dev, "jumbo buffer allocation failed\n");
2348 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2349 1, 0, /* algnmnt, boundary */
2350 BUS_SPACE_MAXADDR, /* lowaddr */
2351 BUS_SPACE_MAXADDR, /* highaddr */
2352 NULL, NULL, /* filter, filterarg */
2353 MCLBYTES * TI_MAXTXSEGS,/* maxsize */
2354 TI_MAXTXSEGS, /* nsegments */
2355 MCLBYTES, /* maxsegsize */
2357 NULL, NULL, /* lockfunc, lockarg */
2358 &sc->ti_mbuftx_dmat) != 0) {
2359 device_printf(dev, "Failed to allocate rdata dmat\n");
2364 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2365 1, 0, /* algnmnt, boundary */
2366 BUS_SPACE_MAXADDR, /* lowaddr */
2367 BUS_SPACE_MAXADDR, /* highaddr */
2368 NULL, NULL, /* filter, filterarg */
2369 MCLBYTES, /* maxsize */
2371 MCLBYTES, /* maxsegsize */
2373 NULL, NULL, /* lockfunc, lockarg */
2374 &sc->ti_mbufrx_dmat) != 0) {
2375 device_printf(dev, "Failed to allocate rdata dmat\n");
2380 if (ti_alloc_dmamaps(sc)) {
2381 device_printf(dev, "dma map creation failed\n");
2387 * We really need a better way to tell a 1000baseTX card
2388 * from a 1000baseSX one, since in theory there could be
2389 * OEMed 1000baseTX cards from lame vendors who aren't
2390 * clever enough to change the PCI ID. For the moment
2391 * though, the AceNIC is the only copper card available.
2393 if (pci_get_vendor(dev) == ALT_VENDORID &&
2394 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2396 /* Ok, it's not the only copper card available. */
2397 if (pci_get_vendor(dev) == NG_VENDORID &&
2398 pci_get_device(dev) == NG_DEVICEID_GA620T)
2401 /* Set default tuneable values. */
2402 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2404 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2406 sc->ti_rx_coal_ticks = 170;
2407 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2408 sc->ti_rx_max_coal_bds = 64;
2410 sc->ti_tx_max_coal_bds = 128;
2412 sc->ti_tx_max_coal_bds = 32;
2413 sc->ti_tx_buf_ratio = 21;
2415 /* Set up ifnet structure */
2417 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2418 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2419 ifp->if_ioctl = ti_ioctl;
2420 ifp->if_start = ti_start;
2421 ifp->if_init = ti_init;
2422 ifp->if_baudrate = 1000000000;
2423 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
2425 /* Set up ifmedia support. */
2426 if (sc->ti_copper) {
2428 * Copper cards allow manual 10/100 mode selection,
2429 * but not manual 1000baseTX mode selection. Why?
2430 * Becuase currently there's no way to specify the
2431 * master/slave setting through the firmware interface,
2432 * so Alteon decided to just bag it and handle it
2433 * via autonegotiation.
2435 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2436 ifmedia_add(&sc->ifmedia,
2437 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2438 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2439 ifmedia_add(&sc->ifmedia,
2440 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2441 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2442 ifmedia_add(&sc->ifmedia,
2443 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2445 /* Fiber cards don't support 10/100 modes. */
2446 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2447 ifmedia_add(&sc->ifmedia,
2448 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2450 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2451 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2454 * We're assuming here that card initialization is a sequential
2455 * thing. If it isn't, multiple cards probing at the same time
2456 * could stomp on the list of softcs here.
2459 /* Register the device */
2460 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
2461 0600, "ti%d", sc->ti_unit);
2462 sc->dev->si_drv1 = sc;
2465 * Call MI attach routine.
2467 ether_ifattach(ifp, eaddr);
2469 /* Hook interrupt last to avoid having to lock softc */
2470 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2471 NULL, ti_intr, sc, &sc->ti_intrhand);
2474 device_printf(dev, "couldn't set up irq\n");
2486 * Shutdown hardware and free up resources. This can be called any
2487 * time after the mutex has been initialized. It is called in both
2488 * the error case in attach and the normal detach case so it needs
2489 * to be careful about only freeing resources that have actually been
2493 ti_detach(device_t dev)
2495 struct ti_softc *sc;
2498 sc = device_get_softc(dev);
2500 destroy_dev(sc->dev);
2501 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2503 if (device_is_attached(dev)) {
2504 ether_ifdetach(ifp);
2510 /* These should only be active if attach succeeded */
2511 callout_drain(&sc->ti_watchdog);
2512 bus_generic_detach(dev);
2513 ti_free_dmamaps(sc);
2514 ifmedia_removeall(&sc->ifmedia);
2516 #ifdef TI_PRIVATE_JUMBOS
2517 if (sc->ti_cdata.ti_jumbo_buf)
2518 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf,
2519 sc->ti_jumbo_dmamap);
2521 if (sc->ti_jumbo_dmat)
2522 bus_dma_tag_destroy(sc->ti_jumbo_dmat);
2523 if (sc->ti_mbuftx_dmat)
2524 bus_dma_tag_destroy(sc->ti_mbuftx_dmat);
2525 if (sc->ti_mbufrx_dmat)
2526 bus_dma_tag_destroy(sc->ti_mbufrx_dmat);
2528 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2529 sc->ti_rdata_dmamap);
2530 if (sc->ti_rdata_dmat)
2531 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2532 if (sc->ti_parent_dmat)
2533 bus_dma_tag_destroy(sc->ti_parent_dmat);
2534 if (sc->ti_intrhand)
2535 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2537 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2539 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2545 mtx_destroy(&sc->ti_mtx);
2550 #ifdef TI_JUMBO_HDRSPLIT
2552 * If hdr_len is 0, that means that header splitting wasn't done on
2553 * this packet for some reason. The two most likely reasons are that
2554 * the protocol isn't a supported protocol for splitting, or this
2555 * packet had a fragment offset that wasn't 0.
2557 * The header length, if it is non-zero, will always be the length of
2558 * the headers on the packet, but that length could be longer than the
2559 * first mbuf. So we take the minimum of the two as the actual
2562 static __inline void
2563 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2566 int lengths[4] = {0, 0, 0, 0};
2567 struct mbuf *m, *mp;
2570 top->m_len = min(hdr_len, top->m_len);
2571 pkt_len -= top->m_len;
2572 lengths[i++] = top->m_len;
2575 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2576 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2577 pkt_len -= m->m_len;
2578 lengths[i++] = m->m_len;
2584 printf("got split packet: ");
2586 printf("got non-split packet: ");
2588 printf("%d,%d,%d,%d = %d\n", lengths[0],
2589 lengths[1], lengths[2], lengths[3],
2590 lengths[0] + lengths[1] + lengths[2] +
2595 panic("header splitting didn't");
2602 if (mp->m_next != NULL)
2603 panic("ti_hdr_split: last mbuf in chain should be null");
2605 #endif /* TI_JUMBO_HDRSPLIT */
2608 * Frame reception handling. This is called if there's a frame
2609 * on the receive return list.
2611 * Note: we have to be able to handle three possibilities here:
2612 * 1) the frame is from the mini receive ring (can only happen)
2613 * on Tigon 2 boards)
2614 * 2) the frame is from the jumbo recieve ring
2615 * 3) the frame is from the standard receive ring
2619 ti_rxeof(struct ti_softc *sc)
2623 struct ti_cmd_desc cmd;
2629 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2630 struct ti_rx_desc *cur_rx;
2631 struct mbuf *m = NULL;
2633 uint16_t vlan_tag = 0;
2637 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2638 rxidx = cur_rx->ti_idx;
2639 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2641 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2643 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2646 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2648 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2649 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2650 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2651 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2652 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
2653 BUS_DMASYNC_POSTREAD);
2654 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
2655 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2657 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2660 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2662 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2665 #ifdef TI_PRIVATE_JUMBOS
2666 m->m_len = cur_rx->ti_len;
2667 #else /* TI_PRIVATE_JUMBOS */
2668 #ifdef TI_JUMBO_HDRSPLIT
2669 if (sc->ti_hdrsplit)
2670 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2671 cur_rx->ti_len, rxidx);
2673 #endif /* TI_JUMBO_HDRSPLIT */
2674 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2675 #endif /* TI_PRIVATE_JUMBOS */
2676 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2677 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2678 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2679 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2680 map = sc->ti_cdata.ti_rx_mini_maps[rxidx];
2681 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2682 BUS_DMASYNC_POSTREAD);
2683 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2684 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2686 ti_newbuf_mini(sc, sc->ti_mini, m);
2689 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2691 ti_newbuf_mini(sc, sc->ti_mini, m);
2694 m->m_len = cur_rx->ti_len;
2696 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2697 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2698 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2699 map = sc->ti_cdata.ti_rx_std_maps[rxidx];
2700 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2701 BUS_DMASYNC_POSTREAD);
2702 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2703 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2705 ti_newbuf_std(sc, sc->ti_std, m);
2708 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2710 ti_newbuf_std(sc, sc->ti_std, m);
2713 m->m_len = cur_rx->ti_len;
2716 m->m_pkthdr.len = cur_rx->ti_len;
2718 m->m_pkthdr.rcvif = ifp;
2720 if (ifp->if_hwassist) {
2721 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2723 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2724 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2725 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2729 * If we received a packet with a vlan tag,
2730 * tag it before passing the packet upward.
2733 m->m_pkthdr.ether_vtag = vlan_tag;
2734 m->m_flags |= M_VLANTAG;
2737 (*ifp->if_input)(ifp, m);
2741 /* Only necessary on the Tigon 1. */
2742 if (sc->ti_hwrev == TI_HWREV_TIGON)
2743 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2744 sc->ti_rx_saved_considx);
2746 TI_UPDATE_STDPROD(sc, sc->ti_std);
2747 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2748 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2752 ti_txeof(struct ti_softc *sc)
2754 struct ti_txdesc *txd;
2755 struct ti_tx_desc txdesc;
2756 struct ti_tx_desc *cur_tx = NULL;
2762 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2766 * Go through our tx ring and free mbufs for those
2767 * frames that have been sent.
2769 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2770 TI_INC(idx, TI_TX_RING_CNT)) {
2771 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2772 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2773 sizeof(txdesc), &txdesc);
2776 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2778 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2779 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2781 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2782 BUS_DMASYNC_POSTWRITE);
2783 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2788 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2789 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2790 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2792 sc->ti_tx_saved_considx = idx;
2794 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0;
2800 struct ti_softc *sc;
2808 /* Avoid this for now -- checking this register is expensive. */
2809 /* Make sure this is really our interrupt. */
2810 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2816 /* Ack interrupt and stop others from occuring. */
2817 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2819 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2820 /* Check RX return ring producer/consumer */
2823 /* Check TX ring producer/consumer */
2827 ti_handle_events(sc);
2829 /* Re-enable interrupts. */
2830 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2832 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2833 ifp->if_snd.ifq_head != NULL)
2834 ti_start_locked(ifp);
2840 ti_stats_update(struct ti_softc *sc)
2846 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2847 BUS_DMASYNC_POSTREAD);
2849 ifp->if_collisions +=
2850 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2851 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2852 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2853 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2856 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2857 BUS_DMASYNC_PREREAD);
2861 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2862 * pointers to descriptors.
2865 ti_encap(struct ti_softc *sc, struct mbuf **m_head)
2867 struct ti_txdesc *txd;
2868 struct ti_tx_desc *f;
2869 struct ti_tx_desc txdesc;
2871 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
2872 uint16_t csum_flags;
2873 int error, frag, i, nseg;
2875 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
2878 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2879 *m_head, txsegs, &nseg, 0);
2880 if (error == EFBIG) {
2881 m = m_defrag(*m_head, M_DONTWAIT);
2888 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat,
2889 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2895 } else if (error != 0)
2903 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
2904 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2910 if (m->m_pkthdr.csum_flags) {
2911 if (m->m_pkthdr.csum_flags & CSUM_IP)
2912 csum_flags |= TI_BDFLAG_IP_CKSUM;
2913 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2914 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2915 if (m->m_flags & M_LASTFRAG)
2916 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2917 else if (m->m_flags & M_FRAG)
2918 csum_flags |= TI_BDFLAG_IP_FRAG;
2921 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2922 BUS_DMASYNC_PREWRITE);
2923 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2924 BUS_DMASYNC_PREWRITE);
2926 frag = sc->ti_tx_saved_prodidx;
2927 for (i = 0; i < nseg; i++) {
2928 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2929 bzero(&txdesc, sizeof(txdesc));
2932 f = &sc->ti_rdata->ti_tx_ring[frag];
2933 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
2934 f->ti_len = txsegs[i].ds_len;
2935 f->ti_flags = csum_flags;
2936 if (m->m_flags & M_VLANTAG) {
2937 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2938 f->ti_vlan_tag = m->m_pkthdr.ether_vtag & 0xfff;
2943 if (sc->ti_hwrev == TI_HWREV_TIGON)
2944 ti_mem_write(sc, TI_TX_RING_BASE + frag *
2945 sizeof(txdesc), sizeof(txdesc), &txdesc);
2946 TI_INC(frag, TI_TX_RING_CNT);
2949 sc->ti_tx_saved_prodidx = frag;
2950 /* set TI_BDFLAG_END on the last descriptor */
2951 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
2952 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2953 txdesc.ti_flags |= TI_BDFLAG_END;
2954 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
2955 sizeof(txdesc), &txdesc);
2957 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
2959 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
2960 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
2962 sc->ti_txcnt += nseg;
2968 ti_start(struct ifnet *ifp)
2970 struct ti_softc *sc;
2974 ti_start_locked(ifp);
2979 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2980 * to the mbuf data regions directly in the transmit descriptors.
2983 ti_start_locked(struct ifnet *ifp)
2985 struct ti_softc *sc;
2986 struct mbuf *m_head = NULL;
2991 for (; ifp->if_snd.ifq_head != NULL &&
2992 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
2993 IF_DEQUEUE(&ifp->if_snd, m_head);
2999 * safety overkill. If this is a fragmented packet chain
3000 * with delayed TCP/UDP checksums, then only encapsulate
3001 * it if we have enough descriptors to handle the entire
3003 * (paranoia -- may not actually be needed)
3005 if (m_head->m_flags & M_FIRSTFRAG &&
3006 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3007 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
3008 m_head->m_pkthdr.csum_data + 16) {
3009 IF_PREPEND(&ifp->if_snd, m_head);
3010 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3016 * Pack the data into the transmit ring. If we
3017 * don't have room, set the OACTIVE flag and wait
3018 * for the NIC to drain the ring.
3020 if (ti_encap(sc, &m_head)) {
3023 IF_PREPEND(&ifp->if_snd, m_head);
3024 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3030 * If there's a BPF listener, bounce a copy of this frame
3033 ETHER_BPF_MTAP(ifp, m_head);
3038 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3041 * Set a timeout in case the chip goes out to lunch.
3050 struct ti_softc *sc;
3059 ti_init_locked(void *xsc)
3061 struct ti_softc *sc = xsc;
3063 /* Cancel pending I/O and flush buffers. */
3066 /* Init the gen info block, ring control blocks and firmware. */
3067 if (ti_gibinit(sc)) {
3068 device_printf(sc->ti_dev, "initialization failure\n");
3073 static void ti_init2(struct ti_softc *sc)
3075 struct ti_cmd_desc cmd;
3078 struct ifmedia *ifm;
3085 /* Specify MTU and interface index. */
3086 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
3087 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3088 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3089 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3091 /* Load our MAC address. */
3092 ea = IF_LLADDR(sc->ti_ifp);
3093 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3094 CSR_WRITE_4(sc, TI_GCR_PAR1,
3095 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3096 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3098 /* Enable or disable promiscuous mode as needed. */
3099 if (ifp->if_flags & IFF_PROMISC) {
3100 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3102 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3105 /* Program multicast filter. */
3109 * If this is a Tigon 1, we should tell the
3110 * firmware to use software packet filtering.
3112 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3113 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3117 ti_init_rx_ring_std(sc);
3119 /* Init jumbo RX ring. */
3120 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3121 ti_init_rx_ring_jumbo(sc);
3124 * If this is a Tigon 2, we can also configure the
3127 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
3128 ti_init_rx_ring_mini(sc);
3130 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3131 sc->ti_rx_saved_considx = 0;
3134 ti_init_tx_ring(sc);
3136 /* Tell firmware we're alive. */
3137 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3139 /* Enable host interrupts. */
3140 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3142 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3143 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3144 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3147 * Make sure to set media properly. We have to do this
3148 * here since we have to issue commands in order to set
3149 * the link negotiation and we can't issue commands until
3150 * the firmware is running.
3153 tmp = ifm->ifm_media;
3154 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3155 ti_ifmedia_upd(ifp);
3156 ifm->ifm_media = tmp;
3160 * Set media options.
3163 ti_ifmedia_upd(struct ifnet *ifp)
3165 struct ti_softc *sc;
3166 struct ifmedia *ifm;
3167 struct ti_cmd_desc cmd;
3173 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3178 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3181 * Transmit flow control doesn't work on the Tigon 1.
3183 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3186 * Transmit flow control can also cause problems on the
3187 * Tigon 2, apparantly with both the copper and fiber
3188 * boards. The symptom is that the interface will just
3189 * hang. This was reproduced with Alteon 180 switches.
3192 if (sc->ti_hwrev != TI_HWREV_TIGON)
3193 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3196 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3197 TI_GLNK_FULL_DUPLEX| flowctl |
3198 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3200 flowctl = TI_LNK_RX_FLOWCTL_Y;
3202 if (sc->ti_hwrev != TI_HWREV_TIGON)
3203 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3206 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3207 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3208 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3209 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3210 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3214 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3216 if (sc->ti_hwrev != TI_HWREV_TIGON)
3217 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3220 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3221 flowctl |TI_GLNK_ENB);
3222 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3223 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3224 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3226 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3227 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3233 flowctl = TI_LNK_RX_FLOWCTL_Y;
3235 if (sc->ti_hwrev != TI_HWREV_TIGON)
3236 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3239 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3240 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3241 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3242 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3243 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3245 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3247 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3248 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3250 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3252 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3253 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3261 * Report current media status.
3264 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3266 struct ti_softc *sc;
3271 ifmr->ifm_status = IFM_AVALID;
3272 ifmr->ifm_active = IFM_ETHER;
3274 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
3277 ifmr->ifm_status |= IFM_ACTIVE;
3279 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3280 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3282 ifmr->ifm_active |= IFM_1000_T;
3284 ifmr->ifm_active |= IFM_1000_SX;
3285 if (media & TI_GLNK_FULL_DUPLEX)
3286 ifmr->ifm_active |= IFM_FDX;
3288 ifmr->ifm_active |= IFM_HDX;
3289 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3290 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3291 if (sc->ti_copper) {
3292 if (media & TI_LNK_100MB)
3293 ifmr->ifm_active |= IFM_100_TX;
3294 if (media & TI_LNK_10MB)
3295 ifmr->ifm_active |= IFM_10_T;
3297 if (media & TI_LNK_100MB)
3298 ifmr->ifm_active |= IFM_100_FX;
3299 if (media & TI_LNK_10MB)
3300 ifmr->ifm_active |= IFM_10_FL;
3302 if (media & TI_LNK_FULL_DUPLEX)
3303 ifmr->ifm_active |= IFM_FDX;
3304 if (media & TI_LNK_HALF_DUPLEX)
3305 ifmr->ifm_active |= IFM_HDX;
3310 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3312 struct ti_softc *sc = ifp->if_softc;
3313 struct ifreq *ifr = (struct ifreq *) data;
3314 struct ti_cmd_desc cmd;
3315 int mask, error = 0;
3320 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3323 ifp->if_mtu = ifr->ifr_mtu;
3330 if (ifp->if_flags & IFF_UP) {
3332 * If only the state of the PROMISC flag changed,
3333 * then just use the 'set promisc mode' command
3334 * instead of reinitializing the entire NIC. Doing
3335 * a full re-init means reloading the firmware and
3336 * waiting for it to start up, which may take a
3339 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3340 ifp->if_flags & IFF_PROMISC &&
3341 !(sc->ti_if_flags & IFF_PROMISC)) {
3342 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3343 TI_CMD_CODE_PROMISC_ENB, 0);
3344 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3345 !(ifp->if_flags & IFF_PROMISC) &&
3346 sc->ti_if_flags & IFF_PROMISC) {
3347 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3348 TI_CMD_CODE_PROMISC_DIS, 0);
3352 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3356 sc->ti_if_flags = ifp->if_flags;
3362 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3368 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3372 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3373 if (mask & IFCAP_HWCSUM) {
3374 if (IFCAP_HWCSUM & ifp->if_capenable)
3375 ifp->if_capenable &= ~IFCAP_HWCSUM;
3377 ifp->if_capenable |= IFCAP_HWCSUM;
3378 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3384 error = ether_ioctl(ifp, command, data);
3392 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3394 struct ti_softc *sc;
3401 sc->ti_flags |= TI_FLAG_DEBUGING;
3408 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3410 struct ti_softc *sc;
3417 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3424 * This ioctl routine goes along with the Tigon character device.
3427 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3430 struct ti_softc *sc;
3442 struct ti_stats *outstats;
3444 outstats = (struct ti_stats *)addr;
3447 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3448 sizeof(struct ti_stats));
3452 case TIIOCGETPARAMS:
3454 struct ti_params *params;
3456 params = (struct ti_params *)addr;
3459 params->ti_stat_ticks = sc->ti_stat_ticks;
3460 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3461 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3462 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3463 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3464 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3465 params->param_mask = TI_PARAM_ALL;
3472 case TIIOCSETPARAMS:
3474 struct ti_params *params;
3476 params = (struct ti_params *)addr;
3479 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3480 sc->ti_stat_ticks = params->ti_stat_ticks;
3481 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3484 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3485 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3486 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3487 sc->ti_rx_coal_ticks);
3490 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3491 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3492 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3493 sc->ti_tx_coal_ticks);
3496 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3497 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3498 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3499 sc->ti_rx_max_coal_bds);
3502 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3503 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3504 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3505 sc->ti_tx_max_coal_bds);
3508 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3509 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3510 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3511 sc->ti_tx_buf_ratio);
3519 case TIIOCSETTRACE: {
3520 ti_trace_type trace_type;
3522 trace_type = *(ti_trace_type *)addr;
3525 * Set tracing to whatever the user asked for. Setting
3526 * this register to 0 should have the effect of disabling
3529 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3535 case TIIOCGETTRACE: {
3536 struct ti_trace_buf *trace_buf;
3537 uint32_t trace_start, cur_trace_ptr, trace_len;
3539 trace_buf = (struct ti_trace_buf *)addr;
3542 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3543 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3544 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3547 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3548 "trace_len = %d\n", trace_start,
3549 cur_trace_ptr, trace_len);
3550 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3551 trace_buf->buf_len);
3554 error = ti_copy_mem(sc, trace_start, min(trace_len,
3555 trace_buf->buf_len),
3556 (caddr_t)trace_buf->buf, 1, 1);
3559 trace_buf->fill_len = min(trace_len,
3560 trace_buf->buf_len);
3561 if (cur_trace_ptr < trace_start)
3562 trace_buf->cur_trace_ptr =
3563 trace_start - cur_trace_ptr;
3565 trace_buf->cur_trace_ptr =
3566 cur_trace_ptr - trace_start;
3568 trace_buf->fill_len = 0;
3575 * For debugging, five ioctls are needed:
3584 * From what I can tell, Alteon's Solaris Tigon driver
3585 * only has one character device, so you have to attach
3586 * to the Tigon board you're interested in. This seems
3587 * like a not-so-good way to do things, since unless you
3588 * subsequently specify the unit number of the device
3589 * you're interested in every ioctl, you'll only be
3590 * able to debug one board at a time.
3594 case ALT_READ_TG_MEM:
3595 case ALT_WRITE_TG_MEM:
3597 struct tg_mem *mem_param;
3598 uint32_t sram_end, scratch_end;
3600 mem_param = (struct tg_mem *)addr;
3602 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3603 sram_end = TI_END_SRAM_I;
3604 scratch_end = TI_END_SCRATCH_I;
3606 sram_end = TI_END_SRAM_II;
3607 scratch_end = TI_END_SCRATCH_II;
3611 * For now, we'll only handle accessing regular SRAM,
3615 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3616 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3618 * In this instance, we always copy to/from user
3619 * space, so the user space argument is set to 1.
3621 error = ti_copy_mem(sc, mem_param->tgAddr,
3623 mem_param->userAddr, 1,
3624 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3625 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3626 && (mem_param->tgAddr <= scratch_end)) {
3627 error = ti_copy_scratch(sc, mem_param->tgAddr,
3629 mem_param->userAddr, 1,
3630 (cmd == ALT_READ_TG_MEM) ?
3631 1 : 0, TI_PROCESSOR_A);
3632 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3633 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3634 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3635 if_printf(sc->ti_ifp,
3636 "invalid memory range for Tigon I\n");
3640 error = ti_copy_scratch(sc, mem_param->tgAddr -
3641 TI_SCRATCH_DEBUG_OFF,
3643 mem_param->userAddr, 1,
3644 (cmd == ALT_READ_TG_MEM) ?
3645 1 : 0, TI_PROCESSOR_B);
3647 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3648 "out of supported range\n",
3649 mem_param->tgAddr, mem_param->len);
3656 case ALT_READ_TG_REG:
3657 case ALT_WRITE_TG_REG:
3659 struct tg_reg *regs;
3662 regs = (struct tg_reg *)addr;
3665 * Make sure the address in question isn't out of range.
3667 if (regs->addr > TI_REG_MAX) {
3672 if (cmd == ALT_READ_TG_REG) {
3673 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3674 regs->addr, &tmpval, 1);
3675 regs->data = ntohl(tmpval);
3677 if ((regs->addr == TI_CPU_STATE)
3678 || (regs->addr == TI_CPU_CTL_B)) {
3679 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3680 regs->addr, tmpval);
3684 tmpval = htonl(regs->data);
3685 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3686 regs->addr, &tmpval, 1);
3700 ti_watchdog(void *arg)
3702 struct ti_softc *sc;
3707 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3708 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3712 * When we're debugging, the chip is often stopped for long periods
3713 * of time, and that would normally cause the watchdog timer to fire.
3714 * Since that impedes debugging, we don't want to do that.
3716 if (sc->ti_flags & TI_FLAG_DEBUGING)
3720 if_printf(ifp, "watchdog timeout -- resetting\n");
3728 * Stop the adapter and free any mbufs allocated to the
3732 ti_stop(struct ti_softc *sc)
3735 struct ti_cmd_desc cmd;
3741 /* Disable host interrupts. */
3742 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3744 * Tell firmware we're shutting down.
3746 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3748 /* Halt and reinitialize. */
3749 if (ti_chipinit(sc) != 0)
3751 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3752 if (ti_chipinit(sc) != 0)
3755 /* Free the RX lists. */
3756 ti_free_rx_ring_std(sc);
3758 /* Free jumbo RX list. */
3759 ti_free_rx_ring_jumbo(sc);
3761 /* Free mini RX list. */
3762 ti_free_rx_ring_mini(sc);
3764 /* Free TX buffers. */
3765 ti_free_tx_ring(sc);
3767 sc->ti_ev_prodidx.ti_idx = 0;
3768 sc->ti_return_prodidx.ti_idx = 0;
3769 sc->ti_tx_considx.ti_idx = 0;
3770 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3772 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3773 callout_stop(&sc->ti_watchdog);
3777 * Stop all chip I/O so that the kernel's probe routines don't
3778 * get confused by errant DMAs when rebooting.
3781 ti_shutdown(device_t dev)
3783 struct ti_softc *sc;
3785 sc = device_get_softc(dev);