2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
94 #include <sys/sf_buf.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
102 #include <net/if_vlan_var.h>
106 #include <netinet/in_systm.h>
107 #include <netinet/in.h>
108 #include <netinet/ip.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 #ifdef TI_SF_BUF_JUMBO
117 #include <vm/vm_page.h>
120 #include <dev/pci/pcireg.h>
121 #include <dev/pci/pcivar.h>
123 #include <sys/tiio.h>
124 #include <dev/ti/if_tireg.h>
125 #include <dev/ti/ti_fw.h>
126 #include <dev/ti/ti_fw2.h>
128 #include <sys/sysctl.h>
130 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
132 * We can only turn on header splitting if we're using extended receive
135 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO)
136 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO"
137 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */
145 * Various supported device vendors/types and their names.
148 static const struct ti_type const ti_devs[] = {
149 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
152 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
153 { TC_VENDORID, TC_DEVICEID_3C985,
154 "3Com 3c985-SX Gigabit Ethernet" },
155 { NG_VENDORID, NG_DEVICEID_GA620,
156 "Netgear GA620 1000baseSX Gigabit Ethernet" },
157 { NG_VENDORID, NG_DEVICEID_GA620T,
158 "Netgear GA620 1000baseT Gigabit Ethernet" },
159 { SGI_VENDORID, SGI_DEVICEID_TIGON,
160 "Silicon Graphics Gigabit Ethernet" },
161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
162 "Farallon PN9000SX Gigabit Ethernet" },
167 static d_open_t ti_open;
168 static d_close_t ti_close;
169 static d_ioctl_t ti_ioctl2;
171 static struct cdevsw ti_cdevsw = {
172 .d_version = D_VERSION,
176 .d_ioctl = ti_ioctl2,
180 static int ti_probe(device_t);
181 static int ti_attach(device_t);
182 static int ti_detach(device_t);
183 static void ti_txeof(struct ti_softc *);
184 static void ti_rxeof(struct ti_softc *);
186 static void ti_stats_update(struct ti_softc *);
187 static int ti_encap(struct ti_softc *, struct mbuf **);
189 static void ti_intr(void *);
190 static void ti_start(struct ifnet *);
191 static void ti_start_locked(struct ifnet *);
192 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
193 static void ti_init(void *);
194 static void ti_init_locked(void *);
195 static void ti_init2(struct ti_softc *);
196 static void ti_stop(struct ti_softc *);
197 static void ti_watchdog(void *);
198 static int ti_shutdown(device_t);
199 static int ti_ifmedia_upd(struct ifnet *);
200 static int ti_ifmedia_upd_locked(struct ti_softc *);
201 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
203 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
204 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
205 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
207 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
208 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
209 static void ti_setmulti(struct ti_softc *);
211 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
212 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
213 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
214 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
216 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
218 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
219 static void ti_loadfw(struct ti_softc *);
220 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
221 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
222 static void ti_handle_events(struct ti_softc *);
223 static int ti_alloc_dmamaps(struct ti_softc *);
224 static void ti_free_dmamaps(struct ti_softc *);
225 static int ti_alloc_jumbo_mem(struct ti_softc *);
226 static int ti_newbuf_std(struct ti_softc *, int);
227 static int ti_newbuf_mini(struct ti_softc *, int);
228 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
229 static int ti_init_rx_ring_std(struct ti_softc *);
230 static void ti_free_rx_ring_std(struct ti_softc *);
231 static int ti_init_rx_ring_jumbo(struct ti_softc *);
232 static void ti_free_rx_ring_jumbo(struct ti_softc *);
233 static int ti_init_rx_ring_mini(struct ti_softc *);
234 static void ti_free_rx_ring_mini(struct ti_softc *);
235 static void ti_free_tx_ring(struct ti_softc *);
236 static int ti_init_tx_ring(struct ti_softc *);
237 static void ti_discard_std(struct ti_softc *, int);
238 #ifndef TI_SF_BUF_JUMBO
239 static void ti_discard_jumbo(struct ti_softc *, int);
241 static void ti_discard_mini(struct ti_softc *, int);
243 static int ti_64bitslot_war(struct ti_softc *);
244 static int ti_chipinit(struct ti_softc *);
245 static int ti_gibinit(struct ti_softc *);
247 #ifdef TI_JUMBO_HDRSPLIT
248 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
250 #endif /* TI_JUMBO_HDRSPLIT */
252 static void ti_sysctl_node(struct ti_softc *);
254 static device_method_t ti_methods[] = {
255 /* Device interface */
256 DEVMETHOD(device_probe, ti_probe),
257 DEVMETHOD(device_attach, ti_attach),
258 DEVMETHOD(device_detach, ti_detach),
259 DEVMETHOD(device_shutdown, ti_shutdown),
263 static driver_t ti_driver = {
266 sizeof(struct ti_softc)
269 static devclass_t ti_devclass;
271 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
272 MODULE_DEPEND(ti, pci, 1, 1, 1);
273 MODULE_DEPEND(ti, ether, 1, 1, 1);
276 * Send an instruction or address to the EEPROM, check for ACK.
279 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
284 * Make sure we're in TX mode.
286 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
289 * Feed in each bit and stobe the clock.
291 for (i = 0x80; i; i >>= 1) {
293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
295 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
298 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
300 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
306 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
311 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
312 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
313 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
319 * Read a byte of data stored in the EEPROM at address 'addr.'
320 * We have to send two address bytes since the EEPROM can hold
321 * more than 256 bytes of data.
324 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
332 * Send write control code to EEPROM.
334 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
335 device_printf(sc->ti_dev,
336 "failed to send write command, status: %x\n",
337 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
342 * Send first byte of address of byte we want to read.
344 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
345 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
346 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
350 * Send second byte address of byte we want to read.
352 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
353 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
354 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
361 * Send read control code to EEPROM.
363 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
364 device_printf(sc->ti_dev,
365 "failed to send read command, status: %x\n",
366 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
371 * Start reading bits from EEPROM.
373 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
374 for (i = 0x80; i; i >>= 1) {
375 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
377 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
379 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
386 * No ACK generated for read, so just return byte.
395 * Read a sequence of bytes from the EEPROM.
398 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
403 for (i = 0; i < cnt; i++) {
404 err = ti_eeprom_getbyte(sc, off + i, &byte);
410 return (err ? 1 : 0);
414 * NIC memory read function.
415 * Can be used to copy data from NIC local memory.
418 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
420 int segptr, segsize, cnt;
431 segsize = TI_WINLEN - (segptr % TI_WINLEN);
432 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
433 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
434 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
444 * NIC memory write function.
445 * Can be used to copy data into NIC local memory.
448 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
450 int segptr, segsize, cnt;
461 segsize = TI_WINLEN - (segptr % TI_WINLEN);
462 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
463 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
464 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
473 * NIC memory read function.
474 * Can be used to clear a section of NIC local memory.
477 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
479 int segptr, segsize, cnt;
488 segsize = TI_WINLEN - (segptr % TI_WINLEN);
489 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
490 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
491 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
498 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
499 caddr_t buf, int useraddr, int readdata)
501 int segptr, segsize, cnt;
510 * At the moment, we don't handle non-aligned cases, we just bail.
511 * If this proves to be a problem, it will be fixed.
513 if (readdata == 0 && (tigon_addr & 0x3) != 0) {
514 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
515 "word-aligned\n", __func__, tigon_addr);
516 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
517 "yet supported\n", __func__);
521 segptr = tigon_addr & ~0x3;
522 segresid = tigon_addr - segptr;
525 * This is the non-aligned amount left over that we'll need to
530 /* Add in the left over amount at the front of the buffer */
535 * If resid + segresid is >= 4, add multiples of 4 to the count and
536 * decrease the residual by that much.
539 resid -= resid & ~0x3;
546 * Save the old window base value.
548 origwin = CSR_READ_4(sc, TI_WINBASE);
551 bus_size_t ti_offset;
556 segsize = TI_WINLEN - (segptr % TI_WINLEN);
557 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
559 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
562 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
563 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
566 * Yeah, this is a little on the kludgy
567 * side, but at least this code is only
568 * used for debugging.
570 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2,
571 segsize, TI_SWAP_NTOH);
575 copyout(&sc->ti_membuf2[segresid], ptr,
579 copyout(sc->ti_membuf2, ptr, segsize);
584 ti_bcopy_swap(sc->ti_membuf,
585 sc->ti_membuf2, segsize,
588 bcopy(&sc->ti_membuf2[segresid], ptr,
593 ti_bcopy_swap(sc->ti_membuf, ptr,
594 segsize, TI_SWAP_NTOH);
600 copyin(ptr, sc->ti_membuf2, segsize);
602 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf,
603 segsize, TI_SWAP_HTON);
605 ti_bcopy_swap(ptr, sc->ti_membuf, segsize,
608 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
609 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
617 * Handle leftover, non-word-aligned bytes.
620 uint32_t tmpval, tmpval2;
621 bus_size_t ti_offset;
624 * Set the segment pointer.
626 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
628 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
631 * First, grab whatever is in our source/destination.
632 * We'll obviously need this for reads, but also for
633 * writes, since we'll be doing read/modify/write.
635 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
636 ti_offset, &tmpval, 1);
639 * Next, translate this from little-endian to big-endian
640 * (at least on i386 boxes).
642 tmpval2 = ntohl(tmpval);
646 * If we're reading, just copy the leftover number
647 * of bytes from the host byte order buffer to
652 copyout(&tmpval2, ptr, resid);
655 bcopy(&tmpval2, ptr, resid);
658 * If we're writing, first copy the bytes to be
659 * written into the network byte order buffer,
660 * leaving the rest of the buffer with whatever was
661 * originally in there. Then, swap the bytes
662 * around into host order and write them out.
664 * XXX KDM the read side of this has been verified
665 * to work, but the write side of it has not been
666 * verified. So user beware.
670 copyin(ptr, &tmpval2, resid);
673 bcopy(ptr, &tmpval2, resid);
675 tmpval = htonl(tmpval2);
677 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
678 ti_offset, &tmpval, 1);
682 CSR_WRITE_4(sc, TI_WINBASE, origwin);
688 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
689 caddr_t buf, int useraddr, int readdata, int cpu)
693 uint32_t tmpval, tmpval2;
699 * At the moment, we don't handle non-aligned cases, we just bail.
700 * If this proves to be a problem, it will be fixed.
702 if (tigon_addr & 0x3) {
703 device_printf(sc->ti_dev, "%s: tigon address %#x "
704 "isn't word-aligned\n", __func__, tigon_addr);
709 device_printf(sc->ti_dev, "%s: transfer length %d "
710 "isn't word-aligned\n", __func__, len);
719 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
722 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
724 tmpval = ntohl(tmpval2);
727 * Note: I've used this debugging interface
728 * extensively with Alteon's 12.3.15 firmware,
729 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
731 * When you compile the firmware without
732 * optimization, which is necessary sometimes in
733 * order to properly step through it, you sometimes
734 * read out a bogus value of 0xc0017c instead of
735 * whatever was supposed to be in that scratchpad
736 * location. That value is on the stack somewhere,
737 * but I've never been able to figure out what was
738 * causing the problem.
740 * The address seems to pop up in random places,
741 * often not in the same place on two subsequent
744 * In any case, the underlying data doesn't seem
745 * to be affected, just the value read out.
750 if (tmpval2 == 0xc0017c)
751 device_printf(sc->ti_dev, "found 0xc0017c at "
752 "%#x (tmpval2)\n", segptr);
754 if (tmpval == 0xc0017c)
755 device_printf(sc->ti_dev, "found 0xc0017c at "
756 "%#x (tmpval)\n", segptr);
759 copyout(&tmpval, ptr, 4);
761 bcopy(&tmpval, ptr, 4);
764 copyin(ptr, &tmpval2, 4);
766 bcopy(ptr, &tmpval2, 4);
768 tmpval = htonl(tmpval2);
770 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
782 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
784 const uint8_t *tmpsrc;
789 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len);
798 if (swap_type == TI_SWAP_NTOH)
799 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc);
801 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc);
811 * Load firmware image into the NIC. Check that the firmware revision
812 * is acceptable and see if we want the firmware for the Tigon 1 or
816 ti_loadfw(struct ti_softc *sc)
821 switch (sc->ti_hwrev) {
823 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
824 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
825 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
826 device_printf(sc->ti_dev, "firmware revision mismatch; "
827 "want %d.%d.%d, got %d.%d.%d\n",
828 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
829 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
830 tigonFwReleaseMinor, tigonFwReleaseFix);
833 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
834 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
835 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
837 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
838 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
839 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
841 case TI_HWREV_TIGON_II:
842 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
843 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
844 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
845 device_printf(sc->ti_dev, "firmware revision mismatch; "
846 "want %d.%d.%d, got %d.%d.%d\n",
847 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
848 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
849 tigon2FwReleaseMinor, tigon2FwReleaseFix);
852 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
854 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
856 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
858 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
859 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
860 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
863 device_printf(sc->ti_dev,
864 "can't load firmware: unknown hardware rev\n");
870 * Send the NIC a command via the command ring.
873 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
877 index = sc->ti_cmd_saved_prodidx;
878 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
879 TI_INC(index, TI_CMD_RING_CNT);
880 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
881 sc->ti_cmd_saved_prodidx = index;
885 * Send the NIC an extended command. The 'len' parameter specifies the
886 * number of command slots to include after the initial command.
889 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
894 index = sc->ti_cmd_saved_prodidx;
895 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
896 TI_INC(index, TI_CMD_RING_CNT);
897 for (i = 0; i < len; i++) {
898 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
899 *(uint32_t *)(&arg[i * 4]));
900 TI_INC(index, TI_CMD_RING_CNT);
902 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
903 sc->ti_cmd_saved_prodidx = index;
907 * Handle events that have triggered interrupts.
910 ti_handle_events(struct ti_softc *sc)
912 struct ti_event_desc *e;
914 if (sc->ti_rdata->ti_event_ring == NULL)
917 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
918 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
919 switch (TI_EVENT_EVENT(e)) {
920 case TI_EV_LINKSTAT_CHANGED:
921 sc->ti_linkstat = TI_EVENT_CODE(e);
922 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
923 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
924 sc->ti_ifp->if_baudrate = IF_Mbps(100);
926 device_printf(sc->ti_dev,
928 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
930 sc->ti_ifp->if_baudrate = IF_Gbps(1UL);
932 device_printf(sc->ti_dev,
933 "gigabit link up\n");
934 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
935 if_link_state_change(sc->ti_ifp,
937 sc->ti_ifp->if_baudrate = 0;
939 device_printf(sc->ti_dev,
944 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
945 device_printf(sc->ti_dev, "invalid command\n");
946 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
947 device_printf(sc->ti_dev, "unknown command\n");
948 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
949 device_printf(sc->ti_dev, "bad config data\n");
951 case TI_EV_FIRMWARE_UP:
954 case TI_EV_STATS_UPDATED:
957 case TI_EV_RESET_JUMBO_RING:
958 case TI_EV_MCAST_UPDATED:
962 device_printf(sc->ti_dev, "unknown event: %d\n",
966 /* Advance the consumer index. */
967 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
968 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
973 ti_alloc_dmamaps(struct ti_softc *sc)
977 for (i = 0; i < TI_TX_RING_CNT; i++) {
978 sc->ti_cdata.ti_txdesc[i].tx_m = NULL;
979 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL;
980 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0,
981 &sc->ti_cdata.ti_txdesc[i].tx_dmamap)) {
982 device_printf(sc->ti_dev,
983 "cannot create DMA map for TX\n");
987 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
988 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
989 &sc->ti_cdata.ti_rx_std_maps[i])) {
990 device_printf(sc->ti_dev,
991 "cannot create DMA map for RX\n");
995 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
996 &sc->ti_cdata.ti_rx_std_sparemap)) {
997 device_printf(sc->ti_dev,
998 "cannot create spare DMA map for RX\n");
1002 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1003 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0,
1004 &sc->ti_cdata.ti_rx_jumbo_maps[i])) {
1005 device_printf(sc->ti_dev,
1006 "cannot create DMA map for jumbo RX\n");
1010 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0,
1011 &sc->ti_cdata.ti_rx_jumbo_sparemap)) {
1012 device_printf(sc->ti_dev,
1013 "cannot create spare DMA map for jumbo RX\n");
1017 /* Mini ring is not available on Tigon 1. */
1018 if (sc->ti_hwrev == TI_HWREV_TIGON)
1021 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1022 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
1023 &sc->ti_cdata.ti_rx_mini_maps[i])) {
1024 device_printf(sc->ti_dev,
1025 "cannot create DMA map for mini RX\n");
1029 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
1030 &sc->ti_cdata.ti_rx_mini_sparemap)) {
1031 device_printf(sc->ti_dev,
1032 "cannot create DMA map for mini RX\n");
1040 ti_free_dmamaps(struct ti_softc *sc)
1044 if (sc->ti_mbuftx_dmat) {
1045 for (i = 0; i < TI_TX_RING_CNT; i++) {
1046 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1047 bus_dmamap_destroy(sc->ti_mbuftx_dmat,
1048 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1049 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL;
1054 if (sc->ti_mbufrx_dmat) {
1055 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1056 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1057 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1058 sc->ti_cdata.ti_rx_std_maps[i]);
1059 sc->ti_cdata.ti_rx_std_maps[i] = NULL;
1062 if (sc->ti_cdata.ti_rx_std_sparemap) {
1063 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1064 sc->ti_cdata.ti_rx_std_sparemap);
1065 sc->ti_cdata.ti_rx_std_sparemap = NULL;
1069 if (sc->ti_jumbo_dmat) {
1070 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1071 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1072 bus_dmamap_destroy(sc->ti_jumbo_dmat,
1073 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1074 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL;
1077 if (sc->ti_cdata.ti_rx_jumbo_sparemap) {
1078 bus_dmamap_destroy(sc->ti_jumbo_dmat,
1079 sc->ti_cdata.ti_rx_jumbo_sparemap);
1080 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL;
1084 if (sc->ti_mbufrx_dmat) {
1085 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1086 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1087 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1088 sc->ti_cdata.ti_rx_mini_maps[i]);
1089 sc->ti_cdata.ti_rx_mini_maps[i] = NULL;
1092 if (sc->ti_cdata.ti_rx_mini_sparemap) {
1093 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1094 sc->ti_cdata.ti_rx_mini_sparemap);
1095 sc->ti_cdata.ti_rx_mini_sparemap = NULL;
1100 #ifndef TI_SF_BUF_JUMBO
1103 ti_alloc_jumbo_mem(struct ti_softc *sc)
1106 if (bus_dma_tag_create(sc->ti_parent_dmat, 1, 0, BUS_SPACE_MAXADDR,
1107 BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, MJUM9BYTES, 0, NULL,
1108 NULL, &sc->ti_jumbo_dmat) != 0) {
1109 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1118 ti_alloc_jumbo_mem(struct ti_softc *sc)
1122 * The VM system will take care of providing aligned pages. Alignment
1123 * is set to 1 here so that busdma resources won't be wasted.
1125 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1126 1, 0, /* algnmnt, boundary */
1127 BUS_SPACE_MAXADDR, /* lowaddr */
1128 BUS_SPACE_MAXADDR, /* highaddr */
1129 NULL, NULL, /* filter, filterarg */
1130 PAGE_SIZE * 4 /*XXX*/, /* maxsize */
1132 PAGE_SIZE, /* maxsegsize */
1134 NULL, NULL, /* lockfunc, lockarg */
1135 &sc->ti_jumbo_dmat) != 0) {
1136 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1143 #endif /* TI_SF_BUF_JUMBO */
1146 * Intialize a standard receive ring descriptor.
1149 ti_newbuf_std(struct ti_softc *sc, int i)
1152 bus_dma_segment_t segs[1];
1154 struct ti_rx_desc *r;
1157 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1160 m->m_len = m->m_pkthdr.len = MCLBYTES;
1161 m_adj(m, ETHER_ALIGN);
1163 error = bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat,
1164 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0);
1169 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1171 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1172 bus_dmamap_sync(sc->ti_mbufrx_dmat,
1173 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD);
1174 bus_dmamap_unload(sc->ti_mbufrx_dmat,
1175 sc->ti_cdata.ti_rx_std_maps[i]);
1178 map = sc->ti_cdata.ti_rx_std_maps[i];
1179 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap;
1180 sc->ti_cdata.ti_rx_std_sparemap = map;
1181 sc->ti_cdata.ti_rx_std_chain[i] = m;
1183 r = &sc->ti_rdata->ti_rx_std_ring[i];
1184 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1185 r->ti_len = segs[0].ds_len;
1186 r->ti_type = TI_BDTYPE_RECV_BD;
1189 r->ti_tcp_udp_cksum = 0;
1190 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1191 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1194 bus_dmamap_sync(sc->ti_mbufrx_dmat, sc->ti_cdata.ti_rx_std_maps[i],
1195 BUS_DMASYNC_PREREAD);
1200 * Intialize a mini receive ring descriptor. This only applies to
1204 ti_newbuf_mini(struct ti_softc *sc, int i)
1207 bus_dma_segment_t segs[1];
1209 struct ti_rx_desc *r;
1212 MGETHDR(m, M_DONTWAIT, MT_DATA);
1215 m->m_len = m->m_pkthdr.len = MHLEN;
1216 m_adj(m, ETHER_ALIGN);
1218 error = bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat,
1219 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0);
1224 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1226 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1227 bus_dmamap_sync(sc->ti_mbufrx_dmat,
1228 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD);
1229 bus_dmamap_unload(sc->ti_mbufrx_dmat,
1230 sc->ti_cdata.ti_rx_mini_maps[i]);
1233 map = sc->ti_cdata.ti_rx_mini_maps[i];
1234 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap;
1235 sc->ti_cdata.ti_rx_mini_sparemap = map;
1236 sc->ti_cdata.ti_rx_mini_chain[i] = m;
1238 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1239 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1240 r->ti_len = segs[0].ds_len;
1241 r->ti_type = TI_BDTYPE_RECV_BD;
1242 r->ti_flags = TI_BDFLAG_MINI_RING;
1244 r->ti_tcp_udp_cksum = 0;
1245 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1246 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1249 bus_dmamap_sync(sc->ti_mbufrx_dmat, sc->ti_cdata.ti_rx_mini_maps[i],
1250 BUS_DMASYNC_PREREAD);
1254 #ifndef TI_SF_BUF_JUMBO
1257 * Initialize a jumbo receive ring descriptor. This allocates
1258 * a jumbo buffer from the pool managed internally by the driver.
1261 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy)
1264 bus_dma_segment_t segs[1];
1266 struct ti_rx_desc *r;
1271 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1274 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1275 m_adj(m, ETHER_ALIGN);
1277 error = bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat,
1278 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1283 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1285 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1286 bus_dmamap_sync(sc->ti_jumbo_dmat,
1287 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD);
1288 bus_dmamap_unload(sc->ti_jumbo_dmat,
1289 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1292 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1293 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap;
1294 sc->ti_cdata.ti_rx_jumbo_sparemap = map;
1295 sc->ti_cdata.ti_rx_jumbo_chain[i] = m;
1297 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1298 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1299 r->ti_len = segs[0].ds_len;
1300 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1301 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1303 r->ti_tcp_udp_cksum = 0;
1304 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1305 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1308 bus_dmamap_sync(sc->ti_jumbo_dmat, sc->ti_cdata.ti_rx_jumbo_maps[i],
1309 BUS_DMASYNC_PREREAD);
1315 #if (PAGE_SIZE == 4096)
1321 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1322 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1323 #define NFS_HDR_LEN (UDP_HDR_LEN)
1324 static int HDR_LEN = TCP_HDR_LEN;
1327 * Initialize a jumbo receive ring descriptor. This allocates
1328 * a jumbo buffer from the pool managed internally by the driver.
1331 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1334 struct mbuf *cur, *m_new = NULL;
1335 struct mbuf *m[3] = {NULL, NULL, NULL};
1336 struct ti_rx_desc_ext *r;
1339 /* 1 extra buf to make nobufs easy*/
1340 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1342 bus_dma_segment_t segs[4];
1345 if (m_old != NULL) {
1347 cur = m_old->m_next;
1348 for (i = 0; i <= NPAYLOAD; i++){
1353 /* Allocate the mbufs. */
1354 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1355 if (m_new == NULL) {
1356 device_printf(sc->ti_dev, "mbuf allocation failed "
1357 "-- packet dropped!\n");
1360 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1361 if (m[NPAYLOAD] == NULL) {
1362 device_printf(sc->ti_dev, "cluster mbuf allocation "
1363 "failed -- packet dropped!\n");
1366 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1367 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1368 device_printf(sc->ti_dev, "mbuf allocation failed "
1369 "-- packet dropped!\n");
1372 m[NPAYLOAD]->m_len = MCLBYTES;
1374 for (i = 0; i < NPAYLOAD; i++){
1375 MGET(m[i], M_DONTWAIT, MT_DATA);
1377 device_printf(sc->ti_dev, "mbuf allocation "
1378 "failed -- packet dropped!\n");
1381 frame = vm_page_alloc(NULL, color++,
1382 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1384 if (frame == NULL) {
1385 device_printf(sc->ti_dev, "buffer allocation "
1386 "failed -- packet dropped!\n");
1387 printf(" index %d page %d\n", idx, i);
1390 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1391 if (sf[i] == NULL) {
1392 vm_page_lock_queues();
1393 vm_page_unwire(frame, 0);
1394 vm_page_free(frame);
1395 vm_page_unlock_queues();
1396 device_printf(sc->ti_dev, "buffer allocation "
1397 "failed -- packet dropped!\n");
1398 printf(" index %d page %d\n", idx, i);
1402 for (i = 0; i < NPAYLOAD; i++){
1403 /* Attach the buffer to the mbuf. */
1404 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1405 m[i]->m_len = PAGE_SIZE;
1406 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1407 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1409 m[i]->m_next = m[i+1];
1411 /* link the buffers to the header */
1412 m_new->m_next = m[0];
1413 m_new->m_data += ETHER_ALIGN;
1414 if (sc->ti_hdrsplit)
1415 m_new->m_len = MHLEN - ETHER_ALIGN;
1417 m_new->m_len = HDR_LEN;
1418 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1421 /* Set up the descriptor. */
1422 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1423 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1424 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1425 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs,
1428 if ((nsegs < 1) || (nsegs > 4))
1430 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1431 r->ti_len0 = m_new->m_len;
1433 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1434 r->ti_len1 = PAGE_SIZE;
1436 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1437 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1439 if (PAGE_SIZE == 4096) {
1440 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1441 r->ti_len3 = MCLBYTES;
1445 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1447 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1449 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1450 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1454 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1461 * This can only be called before the mbufs are strung together.
1462 * If the mbufs are strung together, m_freem() will free the chain,
1463 * so that the later mbufs will be freed multiple times.
1468 for (i = 0; i < 3; i++) {
1472 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1479 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1480 * that's 1MB or memory, which is a lot. For now, we fill only the first
1481 * 256 ring entries and hope that our CPU is fast enough to keep up with
1485 ti_init_rx_ring_std(struct ti_softc *sc)
1488 struct ti_cmd_desc cmd;
1490 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1491 if (ti_newbuf_std(sc, i) != 0)
1495 sc->ti_std = TI_STD_RX_RING_CNT - 1;
1496 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1);
1502 ti_free_rx_ring_std(struct ti_softc *sc)
1507 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1508 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1509 map = sc->ti_cdata.ti_rx_std_maps[i];
1510 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1511 BUS_DMASYNC_POSTREAD);
1512 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1513 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1514 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1516 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1517 sizeof(struct ti_rx_desc));
1522 ti_init_rx_ring_jumbo(struct ti_softc *sc)
1524 struct ti_cmd_desc cmd;
1527 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1528 if (ti_newbuf_jumbo(sc, i, NULL) != 0)
1532 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1;
1533 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1);
1539 ti_free_rx_ring_jumbo(struct ti_softc *sc)
1544 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1545 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1546 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1547 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
1548 BUS_DMASYNC_POSTREAD);
1549 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
1550 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1551 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1553 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1554 sizeof(struct ti_rx_desc));
1559 ti_init_rx_ring_mini(struct ti_softc *sc)
1563 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1564 if (ti_newbuf_mini(sc, i) != 0)
1568 sc->ti_mini = TI_MINI_RX_RING_CNT - 1;
1569 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1);
1575 ti_free_rx_ring_mini(struct ti_softc *sc)
1580 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1581 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1582 map = sc->ti_cdata.ti_rx_mini_maps[i];
1583 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1584 BUS_DMASYNC_POSTREAD);
1585 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1586 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1587 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1589 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1590 sizeof(struct ti_rx_desc));
1595 ti_free_tx_ring(struct ti_softc *sc)
1597 struct ti_txdesc *txd;
1600 if (sc->ti_rdata->ti_tx_ring == NULL)
1603 for (i = 0; i < TI_TX_RING_CNT; i++) {
1604 txd = &sc->ti_cdata.ti_txdesc[i];
1605 if (txd->tx_m != NULL) {
1606 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
1607 BUS_DMASYNC_POSTWRITE);
1608 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
1612 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1613 sizeof(struct ti_tx_desc));
1618 ti_init_tx_ring(struct ti_softc *sc)
1620 struct ti_txdesc *txd;
1623 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1624 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1625 for (i = 0; i < TI_TX_RING_CNT; i++) {
1626 txd = &sc->ti_cdata.ti_txdesc[i];
1627 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1630 sc->ti_tx_saved_considx = 0;
1631 sc->ti_tx_saved_prodidx = 0;
1632 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1637 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1638 * but we have to support the old way too so that Tigon 1 cards will
1642 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1644 struct ti_cmd_desc cmd;
1646 uint32_t ext[2] = {0, 0};
1648 m = (uint16_t *)&addr->octet[0];
1650 switch (sc->ti_hwrev) {
1651 case TI_HWREV_TIGON:
1652 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1653 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1654 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1656 case TI_HWREV_TIGON_II:
1657 ext[0] = htons(m[0]);
1658 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1659 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1662 device_printf(sc->ti_dev, "unknown hwrev\n");
1668 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1670 struct ti_cmd_desc cmd;
1672 uint32_t ext[2] = {0, 0};
1674 m = (uint16_t *)&addr->octet[0];
1676 switch (sc->ti_hwrev) {
1677 case TI_HWREV_TIGON:
1678 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1679 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1680 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1682 case TI_HWREV_TIGON_II:
1683 ext[0] = htons(m[0]);
1684 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1685 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1688 device_printf(sc->ti_dev, "unknown hwrev\n");
1694 * Configure the Tigon's multicast address filter.
1696 * The actual multicast table management is a bit of a pain, thanks to
1697 * slight brain damage on the part of both Alteon and us. With our
1698 * multicast code, we are only alerted when the multicast address table
1699 * changes and at that point we only have the current list of addresses:
1700 * we only know the current state, not the previous state, so we don't
1701 * actually know what addresses were removed or added. The firmware has
1702 * state, but we can't get our grubby mits on it, and there is no 'delete
1703 * all multicast addresses' command. Hence, we have to maintain our own
1704 * state so we know what addresses have been programmed into the NIC at
1708 ti_setmulti(struct ti_softc *sc)
1711 struct ifmultiaddr *ifma;
1712 struct ti_cmd_desc cmd;
1713 struct ti_mc_entry *mc;
1720 if (ifp->if_flags & IFF_ALLMULTI) {
1721 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1724 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1727 /* Disable interrupts. */
1728 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1729 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1731 /* First, zot all the existing filters. */
1732 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1733 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1734 ti_del_mcast(sc, &mc->mc_addr);
1735 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1739 /* Now program new ones. */
1740 if_maddr_rlock(ifp);
1741 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1742 if (ifma->ifma_addr->sa_family != AF_LINK)
1744 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1746 device_printf(sc->ti_dev,
1747 "no memory for mcast filter entry\n");
1750 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1751 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1752 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1753 ti_add_mcast(sc, &mc->mc_addr);
1755 if_maddr_runlock(ifp);
1757 /* Re-enable interrupts. */
1758 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1762 * Check to see if the BIOS has configured us for a 64 bit slot when
1763 * we aren't actually in one. If we detect this condition, we can work
1764 * around it on the Tigon 2 by setting a bit in the PCI state register,
1765 * but for the Tigon 1 we must give up and abort the interface attach.
1768 ti_64bitslot_war(struct ti_softc *sc)
1771 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1772 CSR_WRITE_4(sc, 0x600, 0);
1773 CSR_WRITE_4(sc, 0x604, 0);
1774 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1775 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1776 if (sc->ti_hwrev == TI_HWREV_TIGON)
1779 TI_SETBIT(sc, TI_PCI_STATE,
1780 TI_PCISTATE_32BIT_BUS);
1790 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1791 * self-test results.
1794 ti_chipinit(struct ti_softc *sc)
1797 uint32_t pci_writemax = 0;
1800 /* Initialize link to down state. */
1801 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1803 /* Set endianness before we access any non-PCI registers. */
1804 #if 0 && BYTE_ORDER == BIG_ENDIAN
1805 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1806 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1808 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1809 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1812 /* Check the ROM failed bit to see if self-tests passed. */
1813 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1814 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
1819 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1821 /* Figure out the hardware revision. */
1822 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1823 case TI_REV_TIGON_I:
1824 sc->ti_hwrev = TI_HWREV_TIGON;
1826 case TI_REV_TIGON_II:
1827 sc->ti_hwrev = TI_HWREV_TIGON_II;
1830 device_printf(sc->ti_dev, "unsupported chip revision\n");
1834 /* Do special setup for Tigon 2. */
1835 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1836 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1837 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1838 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1842 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1843 * can't do header splitting.
1845 #ifdef TI_JUMBO_HDRSPLIT
1846 if (sc->ti_hwrev != TI_HWREV_TIGON)
1847 sc->ti_hdrsplit = 1;
1849 device_printf(sc->ti_dev,
1850 "can't do header splitting on a Tigon I board\n");
1851 #endif /* TI_JUMBO_HDRSPLIT */
1853 /* Set up the PCI state register. */
1854 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1855 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1856 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1859 /* Clear the read/write max DMA parameters. */
1860 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1861 TI_PCISTATE_READ_MAXDMA));
1863 /* Get cache line size. */
1864 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1867 * If the system has set enabled the PCI memory write
1868 * and invalidate command in the command register, set
1869 * the write max parameter accordingly. This is necessary
1870 * to use MWI with the Tigon 2.
1872 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1873 switch (cacheline) {
1882 /* Disable PCI memory write and invalidate. */
1884 device_printf(sc->ti_dev, "cache line size %d"
1885 " not supported; disabling PCI MWI\n",
1887 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1888 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1893 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1895 /* This sets the min dma param all the way up (0xff). */
1896 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1898 if (sc->ti_hdrsplit)
1899 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1903 /* Configure DMA variables. */
1904 #if BYTE_ORDER == BIG_ENDIAN
1905 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1906 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1907 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1908 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1909 #else /* BYTE_ORDER */
1910 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1911 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1912 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1913 #endif /* BYTE_ORDER */
1916 * Only allow 1 DMA channel to be active at a time.
1917 * I don't think this is a good idea, but without it
1918 * the firmware racks up lots of nicDmaReadRingFull
1919 * errors. This is not compatible with hardware checksums.
1921 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0)
1922 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1924 /* Recommended settings from Tigon manual. */
1925 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1926 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1928 if (ti_64bitslot_war(sc)) {
1929 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
1938 * Initialize the general information block and firmware, and
1939 * start the CPU(s) running.
1942 ti_gibinit(struct ti_softc *sc)
1952 rdphys = sc->ti_rdata_phys;
1954 /* Disable interrupts for now. */
1955 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1958 * Tell the chip where to find the general information block.
1959 * While this struct could go into >4GB memory, we allocate it in a
1960 * single slab with the other descriptors, and those don't seem to
1961 * support being located in a 64-bit region.
1963 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1964 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
1966 /* Load the firmware into SRAM. */
1969 /* Set up the contents of the general info and ring control blocks. */
1971 /* Set up the event ring and producer pointer. */
1972 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1974 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
1976 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1977 rdphys + TI_RD_OFF(ti_ev_prodidx_r);
1978 sc->ti_ev_prodidx.ti_idx = 0;
1979 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1980 sc->ti_ev_saved_considx = 0;
1982 /* Set up the command ring and producer mailbox. */
1983 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1985 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1987 rcb->ti_max_len = 0;
1988 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1989 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1991 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1992 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1993 sc->ti_cmd_saved_prodidx = 0;
1996 * Assign the address of the stats refresh buffer.
1997 * We re-use the current stats buffer for this to
2000 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
2001 rdphys + TI_RD_OFF(ti_info.ti_stats);
2003 /* Set up the standard receive ring. */
2004 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
2005 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
2006 rcb->ti_max_len = TI_FRAMELEN;
2008 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2009 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2010 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2011 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2012 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2014 /* Set up the jumbo receive ring. */
2015 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
2016 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
2018 #ifndef TI_SF_BUF_JUMBO
2019 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN;
2022 rcb->ti_max_len = PAGE_SIZE;
2023 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2025 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2026 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2027 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2028 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2029 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2032 * Set up the mini ring. Only activated on the
2033 * Tigon 2 but the slot in the config block is
2034 * still there on the Tigon 1.
2036 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
2037 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
2038 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2039 if (sc->ti_hwrev == TI_HWREV_TIGON)
2040 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2043 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2044 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2045 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2046 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2047 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2050 * Set up the receive return ring.
2052 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
2053 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
2055 rcb->ti_max_len = TI_RETURN_RING_CNT;
2056 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
2057 rdphys + TI_RD_OFF(ti_return_prodidx_r);
2060 * Set up the tx ring. Note: for the Tigon 2, we have the option
2061 * of putting the transmit ring in the host's address space and
2062 * letting the chip DMA it instead of leaving the ring in the NIC's
2063 * memory and accessing it through the shared memory region. We
2064 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2065 * so we have to revert to the shared memory scheme if we detect
2068 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2069 bzero((char *)sc->ti_rdata->ti_tx_ring,
2070 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
2071 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
2072 if (sc->ti_hwrev == TI_HWREV_TIGON)
2075 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2076 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2077 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2078 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM)
2079 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2080 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2081 rcb->ti_max_len = TI_TX_RING_CNT;
2082 if (sc->ti_hwrev == TI_HWREV_TIGON)
2083 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
2085 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
2086 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
2087 rdphys + TI_RD_OFF(ti_tx_considx_r);
2089 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2090 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2092 /* Set up tunables */
2094 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2095 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2096 (sc->ti_rx_coal_ticks / 10));
2099 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2100 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2101 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2102 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2103 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2104 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2106 /* Turn interrupts on. */
2107 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2108 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2111 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2117 ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2119 struct ti_softc *sc;
2122 if (error || nseg != 1)
2126 * All of the Tigon data structures need to live at <4GB. This
2127 * cast is fine since busdma was told about this constraint.
2129 sc->ti_rdata_phys = segs[0].ds_addr;
2134 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2135 * against our list and return its name if we find a match.
2138 ti_probe(device_t dev)
2140 const struct ti_type *t;
2144 while (t->ti_name != NULL) {
2145 if ((pci_get_vendor(dev) == t->ti_vid) &&
2146 (pci_get_device(dev) == t->ti_did)) {
2147 device_set_desc(dev, t->ti_name);
2148 return (BUS_PROBE_DEFAULT);
2157 ti_attach(device_t dev)
2160 struct ti_softc *sc;
2164 sc = device_get_softc(dev);
2167 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2169 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2170 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2171 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2173 device_printf(dev, "can not if_alloc()\n");
2177 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
2178 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
2179 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2182 * Map control/status registers.
2184 pci_enable_busmaster(dev);
2187 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2190 if (sc->ti_res == NULL) {
2191 device_printf(dev, "couldn't map memory\n");
2196 sc->ti_btag = rman_get_bustag(sc->ti_res);
2197 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2199 /* Allocate interrupt */
2202 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2203 RF_SHAREABLE | RF_ACTIVE);
2205 if (sc->ti_irq == NULL) {
2206 device_printf(dev, "couldn't map interrupt\n");
2211 if (ti_chipinit(sc)) {
2212 device_printf(dev, "chip initialization failed\n");
2217 /* Zero out the NIC's on-board SRAM. */
2218 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2220 /* Init again -- zeroing memory may have clobbered some registers. */
2221 if (ti_chipinit(sc)) {
2222 device_printf(dev, "chip initialization failed\n");
2228 * Get station address from the EEPROM. Note: the manual states
2229 * that the MAC address is at offset 0x8c, however the data is
2230 * stored as two longwords (since that's how it's loaded into
2231 * the NIC). This means the MAC address is actually preceded
2232 * by two zero bytes. We need to skip over those.
2234 if (ti_read_eeprom(sc, eaddr,
2235 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2236 device_printf(dev, "failed to read station address\n");
2241 /* Allocate working area for memory dump. */
2242 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT);
2243 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF,
2245 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) {
2246 device_printf(dev, "cannot allocate memory buffer\n");
2251 /* Allocate the general information block and ring buffers. */
2252 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
2253 1, 0, /* algnmnt, boundary */
2254 BUS_SPACE_MAXADDR, /* lowaddr */
2255 BUS_SPACE_MAXADDR, /* highaddr */
2256 NULL, NULL, /* filter, filterarg */
2257 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2259 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2261 NULL, NULL, /* lockfunc, lockarg */
2262 &sc->ti_parent_dmat) != 0) {
2263 device_printf(dev, "Failed to allocate parent dmat\n");
2268 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2269 PAGE_SIZE, 0, /* algnmnt, boundary */
2270 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2271 BUS_SPACE_MAXADDR, /* highaddr */
2272 NULL, NULL, /* filter, filterarg */
2273 sizeof(struct ti_ring_data), /* maxsize */
2275 sizeof(struct ti_ring_data), /* maxsegsize */
2277 NULL, NULL, /* lockfunc, lockarg */
2278 &sc->ti_rdata_dmat) != 0) {
2279 device_printf(dev, "Failed to allocate rdata dmat\n");
2284 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2285 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
2286 &sc->ti_rdata_dmamap) != 0) {
2287 device_printf(dev, "Failed to allocate rdata memory\n");
2292 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2293 sc->ti_rdata, sizeof(struct ti_ring_data),
2294 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2295 device_printf(dev, "Failed to load rdata segments\n");
2300 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2302 /* Try to allocate memory for jumbo buffers. */
2303 if (ti_alloc_jumbo_mem(sc)) {
2304 device_printf(dev, "jumbo buffer allocation failed\n");
2309 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2310 1, 0, /* algnmnt, boundary */
2311 BUS_SPACE_MAXADDR, /* lowaddr */
2312 BUS_SPACE_MAXADDR, /* highaddr */
2313 NULL, NULL, /* filter, filterarg */
2314 MCLBYTES * TI_MAXTXSEGS,/* maxsize */
2315 TI_MAXTXSEGS, /* nsegments */
2316 MCLBYTES, /* maxsegsize */
2318 NULL, NULL, /* lockfunc, lockarg */
2319 &sc->ti_mbuftx_dmat) != 0) {
2320 device_printf(dev, "Failed to allocate rdata dmat\n");
2325 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2326 1, 0, /* algnmnt, boundary */
2327 BUS_SPACE_MAXADDR, /* lowaddr */
2328 BUS_SPACE_MAXADDR, /* highaddr */
2329 NULL, NULL, /* filter, filterarg */
2330 MCLBYTES, /* maxsize */
2332 MCLBYTES, /* maxsegsize */
2334 NULL, NULL, /* lockfunc, lockarg */
2335 &sc->ti_mbufrx_dmat) != 0) {
2336 device_printf(dev, "Failed to allocate rdata dmat\n");
2341 if (ti_alloc_dmamaps(sc)) {
2347 * We really need a better way to tell a 1000baseTX card
2348 * from a 1000baseSX one, since in theory there could be
2349 * OEMed 1000baseTX cards from lame vendors who aren't
2350 * clever enough to change the PCI ID. For the moment
2351 * though, the AceNIC is the only copper card available.
2353 if (pci_get_vendor(dev) == ALT_VENDORID &&
2354 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2356 /* Ok, it's not the only copper card available. */
2357 if (pci_get_vendor(dev) == NG_VENDORID &&
2358 pci_get_device(dev) == NG_DEVICEID_GA620T)
2361 /* Set default tunable values. */
2364 /* Set up ifnet structure */
2366 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2367 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2368 ifp->if_ioctl = ti_ioctl;
2369 ifp->if_start = ti_start;
2370 ifp->if_init = ti_init;
2371 ifp->if_baudrate = IF_Gbps(1UL);
2372 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1;
2373 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2374 IFQ_SET_READY(&ifp->if_snd);
2376 /* Set up ifmedia support. */
2377 if (sc->ti_copper) {
2379 * Copper cards allow manual 10/100 mode selection,
2380 * but not manual 1000baseTX mode selection. Why?
2381 * Becuase currently there's no way to specify the
2382 * master/slave setting through the firmware interface,
2383 * so Alteon decided to just bag it and handle it
2384 * via autonegotiation.
2386 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2387 ifmedia_add(&sc->ifmedia,
2388 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2389 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2390 ifmedia_add(&sc->ifmedia,
2391 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2392 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2393 ifmedia_add(&sc->ifmedia,
2394 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2396 /* Fiber cards don't support 10/100 modes. */
2397 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2398 ifmedia_add(&sc->ifmedia,
2399 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2401 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2402 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2405 * We're assuming here that card initialization is a sequential
2406 * thing. If it isn't, multiple cards probing at the same time
2407 * could stomp on the list of softcs here.
2410 /* Register the device */
2411 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT,
2412 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev));
2413 sc->dev->si_drv1 = sc;
2416 * Call MI attach routine.
2418 ether_ifattach(ifp, eaddr);
2420 /* VLAN capability setup. */
2421 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM |
2422 IFCAP_VLAN_HWTAGGING;
2423 ifp->if_capenable = ifp->if_capabilities;
2424 /* Tell the upper layer we support VLAN over-sized frames. */
2425 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2427 /* Driver supports link state tracking. */
2428 ifp->if_capabilities |= IFCAP_LINKSTATE;
2429 ifp->if_capenable |= IFCAP_LINKSTATE;
2431 /* Hook interrupt last to avoid having to lock softc */
2432 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2433 NULL, ti_intr, sc, &sc->ti_intrhand);
2436 device_printf(dev, "couldn't set up irq\n");
2448 * Shutdown hardware and free up resources. This can be called any
2449 * time after the mutex has been initialized. It is called in both
2450 * the error case in attach and the normal detach case so it needs
2451 * to be careful about only freeing resources that have actually been
2455 ti_detach(device_t dev)
2457 struct ti_softc *sc;
2460 sc = device_get_softc(dev);
2462 destroy_dev(sc->dev);
2463 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2465 if (device_is_attached(dev)) {
2466 ether_ifdetach(ifp);
2472 /* These should only be active if attach succeeded */
2473 callout_drain(&sc->ti_watchdog);
2474 bus_generic_detach(dev);
2475 ti_free_dmamaps(sc);
2476 ifmedia_removeall(&sc->ifmedia);
2478 if (sc->ti_jumbo_dmat)
2479 bus_dma_tag_destroy(sc->ti_jumbo_dmat);
2480 if (sc->ti_mbuftx_dmat)
2481 bus_dma_tag_destroy(sc->ti_mbuftx_dmat);
2482 if (sc->ti_mbufrx_dmat)
2483 bus_dma_tag_destroy(sc->ti_mbufrx_dmat);
2484 if (sc->ti_rdata && sc->ti_rdata_dmamap)
2485 bus_dmamap_unload(sc->ti_rdata_dmat, sc->ti_rdata_dmamap);
2487 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2488 sc->ti_rdata_dmamap);
2489 if (sc->ti_rdata_dmat)
2490 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2491 if (sc->ti_parent_dmat)
2492 bus_dma_tag_destroy(sc->ti_parent_dmat);
2493 if (sc->ti_intrhand)
2494 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2496 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2498 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2504 free(sc->ti_membuf, M_DEVBUF);
2506 free(sc->ti_membuf2, M_DEVBUF);
2508 mtx_destroy(&sc->ti_mtx);
2513 #ifdef TI_JUMBO_HDRSPLIT
2515 * If hdr_len is 0, that means that header splitting wasn't done on
2516 * this packet for some reason. The two most likely reasons are that
2517 * the protocol isn't a supported protocol for splitting, or this
2518 * packet had a fragment offset that wasn't 0.
2520 * The header length, if it is non-zero, will always be the length of
2521 * the headers on the packet, but that length could be longer than the
2522 * first mbuf. So we take the minimum of the two as the actual
2525 static __inline void
2526 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2529 int lengths[4] = {0, 0, 0, 0};
2530 struct mbuf *m, *mp;
2533 top->m_len = min(hdr_len, top->m_len);
2534 pkt_len -= top->m_len;
2535 lengths[i++] = top->m_len;
2538 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2539 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2540 pkt_len -= m->m_len;
2541 lengths[i++] = m->m_len;
2547 printf("got split packet: ");
2549 printf("got non-split packet: ");
2551 printf("%d,%d,%d,%d = %d\n", lengths[0],
2552 lengths[1], lengths[2], lengths[3],
2553 lengths[0] + lengths[1] + lengths[2] +
2558 panic("header splitting didn't");
2565 if (mp->m_next != NULL)
2566 panic("ti_hdr_split: last mbuf in chain should be null");
2568 #endif /* TI_JUMBO_HDRSPLIT */
2571 ti_discard_std(struct ti_softc *sc, int i)
2574 struct ti_rx_desc *r;
2576 r = &sc->ti_rdata->ti_rx_std_ring[i];
2577 r->ti_len = MCLBYTES - ETHER_ALIGN;
2578 r->ti_type = TI_BDTYPE_RECV_BD;
2581 r->ti_tcp_udp_cksum = 0;
2582 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2583 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2588 ti_discard_mini(struct ti_softc *sc, int i)
2591 struct ti_rx_desc *r;
2593 r = &sc->ti_rdata->ti_rx_mini_ring[i];
2594 r->ti_len = MHLEN - ETHER_ALIGN;
2595 r->ti_type = TI_BDTYPE_RECV_BD;
2596 r->ti_flags = TI_BDFLAG_MINI_RING;
2598 r->ti_tcp_udp_cksum = 0;
2599 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2600 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2604 #ifndef TI_SF_BUF_JUMBO
2606 ti_discard_jumbo(struct ti_softc *sc, int i)
2609 struct ti_rx_desc *r;
2611 r = &sc->ti_rdata->ti_rx_mini_ring[i];
2612 r->ti_len = MJUM9BYTES - ETHER_ALIGN;
2613 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
2614 r->ti_flags = TI_BDFLAG_JUMBO_RING;
2616 r->ti_tcp_udp_cksum = 0;
2617 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2618 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2624 * Frame reception handling. This is called if there's a frame
2625 * on the receive return list.
2627 * Note: we have to be able to handle three possibilities here:
2628 * 1) the frame is from the mini receive ring (can only happen)
2629 * on Tigon 2 boards)
2630 * 2) the frame is from the jumbo recieve ring
2631 * 3) the frame is from the standard receive ring
2635 ti_rxeof(struct ti_softc *sc)
2638 #ifdef TI_SF_BUF_JUMBO
2641 struct ti_cmd_desc cmd;
2642 int jumbocnt, minicnt, stdcnt, ti_len;
2648 jumbocnt = minicnt = stdcnt = 0;
2649 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2650 struct ti_rx_desc *cur_rx;
2652 struct mbuf *m = NULL;
2653 uint16_t vlan_tag = 0;
2657 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2658 rxidx = cur_rx->ti_idx;
2659 ti_len = cur_rx->ti_len;
2660 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2662 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2664 vlan_tag = cur_rx->ti_vlan_tag;
2667 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2669 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2670 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2671 #ifndef TI_SF_BUF_JUMBO
2672 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2674 ti_discard_jumbo(sc, rxidx);
2677 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) {
2679 ti_discard_jumbo(sc, rxidx);
2683 #else /* !TI_SF_BUF_JUMBO */
2684 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2685 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2686 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
2687 BUS_DMASYNC_POSTREAD);
2688 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
2689 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2691 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2694 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2696 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2699 #ifdef TI_JUMBO_HDRSPLIT
2700 if (sc->ti_hdrsplit)
2701 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2704 #endif /* TI_JUMBO_HDRSPLIT */
2705 m_adj(m, ti_len - m->m_pkthdr.len);
2706 #endif /* TI_SF_BUF_JUMBO */
2707 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2709 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2710 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2711 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2713 ti_discard_mini(sc, rxidx);
2716 if (ti_newbuf_mini(sc, rxidx) != 0) {
2718 ti_discard_mini(sc, rxidx);
2724 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2725 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2726 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2728 ti_discard_std(sc, rxidx);
2731 if (ti_newbuf_std(sc, rxidx) != 0) {
2733 ti_discard_std(sc, rxidx);
2739 m->m_pkthdr.len = ti_len;
2741 m->m_pkthdr.rcvif = ifp;
2743 if (ifp->if_capenable & IFCAP_RXCSUM) {
2744 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) {
2745 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2746 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2747 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2749 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) {
2750 m->m_pkthdr.csum_data =
2751 cur_rx->ti_tcp_udp_cksum;
2752 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2757 * If we received a packet with a vlan tag,
2758 * tag it before passing the packet upward.
2761 m->m_pkthdr.ether_vtag = vlan_tag;
2762 m->m_flags |= M_VLANTAG;
2765 (*ifp->if_input)(ifp, m);
2769 /* Only necessary on the Tigon 1. */
2770 if (sc->ti_hwrev == TI_HWREV_TIGON)
2771 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2772 sc->ti_rx_saved_considx);
2775 TI_UPDATE_STDPROD(sc, sc->ti_std);
2777 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2779 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2783 ti_txeof(struct ti_softc *sc)
2785 struct ti_txdesc *txd;
2786 struct ti_tx_desc txdesc;
2787 struct ti_tx_desc *cur_tx = NULL;
2793 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2797 * Go through our tx ring and free mbufs for those
2798 * frames that have been sent.
2800 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2801 TI_INC(idx, TI_TX_RING_CNT)) {
2802 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2803 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2804 sizeof(txdesc), &txdesc);
2807 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2809 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2810 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2812 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2813 BUS_DMASYNC_POSTWRITE);
2814 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2819 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2820 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2821 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2823 sc->ti_tx_saved_considx = idx;
2825 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0;
2831 struct ti_softc *sc;
2838 /* Make sure this is really our interrupt. */
2839 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2844 /* Ack interrupt and stop others from occuring. */
2845 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2847 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2848 /* Check RX return ring producer/consumer */
2851 /* Check TX ring producer/consumer */
2855 ti_handle_events(sc);
2857 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2858 /* Re-enable interrupts. */
2859 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2860 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2861 ti_start_locked(ifp);
2868 ti_stats_update(struct ti_softc *sc)
2874 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2875 BUS_DMASYNC_POSTREAD);
2877 ifp->if_collisions +=
2878 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2879 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2880 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2881 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2884 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2885 BUS_DMASYNC_PREREAD);
2889 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2890 * pointers to descriptors.
2893 ti_encap(struct ti_softc *sc, struct mbuf **m_head)
2895 struct ti_txdesc *txd;
2896 struct ti_tx_desc *f;
2897 struct ti_tx_desc txdesc;
2899 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
2900 uint16_t csum_flags;
2901 int error, frag, i, nseg;
2903 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
2906 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2907 *m_head, txsegs, &nseg, 0);
2908 if (error == EFBIG) {
2909 m = m_defrag(*m_head, M_DONTWAIT);
2916 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat,
2917 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2923 } else if (error != 0)
2931 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
2932 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2938 if (m->m_pkthdr.csum_flags) {
2939 if (m->m_pkthdr.csum_flags & CSUM_IP)
2940 csum_flags |= TI_BDFLAG_IP_CKSUM;
2941 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2942 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2943 if (m->m_flags & M_LASTFRAG)
2944 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2945 else if (m->m_flags & M_FRAG)
2946 csum_flags |= TI_BDFLAG_IP_FRAG;
2949 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2950 BUS_DMASYNC_PREWRITE);
2951 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2952 BUS_DMASYNC_PREWRITE);
2954 frag = sc->ti_tx_saved_prodidx;
2955 for (i = 0; i < nseg; i++) {
2956 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2957 bzero(&txdesc, sizeof(txdesc));
2960 f = &sc->ti_rdata->ti_tx_ring[frag];
2961 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
2962 f->ti_len = txsegs[i].ds_len;
2963 f->ti_flags = csum_flags;
2964 if (m->m_flags & M_VLANTAG) {
2965 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2966 f->ti_vlan_tag = m->m_pkthdr.ether_vtag;
2971 if (sc->ti_hwrev == TI_HWREV_TIGON)
2972 ti_mem_write(sc, TI_TX_RING_BASE + frag *
2973 sizeof(txdesc), sizeof(txdesc), &txdesc);
2974 TI_INC(frag, TI_TX_RING_CNT);
2977 sc->ti_tx_saved_prodidx = frag;
2978 /* set TI_BDFLAG_END on the last descriptor */
2979 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
2980 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2981 txdesc.ti_flags |= TI_BDFLAG_END;
2982 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
2983 sizeof(txdesc), &txdesc);
2985 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
2987 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
2988 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
2990 sc->ti_txcnt += nseg;
2996 ti_start(struct ifnet *ifp)
2998 struct ti_softc *sc;
3002 ti_start_locked(ifp);
3007 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3008 * to the mbuf data regions directly in the transmit descriptors.
3011 ti_start_locked(struct ifnet *ifp)
3013 struct ti_softc *sc;
3014 struct mbuf *m_head = NULL;
3019 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
3020 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3021 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3027 * safety overkill. If this is a fragmented packet chain
3028 * with delayed TCP/UDP checksums, then only encapsulate
3029 * it if we have enough descriptors to handle the entire
3031 * (paranoia -- may not actually be needed)
3033 if (m_head->m_flags & M_FIRSTFRAG &&
3034 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3035 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
3036 m_head->m_pkthdr.csum_data + 16) {
3037 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3038 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3044 * Pack the data into the transmit ring. If we
3045 * don't have room, set the OACTIVE flag and wait
3046 * for the NIC to drain the ring.
3048 if (ti_encap(sc, &m_head)) {
3051 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3052 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3058 * If there's a BPF listener, bounce a copy of this frame
3061 ETHER_BPF_MTAP(ifp, m_head);
3066 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3069 * Set a timeout in case the chip goes out to lunch.
3078 struct ti_softc *sc;
3087 ti_init_locked(void *xsc)
3089 struct ti_softc *sc = xsc;
3091 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING)
3094 /* Cancel pending I/O and flush buffers. */
3097 /* Init the gen info block, ring control blocks and firmware. */
3098 if (ti_gibinit(sc)) {
3099 device_printf(sc->ti_dev, "initialization failure\n");
3104 static void ti_init2(struct ti_softc *sc)
3106 struct ti_cmd_desc cmd;
3109 struct ifmedia *ifm;
3116 /* Specify MTU and interface index. */
3117 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev));
3118 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3119 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3120 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3122 /* Load our MAC address. */
3123 ea = IF_LLADDR(sc->ti_ifp);
3124 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3125 CSR_WRITE_4(sc, TI_GCR_PAR1,
3126 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3127 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3129 /* Enable or disable promiscuous mode as needed. */
3130 if (ifp->if_flags & IFF_PROMISC) {
3131 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3133 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3136 /* Program multicast filter. */
3140 * If this is a Tigon 1, we should tell the
3141 * firmware to use software packet filtering.
3143 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3144 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3148 if (ti_init_rx_ring_std(sc) != 0) {
3150 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n");
3154 /* Init jumbo RX ring. */
3155 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3156 if (ti_init_rx_ring_jumbo(sc) != 0) {
3158 device_printf(sc->ti_dev,
3159 "no memory for jumbo Rx buffers.\n");
3165 * If this is a Tigon 2, we can also configure the
3168 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
3169 if (ti_init_rx_ring_mini(sc) != 0) {
3171 device_printf(sc->ti_dev,
3172 "no memory for mini Rx buffers.\n");
3177 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3178 sc->ti_rx_saved_considx = 0;
3181 ti_init_tx_ring(sc);
3183 /* Tell firmware we're alive. */
3184 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3186 /* Enable host interrupts. */
3187 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3189 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3190 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3191 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3194 * Make sure to set media properly. We have to do this
3195 * here since we have to issue commands in order to set
3196 * the link negotiation and we can't issue commands until
3197 * the firmware is running.
3200 tmp = ifm->ifm_media;
3201 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3202 ti_ifmedia_upd_locked(sc);
3203 ifm->ifm_media = tmp;
3207 * Set media options.
3210 ti_ifmedia_upd(struct ifnet *ifp)
3212 struct ti_softc *sc;
3217 error = ti_ifmedia_upd(ifp);
3224 ti_ifmedia_upd_locked(struct ti_softc *sc)
3226 struct ifmedia *ifm;
3227 struct ti_cmd_desc cmd;
3232 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3237 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3240 * Transmit flow control doesn't work on the Tigon 1.
3242 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3245 * Transmit flow control can also cause problems on the
3246 * Tigon 2, apparantly with both the copper and fiber
3247 * boards. The symptom is that the interface will just
3248 * hang. This was reproduced with Alteon 180 switches.
3251 if (sc->ti_hwrev != TI_HWREV_TIGON)
3252 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3255 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3256 TI_GLNK_FULL_DUPLEX| flowctl |
3257 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3259 flowctl = TI_LNK_RX_FLOWCTL_Y;
3261 if (sc->ti_hwrev != TI_HWREV_TIGON)
3262 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3265 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3266 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3267 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3268 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3269 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3273 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3275 if (sc->ti_hwrev != TI_HWREV_TIGON)
3276 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3279 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3280 flowctl |TI_GLNK_ENB);
3281 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3282 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3283 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3285 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3286 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3292 flowctl = TI_LNK_RX_FLOWCTL_Y;
3294 if (sc->ti_hwrev != TI_HWREV_TIGON)
3295 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3298 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3299 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3300 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3301 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3302 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3304 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3306 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3307 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3309 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3311 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3312 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3320 * Report current media status.
3323 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3325 struct ti_softc *sc;
3332 ifmr->ifm_status = IFM_AVALID;
3333 ifmr->ifm_active = IFM_ETHER;
3335 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
3340 ifmr->ifm_status |= IFM_ACTIVE;
3342 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3343 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3345 ifmr->ifm_active |= IFM_1000_T;
3347 ifmr->ifm_active |= IFM_1000_SX;
3348 if (media & TI_GLNK_FULL_DUPLEX)
3349 ifmr->ifm_active |= IFM_FDX;
3351 ifmr->ifm_active |= IFM_HDX;
3352 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3353 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3354 if (sc->ti_copper) {
3355 if (media & TI_LNK_100MB)
3356 ifmr->ifm_active |= IFM_100_TX;
3357 if (media & TI_LNK_10MB)
3358 ifmr->ifm_active |= IFM_10_T;
3360 if (media & TI_LNK_100MB)
3361 ifmr->ifm_active |= IFM_100_FX;
3362 if (media & TI_LNK_10MB)
3363 ifmr->ifm_active |= IFM_10_FL;
3365 if (media & TI_LNK_FULL_DUPLEX)
3366 ifmr->ifm_active |= IFM_FDX;
3367 if (media & TI_LNK_HALF_DUPLEX)
3368 ifmr->ifm_active |= IFM_HDX;
3374 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3376 struct ti_softc *sc = ifp->if_softc;
3377 struct ifreq *ifr = (struct ifreq *) data;
3378 struct ti_cmd_desc cmd;
3379 int mask, error = 0;
3384 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU)
3387 ifp->if_mtu = ifr->ifr_mtu;
3388 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3389 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3397 if (ifp->if_flags & IFF_UP) {
3399 * If only the state of the PROMISC flag changed,
3400 * then just use the 'set promisc mode' command
3401 * instead of reinitializing the entire NIC. Doing
3402 * a full re-init means reloading the firmware and
3403 * waiting for it to start up, which may take a
3406 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3407 ifp->if_flags & IFF_PROMISC &&
3408 !(sc->ti_if_flags & IFF_PROMISC)) {
3409 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3410 TI_CMD_CODE_PROMISC_ENB, 0);
3411 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3412 !(ifp->if_flags & IFF_PROMISC) &&
3413 sc->ti_if_flags & IFF_PROMISC) {
3414 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3415 TI_CMD_CODE_PROMISC_DIS, 0);
3419 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3423 sc->ti_if_flags = ifp->if_flags;
3429 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3435 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3439 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3440 if ((mask & IFCAP_TXCSUM) != 0 &&
3441 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3442 ifp->if_capenable ^= IFCAP_TXCSUM;
3443 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3444 ifp->if_hwassist |= TI_CSUM_FEATURES;
3446 ifp->if_hwassist &= ~TI_CSUM_FEATURES;
3448 if ((mask & IFCAP_RXCSUM) != 0 &&
3449 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3450 ifp->if_capenable ^= IFCAP_RXCSUM;
3451 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3452 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0)
3453 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3454 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3455 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
3456 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
3457 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM |
3458 IFCAP_VLAN_HWTAGGING)) != 0) {
3459 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3460 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3465 VLAN_CAPABILITIES(ifp);
3468 error = ether_ioctl(ifp, command, data);
3476 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3478 struct ti_softc *sc;
3485 sc->ti_flags |= TI_FLAG_DEBUGING;
3492 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3494 struct ti_softc *sc;
3501 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3508 * This ioctl routine goes along with the Tigon character device.
3511 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3514 struct ti_softc *sc;
3526 struct ti_stats *outstats;
3528 outstats = (struct ti_stats *)addr;
3531 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3532 sizeof(struct ti_stats));
3536 case TIIOCGETPARAMS:
3538 struct ti_params *params;
3540 params = (struct ti_params *)addr;
3543 params->ti_stat_ticks = sc->ti_stat_ticks;
3544 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3545 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3546 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3547 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3548 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3549 params->param_mask = TI_PARAM_ALL;
3553 case TIIOCSETPARAMS:
3555 struct ti_params *params;
3557 params = (struct ti_params *)addr;
3560 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3561 sc->ti_stat_ticks = params->ti_stat_ticks;
3562 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3565 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3566 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3567 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3568 sc->ti_rx_coal_ticks);
3571 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3572 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3573 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3574 sc->ti_tx_coal_ticks);
3577 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3578 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3579 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3580 sc->ti_rx_max_coal_bds);
3583 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3584 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3585 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3586 sc->ti_tx_max_coal_bds);
3589 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3590 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3591 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3592 sc->ti_tx_buf_ratio);
3597 case TIIOCSETTRACE: {
3598 ti_trace_type trace_type;
3600 trace_type = *(ti_trace_type *)addr;
3603 * Set tracing to whatever the user asked for. Setting
3604 * this register to 0 should have the effect of disabling
3608 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3612 case TIIOCGETTRACE: {
3613 struct ti_trace_buf *trace_buf;
3614 uint32_t trace_start, cur_trace_ptr, trace_len;
3616 trace_buf = (struct ti_trace_buf *)addr;
3619 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3620 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3621 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3623 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3624 "trace_len = %d\n", trace_start,
3625 cur_trace_ptr, trace_len);
3626 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3627 trace_buf->buf_len);
3629 error = ti_copy_mem(sc, trace_start, min(trace_len,
3630 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1);
3632 trace_buf->fill_len = min(trace_len,
3633 trace_buf->buf_len);
3634 if (cur_trace_ptr < trace_start)
3635 trace_buf->cur_trace_ptr =
3636 trace_start - cur_trace_ptr;
3638 trace_buf->cur_trace_ptr =
3639 cur_trace_ptr - trace_start;
3641 trace_buf->fill_len = 0;
3647 * For debugging, five ioctls are needed:
3656 * From what I can tell, Alteon's Solaris Tigon driver
3657 * only has one character device, so you have to attach
3658 * to the Tigon board you're interested in. This seems
3659 * like a not-so-good way to do things, since unless you
3660 * subsequently specify the unit number of the device
3661 * you're interested in every ioctl, you'll only be
3662 * able to debug one board at a time.
3665 case ALT_READ_TG_MEM:
3666 case ALT_WRITE_TG_MEM:
3668 struct tg_mem *mem_param;
3669 uint32_t sram_end, scratch_end;
3671 mem_param = (struct tg_mem *)addr;
3673 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3674 sram_end = TI_END_SRAM_I;
3675 scratch_end = TI_END_SCRATCH_I;
3677 sram_end = TI_END_SRAM_II;
3678 scratch_end = TI_END_SCRATCH_II;
3682 * For now, we'll only handle accessing regular SRAM,
3686 if (mem_param->tgAddr >= TI_BEG_SRAM &&
3687 mem_param->tgAddr + mem_param->len <= sram_end) {
3689 * In this instance, we always copy to/from user
3690 * space, so the user space argument is set to 1.
3692 error = ti_copy_mem(sc, mem_param->tgAddr,
3693 mem_param->len, mem_param->userAddr, 1,
3694 cmd == ALT_READ_TG_MEM ? 1 : 0);
3695 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH &&
3696 mem_param->tgAddr <= scratch_end) {
3697 error = ti_copy_scratch(sc, mem_param->tgAddr,
3698 mem_param->len, mem_param->userAddr, 1,
3699 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A);
3700 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG &&
3701 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) {
3702 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3703 if_printf(sc->ti_ifp,
3704 "invalid memory range for Tigon I\n");
3708 error = ti_copy_scratch(sc, mem_param->tgAddr -
3709 TI_SCRATCH_DEBUG_OFF, mem_param->len,
3710 mem_param->userAddr, 1,
3711 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B);
3713 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3714 "out of supported range\n",
3715 mem_param->tgAddr, mem_param->len);
3721 case ALT_READ_TG_REG:
3722 case ALT_WRITE_TG_REG:
3724 struct tg_reg *regs;
3727 regs = (struct tg_reg *)addr;
3730 * Make sure the address in question isn't out of range.
3732 if (regs->addr > TI_REG_MAX) {
3737 if (cmd == ALT_READ_TG_REG) {
3738 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3739 regs->addr, &tmpval, 1);
3740 regs->data = ntohl(tmpval);
3742 if ((regs->addr == TI_CPU_STATE)
3743 || (regs->addr == TI_CPU_CTL_B)) {
3744 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3745 regs->addr, tmpval);
3749 tmpval = htonl(regs->data);
3750 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3751 regs->addr, &tmpval, 1);
3764 ti_watchdog(void *arg)
3766 struct ti_softc *sc;
3771 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3772 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3776 * When we're debugging, the chip is often stopped for long periods
3777 * of time, and that would normally cause the watchdog timer to fire.
3778 * Since that impedes debugging, we don't want to do that.
3780 if (sc->ti_flags & TI_FLAG_DEBUGING)
3784 if_printf(ifp, "watchdog timeout -- resetting\n");
3785 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3792 * Stop the adapter and free any mbufs allocated to the
3796 ti_stop(struct ti_softc *sc)
3799 struct ti_cmd_desc cmd;
3805 /* Disable host interrupts. */
3806 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3808 * Tell firmware we're shutting down.
3810 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3812 /* Halt and reinitialize. */
3813 if (ti_chipinit(sc) == 0) {
3814 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3815 /* XXX ignore init errors. */
3819 /* Free the RX lists. */
3820 ti_free_rx_ring_std(sc);
3822 /* Free jumbo RX list. */
3823 ti_free_rx_ring_jumbo(sc);
3825 /* Free mini RX list. */
3826 ti_free_rx_ring_mini(sc);
3828 /* Free TX buffers. */
3829 ti_free_tx_ring(sc);
3831 sc->ti_ev_prodidx.ti_idx = 0;
3832 sc->ti_return_prodidx.ti_idx = 0;
3833 sc->ti_tx_considx.ti_idx = 0;
3834 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3836 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3837 callout_stop(&sc->ti_watchdog);
3841 * Stop all chip I/O so that the kernel's probe routines don't
3842 * get confused by errant DMAs when rebooting.
3845 ti_shutdown(device_t dev)
3847 struct ti_softc *sc;
3849 sc = device_get_softc(dev);
3858 ti_sysctl_node(struct ti_softc *sc)
3860 struct sysctl_ctx_list *ctx;
3861 struct sysctl_oid_list *child;
3863 ctx = device_get_sysctl_ctx(sc->ti_dev);
3864 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev));
3866 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW,
3867 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks");
3868 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW,
3869 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs");
3871 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW,
3872 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks");
3873 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW,
3874 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs");
3875 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW,
3876 &sc->ti_tx_buf_ratio, 0,
3877 "Ratio of NIC memory devoted to TX buffer");
3879 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW,
3880 &sc->ti_stat_ticks, 0,
3881 "Number of clock ticks for statistics update interval");
3883 /* Pull in device tunables. */
3884 sc->ti_rx_coal_ticks = 170;
3885 resource_int_value(device_get_name(sc->ti_dev),
3886 device_get_unit(sc->ti_dev), "rx_coal_ticks",
3887 &sc->ti_rx_coal_ticks);
3888 sc->ti_rx_max_coal_bds = 64;
3889 resource_int_value(device_get_name(sc->ti_dev),
3890 device_get_unit(sc->ti_dev), "rx_max_coal_bds",
3891 &sc->ti_rx_max_coal_bds);
3893 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
3894 resource_int_value(device_get_name(sc->ti_dev),
3895 device_get_unit(sc->ti_dev), "tx_coal_ticks",
3896 &sc->ti_tx_coal_ticks);
3897 sc->ti_tx_max_coal_bds = 32;
3898 resource_int_value(device_get_name(sc->ti_dev),
3899 device_get_unit(sc->ti_dev), "tx_max_coal_bds",
3900 &sc->ti_tx_max_coal_bds);
3901 sc->ti_tx_buf_ratio = 21;
3902 resource_int_value(device_get_name(sc->ti_dev),
3903 device_get_unit(sc->ti_dev), "tx_buf_ratio",
3904 &sc->ti_tx_buf_ratio);
3906 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
3907 resource_int_value(device_get_name(sc->ti_dev),
3908 device_get_unit(sc->ti_dev), "stat_ticks",
3909 &sc->ti_stat_ticks);