3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2010-2022 Hans Petter Selasky
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
32 * The XHCI 1.0 spec can be found at
33 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
34 * and the USB 3.0 spec at
35 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
39 * A few words about the design implementation: This driver emulates
40 * the concept about TDs which is found in EHCI specification. This
41 * way we achieve that the USB controller drivers look similar to
42 * eachother which makes it easier to understand the code.
45 #ifdef USB_GLOBAL_INCLUDE_FILE
46 #include USB_GLOBAL_INCLUDE_FILE
48 #include <sys/stdint.h>
49 #include <sys/stddef.h>
50 #include <sys/param.h>
51 #include <sys/queue.h>
52 #include <sys/types.h>
53 #include <sys/systm.h>
54 #include <sys/kernel.h>
56 #include <sys/module.h>
58 #include <sys/mutex.h>
59 #include <sys/condvar.h>
60 #include <sys/sysctl.h>
62 #include <sys/unistd.h>
63 #include <sys/callout.h>
64 #include <sys/malloc.h>
67 #include <dev/usb/usb.h>
68 #include <dev/usb/usbdi.h>
70 #define USB_DEBUG_VAR xhcidebug
72 #include <dev/usb/usb_core.h>
73 #include <dev/usb/usb_debug.h>
74 #include <dev/usb/usb_busdma.h>
75 #include <dev/usb/usb_process.h>
76 #include <dev/usb/usb_transfer.h>
77 #include <dev/usb/usb_device.h>
78 #include <dev/usb/usb_hub.h>
79 #include <dev/usb/usb_util.h>
81 #include <dev/usb/usb_controller.h>
82 #include <dev/usb/usb_bus.h>
83 #endif /* USB_GLOBAL_INCLUDE_FILE */
85 #include <dev/usb/controller/xhci.h>
86 #include <dev/usb/controller/xhcireg.h>
88 #define XHCI_BUS2SC(bus) \
89 __containerof(bus, struct xhci_softc, sc_bus)
91 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
94 static int xhcistreams;
95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN,
96 &xhcistreams, 0, "Set to enable streams mode support");
98 static int xhcictlquirk = 1;
99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN,
100 &xhcictlquirk, 0, "Set to enable control endpoint quirk");
102 static int xhcidcepquirk;
103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dcepquirk, CTLFLAG_RWTUN,
104 &xhcidcepquirk, 0, "Set to disable endpoint deconfigure command");
107 static int xhcidebug;
108 static int xhciroute;
109 static int xhcipolling;
110 static int xhcidma32;
111 static int xhcictlstep;
113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
114 &xhcidebug, 0, "Debug level");
115 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
116 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
117 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
118 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
119 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
120 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
121 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
122 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
126 #define xhcictlstep 0
129 #define XHCI_INTR_ENDPT 1
131 struct xhci_std_temp {
132 struct xhci_softc *sc;
133 struct usb_page_cache *pc;
135 struct xhci_td *td_next;
138 uint32_t max_packet_size;
150 uint8_t do_isoc_sync;
153 static void xhci_do_poll(struct usb_bus *);
154 static void xhci_device_done(struct usb_xfer *, usb_error_t);
155 static void xhci_root_intr(struct xhci_softc *);
156 static void xhci_free_device_ext(struct usb_device *);
157 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
158 struct usb_endpoint_descriptor *);
159 static usb_proc_callback_t xhci_configure_msg;
160 static usb_error_t xhci_configure_device(struct usb_device *);
161 static usb_error_t xhci_configure_endpoint(struct usb_device *,
162 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
163 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
165 static usb_error_t xhci_configure_mask(struct usb_device *,
167 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
169 static void xhci_endpoint_doorbell(struct usb_xfer *);
170 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
171 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
172 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
174 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
177 static const struct usb_bus_methods xhci_bus_methods;
181 xhci_dump_trb(struct xhci_trb *trb)
183 DPRINTFN(5, "trb = %p\n", trb);
184 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
185 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
186 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
190 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
192 DPRINTFN(5, "pep = %p\n", pep);
193 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
194 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
195 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
196 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
197 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
198 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
199 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
203 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
205 DPRINTFN(5, "psl = %p\n", psl);
206 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
207 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
208 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
209 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
214 xhci_use_polling(void)
217 return (xhcipolling != 0);
224 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
226 struct xhci_softc *sc = XHCI_BUS2SC(bus);
229 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
230 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
232 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
233 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
235 for (i = 0; i != sc->sc_noscratch; i++) {
236 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
237 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
242 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
244 if (sc->sc_ctx_is_64_byte) {
246 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
247 /* all contexts are initially 32-bytes */
248 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
249 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
255 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
257 if (sc->sc_ctx_is_64_byte) {
259 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
260 /* all contexts are initially 32-bytes */
261 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
262 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
264 return (le32toh(*ptr));
268 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
270 if (sc->sc_ctx_is_64_byte) {
272 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
273 /* all contexts are initially 32-bytes */
274 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
275 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
282 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
284 if (sc->sc_ctx_is_64_byte) {
286 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
287 /* all contexts are initially 32-bytes */
288 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
289 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
291 return (le64toh(*ptr));
296 xhci_reset_command_queue_locked(struct xhci_softc *sc)
298 struct usb_page_search buf_res;
299 struct xhci_hw_root *phwr;
305 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
306 if (temp & XHCI_CRCR_LO_CRR) {
307 DPRINTF("Command ring running\n");
308 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
311 * Try to abort the last command as per section
312 * 4.6.1.2 "Aborting a Command" of the XHCI
316 /* stop and cancel */
317 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
318 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
320 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
321 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
324 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
326 /* check if command ring is still running */
327 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
328 if (temp & XHCI_CRCR_LO_CRR) {
329 DPRINTF("Comand ring still running\n");
330 return (USB_ERR_IOERROR);
334 /* reset command ring */
335 sc->sc_command_ccs = 1;
336 sc->sc_command_idx = 0;
338 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
340 /* set up command ring control base address */
341 addr = buf_res.physaddr;
342 phwr = buf_res.buffer;
343 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]);
345 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
347 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
348 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
350 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
352 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
353 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
359 xhci_start_controller(struct xhci_softc *sc)
361 struct usb_page_search buf_res;
362 struct xhci_hw_root *phwr;
363 struct xhci_dev_ctx_addr *pdctxa;
371 sc->sc_event_ccs = 1;
372 sc->sc_event_idx = 0;
373 sc->sc_command_ccs = 1;
374 sc->sc_command_idx = 0;
376 err = xhci_reset_controller(sc);
380 /* set up number of device slots */
381 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
382 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
384 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
386 temp = XREAD4(sc, oper, XHCI_USBSTS);
388 /* clear interrupts */
389 XWRITE4(sc, oper, XHCI_USBSTS, temp);
390 /* disable all device notifications */
391 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
393 /* set up device context base address */
394 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
395 pdctxa = buf_res.buffer;
396 memset(pdctxa, 0, sizeof(*pdctxa));
398 addr = buf_res.physaddr;
399 addr += __offsetof(struct xhci_dev_ctx_addr, qwSpBufPtr[0]);
401 /* slot 0 points to the table of scratchpad pointers */
402 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
404 for (i = 0; i != sc->sc_noscratch; i++) {
405 struct usb_page_search buf_scp;
406 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
407 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
410 addr = buf_res.physaddr;
412 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
413 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
414 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
415 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
417 /* set up event table size */
418 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
419 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
421 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
423 /* set up interrupt rate */
424 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
426 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
428 phwr = buf_res.buffer;
429 addr = buf_res.physaddr;
430 addr += __offsetof(struct xhci_hw_root, hwr_events[0]);
432 /* reset hardware root structure */
433 memset(phwr, 0, sizeof(*phwr));
435 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
436 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
441 * According to the XHCI specification, the XWRITE4's to
442 * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the
443 * qwEvrsTablePtr and dwEvrsTableSize values above at that
444 * time, as the XHCI initializes its event ring support. This
445 * is before the event ring starts to pay attention to the
446 * RUN/STOP bit. Thus, make sure the values are observable to
447 * the XHCI before that point.
449 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
451 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
453 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
454 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
456 addr = buf_res.physaddr;
458 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
460 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
461 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
463 /* set up interrupter registers */
464 temp = XREAD4(sc, runt, XHCI_IMAN(0));
465 temp |= XHCI_IMAN_INTR_ENA;
466 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
468 /* set up command ring control base address */
469 addr = buf_res.physaddr;
470 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]);
472 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
474 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
475 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
477 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
479 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
482 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
483 XHCI_CMD_INTE | XHCI_CMD_HSEE);
485 for (i = 0; i != 100; i++) {
486 usb_pause_mtx(NULL, hz / 100);
487 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
492 XWRITE4(sc, oper, XHCI_USBCMD, 0);
493 device_printf(sc->sc_bus.parent, "Run timeout.\n");
494 return (USB_ERR_IOERROR);
497 /* catch any lost interrupts */
498 xhci_do_poll(&sc->sc_bus);
500 if (sc->sc_port_route != NULL) {
501 /* Route all ports to the XHCI by default */
502 sc->sc_port_route(sc->sc_bus.parent,
503 ~xhciroute, xhciroute);
509 xhci_halt_controller(struct xhci_softc *sc)
517 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
518 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
519 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
521 /* Halt controller */
522 XWRITE4(sc, oper, XHCI_USBCMD, 0);
524 for (i = 0; i != 100; i++) {
525 usb_pause_mtx(NULL, hz / 100);
526 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
532 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
533 return (USB_ERR_IOERROR);
539 xhci_reset_controller(struct xhci_softc *sc)
546 /* Reset controller */
547 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
549 for (i = 0; i != 100; i++) {
550 usb_pause_mtx(NULL, hz / 100);
551 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
552 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
558 device_printf(sc->sc_bus.parent, "Controller "
560 return (USB_ERR_IOERROR);
566 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
572 /* initialize some bus fields */
573 sc->sc_bus.parent = self;
575 /* set the bus revision */
576 sc->sc_bus.usbrev = USB_REV_3_0;
578 /* set up the bus struct */
579 sc->sc_bus.methods = &xhci_bus_methods;
581 /* set up devices array */
582 sc->sc_bus.devices = sc->sc_devices;
583 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
585 /* set default cycle state in case of early interrupts */
586 sc->sc_event_ccs = 1;
587 sc->sc_command_ccs = 1;
589 /* set up bus space offsets */
591 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
592 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
593 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
595 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
596 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
597 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
599 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
601 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
602 device_printf(sc->sc_bus.parent, "Controller does "
603 "not support 4K page size.\n");
607 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
609 DPRINTF("HCS0 = 0x%08x\n", temp);
611 /* set up context size */
612 if (XHCI_HCS0_CSZ(temp)) {
613 sc->sc_ctx_is_64_byte = 1;
615 sc->sc_ctx_is_64_byte = 0;
619 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
620 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
622 device_printf(self, "%d bytes context size, %d-bit DMA\n",
623 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
625 /* enable 64Kbyte control endpoint quirk */
626 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0);
628 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
630 /* get number of device slots */
631 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
633 if (sc->sc_noport == 0) {
634 device_printf(sc->sc_bus.parent, "Invalid number "
635 "of ports: %u\n", sc->sc_noport);
639 sc->sc_noport = sc->sc_noport;
640 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
642 DPRINTF("Max slots: %u\n", sc->sc_noslot);
644 if (sc->sc_noslot > XHCI_MAX_DEVICES)
645 sc->sc_noslot = XHCI_MAX_DEVICES;
647 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
649 DPRINTF("HCS2=0x%08x\n", temp);
651 /* get isochronous scheduling threshold */
652 sc->sc_ist = XHCI_HCS2_IST(temp);
654 /* get number of scratchpads */
655 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
657 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
658 device_printf(sc->sc_bus.parent, "XHCI request "
659 "too many scratchpads\n");
663 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
665 /* get event table size */
666 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
667 if (sc->sc_erst_max > XHCI_MAX_RSEG)
668 sc->sc_erst_max = XHCI_MAX_RSEG;
670 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
672 /* get maximum exit latency */
673 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
674 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
676 /* Check if we should use the default IMOD value. */
677 if (sc->sc_imod_default == 0)
678 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
680 /* get all DMA memory */
681 if (usb_bus_mem_alloc_all(&sc->sc_bus,
682 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
686 /* set up command queue mutex and condition varible */
687 cv_init(&sc->sc_cmd_cv, "CMDQ");
688 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
690 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
691 sc->sc_config_msg[0].bus = &sc->sc_bus;
692 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
693 sc->sc_config_msg[1].bus = &sc->sc_bus;
699 xhci_uninit(struct xhci_softc *sc)
702 * NOTE: At this point the control transfer process is gone
703 * and "xhci_configure_msg" is no longer called. Consequently
704 * waiting for the configuration messages to complete is not
707 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
709 cv_destroy(&sc->sc_cmd_cv);
710 sx_destroy(&sc->sc_cmd_sx);
714 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
716 struct xhci_softc *sc = XHCI_BUS2SC(bus);
719 case USB_HW_POWER_SUSPEND:
720 DPRINTF("Stopping the XHCI\n");
721 xhci_halt_controller(sc);
722 xhci_reset_controller(sc);
724 case USB_HW_POWER_SHUTDOWN:
725 DPRINTF("Stopping the XHCI\n");
726 xhci_halt_controller(sc);
727 xhci_reset_controller(sc);
729 case USB_HW_POWER_RESUME:
730 DPRINTF("Starting the XHCI\n");
731 xhci_start_controller(sc);
739 xhci_generic_done_sub(struct usb_xfer *xfer)
742 struct xhci_td *td_alt_next;
746 td = xfer->td_transfer_cache;
747 td_alt_next = td->alt_next;
749 if (xfer->aframes != xfer->nframes)
750 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
753 usb_pc_cpu_invalidate(td->page_cache);
758 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
759 xfer, (unsigned int)xfer->aframes,
760 (unsigned int)xfer->nframes,
761 (unsigned int)len, (unsigned int)td->len,
762 (unsigned int)status);
765 * Verify the status length and
766 * add the length to "frlengths[]":
769 /* should not happen */
770 DPRINTF("Invalid status length, "
771 "0x%04x/0x%04x bytes\n", len, td->len);
772 status = XHCI_TRB_ERROR_LENGTH;
773 } else if (xfer->aframes != xfer->nframes) {
774 xfer->frlengths[xfer->aframes] += td->len - len;
776 /* Check for last transfer */
777 if (((void *)td) == xfer->td_transfer_last) {
781 /* Check for transfer error */
782 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
783 status != XHCI_TRB_ERROR_SUCCESS) {
784 /* the transfer is finished */
788 /* Check for short transfer */
790 if (xfer->flags_int.short_frames_ok ||
791 xfer->flags_int.isochronous_xfr ||
792 xfer->flags_int.control_xfr) {
793 /* follow alt next */
796 /* the transfer is finished */
803 if (td->alt_next != td_alt_next) {
804 /* this USB frame is complete */
809 /* update transfer cache */
811 xfer->td_transfer_cache = td;
813 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
814 (status != XHCI_TRB_ERROR_SHORT_PKT &&
815 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
816 USB_ERR_NORMAL_COMPLETION);
820 xhci_generic_done(struct usb_xfer *xfer)
824 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
825 xfer, xfer->endpoint);
829 xfer->td_transfer_cache = xfer->td_transfer_first;
831 if (xfer->flags_int.control_xfr) {
832 if (xfer->flags_int.control_hdr)
833 err = xhci_generic_done_sub(xfer);
837 if (xfer->td_transfer_cache == NULL)
841 while (xfer->aframes != xfer->nframes) {
842 err = xhci_generic_done_sub(xfer);
845 if (xfer->td_transfer_cache == NULL)
849 if (xfer->flags_int.control_xfr &&
850 !xfer->flags_int.control_act)
851 err = xhci_generic_done_sub(xfer);
853 /* transfer is complete */
854 xhci_device_done(xfer, err);
858 xhci_activate_transfer(struct usb_xfer *xfer)
862 td = xfer->td_transfer_cache;
864 usb_pc_cpu_invalidate(td->page_cache);
866 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
867 /* activate the transfer */
869 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
870 usb_pc_cpu_flush(td->page_cache);
872 xhci_endpoint_doorbell(xfer);
877 xhci_skip_transfer(struct usb_xfer *xfer)
880 struct xhci_td *td_last;
882 td = xfer->td_transfer_cache;
883 td_last = xfer->td_transfer_last;
887 usb_pc_cpu_invalidate(td->page_cache);
889 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
890 usb_pc_cpu_invalidate(td_last->page_cache);
892 /* copy LINK TRB to current waiting location */
894 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
895 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
896 usb_pc_cpu_flush(td->page_cache);
898 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
899 usb_pc_cpu_flush(td->page_cache);
901 xhci_endpoint_doorbell(xfer);
905 /*------------------------------------------------------------------------*
906 * xhci_check_transfer
907 *------------------------------------------------------------------------*/
909 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
911 struct xhci_endpoint_ext *pepext;
916 uint16_t stream_id = 0;
924 td_event = le64toh(trb->qwTrb0);
925 temp = le32toh(trb->dwTrb2);
927 remainder = XHCI_TRB_2_REM_GET(temp);
928 status = XHCI_TRB_2_ERROR_GET(temp);
930 temp = le32toh(trb->dwTrb3);
931 epno = XHCI_TRB_3_EP_GET(temp);
932 index = XHCI_TRB_3_SLOT_GET(temp);
934 /* check if error means halted */
935 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
936 status != XHCI_TRB_ERROR_SUCCESS);
938 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
939 index, epno, remainder, status);
941 if (index > sc->sc_noslot) {
942 DPRINTF("Invalid slot.\n");
946 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
947 DPRINTF("Invalid endpoint.\n");
951 pepext = &sc->sc_hw.devs[index].endp[epno];
953 /* try to find the USB transfer that generated the event */
955 struct usb_xfer *xfer;
958 if (i == (XHCI_MAX_TRANSFERS - 1)) {
959 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS ||
960 stream_id == (XHCI_MAX_STREAMS - 1))
964 DPRINTFN(5, "stream_id=%u\n", stream_id);
967 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
971 td = xfer->td_transfer_cache;
973 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
975 (long long)td->td_self,
976 (long long)td->td_self + sizeof(td->td_trb));
979 * NOTE: Some XHCI implementations might not trigger
980 * an event on the last LINK TRB so we need to
981 * consider both the last and second last event
982 * address as conditions for a successful transfer.
984 * NOTE: We assume that the XHCI will only trigger one
985 * event per chain of TRBs.
988 offset = td_event - td->td_self;
991 offset < (int64_t)sizeof(td->td_trb)) {
992 usb_pc_cpu_invalidate(td->page_cache);
994 /* compute rest of remainder, if any */
995 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
996 temp = le32toh(td->td_trb[i].dwTrb2);
997 remainder += XHCI_TRB_2_BYTES_GET(temp);
1000 DPRINTFN(5, "New remainder: %u\n", remainder);
1002 /* clear isochronous transfer errors */
1003 if (xfer->flags_int.isochronous_xfr) {
1006 status = XHCI_TRB_ERROR_SUCCESS;
1007 remainder = td->len;
1011 /* "td->remainder" is verified later */
1012 td->remainder = remainder;
1013 td->status = status;
1015 usb_pc_cpu_flush(td->page_cache);
1018 * 1) Last transfer descriptor makes the
1021 if (((void *)td) == xfer->td_transfer_last) {
1022 DPRINTF("TD is last\n");
1023 xhci_generic_done(xfer);
1028 * 2) Any kind of error makes the transfer
1032 DPRINTF("TD has I/O error\n");
1033 xhci_generic_done(xfer);
1038 * 3) If there is no alternate next transfer,
1039 * a short packet also makes the transfer done
1041 if (td->remainder > 0) {
1042 if (td->alt_next == NULL) {
1044 "short TD has no alternate next\n");
1045 xhci_generic_done(xfer);
1048 DPRINTF("TD has short pkt\n");
1049 if (xfer->flags_int.short_frames_ok ||
1050 xfer->flags_int.isochronous_xfr ||
1051 xfer->flags_int.control_xfr) {
1052 /* follow the alt next */
1053 xfer->td_transfer_cache = td->alt_next;
1054 xhci_activate_transfer(xfer);
1057 xhci_skip_transfer(xfer);
1058 xhci_generic_done(xfer);
1063 * 4) Transfer complete - go to next TD
1065 DPRINTF("Following next TD\n");
1066 xfer->td_transfer_cache = td->obj_next;
1067 xhci_activate_transfer(xfer);
1068 break; /* there should only be one match */
1074 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1076 if (sc->sc_cmd_addr == trb->qwTrb0) {
1077 DPRINTF("Received command event\n");
1078 sc->sc_cmd_result[0] = trb->dwTrb2;
1079 sc->sc_cmd_result[1] = trb->dwTrb3;
1080 cv_signal(&sc->sc_cmd_cv);
1081 return (1); /* command match */
1087 xhci_interrupt_poll(struct xhci_softc *sc)
1089 struct usb_page_search buf_res;
1090 struct xhci_hw_root *phwr;
1100 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1102 phwr = buf_res.buffer;
1104 /* Receive any events */
1106 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1108 i = sc->sc_event_idx;
1109 j = sc->sc_event_ccs;
1113 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1115 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1120 event = XHCI_TRB_3_TYPE_GET(temp);
1122 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1123 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1124 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1125 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1128 case XHCI_TRB_EVENT_TRANSFER:
1129 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1131 case XHCI_TRB_EVENT_CMD_COMPLETE:
1132 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1135 DPRINTF("Unhandled event = %u\n", event);
1141 if (i == XHCI_MAX_EVENTS) {
1145 /* check for timeout */
1151 sc->sc_event_idx = i;
1152 sc->sc_event_ccs = j;
1155 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1156 * latched. That means to activate the register we need to
1157 * write both the low and high double word of the 64-bit
1161 addr = buf_res.physaddr;
1162 addr += __offsetof(struct xhci_hw_root, hwr_events[i]);
1164 /* try to clear busy bit */
1165 addr |= XHCI_ERDP_LO_BUSY;
1167 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1168 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1174 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1175 uint16_t timeout_ms)
1177 struct usb_page_search buf_res;
1178 struct xhci_hw_root *phwr;
1183 uint8_t timeout = 0;
1186 XHCI_CMD_ASSERT_LOCKED(sc);
1188 /* get hardware root structure */
1190 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1192 phwr = buf_res.buffer;
1196 USB_BUS_LOCK(&sc->sc_bus);
1198 i = sc->sc_command_idx;
1199 j = sc->sc_command_ccs;
1201 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1202 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1203 (long long)le64toh(trb->qwTrb0),
1204 (long)le32toh(trb->dwTrb2),
1205 (long)le32toh(trb->dwTrb3));
1207 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1208 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1210 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1215 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1217 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1219 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1221 phwr->hwr_commands[i].dwTrb3 = temp;
1223 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1225 addr = buf_res.physaddr;
1226 addr += __offsetof(struct xhci_hw_root, hwr_commands[i]);
1228 sc->sc_cmd_addr = htole64(addr);
1232 if (i == (XHCI_MAX_COMMANDS - 1)) {
1234 temp = htole32(XHCI_TRB_3_TC_BIT |
1235 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1236 XHCI_TRB_3_CYCLE_BIT);
1238 temp = htole32(XHCI_TRB_3_TC_BIT |
1239 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1242 phwr->hwr_commands[i].dwTrb3 = temp;
1244 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1250 sc->sc_command_idx = i;
1251 sc->sc_command_ccs = j;
1253 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1255 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1256 USB_MS_TO_TICKS(timeout_ms));
1259 * In some error cases event interrupts are not generated.
1260 * Poll one time to see if the command has completed.
1262 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1263 DPRINTF("Command was completed when polling\n");
1267 DPRINTF("Command timeout!\n");
1269 * After some weeks of continuous operation, it has
1270 * been observed that the ASMedia Technology, ASM1042
1271 * SuperSpeed USB Host Controller can suddenly stop
1272 * accepting commands via the command queue. Try to
1273 * first reset the command queue. If that fails do a
1274 * host controller reset.
1277 xhci_reset_command_queue_locked(sc) == 0) {
1278 temp = le32toh(trb->dwTrb3);
1281 * Avoid infinite XHCI reset loops if the set
1282 * address command fails to respond due to a
1283 * non-enumerating device:
1285 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1286 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1287 DPRINTF("Set address timeout\n");
1293 DPRINTF("Controller reset!\n");
1294 usb_bus_reset_async_locked(&sc->sc_bus);
1296 err = USB_ERR_TIMEOUT;
1300 temp = le32toh(sc->sc_cmd_result[0]);
1301 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1302 err = USB_ERR_IOERROR;
1304 trb->dwTrb2 = sc->sc_cmd_result[0];
1305 trb->dwTrb3 = sc->sc_cmd_result[1];
1308 USB_BUS_UNLOCK(&sc->sc_bus);
1315 xhci_cmd_nop(struct xhci_softc *sc)
1317 struct xhci_trb trb;
1324 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1326 trb.dwTrb3 = htole32(temp);
1328 return (xhci_do_command(sc, &trb, 100 /* ms */));
1333 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1335 struct xhci_trb trb;
1343 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1345 err = xhci_do_command(sc, &trb, 100 /* ms */);
1349 temp = le32toh(trb.dwTrb3);
1351 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1358 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1360 struct xhci_trb trb;
1367 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1368 XHCI_TRB_3_SLOT_SET(slot_id);
1370 trb.dwTrb3 = htole32(temp);
1372 return (xhci_do_command(sc, &trb, 100 /* ms */));
1376 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1377 uint8_t bsr, uint8_t slot_id)
1379 struct xhci_trb trb;
1384 trb.qwTrb0 = htole64(input_ctx);
1386 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1387 XHCI_TRB_3_SLOT_SET(slot_id);
1390 temp |= XHCI_TRB_3_BSR_BIT;
1392 trb.dwTrb3 = htole32(temp);
1394 return (xhci_do_command(sc, &trb, 500 /* ms */));
1398 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1400 struct usb_page_search buf_inp;
1401 struct usb_page_search buf_dev;
1402 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1403 struct xhci_hw_dev *hdev;
1404 struct xhci_dev_ctx *pdev;
1405 struct xhci_endpoint_ext *pepext;
1411 /* the root HUB case is not handled here */
1412 if (udev->parent_hub == NULL)
1413 return (USB_ERR_INVAL);
1415 index = udev->controller_slot_id;
1417 hdev = &sc->sc_hw.devs[index];
1424 switch (hdev->state) {
1425 case XHCI_ST_DEFAULT:
1426 case XHCI_ST_ENABLED:
1428 hdev->state = XHCI_ST_ENABLED;
1430 /* set configure mask to slot and EP0 */
1431 xhci_configure_mask(udev, 3, 0);
1433 /* configure input slot context structure */
1434 err = xhci_configure_device(udev);
1437 DPRINTF("Could not configure device\n");
1441 /* configure input endpoint context structure */
1442 switch (udev->speed) {
1444 case USB_SPEED_FULL:
1447 case USB_SPEED_HIGH:
1455 pepext = xhci_get_endpoint_ext(udev,
1456 &udev->ctrl_ep_desc);
1458 /* ensure the control endpoint is setup again */
1459 USB_BUS_LOCK(udev->bus);
1460 pepext->trb_halted = 1;
1461 pepext->trb_running = 0;
1462 USB_BUS_UNLOCK(udev->bus);
1464 err = xhci_configure_endpoint(udev,
1465 &udev->ctrl_ep_desc, pepext,
1466 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1469 DPRINTF("Could not configure default endpoint\n");
1473 /* execute set address command */
1474 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1476 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1477 (address == 0), index);
1480 temp = le32toh(sc->sc_cmd_result[0]);
1481 if (address == 0 && sc->sc_port_route != NULL &&
1482 XHCI_TRB_2_ERROR_GET(temp) ==
1483 XHCI_TRB_ERROR_PARAMETER) {
1484 /* LynxPoint XHCI - ports are not switchable */
1485 /* Un-route all ports from the XHCI */
1486 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1488 DPRINTF("Could not set address "
1489 "for slot %u.\n", index);
1494 /* update device address to new value */
1496 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1497 pdev = buf_dev.buffer;
1498 usb_pc_cpu_invalidate(&hdev->device_pc);
1500 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1501 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1503 /* update device state to new value */
1506 hdev->state = XHCI_ST_ADDRESSED;
1508 hdev->state = XHCI_ST_DEFAULT;
1512 DPRINTF("Wrong state for set address.\n");
1513 err = USB_ERR_IOERROR;
1516 XHCI_CMD_UNLOCK(sc);
1525 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1526 uint8_t deconfigure, uint8_t slot_id)
1528 struct xhci_trb trb;
1533 trb.qwTrb0 = htole64(input_ctx);
1535 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1536 XHCI_TRB_3_SLOT_SET(slot_id);
1539 if (sc->sc_no_deconfigure != 0 || xhcidcepquirk != 0)
1540 return (0); /* Success */
1541 temp |= XHCI_TRB_3_DCEP_BIT;
1544 trb.dwTrb3 = htole32(temp);
1546 return (xhci_do_command(sc, &trb, 100 /* ms */));
1550 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1553 struct xhci_trb trb;
1558 trb.qwTrb0 = htole64(input_ctx);
1560 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1561 XHCI_TRB_3_SLOT_SET(slot_id);
1562 trb.dwTrb3 = htole32(temp);
1564 return (xhci_do_command(sc, &trb, 100 /* ms */));
1568 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1569 uint8_t ep_id, uint8_t slot_id)
1571 struct xhci_trb trb;
1578 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1579 XHCI_TRB_3_SLOT_SET(slot_id) |
1580 XHCI_TRB_3_EP_SET(ep_id);
1583 temp |= XHCI_TRB_3_PRSV_BIT;
1585 trb.dwTrb3 = htole32(temp);
1587 return (xhci_do_command(sc, &trb, 100 /* ms */));
1591 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1592 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1594 struct xhci_trb trb;
1599 trb.qwTrb0 = htole64(dequeue_ptr);
1601 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1602 trb.dwTrb2 = htole32(temp);
1604 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1605 XHCI_TRB_3_SLOT_SET(slot_id) |
1606 XHCI_TRB_3_EP_SET(ep_id);
1607 trb.dwTrb3 = htole32(temp);
1609 return (xhci_do_command(sc, &trb, 100 /* ms */));
1613 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1614 uint8_t ep_id, uint8_t slot_id)
1616 struct xhci_trb trb;
1623 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1624 XHCI_TRB_3_SLOT_SET(slot_id) |
1625 XHCI_TRB_3_EP_SET(ep_id);
1628 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1630 trb.dwTrb3 = htole32(temp);
1632 return (xhci_do_command(sc, &trb, 100 /* ms */));
1636 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1638 struct xhci_trb trb;
1645 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1646 XHCI_TRB_3_SLOT_SET(slot_id);
1648 trb.dwTrb3 = htole32(temp);
1650 return (xhci_do_command(sc, &trb, 100 /* ms */));
1653 /*------------------------------------------------------------------------*
1654 * xhci_interrupt - XHCI interrupt handler
1655 *------------------------------------------------------------------------*/
1657 xhci_interrupt(struct xhci_softc *sc)
1662 USB_BUS_LOCK(&sc->sc_bus);
1664 status = XREAD4(sc, oper, XHCI_USBSTS);
1666 /* acknowledge interrupts, if any */
1668 XWRITE4(sc, oper, XHCI_USBSTS, status);
1669 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1672 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1674 /* force clearing of pending interrupts */
1675 if (temp & XHCI_IMAN_INTR_PEND)
1676 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1678 /* check for event(s) */
1679 xhci_interrupt_poll(sc);
1681 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1682 XHCI_STS_HSE | XHCI_STS_HCE)) {
1683 if (status & XHCI_STS_PCD) {
1687 if (status & XHCI_STS_HCH) {
1688 printf("%s: host controller halted\n",
1692 if (status & XHCI_STS_HSE) {
1693 printf("%s: host system error\n",
1697 if (status & XHCI_STS_HCE) {
1698 printf("%s: host controller error\n",
1702 USB_BUS_UNLOCK(&sc->sc_bus);
1705 /*------------------------------------------------------------------------*
1706 * xhci_timeout - XHCI timeout handler
1707 *------------------------------------------------------------------------*/
1709 xhci_timeout(void *arg)
1711 struct usb_xfer *xfer = arg;
1713 DPRINTF("xfer=%p\n", xfer);
1715 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1717 /* transfer is transferred */
1718 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1722 xhci_do_poll(struct usb_bus *bus)
1724 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1726 USB_BUS_LOCK(&sc->sc_bus);
1727 xhci_interrupt_poll(sc);
1728 USB_BUS_UNLOCK(&sc->sc_bus);
1732 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1734 struct usb_page_search buf_res;
1736 struct xhci_td *td_next;
1737 struct xhci_td *td_alt_next;
1738 struct xhci_td *td_first;
1739 uint32_t buf_offset;
1744 uint8_t shortpkt_old;
1750 shortpkt_old = temp->shortpkt;
1751 len_old = temp->len;
1758 td_next = td_first = temp->td_next;
1761 if (temp->len == 0) {
1765 /* send a Zero Length Packet, ZLP, last */
1771 average = temp->average;
1773 if (temp->len < average) {
1774 if (temp->len % temp->max_packet_size) {
1777 average = temp->len;
1781 if (td_next == NULL)
1782 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1787 td_next = td->obj_next;
1789 /* check if we are pre-computing */
1792 /* update remaining length */
1794 temp->len -= average;
1798 /* fill out current TD */
1804 /* update remaining length */
1806 temp->len -= average;
1808 /* reset TRB index */
1812 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1813 /* immediate data */
1818 td->td_trb[0].qwTrb0 = 0;
1820 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1821 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1824 dword = XHCI_TRB_2_BYTES_SET(8) |
1825 XHCI_TRB_2_TDSZ_SET(0) |
1826 XHCI_TRB_2_IRQ_SET(0);
1828 td->td_trb[0].dwTrb2 = htole32(dword);
1830 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1831 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1834 if (td->td_trb[0].qwTrb0 &
1835 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1836 if (td->td_trb[0].qwTrb0 &
1837 htole64(XHCI_TRB_0_DIR_IN_MASK))
1838 dword |= XHCI_TRB_3_TRT_IN;
1840 dword |= XHCI_TRB_3_TRT_OUT;
1843 td->td_trb[0].dwTrb3 = htole32(dword);
1845 xhci_dump_trb(&td->td_trb[x]);
1852 /* fill out buffer pointers */
1855 memset(&buf_res, 0, sizeof(buf_res));
1857 usbd_get_page(temp->pc, temp->offset +
1858 buf_offset, &buf_res);
1860 /* get length to end of page */
1861 if (buf_res.length > average)
1862 buf_res.length = average;
1864 /* check for maximum length */
1865 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1866 buf_res.length = XHCI_TD_PAGE_SIZE;
1868 npkt_off += buf_res.length;
1872 npkt = howmany(len_old - npkt_off,
1873 temp->max_packet_size);
1880 /* fill out TRB's */
1881 td->td_trb[x].qwTrb0 =
1882 htole64((uint64_t)buf_res.physaddr);
1885 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1886 XHCI_TRB_2_TDSZ_SET(npkt) |
1887 XHCI_TRB_2_IRQ_SET(0);
1889 td->td_trb[x].dwTrb2 = htole32(dword);
1891 switch (temp->trb_type) {
1892 case XHCI_TRB_TYPE_ISOCH:
1893 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1894 XHCI_TRB_3_TBC_SET(temp->tbc) |
1895 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1896 if (td != td_first) {
1897 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1898 } else if (temp->do_isoc_sync != 0) {
1899 temp->do_isoc_sync = 0;
1900 /* wait until "isoc_frame" */
1901 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1902 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1904 /* start data transfer at next interval */
1905 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1906 XHCI_TRB_3_ISO_SIA_BIT;
1908 if (temp->direction == UE_DIR_IN)
1909 dword |= XHCI_TRB_3_ISP_BIT;
1911 case XHCI_TRB_TYPE_DATA_STAGE:
1912 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1913 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1914 if (temp->direction == UE_DIR_IN)
1915 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1917 * Section 3.2.9 in the XHCI
1918 * specification about control
1919 * transfers says that we should use a
1920 * normal-TRB if there are more TRBs
1921 * extending the data-stage
1922 * TRB. Update the "trb_type".
1924 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1926 case XHCI_TRB_TYPE_STATUS_STAGE:
1927 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1928 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1929 if (temp->direction == UE_DIR_IN)
1930 dword |= XHCI_TRB_3_DIR_IN;
1932 default: /* XHCI_TRB_TYPE_NORMAL */
1933 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1934 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1935 if (temp->direction == UE_DIR_IN)
1936 dword |= XHCI_TRB_3_ISP_BIT;
1939 td->td_trb[x].dwTrb3 = htole32(dword);
1941 average -= buf_res.length;
1942 buf_offset += buf_res.length;
1944 xhci_dump_trb(&td->td_trb[x]);
1948 } while (average != 0);
1950 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1952 /* store number of data TRB's */
1956 DPRINTF("NTRB=%u\n", x);
1958 /* fill out link TRB */
1960 if (td_next != NULL) {
1961 /* link the current TD with the next one */
1962 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1963 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1965 /* this field will get updated later */
1966 DPRINTF("NOLINK\n");
1969 dword = XHCI_TRB_2_IRQ_SET(0);
1971 td->td_trb[x].dwTrb2 = htole32(dword);
1973 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1974 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1976 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1977 * frame only receives a single short packet event
1978 * by setting the CHAIN bit in the LINK field. In
1979 * addition some XHCI controllers have problems
1980 * sending a ZLP unless the CHAIN-BIT is set in
1983 XHCI_TRB_3_CHAIN_BIT;
1985 td->td_trb[x].dwTrb3 = htole32(dword);
1987 td->alt_next = td_alt_next;
1989 xhci_dump_trb(&td->td_trb[x]);
1991 usb_pc_cpu_flush(td->page_cache);
1997 /* set up alt next pointer, if any */
1998 if (temp->last_frame) {
2001 /* we use this field internally */
2002 td_alt_next = td_next;
2006 temp->shortpkt = shortpkt_old;
2007 temp->len = len_old;
2012 * Remove cycle bit from the first TRB if we are
2015 if (temp->step_td != 0) {
2016 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2017 usb_pc_cpu_flush(td_first->page_cache);
2020 /* clear TD SIZE to zero, hence this is the last TRB */
2021 /* remove chain bit because this is the last data TRB in the chain */
2022 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31));
2023 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2024 /* remove CHAIN-BIT from last LINK TRB */
2025 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2027 usb_pc_cpu_flush(td->page_cache);
2030 temp->td_next = td_next;
2034 xhci_setup_generic_chain(struct usb_xfer *xfer)
2036 struct xhci_std_temp temp;
2042 temp.do_isoc_sync = 0;
2046 temp.average = xfer->max_hc_frame_size;
2047 temp.max_packet_size = xfer->max_packet_size;
2048 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2050 temp.last_frame = 0;
2052 temp.multishort = xfer->flags_int.isochronous_xfr ||
2053 xfer->flags_int.control_xfr ||
2054 xfer->flags_int.short_frames_ok;
2056 /* toggle the DMA set we are using */
2057 xfer->flags_int.curr_dma_set ^= 1;
2059 /* get next DMA set */
2060 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2065 xfer->td_transfer_first = td;
2066 xfer->td_transfer_cache = td;
2068 if (xfer->flags_int.isochronous_xfr) {
2071 /* compute multiplier for ISOCHRONOUS transfers */
2072 mult = xfer->endpoint->ecomp ?
2073 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2075 /* check for USB 2.0 multiplier */
2077 mult = (xfer->endpoint->edesc->
2078 wMaxPacketSize[1] >> 3) & 3;
2086 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2088 DPRINTF("MFINDEX=0x%08x IST=0x%x\n", x, temp.sc->sc_ist);
2090 switch (usbd_get_speed(xfer->xroot->udev)) {
2091 case USB_SPEED_FULL:
2093 temp.isoc_delta = 8; /* 1ms */
2096 shift = usbd_xfer_get_fps_shift(xfer);
2097 temp.isoc_delta = 1U << shift;
2101 /* Compute isochronous scheduling threshold. */
2102 if (temp.sc->sc_ist & 8)
2103 y = (temp.sc->sc_ist & 7) << 3;
2105 y = (temp.sc->sc_ist & 7);
2107 /* Range check the IST. */
2110 } else if (y > 15) {
2111 DPRINTFN(3, "IST(%d) is too big!\n", temp.sc->sc_ist);
2113 * The USB stack minimum isochronous transfer
2114 * size is typically 2x2 ms of payload. If the
2115 * IST makes is above 15 microframes, we have
2116 * an effective scheduling delay of more than
2117 * or equal to 2 milliseconds, which is too
2123 * Subtract one millisecond, because the
2124 * generic code adds that to the latency.
2129 if (usbd_xfer_get_isochronous_start_frame(
2130 xfer, x, y, 8, XHCI_MFINDEX_GET(-1), &temp.isoc_frame)) {
2131 /* Start isochronous transfer at specified time. */
2132 temp.do_isoc_sync = 1;
2134 DPRINTFN(3, "start next=%d\n", temp.isoc_frame);
2138 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2140 } else if (xfer->flags_int.control_xfr) {
2141 /* check if we should prepend a setup message */
2143 if (xfer->flags_int.control_hdr) {
2144 temp.len = xfer->frlengths[0];
2145 temp.pc = xfer->frbuffers + 0;
2146 temp.shortpkt = temp.len ? 1 : 0;
2147 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2150 /* check for last frame */
2151 if (xfer->nframes == 1) {
2152 /* no STATUS stage yet, SETUP is last */
2153 if (xfer->flags_int.control_act)
2154 temp.last_frame = 1;
2157 xhci_setup_generic_chain_sub(&temp);
2161 temp.isoc_delta = 0;
2162 temp.isoc_frame = 0;
2163 temp.trb_type = xfer->flags_int.control_did_data ?
2164 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2168 temp.isoc_delta = 0;
2169 temp.isoc_frame = 0;
2170 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2173 if (x != xfer->nframes) {
2174 /* set up page_cache pointer */
2175 temp.pc = xfer->frbuffers + x;
2176 /* set endpoint direction */
2177 temp.direction = UE_GET_DIR(xfer->endpointno);
2180 while (x != xfer->nframes) {
2181 /* DATA0 / DATA1 message */
2183 temp.len = xfer->frlengths[x];
2184 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2185 x != 0 && temp.multishort == 0);
2189 if (x == xfer->nframes) {
2190 if (xfer->flags_int.control_xfr) {
2191 /* no STATUS stage yet, DATA is last */
2192 if (xfer->flags_int.control_act)
2193 temp.last_frame = 1;
2195 temp.last_frame = 1;
2198 if (temp.len == 0) {
2199 /* make sure that we send an USB packet */
2204 temp.tlbpc = mult - 1;
2206 } else if (xfer->flags_int.isochronous_xfr) {
2210 * Isochronous transfers don't have short
2211 * packet termination:
2216 /* isochronous transfers have a transfer limit */
2218 if (temp.len > xfer->max_frame_size)
2219 temp.len = xfer->max_frame_size;
2221 /* compute TD packet count */
2222 tdpc = howmany(temp.len, xfer->max_packet_size);
2224 temp.tbc = howmany(tdpc, mult) - 1;
2225 temp.tlbpc = (tdpc % mult);
2227 if (temp.tlbpc == 0)
2228 temp.tlbpc = mult - 1;
2232 /* regular data transfer */
2234 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2237 xhci_setup_generic_chain_sub(&temp);
2239 if (xfer->flags_int.isochronous_xfr) {
2240 temp.offset += xfer->frlengths[x - 1];
2241 temp.isoc_frame += temp.isoc_delta;
2243 /* get next Page Cache pointer */
2244 temp.pc = xfer->frbuffers + x;
2248 /* check if we should append a status stage */
2250 if (xfer->flags_int.control_xfr &&
2251 !xfer->flags_int.control_act) {
2253 * Send a DATA1 message and invert the current
2254 * endpoint direction.
2256 if (xhcictlstep || temp.sc->sc_ctlstep) {
2258 * Some XHCI controllers will not delay the
2259 * status stage until the next SOF. Force this
2260 * behaviour to avoid failed control
2263 temp.step_td = (xfer->nframes != 0);
2267 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2271 temp.last_frame = 1;
2272 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2274 xhci_setup_generic_chain_sub(&temp);
2279 /* must have at least one frame! */
2281 xfer->td_transfer_last = td;
2283 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2287 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2289 struct usb_page_search buf_res;
2290 struct xhci_dev_ctx_addr *pdctxa;
2292 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2294 pdctxa = buf_res.buffer;
2296 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2298 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2300 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2304 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2306 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2307 struct usb_page_search buf_inp;
2308 struct xhci_input_dev_ctx *pinp;
2313 index = udev->controller_slot_id;
2315 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2317 pinp = buf_inp.buffer;
2320 mask &= XHCI_INCTX_NON_CTRL_MASK;
2321 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2322 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2325 * Some hardware requires that we drop the endpoint
2326 * context before adding it again:
2328 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2329 mask & XHCI_INCTX_NON_CTRL_MASK);
2331 /* Add new endpoint context */
2332 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2334 /* find most significant set bit */
2335 for (x = 31; x != 1; x--) {
2336 if (mask & (1 << x))
2343 /* figure out the maximum number of contexts */
2344 if (x > sc->sc_hw.devs[index].context_num)
2345 sc->sc_hw.devs[index].context_num = x;
2347 x = sc->sc_hw.devs[index].context_num;
2349 /* update number of contexts */
2350 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2351 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2352 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2353 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2355 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2360 xhci_configure_endpoint(struct usb_device *udev,
2361 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2362 uint16_t interval, uint8_t max_packet_count,
2363 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2364 uint16_t max_frame_size, uint8_t ep_mode)
2366 struct usb_page_search buf_inp;
2367 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2368 struct xhci_input_dev_ctx *pinp;
2369 uint64_t ring_addr = pepext->physaddr;
2375 index = udev->controller_slot_id;
2377 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2379 pinp = buf_inp.buffer;
2381 epno = edesc->bEndpointAddress;
2382 type = edesc->bmAttributes & UE_XFERTYPE;
2384 if (type == UE_CONTROL)
2387 epno = XHCI_EPNO2EPID(epno);
2390 return (USB_ERR_NO_PIPE); /* invalid */
2392 if (max_packet_count == 0)
2393 return (USB_ERR_BAD_BUFSIZE);
2398 return (USB_ERR_BAD_BUFSIZE);
2400 /* store endpoint mode */
2401 pepext->trb_ep_mode = ep_mode;
2402 /* store bMaxPacketSize for control endpoints */
2403 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2404 usb_pc_cpu_flush(pepext->page_cache);
2406 if (ep_mode == USB_EP_MODE_STREAMS) {
2407 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2408 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2409 XHCI_EPCTX_0_LSA_SET(1);
2411 ring_addr += sizeof(struct xhci_trb) *
2412 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2414 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2415 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2416 XHCI_EPCTX_0_LSA_SET(0);
2418 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2421 switch (udev->speed) {
2422 case USB_SPEED_FULL:
2435 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2437 case UE_ISOCHRONOUS:
2438 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2440 switch (udev->speed) {
2441 case USB_SPEED_SUPER:
2444 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2445 max_packet_count /= mult;
2455 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2458 XHCI_EPCTX_1_HID_SET(0) |
2459 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2460 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2463 * Always enable the "three strikes and you are gone" feature
2464 * except for ISOCHRONOUS endpoints. This is suggested by
2465 * section 4.3.3 in the XHCI specification about device slot
2468 if (type != UE_ISOCHRONOUS)
2469 temp |= XHCI_EPCTX_1_CERR_SET(3);
2473 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2475 case UE_ISOCHRONOUS:
2476 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2479 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2482 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2486 /* check for IN direction */
2488 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2490 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2491 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2493 switch (edesc->bmAttributes & UE_XFERTYPE) {
2495 case UE_ISOCHRONOUS:
2496 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2497 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2501 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2504 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2508 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2511 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2513 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2515 return (0); /* success */
2519 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2521 struct xhci_endpoint_ext *pepext;
2522 struct usb_endpoint_ss_comp_descriptor *ecomp;
2525 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2526 xfer->endpoint->edesc);
2528 ecomp = xfer->endpoint->ecomp;
2530 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2533 /* halt any transfers */
2534 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2536 /* compute start of TRB ring for stream "x" */
2537 temp = pepext->physaddr +
2538 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2539 XHCI_SCTX_0_SCT_SEC_TR_RING;
2541 /* make tree structure */
2542 pepext->trb[(XHCI_MAX_TRANSFERS *
2543 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2545 /* reserved fields */
2546 pepext->trb[(XHCI_MAX_TRANSFERS *
2547 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2548 pepext->trb[(XHCI_MAX_TRANSFERS *
2549 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2551 usb_pc_cpu_flush(pepext->page_cache);
2553 return (xhci_configure_endpoint(xfer->xroot->udev,
2554 xfer->endpoint->edesc, pepext,
2555 xfer->interval, xfer->max_packet_count,
2556 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2557 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2558 xfer->max_frame_size, xfer->endpoint->ep_mode));
2562 xhci_configure_device(struct usb_device *udev)
2564 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2565 struct usb_page_search buf_inp;
2566 struct usb_page_cache *pcinp;
2567 struct xhci_input_dev_ctx *pinp;
2568 struct usb_device *hubdev;
2576 index = udev->controller_slot_id;
2578 DPRINTF("index=%u\n", index);
2580 pcinp = &sc->sc_hw.devs[index].input_pc;
2582 usbd_get_page(pcinp, 0, &buf_inp);
2584 pinp = buf_inp.buffer;
2589 /* figure out route string and root HUB port number */
2591 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2592 if (hubdev->parent_hub == NULL)
2595 depth = hubdev->parent_hub->depth;
2598 * NOTE: HS/FS/LS devices and the SS root HUB can have
2599 * more than 15 ports
2602 rh_port = hubdev->port_no;
2611 route |= rh_port << (4 * (depth - 1));
2614 DPRINTF("Route=0x%08x\n", route);
2616 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2617 XHCI_SCTX_0_CTX_NUM_SET(
2618 sc->sc_hw.devs[index].context_num + 1);
2620 switch (udev->speed) {
2622 temp |= XHCI_SCTX_0_SPEED_SET(2);
2623 if (udev->parent_hs_hub != NULL &&
2624 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2626 DPRINTF("Device inherits MTT\n");
2627 temp |= XHCI_SCTX_0_MTT_SET(1);
2630 case USB_SPEED_HIGH:
2631 temp |= XHCI_SCTX_0_SPEED_SET(3);
2632 if (sc->sc_hw.devs[index].nports != 0 &&
2633 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2634 DPRINTF("HUB supports MTT\n");
2635 temp |= XHCI_SCTX_0_MTT_SET(1);
2638 case USB_SPEED_FULL:
2639 temp |= XHCI_SCTX_0_SPEED_SET(1);
2640 if (udev->parent_hs_hub != NULL &&
2641 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2643 DPRINTF("Device inherits MTT\n");
2644 temp |= XHCI_SCTX_0_MTT_SET(1);
2648 temp |= XHCI_SCTX_0_SPEED_SET(4);
2652 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2653 (udev->speed == USB_SPEED_SUPER ||
2654 udev->speed == USB_SPEED_HIGH);
2657 temp |= XHCI_SCTX_0_HUB_SET(1);
2659 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2661 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2664 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2665 sc->sc_hw.devs[index].nports);
2668 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2670 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2673 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2674 sc->sc_hw.devs[index].tt);
2677 hubdev = udev->parent_hs_hub;
2679 /* check if we should activate the transaction translator */
2680 switch (udev->speed) {
2681 case USB_SPEED_FULL:
2683 if (hubdev != NULL) {
2684 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2685 hubdev->controller_slot_id);
2686 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2694 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2697 * These fields should be initialized to zero, according to
2698 * XHCI section 6.2.2 - slot context:
2700 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2701 XHCI_SCTX_3_SLOT_STATE_SET(0);
2703 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2706 xhci_dump_device(sc, &pinp->ctx_slot);
2708 usb_pc_cpu_flush(pcinp);
2710 return (0); /* success */
2714 xhci_alloc_device_ext(struct usb_device *udev)
2716 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2717 struct usb_page_search buf_dev;
2718 struct usb_page_search buf_ep;
2719 struct xhci_trb *trb;
2720 struct usb_page_cache *pc;
2721 struct usb_page *pg;
2726 index = udev->controller_slot_id;
2728 pc = &sc->sc_hw.devs[index].device_pc;
2729 pg = &sc->sc_hw.devs[index].device_pg;
2731 /* need to initialize the page cache */
2732 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2734 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2735 (2 * sizeof(struct xhci_dev_ctx)) :
2736 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2739 usbd_get_page(pc, 0, &buf_dev);
2741 pc = &sc->sc_hw.devs[index].input_pc;
2742 pg = &sc->sc_hw.devs[index].input_pg;
2744 /* need to initialize the page cache */
2745 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2747 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2748 (2 * sizeof(struct xhci_input_dev_ctx)) :
2749 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2753 /* initialize all endpoint LINK TRBs */
2755 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2756 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2757 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2759 /* need to initialize the page cache */
2760 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2762 if (usb_pc_alloc_mem(pc, pg,
2763 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2767 /* lookup endpoint TRB ring */
2768 usbd_get_page(pc, 0, &buf_ep);
2770 /* get TRB pointer */
2771 trb = buf_ep.buffer;
2772 trb += XHCI_MAX_TRANSFERS - 1;
2774 /* get TRB start address */
2775 addr = buf_ep.physaddr;
2777 /* create LINK TRB */
2778 trb->qwTrb0 = htole64(addr);
2779 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2780 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2781 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2783 usb_pc_cpu_flush(pc);
2786 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2791 xhci_free_device_ext(udev);
2793 return (USB_ERR_NOMEM);
2797 xhci_free_device_ext(struct usb_device *udev)
2799 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2803 index = udev->controller_slot_id;
2804 xhci_set_slot_pointer(sc, index, 0);
2806 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2807 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2808 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2809 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2812 static struct xhci_endpoint_ext *
2813 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2815 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2816 struct xhci_endpoint_ext *pepext;
2817 struct usb_page_cache *pc;
2818 struct usb_page_search buf_ep;
2822 epno = edesc->bEndpointAddress;
2823 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2826 epno = XHCI_EPNO2EPID(epno);
2828 index = udev->controller_slot_id;
2830 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2832 usbd_get_page(pc, 0, &buf_ep);
2834 pepext = &sc->sc_hw.devs[index].endp[epno];
2835 pepext->page_cache = pc;
2836 pepext->trb = buf_ep.buffer;
2837 pepext->physaddr = buf_ep.physaddr;
2843 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2845 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2849 epno = xfer->endpointno;
2850 if (xfer->flags_int.control_xfr)
2853 epno = XHCI_EPNO2EPID(epno);
2854 index = xfer->xroot->udev->controller_slot_id;
2856 if (xfer->xroot->udev->flags.self_suspended == 0) {
2857 XWRITE4(sc, door, XHCI_DOORBELL(index),
2858 epno | XHCI_DB_SID_SET(xfer->stream_id));
2863 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2865 struct xhci_endpoint_ext *pepext;
2867 if (xfer->flags_int.bandwidth_reclaimed) {
2868 xfer->flags_int.bandwidth_reclaimed = 0;
2870 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2871 xfer->endpoint->edesc);
2873 pepext->trb_used[xfer->stream_id]--;
2875 pepext->xfer[xfer->qh_pos] = NULL;
2877 if (error && pepext->trb_running != 0) {
2878 pepext->trb_halted = 1;
2879 pepext->trb_running = 0;
2885 xhci_transfer_insert(struct usb_xfer *xfer)
2887 struct xhci_td *td_first;
2888 struct xhci_td *td_last;
2889 struct xhci_trb *trb_link;
2890 struct xhci_endpoint_ext *pepext;
2899 id = xfer->stream_id;
2901 /* check if already inserted */
2902 if (xfer->flags_int.bandwidth_reclaimed) {
2903 DPRINTFN(8, "Already in schedule\n");
2907 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2908 xfer->endpoint->edesc);
2910 td_first = xfer->td_transfer_first;
2911 td_last = xfer->td_transfer_last;
2912 addr = pepext->physaddr;
2914 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2917 /* single buffered */
2921 /* multi buffered */
2922 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2926 if (pepext->trb_used[id] >= trb_limit) {
2927 DPRINTFN(8, "Too many TDs queued.\n");
2928 return (USB_ERR_NOMEM);
2931 /* check if bMaxPacketSize changed */
2932 if (xfer->flags_int.control_xfr != 0 &&
2933 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2934 DPRINTFN(8, "Reconfigure control endpoint\n");
2936 /* force driver to reconfigure endpoint */
2937 pepext->trb_halted = 1;
2938 pepext->trb_running = 0;
2941 /* check for stopped condition, after putting transfer on interrupt queue */
2942 if (pepext->trb_running == 0) {
2943 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2945 DPRINTFN(8, "Not running\n");
2947 /* start configuration */
2948 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2949 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2953 pepext->trb_used[id]++;
2955 /* get current TRB index */
2956 i = pepext->trb_index[id];
2958 /* get next TRB index */
2961 /* the last entry of the ring is a hardcoded link TRB */
2962 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2965 /* store next TRB index, before stream ID offset is added */
2966 pepext->trb_index[id] = inext;
2968 /* offset for stream */
2969 i += id * XHCI_MAX_TRANSFERS;
2970 inext += id * XHCI_MAX_TRANSFERS;
2972 /* compute terminating return address */
2973 addr += (inext * sizeof(struct xhci_trb));
2975 /* compute link TRB pointer */
2976 trb_link = td_last->td_trb + td_last->ntrb;
2978 /* update next pointer of last link TRB */
2979 trb_link->qwTrb0 = htole64(addr);
2980 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2981 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2982 XHCI_TRB_3_CYCLE_BIT |
2983 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2986 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2988 usb_pc_cpu_flush(td_last->page_cache);
2990 /* write ahead chain end marker */
2992 pepext->trb[inext].qwTrb0 = 0;
2993 pepext->trb[inext].dwTrb2 = 0;
2994 pepext->trb[inext].dwTrb3 = 0;
2996 /* update next pointer of link TRB */
2998 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2999 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3002 xhci_dump_trb(&pepext->trb[i]);
3004 usb_pc_cpu_flush(pepext->page_cache);
3006 /* toggle cycle bit which activates the transfer chain */
3008 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3009 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3011 usb_pc_cpu_flush(pepext->page_cache);
3013 DPRINTF("qh_pos = %u\n", i);
3015 pepext->xfer[i] = xfer;
3019 xfer->flags_int.bandwidth_reclaimed = 1;
3021 xhci_endpoint_doorbell(xfer);
3027 xhci_root_intr(struct xhci_softc *sc)
3031 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3033 /* clear any old interrupt data */
3034 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3036 for (i = 1; i <= sc->sc_noport; i++) {
3037 /* pick out CHANGE bits from the status register */
3038 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3039 XHCI_PS_CSC | XHCI_PS_PEC |
3040 XHCI_PS_OCC | XHCI_PS_WRC |
3041 XHCI_PS_PRC | XHCI_PS_PLC |
3043 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3044 DPRINTF("port %d changed\n", i);
3047 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3048 sizeof(sc->sc_hub_idata));
3051 /*------------------------------------------------------------------------*
3052 * xhci_device_done - XHCI done handler
3054 * NOTE: This function can be called two times in a row on
3055 * the same USB transfer. From close and from interrupt.
3056 *------------------------------------------------------------------------*/
3058 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3060 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3061 xfer, xfer->endpoint, error);
3063 /* remove transfer from HW queue */
3064 xhci_transfer_remove(xfer, error);
3066 /* dequeue transfer and start next transfer */
3067 usbd_transfer_done(xfer, error);
3070 /*------------------------------------------------------------------------*
3071 * XHCI data transfer support (generic type)
3072 *------------------------------------------------------------------------*/
3074 xhci_device_generic_open(struct usb_xfer *xfer)
3080 xhci_device_generic_close(struct usb_xfer *xfer)
3084 xhci_device_done(xfer, USB_ERR_CANCELLED);
3088 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3089 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3091 struct usb_xfer *xfer;
3093 /* check if there is a current transfer */
3094 xfer = ep->endpoint_q[stream_id].curr;
3099 * Check if the current transfer is started and then pickup
3100 * the next one, if any. Else wait for next start event due to
3101 * block on failure feature.
3103 if (!xfer->flags_int.bandwidth_reclaimed)
3106 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3109 * In case of enter we have to consider that the
3110 * transfer is queued by the USB core after the enter
3119 /* try to multi buffer */
3120 xhci_transfer_insert(xfer);
3124 xhci_device_generic_enter(struct usb_xfer *xfer)
3128 /* set up TD's and QH */
3129 xhci_setup_generic_chain(xfer);
3131 xhci_device_generic_multi_enter(xfer->endpoint,
3132 xfer->stream_id, xfer);
3136 xhci_device_generic_start(struct usb_xfer *xfer)
3140 /* try to insert xfer on HW queue */
3141 xhci_transfer_insert(xfer);
3143 /* try to multi buffer */
3144 xhci_device_generic_multi_enter(xfer->endpoint,
3145 xfer->stream_id, NULL);
3147 /* add transfer last on interrupt queue */
3148 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3150 /* start timeout, if any */
3151 if (xfer->timeout != 0)
3152 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3155 static const struct usb_pipe_methods xhci_device_generic_methods =
3157 .open = xhci_device_generic_open,
3158 .close = xhci_device_generic_close,
3159 .enter = xhci_device_generic_enter,
3160 .start = xhci_device_generic_start,
3163 /*------------------------------------------------------------------------*
3164 * xhci root HUB support
3165 *------------------------------------------------------------------------*
3166 * Simulate a hardware HUB by handling all the necessary requests.
3167 *------------------------------------------------------------------------*/
3168 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3171 struct usb_device_descriptor xhci_devd =
3173 .bLength = sizeof(xhci_devd),
3174 .bDescriptorType = UDESC_DEVICE, /* type */
3175 HSETW(.bcdUSB, 0x0300), /* USB version */
3176 .bDeviceClass = UDCLASS_HUB, /* class */
3177 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3178 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3179 .bMaxPacketSize = 9, /* max packet size */
3180 HSETW(.idVendor, 0x0000), /* vendor */
3181 HSETW(.idProduct, 0x0000), /* product */
3182 HSETW(.bcdDevice, 0x0100), /* device version */
3186 .bNumConfigurations = 1, /* # of configurations */
3190 struct xhci_bos_desc xhci_bosd = {
3192 .bLength = sizeof(xhci_bosd.bosd),
3193 .bDescriptorType = UDESC_BOS,
3194 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3195 .bNumDeviceCaps = 3,
3198 .bLength = sizeof(xhci_bosd.usb2extd),
3199 .bDescriptorType = 1,
3200 .bDevCapabilityType = 2,
3201 .bmAttributes[0] = 2,
3204 .bLength = sizeof(xhci_bosd.usbdcd),
3205 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3206 .bDevCapabilityType = 3,
3207 .bmAttributes = 0, /* XXX */
3208 HSETW(.wSpeedsSupported, 0x000C),
3209 .bFunctionalitySupport = 8,
3210 .bU1DevExitLat = 255, /* dummy - not used */
3211 .wU2DevExitLat = { 0x00, 0x08 },
3214 .bLength = sizeof(xhci_bosd.cidd),
3215 .bDescriptorType = 1,
3216 .bDevCapabilityType = 4,
3218 .bContainerID = 0, /* XXX */
3223 struct xhci_config_desc xhci_confd = {
3225 .bLength = sizeof(xhci_confd.confd),
3226 .bDescriptorType = UDESC_CONFIG,
3227 .wTotalLength[0] = sizeof(xhci_confd),
3229 .bConfigurationValue = 1,
3230 .iConfiguration = 0,
3231 .bmAttributes = UC_SELF_POWERED,
3232 .bMaxPower = 0 /* max power */
3235 .bLength = sizeof(xhci_confd.ifcd),
3236 .bDescriptorType = UDESC_INTERFACE,
3238 .bInterfaceClass = UICLASS_HUB,
3239 .bInterfaceSubClass = UISUBCLASS_HUB,
3240 .bInterfaceProtocol = 0,
3243 .bLength = sizeof(xhci_confd.endpd),
3244 .bDescriptorType = UDESC_ENDPOINT,
3245 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3246 .bmAttributes = UE_INTERRUPT,
3247 .wMaxPacketSize[0] = 2, /* max 15 ports */
3251 .bLength = sizeof(xhci_confd.endpcd),
3252 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3259 struct usb_hub_ss_descriptor xhci_hubd = {
3260 .bLength = sizeof(xhci_hubd),
3261 .bDescriptorType = UDESC_SS_HUB,
3265 xhci_roothub_exec(struct usb_device *udev,
3266 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3268 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3269 const char *str_ptr;
3280 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3283 ptr = (const void *)&sc->sc_hub_desc;
3287 value = UGETW(req->wValue);
3288 index = UGETW(req->wIndex);
3290 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3291 "wValue=0x%04x wIndex=0x%04x\n",
3292 req->bmRequestType, req->bRequest,
3293 UGETW(req->wLength), value, index);
3295 #define C(x,y) ((x) | ((y) << 8))
3296 switch (C(req->bRequest, req->bmRequestType)) {
3297 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3298 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3299 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3301 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3302 * for the integrated root hub.
3305 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3307 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3309 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3310 switch (value >> 8) {
3312 if ((value & 0xff) != 0) {
3313 err = USB_ERR_IOERROR;
3316 len = sizeof(xhci_devd);
3317 ptr = (const void *)&xhci_devd;
3321 if ((value & 0xff) != 0) {
3322 err = USB_ERR_IOERROR;
3325 len = sizeof(xhci_bosd);
3326 ptr = (const void *)&xhci_bosd;
3330 if ((value & 0xff) != 0) {
3331 err = USB_ERR_IOERROR;
3334 len = sizeof(xhci_confd);
3335 ptr = (const void *)&xhci_confd;
3339 switch (value & 0xff) {
3340 case 0: /* Language table */
3344 case 1: /* Vendor */
3345 str_ptr = sc->sc_vendor;
3348 case 2: /* Product */
3349 str_ptr = "XHCI root HUB";
3357 len = usb_make_str_desc(
3358 sc->sc_hub_desc.temp,
3359 sizeof(sc->sc_hub_desc.temp),
3364 err = USB_ERR_IOERROR;
3368 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3370 sc->sc_hub_desc.temp[0] = 0;
3372 case C(UR_GET_STATUS, UT_READ_DEVICE):
3374 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3376 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3377 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3379 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3381 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3382 if (value >= XHCI_MAX_DEVICES) {
3383 err = USB_ERR_IOERROR;
3387 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3388 if (value != 0 && value != 1) {
3389 err = USB_ERR_IOERROR;
3392 sc->sc_conf = value;
3394 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3396 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3397 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3398 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3399 err = USB_ERR_IOERROR;
3401 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3403 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3406 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3408 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3409 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3412 (index > sc->sc_noport)) {
3413 err = USB_ERR_IOERROR;
3416 port = XHCI_PORTSC(index);
3418 v = XREAD4(sc, oper, port);
3419 i = XHCI_PS_PLS_GET(v);
3420 v &= ~XHCI_PS_CLEAR;
3423 case UHF_C_BH_PORT_RESET:
3424 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3426 case UHF_C_PORT_CONFIG_ERROR:
3427 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3429 case UHF_C_PORT_SUSPEND:
3430 case UHF_C_PORT_LINK_STATE:
3431 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3433 case UHF_C_PORT_CONNECTION:
3434 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3436 case UHF_C_PORT_ENABLE:
3437 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3439 case UHF_C_PORT_OVER_CURRENT:
3440 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3442 case UHF_C_PORT_RESET:
3443 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3445 case UHF_PORT_ENABLE:
3446 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3448 case UHF_PORT_POWER:
3449 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3451 case UHF_PORT_INDICATOR:
3452 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3454 case UHF_PORT_SUSPEND:
3458 XWRITE4(sc, oper, port, v |
3459 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3462 /* wait 20ms for resume sequence to complete */
3463 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3466 XWRITE4(sc, oper, port, v |
3467 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3470 err = USB_ERR_IOERROR;
3475 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3476 if ((value & 0xff) != 0) {
3477 err = USB_ERR_IOERROR;
3481 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3483 sc->sc_hub_desc.hubd = xhci_hubd;
3485 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3487 if (XHCI_HCS0_PPC(v))
3488 i = UHD_PWR_INDIVIDUAL;
3492 if (XHCI_HCS0_PIND(v))
3495 i |= UHD_OC_INDIVIDUAL;
3497 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3499 /* see XHCI section 5.4.9: */
3500 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3502 for (j = 1; j <= sc->sc_noport; j++) {
3503 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3504 if (v & XHCI_PS_DR) {
3505 sc->sc_hub_desc.hubd.
3506 DeviceRemovable[j / 8] |= 1U << (j % 8);
3509 len = sc->sc_hub_desc.hubd.bLength;
3512 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3514 memset(sc->sc_hub_desc.temp, 0, 16);
3517 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3518 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3521 (index > sc->sc_noport)) {
3522 err = USB_ERR_IOERROR;
3526 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3528 DPRINTFN(9, "port status=0x%08x\n", v);
3530 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3532 switch (XHCI_PS_SPEED_GET(v)) {
3534 i |= UPS_HIGH_SPEED;
3543 i |= UPS_OTHER_SPEED;
3547 if (v & XHCI_PS_CCS)
3548 i |= UPS_CURRENT_CONNECT_STATUS;
3549 if (v & XHCI_PS_PED)
3550 i |= UPS_PORT_ENABLED;
3551 if (v & XHCI_PS_OCA)
3552 i |= UPS_OVERCURRENT_INDICATOR;
3559 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3562 if (v & XHCI_PS_CSC)
3563 i |= UPS_C_CONNECT_STATUS;
3564 if (v & XHCI_PS_PEC)
3565 i |= UPS_C_PORT_ENABLED;
3566 if (v & XHCI_PS_OCC)
3567 i |= UPS_C_OVERCURRENT_INDICATOR;
3568 if (v & XHCI_PS_WRC)
3569 i |= UPS_C_BH_PORT_RESET;
3570 if (v & XHCI_PS_PRC)
3571 i |= UPS_C_PORT_RESET;
3572 if (v & XHCI_PS_PLC)
3573 i |= UPS_C_PORT_LINK_STATE;
3574 if (v & XHCI_PS_CEC)
3575 i |= UPS_C_PORT_CONFIG_ERROR;
3577 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3578 len = sizeof(sc->sc_hub_desc.ps);
3581 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3582 err = USB_ERR_IOERROR;
3585 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3588 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3594 (index > sc->sc_noport)) {
3595 err = USB_ERR_IOERROR;
3599 port = XHCI_PORTSC(index);
3600 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3603 case UHF_PORT_U1_TIMEOUT:
3604 if (XHCI_PS_SPEED_GET(v) != 4) {
3605 err = USB_ERR_IOERROR;
3608 port = XHCI_PORTPMSC(index);
3609 v = XREAD4(sc, oper, port);
3610 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3611 v |= XHCI_PM3_U1TO_SET(i);
3612 XWRITE4(sc, oper, port, v);
3614 case UHF_PORT_U2_TIMEOUT:
3615 if (XHCI_PS_SPEED_GET(v) != 4) {
3616 err = USB_ERR_IOERROR;
3619 port = XHCI_PORTPMSC(index);
3620 v = XREAD4(sc, oper, port);
3621 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3622 v |= XHCI_PM3_U2TO_SET(i);
3623 XWRITE4(sc, oper, port, v);
3625 case UHF_BH_PORT_RESET:
3626 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3628 case UHF_PORT_LINK_STATE:
3629 XWRITE4(sc, oper, port, v |
3630 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3631 /* 4ms settle time */
3632 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3634 case UHF_PORT_ENABLE:
3635 DPRINTFN(3, "set port enable %d\n", index);
3637 case UHF_PORT_SUSPEND:
3638 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3639 j = XHCI_PS_SPEED_GET(v);
3640 if ((j < 1) || (j > 3)) {
3641 /* non-supported speed */
3642 err = USB_ERR_IOERROR;
3645 XWRITE4(sc, oper, port, v |
3646 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3648 case UHF_PORT_RESET:
3649 DPRINTFN(6, "reset port %d\n", index);
3650 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3652 case UHF_PORT_POWER:
3653 DPRINTFN(3, "set port power %d\n", index);
3654 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3657 DPRINTFN(3, "set port test %d\n", index);
3659 case UHF_PORT_INDICATOR:
3660 DPRINTFN(3, "set port indicator %d\n", index);
3662 v &= ~XHCI_PS_PIC_SET(3);
3663 v |= XHCI_PS_PIC_SET(1);
3665 XWRITE4(sc, oper, port, v);
3668 err = USB_ERR_IOERROR;
3673 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3674 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3675 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3676 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3679 err = USB_ERR_IOERROR;
3689 xhci_xfer_setup(struct usb_setup_params *parm)
3691 struct usb_page_search page_info;
3692 struct usb_page_cache *pc;
3693 struct usb_xfer *xfer;
3698 xfer = parm->curr_xfer;
3701 * The proof for the "ntd" formula is illustrated like this:
3703 * +------------------------------------+
3707 * | | xxx | x | frm 0 |
3709 * | | xxx | xx | frm 1 |
3712 * +------------------------------------+
3714 * "xxx" means a completely full USB transfer descriptor
3716 * "x" and "xx" means a short USB packet
3718 * For the remainder of an USB transfer modulo
3719 * "max_data_length" we need two USB transfer descriptors.
3720 * One to transfer the remaining data and one to finalise with
3721 * a zero length packet in case the "force_short_xfer" flag is
3722 * set. We only need two USB transfer descriptors in the case
3723 * where the transfer length of the first one is a factor of
3724 * "max_frame_size". The rest of the needed USB transfer
3725 * descriptors is given by the buffer size divided by the
3726 * maximum data payload.
3728 parm->hc_max_packet_size = 0x400;
3729 parm->hc_max_packet_count = 16 * 3;
3730 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3732 xfer->flags_int.bdma_enable = 1;
3734 usbd_transfer_setup_sub(parm);
3736 if (xfer->flags_int.isochronous_xfr) {
3737 ntd = ((1 * xfer->nframes)
3738 + (xfer->max_data_length / xfer->max_hc_frame_size));
3739 } else if (xfer->flags_int.control_xfr) {
3740 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3741 + (xfer->max_data_length / xfer->max_hc_frame_size));
3743 ntd = ((2 * xfer->nframes)
3744 + (xfer->max_data_length / xfer->max_hc_frame_size));
3753 * Allocate queue heads and transfer descriptors
3757 if (usbd_transfer_setup_sub_malloc(
3758 parm, &pc, sizeof(struct xhci_td),
3759 XHCI_TD_ALIGN, ntd)) {
3760 parm->err = USB_ERR_NOMEM;
3764 for (n = 0; n != ntd; n++) {
3767 usbd_get_page(pc + n, 0, &page_info);
3769 td = page_info.buffer;
3772 td->td_self = page_info.physaddr;
3773 td->obj_next = last_obj;
3774 td->page_cache = pc + n;
3778 usb_pc_cpu_flush(pc + n);
3781 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3783 if (!xfer->flags_int.curr_dma_set) {
3784 xfer->flags_int.curr_dma_set = 1;
3790 xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno)
3792 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3793 struct usb_page_search buf_dev;
3794 struct xhci_hw_dev *hdev;
3795 struct xhci_dev_ctx *pdev;
3800 hdev = &sc->sc_hw.devs[udev->controller_slot_id];
3802 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
3803 pdev = buf_dev.buffer;
3804 usb_pc_cpu_invalidate(&hdev->device_pc);
3806 temp = xhci_ctx_get_le32(sc, &pdev->ctx_ep[epno - 1].dwEpCtx0);
3808 return (XHCI_EPCTX_0_EPSTATE_GET(temp));
3812 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3814 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3815 struct usb_page_search buf_inp;
3816 struct usb_device *udev;
3817 struct xhci_endpoint_ext *pepext;
3818 struct usb_endpoint_descriptor *edesc;
3819 struct usb_page_cache *pcinp;
3821 usb_stream_t stream_id;
3827 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3828 xfer->endpoint->edesc);
3830 udev = xfer->xroot->udev;
3831 index = udev->controller_slot_id;
3833 pcinp = &sc->sc_hw.devs[index].input_pc;
3835 usbd_get_page(pcinp, 0, &buf_inp);
3837 edesc = xfer->endpoint->edesc;
3839 epno = edesc->bEndpointAddress;
3840 stream_id = xfer->stream_id;
3842 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3845 epno = XHCI_EPNO2EPID(epno);
3848 return (USB_ERR_NO_PIPE); /* invalid */
3852 /* configure endpoint */
3854 err = xhci_configure_endpoint_by_xfer(xfer);
3857 XHCI_CMD_UNLOCK(sc);
3862 * Get the endpoint into the stopped state according to the
3863 * endpoint context state diagram in the XHCI specification:
3865 switch (xhci_get_endpoint_state(udev, epno)) {
3866 case XHCI_EPCTX_0_EPSTATE_DISABLED:
3869 case XHCI_EPCTX_0_EPSTATE_STOPPED:
3872 case XHCI_EPCTX_0_EPSTATE_HALTED:
3873 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3876 DPRINTF("Could not reset endpoint %u\n", epno);
3880 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3882 DPRINTF("Could not stop endpoint %u\n", epno);
3886 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3887 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3888 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3889 stream_id, epno, index);
3892 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3895 * Get the endpoint into the running state according to the
3896 * endpoint context state diagram in the XHCI specification:
3899 mask = (1U << epno);
3902 * So-called control and isochronous transfer types have
3903 * predefined data toggles (USB 2.0) or sequence numbers (USB
3904 * 3.0) and does not need to be dropped.
3907 (edesc->bmAttributes & UE_XFERTYPE) != UE_CONTROL &&
3908 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) {
3909 /* drop endpoint context to reset data toggle value, if any. */
3910 xhci_configure_mask(udev, mask, 1);
3911 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3913 DPRINTF("Could not drop "
3914 "endpoint %u at slot %u.\n", epno, index);
3916 sc->sc_hw.devs[index].ep_configured &= ~mask;
3920 xhci_configure_mask(udev, mask, 0);
3922 if (!(sc->sc_hw.devs[index].ep_configured & mask)) {
3923 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3925 sc->sc_hw.devs[index].ep_configured |= mask;
3927 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3931 DPRINTF("Could not configure "
3932 "endpoint %u at slot %u.\n", epno, index);
3934 XHCI_CMD_UNLOCK(sc);
3940 xhci_xfer_unsetup(struct usb_xfer *xfer)
3946 xhci_start_dma_delay(struct usb_xfer *xfer)
3948 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3950 /* put transfer on interrupt queue (again) */
3951 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3953 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3954 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3958 xhci_configure_msg(struct usb_proc_msg *pm)
3960 struct xhci_softc *sc;
3961 struct xhci_endpoint_ext *pepext;
3962 struct usb_xfer *xfer;
3964 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3967 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3968 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3969 xfer->endpoint->edesc);
3971 if ((pepext->trb_halted != 0) ||
3972 (pepext->trb_running == 0)) {
3975 /* clear halted and running */
3976 pepext->trb_halted = 0;
3977 pepext->trb_running = 0;
3979 /* nuke remaining buffered transfers */
3981 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3982 XHCI_MAX_STREAMS); i++) {
3984 * NOTE: We need to use the timeout
3985 * error code here else existing
3986 * isochronous clients can get
3989 if (pepext->xfer[i] != NULL) {
3990 xhci_device_done(pepext->xfer[i],
3996 * NOTE: The USB transfer cannot vanish in
4000 USB_BUS_UNLOCK(&sc->sc_bus);
4002 xhci_configure_reset_endpoint(xfer);
4004 USB_BUS_LOCK(&sc->sc_bus);
4006 /* check if halted is still cleared */
4007 if (pepext->trb_halted == 0) {
4008 pepext->trb_running = 1;
4009 memset(pepext->trb_index, 0,
4010 sizeof(pepext->trb_index));
4015 if (xfer->flags_int.did_dma_delay) {
4016 /* remove transfer from interrupt queue (again) */
4017 usbd_transfer_dequeue(xfer);
4019 /* we are finally done */
4020 usb_dma_delay_done_cb(xfer);
4022 /* queue changed - restart */
4027 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4028 /* try to insert xfer on HW queue */
4029 xhci_transfer_insert(xfer);
4031 /* try to multi buffer */
4032 xhci_device_generic_multi_enter(xfer->endpoint,
4033 xfer->stream_id, NULL);
4038 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4039 struct usb_endpoint *ep)
4041 struct xhci_endpoint_ext *pepext;
4042 struct xhci_softc *sc;
4046 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4047 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4049 if (udev->parent_hub == NULL) {
4050 /* root HUB has special endpoint handling */
4054 ep->methods = &xhci_device_generic_methods;
4056 pepext = xhci_get_endpoint_ext(udev, edesc);
4058 USB_BUS_LOCK(udev->bus);
4059 pepext->trb_halted = 1;
4060 pepext->trb_running = 0;
4063 * When doing an alternate setting, except for control
4064 * endpoints, we need to re-configure the XHCI endpoint
4067 if ((edesc->bEndpointAddress & UE_ADDR) != 0) {
4068 sc = XHCI_BUS2SC(udev->bus);
4069 index = udev->controller_slot_id;
4070 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress);
4071 sc->sc_hw.devs[index].ep_configured &= ~(1U << epno);
4073 USB_BUS_UNLOCK(udev->bus);
4077 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4083 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4085 struct xhci_endpoint_ext *pepext;
4089 if (udev->flags.usb_mode != USB_MODE_HOST) {
4093 if (udev->parent_hub == NULL) {
4094 /* root HUB has special endpoint handling */
4098 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4100 USB_BUS_LOCK(udev->bus);
4101 pepext->trb_halted = 1;
4102 pepext->trb_running = 0;
4103 USB_BUS_UNLOCK(udev->bus);
4107 xhci_device_init(struct usb_device *udev)
4109 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4113 /* no init for root HUB */
4114 if (udev->parent_hub == NULL)
4119 /* set invalid default */
4121 udev->controller_slot_id = sc->sc_noslot + 1;
4123 /* try to get a new slot ID from the XHCI */
4125 err = xhci_cmd_enable_slot(sc, &temp);
4128 XHCI_CMD_UNLOCK(sc);
4132 if (temp > sc->sc_noslot) {
4133 XHCI_CMD_UNLOCK(sc);
4134 return (USB_ERR_BAD_ADDRESS);
4137 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4138 DPRINTF("slot %u already allocated.\n", temp);
4139 XHCI_CMD_UNLOCK(sc);
4140 return (USB_ERR_BAD_ADDRESS);
4143 /* store slot ID for later reference */
4145 udev->controller_slot_id = temp;
4147 /* reset data structure */
4149 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4151 /* set mark slot allocated */
4153 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4155 err = xhci_alloc_device_ext(udev);
4157 XHCI_CMD_UNLOCK(sc);
4159 /* get device into default state */
4162 err = xhci_set_address(udev, NULL, 0);
4168 xhci_device_uninit(struct usb_device *udev)
4170 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4173 /* no init for root HUB */
4174 if (udev->parent_hub == NULL)
4179 index = udev->controller_slot_id;
4181 if (index <= sc->sc_noslot) {
4182 xhci_cmd_disable_slot(sc, index);
4183 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4185 /* free device extension */
4186 xhci_free_device_ext(udev);
4189 XHCI_CMD_UNLOCK(sc);
4193 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4196 * Wait until the hardware has finished any possible use of
4197 * the transfer descriptor(s)
4199 *pus = 2048; /* microseconds */
4203 xhci_device_resume(struct usb_device *udev)
4205 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4212 /* check for root HUB */
4213 if (udev->parent_hub == NULL)
4216 index = udev->controller_slot_id;
4220 /* blindly resume all endpoints */
4222 USB_BUS_LOCK(udev->bus);
4224 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4225 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4226 XWRITE4(sc, door, XHCI_DOORBELL(index),
4227 n | XHCI_DB_SID_SET(p));
4231 USB_BUS_UNLOCK(udev->bus);
4233 XHCI_CMD_UNLOCK(sc);
4237 xhci_device_suspend(struct usb_device *udev)
4239 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4246 /* check for root HUB */
4247 if (udev->parent_hub == NULL)
4250 index = udev->controller_slot_id;
4254 /* blindly suspend all endpoints */
4256 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4257 err = xhci_cmd_stop_ep(sc, 1, n, index);
4259 DPRINTF("Failed to suspend endpoint "
4260 "%u on slot %u (ignored).\n", n, index);
4264 XHCI_CMD_UNLOCK(sc);
4268 xhci_set_hw_power(struct usb_bus *bus)
4274 xhci_device_state_change(struct usb_device *udev)
4276 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4277 struct usb_page_search buf_inp;
4281 /* check for root HUB */
4282 if (udev->parent_hub == NULL)
4285 index = udev->controller_slot_id;
4289 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4290 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4291 &sc->sc_hw.devs[index].tt);
4293 sc->sc_hw.devs[index].nports = 0;
4298 switch (usb_get_device_state(udev)) {
4299 case USB_STATE_POWERED:
4300 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4303 /* set default state */
4304 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4305 sc->sc_hw.devs[index].ep_configured = 3U;
4307 /* reset number of contexts */
4308 sc->sc_hw.devs[index].context_num = 0;
4310 err = xhci_cmd_reset_dev(sc, index);
4313 DPRINTF("Device reset failed "
4314 "for slot %u.\n", index);
4318 case USB_STATE_ADDRESSED:
4319 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4322 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4323 sc->sc_hw.devs[index].ep_configured = 3U;
4325 /* set configure mask to slot only */
4326 xhci_configure_mask(udev, 1, 0);
4328 /* deconfigure all endpoints, except EP0 */
4329 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4332 DPRINTF("Failed to deconfigure "
4333 "slot %u.\n", index);
4337 case USB_STATE_CONFIGURED:
4338 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) {
4339 /* deconfigure all endpoints, except EP0 */
4340 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4343 DPRINTF("Failed to deconfigure "
4344 "slot %u.\n", index);
4348 /* set configured state */
4349 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4350 sc->sc_hw.devs[index].ep_configured = 3U;
4352 /* reset number of contexts */
4353 sc->sc_hw.devs[index].context_num = 0;
4355 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4357 xhci_configure_mask(udev, 3, 0);
4359 err = xhci_configure_device(udev);
4361 DPRINTF("Could not configure device "
4362 "at slot %u.\n", index);
4365 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4367 DPRINTF("Could not evaluate device "
4368 "context at slot %u.\n", index);
4375 XHCI_CMD_UNLOCK(sc);
4379 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4383 case USB_EP_MODE_DEFAULT:
4385 case USB_EP_MODE_STREAMS:
4386 if (xhcistreams == 0 ||
4387 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4388 udev->speed != USB_SPEED_SUPER)
4389 return (USB_ERR_INVAL);
4392 return (USB_ERR_INVAL);
4396 static const struct usb_bus_methods xhci_bus_methods = {
4397 .endpoint_init = xhci_ep_init,
4398 .endpoint_uninit = xhci_ep_uninit,
4399 .xfer_setup = xhci_xfer_setup,
4400 .xfer_unsetup = xhci_xfer_unsetup,
4401 .get_dma_delay = xhci_get_dma_delay,
4402 .device_init = xhci_device_init,
4403 .device_uninit = xhci_device_uninit,
4404 .device_resume = xhci_device_resume,
4405 .device_suspend = xhci_device_suspend,
4406 .set_hw_power = xhci_set_hw_power,
4407 .roothub_exec = xhci_roothub_exec,
4408 .xfer_poll = xhci_do_poll,
4409 .start_dma_delay = xhci_start_dma_delay,
4410 .set_address = xhci_set_address,
4411 .clear_stall = xhci_ep_clear_stall,
4412 .device_state_change = xhci_device_state_change,
4413 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4414 .set_endpoint_mode = xhci_set_endpoint_mode,