3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
30 * The XHCI 1.0 spec can be found at
31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
32 * and the USB 3.0 spec at
33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
37 * A few words about the design implementation: This driver emulates
38 * the concept about TDs which is found in EHCI specification. This
39 * way we achieve that the USB controller drivers look similar to
40 * eachother which makes it easier to understand the code.
43 #ifdef USB_GLOBAL_INCLUDE_FILE
44 #include USB_GLOBAL_INCLUDE_FILE
46 #include <sys/stdint.h>
47 #include <sys/stddef.h>
48 #include <sys/param.h>
49 #include <sys/queue.h>
50 #include <sys/types.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
54 #include <sys/module.h>
56 #include <sys/mutex.h>
57 #include <sys/condvar.h>
58 #include <sys/sysctl.h>
60 #include <sys/unistd.h>
61 #include <sys/callout.h>
62 #include <sys/malloc.h>
65 #include <dev/usb/usb.h>
66 #include <dev/usb/usbdi.h>
68 #define USB_DEBUG_VAR xhcidebug
70 #include <dev/usb/usb_core.h>
71 #include <dev/usb/usb_debug.h>
72 #include <dev/usb/usb_busdma.h>
73 #include <dev/usb/usb_process.h>
74 #include <dev/usb/usb_transfer.h>
75 #include <dev/usb/usb_device.h>
76 #include <dev/usb/usb_hub.h>
77 #include <dev/usb/usb_util.h>
79 #include <dev/usb/usb_controller.h>
80 #include <dev/usb/usb_bus.h>
81 #endif /* USB_GLOBAL_INCLUDE_FILE */
83 #include <dev/usb/controller/xhci.h>
84 #include <dev/usb/controller/xhcireg.h>
86 #define XHCI_BUS2SC(bus) \
87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
92 static int xhcistreams;
93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
94 &xhcistreams, 0, "Set to enable streams mode support");
95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
100 static int xhcipolling;
101 static int xhcidma32;
102 static int xhcictlstep;
104 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
105 &xhcidebug, 0, "Debug level");
106 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
107 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
108 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
109 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
110 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
111 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
112 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
114 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
115 TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32);
116 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
117 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
118 TUNABLE_INT("hw.usb.xhci.ctlstep", &xhcictlstep);
122 #define xhcictlstep 0
125 #define XHCI_INTR_ENDPT 1
127 struct xhci_std_temp {
128 struct xhci_softc *sc;
129 struct usb_page_cache *pc;
131 struct xhci_td *td_next;
134 uint32_t max_packet_size;
146 uint8_t do_isoc_sync;
149 static void xhci_do_poll(struct usb_bus *);
150 static void xhci_device_done(struct usb_xfer *, usb_error_t);
151 static void xhci_root_intr(struct xhci_softc *);
152 static void xhci_free_device_ext(struct usb_device *);
153 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
154 struct usb_endpoint_descriptor *);
155 static usb_proc_callback_t xhci_configure_msg;
156 static usb_error_t xhci_configure_device(struct usb_device *);
157 static usb_error_t xhci_configure_endpoint(struct usb_device *,
158 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
159 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
161 static usb_error_t xhci_configure_mask(struct usb_device *,
163 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
165 static void xhci_endpoint_doorbell(struct usb_xfer *);
166 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
167 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
168 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
170 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
173 extern struct usb_bus_methods xhci_bus_methods;
177 xhci_dump_trb(struct xhci_trb *trb)
179 DPRINTFN(5, "trb = %p\n", trb);
180 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
181 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
182 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
186 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
188 DPRINTFN(5, "pep = %p\n", pep);
189 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
190 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
191 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
192 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
193 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
194 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
195 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
199 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
201 DPRINTFN(5, "psl = %p\n", psl);
202 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
203 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
204 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
205 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
210 xhci_use_polling(void)
213 return (xhcipolling != 0);
220 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
222 struct xhci_softc *sc = XHCI_BUS2SC(bus);
225 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
226 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
228 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
229 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
231 for (i = 0; i != sc->sc_noscratch; i++) {
232 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
233 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
238 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
240 if (sc->sc_ctx_is_64_byte) {
242 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
243 /* all contexts are initially 32-bytes */
244 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
245 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
251 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
253 if (sc->sc_ctx_is_64_byte) {
255 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
256 /* all contexts are initially 32-bytes */
257 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
258 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
260 return (le32toh(*ptr));
264 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
266 if (sc->sc_ctx_is_64_byte) {
268 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
269 /* all contexts are initially 32-bytes */
270 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
271 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
278 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
280 if (sc->sc_ctx_is_64_byte) {
282 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
283 /* all contexts are initially 32-bytes */
284 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
285 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
287 return (le64toh(*ptr));
292 xhci_reset_command_queue_locked(struct xhci_softc *sc)
294 struct usb_page_search buf_res;
295 struct xhci_hw_root *phwr;
301 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
302 if (temp & XHCI_CRCR_LO_CRR) {
303 DPRINTF("Command ring running\n");
304 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
307 * Try to abort the last command as per section
308 * 4.6.1.2 "Aborting a Command" of the XHCI
312 /* stop and cancel */
313 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
314 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
316 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
317 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
320 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
322 /* check if command ring is still running */
323 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
324 if (temp & XHCI_CRCR_LO_CRR) {
325 DPRINTF("Comand ring still running\n");
326 return (USB_ERR_IOERROR);
330 /* reset command ring */
331 sc->sc_command_ccs = 1;
332 sc->sc_command_idx = 0;
334 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
336 /* set up command ring control base address */
337 addr = buf_res.physaddr;
338 phwr = buf_res.buffer;
339 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
341 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
343 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
344 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
346 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
348 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
349 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
355 xhci_start_controller(struct xhci_softc *sc)
357 struct usb_page_search buf_res;
358 struct xhci_hw_root *phwr;
359 struct xhci_dev_ctx_addr *pdctxa;
367 sc->sc_event_ccs = 1;
368 sc->sc_event_idx = 0;
369 sc->sc_command_ccs = 1;
370 sc->sc_command_idx = 0;
372 err = xhci_reset_controller(sc);
376 /* set up number of device slots */
377 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
378 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
380 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
382 temp = XREAD4(sc, oper, XHCI_USBSTS);
384 /* clear interrupts */
385 XWRITE4(sc, oper, XHCI_USBSTS, temp);
386 /* disable all device notifications */
387 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
389 /* set up device context base address */
390 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
391 pdctxa = buf_res.buffer;
392 memset(pdctxa, 0, sizeof(*pdctxa));
394 addr = buf_res.physaddr;
395 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
397 /* slot 0 points to the table of scratchpad pointers */
398 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
400 for (i = 0; i != sc->sc_noscratch; i++) {
401 struct usb_page_search buf_scp;
402 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
403 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
406 addr = buf_res.physaddr;
408 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
409 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
410 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
411 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
413 /* set up event table size */
414 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
415 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
417 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
419 /* set up interrupt rate */
420 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
422 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
424 phwr = buf_res.buffer;
425 addr = buf_res.physaddr;
426 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
428 /* reset hardware root structure */
429 memset(phwr, 0, sizeof(*phwr));
431 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
432 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
434 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
436 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
437 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
439 addr = buf_res.physaddr;
441 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
443 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
444 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
446 /* set up interrupter registers */
447 temp = XREAD4(sc, runt, XHCI_IMAN(0));
448 temp |= XHCI_IMAN_INTR_ENA;
449 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
451 /* set up command ring control base address */
452 addr = buf_res.physaddr;
453 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
455 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
457 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
458 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
460 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
462 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
465 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
466 XHCI_CMD_INTE | XHCI_CMD_HSEE);
468 for (i = 0; i != 100; i++) {
469 usb_pause_mtx(NULL, hz / 100);
470 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
475 XWRITE4(sc, oper, XHCI_USBCMD, 0);
476 device_printf(sc->sc_bus.parent, "Run timeout.\n");
477 return (USB_ERR_IOERROR);
480 /* catch any lost interrupts */
481 xhci_do_poll(&sc->sc_bus);
483 if (sc->sc_port_route != NULL) {
484 /* Route all ports to the XHCI by default */
485 sc->sc_port_route(sc->sc_bus.parent,
486 ~xhciroute, xhciroute);
492 xhci_halt_controller(struct xhci_softc *sc)
500 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
501 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
502 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
504 /* Halt controller */
505 XWRITE4(sc, oper, XHCI_USBCMD, 0);
507 for (i = 0; i != 100; i++) {
508 usb_pause_mtx(NULL, hz / 100);
509 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
515 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
516 return (USB_ERR_IOERROR);
522 xhci_reset_controller(struct xhci_softc *sc)
529 /* Reset controller */
530 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
532 for (i = 0; i != 100; i++) {
533 usb_pause_mtx(NULL, hz / 100);
534 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
535 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
541 device_printf(sc->sc_bus.parent, "Controller "
543 return (USB_ERR_IOERROR);
549 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
555 /* initialize some bus fields */
556 sc->sc_bus.parent = self;
558 /* set the bus revision */
559 sc->sc_bus.usbrev = USB_REV_3_0;
561 /* set up the bus struct */
562 sc->sc_bus.methods = &xhci_bus_methods;
564 /* set up devices array */
565 sc->sc_bus.devices = sc->sc_devices;
566 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
568 /* set default cycle state in case of early interrupts */
569 sc->sc_event_ccs = 1;
570 sc->sc_command_ccs = 1;
572 /* set up bus space offsets */
574 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
575 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
576 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
578 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
579 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
580 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
582 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
584 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
585 device_printf(sc->sc_bus.parent, "Controller does "
586 "not support 4K page size.\n");
590 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
592 DPRINTF("HCS0 = 0x%08x\n", temp);
594 /* set up context size */
595 if (XHCI_HCS0_CSZ(temp)) {
596 sc->sc_ctx_is_64_byte = 1;
598 sc->sc_ctx_is_64_byte = 0;
602 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
603 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
605 device_printf(self, "%d bytes context size, %d-bit DMA\n",
606 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
608 /* enable 64Kbyte control endpoint quirk */
609 sc->sc_bus.control_ep_quirk = 1;
611 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
613 /* get number of device slots */
614 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
616 if (sc->sc_noport == 0) {
617 device_printf(sc->sc_bus.parent, "Invalid number "
618 "of ports: %u\n", sc->sc_noport);
622 sc->sc_noport = sc->sc_noport;
623 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
625 DPRINTF("Max slots: %u\n", sc->sc_noslot);
627 if (sc->sc_noslot > XHCI_MAX_DEVICES)
628 sc->sc_noslot = XHCI_MAX_DEVICES;
630 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
632 DPRINTF("HCS2=0x%08x\n", temp);
634 /* get number of scratchpads */
635 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
637 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
638 device_printf(sc->sc_bus.parent, "XHCI request "
639 "too many scratchpads\n");
643 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
645 /* get event table size */
646 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
647 if (sc->sc_erst_max > XHCI_MAX_RSEG)
648 sc->sc_erst_max = XHCI_MAX_RSEG;
650 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
652 /* get maximum exit latency */
653 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
654 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
656 /* Check if we should use the default IMOD value. */
657 if (sc->sc_imod_default == 0)
658 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
660 /* get all DMA memory */
661 if (usb_bus_mem_alloc_all(&sc->sc_bus,
662 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
666 /* set up command queue mutex and condition varible */
667 cv_init(&sc->sc_cmd_cv, "CMDQ");
668 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
670 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
671 sc->sc_config_msg[0].bus = &sc->sc_bus;
672 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
673 sc->sc_config_msg[1].bus = &sc->sc_bus;
679 xhci_uninit(struct xhci_softc *sc)
682 * NOTE: At this point the control transfer process is gone
683 * and "xhci_configure_msg" is no longer called. Consequently
684 * waiting for the configuration messages to complete is not
687 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
689 cv_destroy(&sc->sc_cmd_cv);
690 sx_destroy(&sc->sc_cmd_sx);
694 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
696 struct xhci_softc *sc = XHCI_BUS2SC(bus);
699 case USB_HW_POWER_SUSPEND:
700 DPRINTF("Stopping the XHCI\n");
701 xhci_halt_controller(sc);
702 xhci_reset_controller(sc);
704 case USB_HW_POWER_SHUTDOWN:
705 DPRINTF("Stopping the XHCI\n");
706 xhci_halt_controller(sc);
707 xhci_reset_controller(sc);
709 case USB_HW_POWER_RESUME:
710 DPRINTF("Starting the XHCI\n");
711 xhci_start_controller(sc);
719 xhci_generic_done_sub(struct usb_xfer *xfer)
722 struct xhci_td *td_alt_next;
726 td = xfer->td_transfer_cache;
727 td_alt_next = td->alt_next;
729 if (xfer->aframes != xfer->nframes)
730 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
734 usb_pc_cpu_invalidate(td->page_cache);
739 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
740 xfer, (unsigned int)xfer->aframes,
741 (unsigned int)xfer->nframes,
742 (unsigned int)len, (unsigned int)td->len,
743 (unsigned int)status);
746 * Verify the status length and
747 * add the length to "frlengths[]":
750 /* should not happen */
751 DPRINTF("Invalid status length, "
752 "0x%04x/0x%04x bytes\n", len, td->len);
753 status = XHCI_TRB_ERROR_LENGTH;
754 } else if (xfer->aframes != xfer->nframes) {
755 xfer->frlengths[xfer->aframes] += td->len - len;
757 /* Check for last transfer */
758 if (((void *)td) == xfer->td_transfer_last) {
762 /* Check for transfer error */
763 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
764 status != XHCI_TRB_ERROR_SUCCESS) {
765 /* the transfer is finished */
769 /* Check for short transfer */
771 if (xfer->flags_int.short_frames_ok ||
772 xfer->flags_int.isochronous_xfr ||
773 xfer->flags_int.control_xfr) {
774 /* follow alt next */
777 /* the transfer is finished */
784 if (td->alt_next != td_alt_next) {
785 /* this USB frame is complete */
790 /* update transfer cache */
792 xfer->td_transfer_cache = td;
794 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
795 (status != XHCI_TRB_ERROR_SHORT_PKT &&
796 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
797 USB_ERR_NORMAL_COMPLETION);
801 xhci_generic_done(struct usb_xfer *xfer)
805 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
806 xfer, xfer->endpoint);
810 xfer->td_transfer_cache = xfer->td_transfer_first;
812 if (xfer->flags_int.control_xfr) {
814 if (xfer->flags_int.control_hdr)
815 err = xhci_generic_done_sub(xfer);
819 if (xfer->td_transfer_cache == NULL)
823 while (xfer->aframes != xfer->nframes) {
825 err = xhci_generic_done_sub(xfer);
828 if (xfer->td_transfer_cache == NULL)
832 if (xfer->flags_int.control_xfr &&
833 !xfer->flags_int.control_act)
834 err = xhci_generic_done_sub(xfer);
836 /* transfer is complete */
837 xhci_device_done(xfer, err);
841 xhci_activate_transfer(struct usb_xfer *xfer)
845 td = xfer->td_transfer_cache;
847 usb_pc_cpu_invalidate(td->page_cache);
849 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
851 /* activate the transfer */
853 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
854 usb_pc_cpu_flush(td->page_cache);
856 xhci_endpoint_doorbell(xfer);
861 xhci_skip_transfer(struct usb_xfer *xfer)
864 struct xhci_td *td_last;
866 td = xfer->td_transfer_cache;
867 td_last = xfer->td_transfer_last;
871 usb_pc_cpu_invalidate(td->page_cache);
873 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
875 usb_pc_cpu_invalidate(td_last->page_cache);
877 /* copy LINK TRB to current waiting location */
879 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
880 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
881 usb_pc_cpu_flush(td->page_cache);
883 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
884 usb_pc_cpu_flush(td->page_cache);
886 xhci_endpoint_doorbell(xfer);
890 /*------------------------------------------------------------------------*
891 * xhci_check_transfer
892 *------------------------------------------------------------------------*/
894 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
896 struct xhci_endpoint_ext *pepext;
901 uint16_t stream_id = 0;
909 td_event = le64toh(trb->qwTrb0);
910 temp = le32toh(trb->dwTrb2);
912 remainder = XHCI_TRB_2_REM_GET(temp);
913 status = XHCI_TRB_2_ERROR_GET(temp);
915 temp = le32toh(trb->dwTrb3);
916 epno = XHCI_TRB_3_EP_GET(temp);
917 index = XHCI_TRB_3_SLOT_GET(temp);
919 /* check if error means halted */
920 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
921 status != XHCI_TRB_ERROR_SUCCESS);
923 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
924 index, epno, remainder, status);
926 if (index > sc->sc_noslot) {
927 DPRINTF("Invalid slot.\n");
931 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
932 DPRINTF("Invalid endpoint.\n");
936 pepext = &sc->sc_hw.devs[index].endp[epno];
938 /* try to find the USB transfer that generated the event */
940 struct usb_xfer *xfer;
943 if (i == (XHCI_MAX_TRANSFERS - 1)) {
944 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS ||
945 stream_id == (XHCI_MAX_STREAMS - 1))
949 DPRINTFN(5, "stream_id=%u\n", stream_id);
952 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
956 td = xfer->td_transfer_cache;
958 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
960 (long long)td->td_self,
961 (long long)td->td_self + sizeof(td->td_trb));
964 * NOTE: Some XHCI implementations might not trigger
965 * an event on the last LINK TRB so we need to
966 * consider both the last and second last event
967 * address as conditions for a successful transfer.
969 * NOTE: We assume that the XHCI will only trigger one
970 * event per chain of TRBs.
973 offset = td_event - td->td_self;
976 offset < (int64_t)sizeof(td->td_trb)) {
978 usb_pc_cpu_invalidate(td->page_cache);
980 /* compute rest of remainder, if any */
981 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
982 temp = le32toh(td->td_trb[i].dwTrb2);
983 remainder += XHCI_TRB_2_BYTES_GET(temp);
986 DPRINTFN(5, "New remainder: %u\n", remainder);
988 /* clear isochronous transfer errors */
989 if (xfer->flags_int.isochronous_xfr) {
992 status = XHCI_TRB_ERROR_SUCCESS;
997 /* "td->remainder" is verified later */
998 td->remainder = remainder;
1001 usb_pc_cpu_flush(td->page_cache);
1004 * 1) Last transfer descriptor makes the
1007 if (((void *)td) == xfer->td_transfer_last) {
1008 DPRINTF("TD is last\n");
1009 xhci_generic_done(xfer);
1014 * 2) Any kind of error makes the transfer
1018 DPRINTF("TD has I/O error\n");
1019 xhci_generic_done(xfer);
1024 * 3) If there is no alternate next transfer,
1025 * a short packet also makes the transfer done
1027 if (td->remainder > 0) {
1028 if (td->alt_next == NULL) {
1030 "short TD has no alternate next\n");
1031 xhci_generic_done(xfer);
1034 DPRINTF("TD has short pkt\n");
1035 if (xfer->flags_int.short_frames_ok ||
1036 xfer->flags_int.isochronous_xfr ||
1037 xfer->flags_int.control_xfr) {
1038 /* follow the alt next */
1039 xfer->td_transfer_cache = td->alt_next;
1040 xhci_activate_transfer(xfer);
1043 xhci_skip_transfer(xfer);
1044 xhci_generic_done(xfer);
1049 * 4) Transfer complete - go to next TD
1051 DPRINTF("Following next TD\n");
1052 xfer->td_transfer_cache = td->obj_next;
1053 xhci_activate_transfer(xfer);
1054 break; /* there should only be one match */
1060 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1062 if (sc->sc_cmd_addr == trb->qwTrb0) {
1063 DPRINTF("Received command event\n");
1064 sc->sc_cmd_result[0] = trb->dwTrb2;
1065 sc->sc_cmd_result[1] = trb->dwTrb3;
1066 cv_signal(&sc->sc_cmd_cv);
1067 return (1); /* command match */
1073 xhci_interrupt_poll(struct xhci_softc *sc)
1075 struct usb_page_search buf_res;
1076 struct xhci_hw_root *phwr;
1086 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1088 phwr = buf_res.buffer;
1090 /* Receive any events */
1092 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1094 i = sc->sc_event_idx;
1095 j = sc->sc_event_ccs;
1100 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1102 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1107 event = XHCI_TRB_3_TYPE_GET(temp);
1109 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1110 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1111 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1112 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1115 case XHCI_TRB_EVENT_TRANSFER:
1116 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1118 case XHCI_TRB_EVENT_CMD_COMPLETE:
1119 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1122 DPRINTF("Unhandled event = %u\n", event);
1128 if (i == XHCI_MAX_EVENTS) {
1132 /* check for timeout */
1138 sc->sc_event_idx = i;
1139 sc->sc_event_ccs = j;
1142 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1143 * latched. That means to activate the register we need to
1144 * write both the low and high double word of the 64-bit
1148 addr = buf_res.physaddr;
1149 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1151 /* try to clear busy bit */
1152 addr |= XHCI_ERDP_LO_BUSY;
1154 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1155 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1161 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1162 uint16_t timeout_ms)
1164 struct usb_page_search buf_res;
1165 struct xhci_hw_root *phwr;
1170 uint8_t timeout = 0;
1173 XHCI_CMD_ASSERT_LOCKED(sc);
1175 /* get hardware root structure */
1177 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1179 phwr = buf_res.buffer;
1183 USB_BUS_LOCK(&sc->sc_bus);
1185 i = sc->sc_command_idx;
1186 j = sc->sc_command_ccs;
1188 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1189 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1190 (long long)le64toh(trb->qwTrb0),
1191 (long)le32toh(trb->dwTrb2),
1192 (long)le32toh(trb->dwTrb3));
1194 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1195 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1197 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1202 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1204 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1206 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1208 phwr->hwr_commands[i].dwTrb3 = temp;
1210 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1212 addr = buf_res.physaddr;
1213 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1215 sc->sc_cmd_addr = htole64(addr);
1219 if (i == (XHCI_MAX_COMMANDS - 1)) {
1222 temp = htole32(XHCI_TRB_3_TC_BIT |
1223 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1224 XHCI_TRB_3_CYCLE_BIT);
1226 temp = htole32(XHCI_TRB_3_TC_BIT |
1227 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1230 phwr->hwr_commands[i].dwTrb3 = temp;
1232 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1238 sc->sc_command_idx = i;
1239 sc->sc_command_ccs = j;
1241 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1243 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1244 USB_MS_TO_TICKS(timeout_ms));
1247 * In some error cases event interrupts are not generated.
1248 * Poll one time to see if the command has completed.
1250 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1251 DPRINTF("Command was completed when polling\n");
1255 DPRINTF("Command timeout!\n");
1257 * After some weeks of continuous operation, it has
1258 * been observed that the ASMedia Technology, ASM1042
1259 * SuperSpeed USB Host Controller can suddenly stop
1260 * accepting commands via the command queue. Try to
1261 * first reset the command queue. If that fails do a
1262 * host controller reset.
1265 xhci_reset_command_queue_locked(sc) == 0) {
1266 temp = le32toh(trb->dwTrb3);
1269 * Avoid infinite XHCI reset loops if the set
1270 * address command fails to respond due to a
1271 * non-enumerating device:
1273 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1274 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1275 DPRINTF("Set address timeout\n");
1281 DPRINTF("Controller reset!\n");
1282 usb_bus_reset_async_locked(&sc->sc_bus);
1284 err = USB_ERR_TIMEOUT;
1288 temp = le32toh(sc->sc_cmd_result[0]);
1289 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1290 err = USB_ERR_IOERROR;
1292 trb->dwTrb2 = sc->sc_cmd_result[0];
1293 trb->dwTrb3 = sc->sc_cmd_result[1];
1296 USB_BUS_UNLOCK(&sc->sc_bus);
1303 xhci_cmd_nop(struct xhci_softc *sc)
1305 struct xhci_trb trb;
1312 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1314 trb.dwTrb3 = htole32(temp);
1316 return (xhci_do_command(sc, &trb, 100 /* ms */));
1321 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1323 struct xhci_trb trb;
1331 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1333 err = xhci_do_command(sc, &trb, 100 /* ms */);
1337 temp = le32toh(trb.dwTrb3);
1339 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1346 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1348 struct xhci_trb trb;
1355 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1356 XHCI_TRB_3_SLOT_SET(slot_id);
1358 trb.dwTrb3 = htole32(temp);
1360 return (xhci_do_command(sc, &trb, 100 /* ms */));
1364 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1365 uint8_t bsr, uint8_t slot_id)
1367 struct xhci_trb trb;
1372 trb.qwTrb0 = htole64(input_ctx);
1374 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1375 XHCI_TRB_3_SLOT_SET(slot_id);
1378 temp |= XHCI_TRB_3_BSR_BIT;
1380 trb.dwTrb3 = htole32(temp);
1382 return (xhci_do_command(sc, &trb, 500 /* ms */));
1386 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1388 struct usb_page_search buf_inp;
1389 struct usb_page_search buf_dev;
1390 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1391 struct xhci_hw_dev *hdev;
1392 struct xhci_dev_ctx *pdev;
1393 struct xhci_endpoint_ext *pepext;
1399 /* the root HUB case is not handled here */
1400 if (udev->parent_hub == NULL)
1401 return (USB_ERR_INVAL);
1403 index = udev->controller_slot_id;
1405 hdev = &sc->sc_hw.devs[index];
1412 switch (hdev->state) {
1413 case XHCI_ST_DEFAULT:
1414 case XHCI_ST_ENABLED:
1416 hdev->state = XHCI_ST_ENABLED;
1418 /* set configure mask to slot and EP0 */
1419 xhci_configure_mask(udev, 3, 0);
1421 /* configure input slot context structure */
1422 err = xhci_configure_device(udev);
1425 DPRINTF("Could not configure device\n");
1429 /* configure input endpoint context structure */
1430 switch (udev->speed) {
1432 case USB_SPEED_FULL:
1435 case USB_SPEED_HIGH:
1443 pepext = xhci_get_endpoint_ext(udev,
1444 &udev->ctrl_ep_desc);
1446 /* ensure the control endpoint is setup again */
1447 USB_BUS_LOCK(udev->bus);
1448 pepext->trb_halted = 1;
1449 pepext->trb_running = 0;
1450 USB_BUS_UNLOCK(udev->bus);
1452 err = xhci_configure_endpoint(udev,
1453 &udev->ctrl_ep_desc, pepext,
1454 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1457 DPRINTF("Could not configure default endpoint\n");
1461 /* execute set address command */
1462 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1464 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1465 (address == 0), index);
1468 temp = le32toh(sc->sc_cmd_result[0]);
1469 if (address == 0 && sc->sc_port_route != NULL &&
1470 XHCI_TRB_2_ERROR_GET(temp) ==
1471 XHCI_TRB_ERROR_PARAMETER) {
1472 /* LynxPoint XHCI - ports are not switchable */
1473 /* Un-route all ports from the XHCI */
1474 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1476 DPRINTF("Could not set address "
1477 "for slot %u.\n", index);
1482 /* update device address to new value */
1484 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1485 pdev = buf_dev.buffer;
1486 usb_pc_cpu_invalidate(&hdev->device_pc);
1488 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1489 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1491 /* update device state to new value */
1494 hdev->state = XHCI_ST_ADDRESSED;
1496 hdev->state = XHCI_ST_DEFAULT;
1500 DPRINTF("Wrong state for set address.\n");
1501 err = USB_ERR_IOERROR;
1504 XHCI_CMD_UNLOCK(sc);
1513 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1514 uint8_t deconfigure, uint8_t slot_id)
1516 struct xhci_trb trb;
1521 trb.qwTrb0 = htole64(input_ctx);
1523 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1524 XHCI_TRB_3_SLOT_SET(slot_id);
1527 temp |= XHCI_TRB_3_DCEP_BIT;
1529 trb.dwTrb3 = htole32(temp);
1531 return (xhci_do_command(sc, &trb, 100 /* ms */));
1535 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1538 struct xhci_trb trb;
1543 trb.qwTrb0 = htole64(input_ctx);
1545 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1546 XHCI_TRB_3_SLOT_SET(slot_id);
1547 trb.dwTrb3 = htole32(temp);
1549 return (xhci_do_command(sc, &trb, 100 /* ms */));
1553 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1554 uint8_t ep_id, uint8_t slot_id)
1556 struct xhci_trb trb;
1563 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1564 XHCI_TRB_3_SLOT_SET(slot_id) |
1565 XHCI_TRB_3_EP_SET(ep_id);
1568 temp |= XHCI_TRB_3_PRSV_BIT;
1570 trb.dwTrb3 = htole32(temp);
1572 return (xhci_do_command(sc, &trb, 100 /* ms */));
1576 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1577 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1579 struct xhci_trb trb;
1584 trb.qwTrb0 = htole64(dequeue_ptr);
1586 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1587 trb.dwTrb2 = htole32(temp);
1589 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1590 XHCI_TRB_3_SLOT_SET(slot_id) |
1591 XHCI_TRB_3_EP_SET(ep_id);
1592 trb.dwTrb3 = htole32(temp);
1594 return (xhci_do_command(sc, &trb, 100 /* ms */));
1598 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1599 uint8_t ep_id, uint8_t slot_id)
1601 struct xhci_trb trb;
1608 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1609 XHCI_TRB_3_SLOT_SET(slot_id) |
1610 XHCI_TRB_3_EP_SET(ep_id);
1613 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1615 trb.dwTrb3 = htole32(temp);
1617 return (xhci_do_command(sc, &trb, 100 /* ms */));
1621 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1623 struct xhci_trb trb;
1630 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1631 XHCI_TRB_3_SLOT_SET(slot_id);
1633 trb.dwTrb3 = htole32(temp);
1635 return (xhci_do_command(sc, &trb, 100 /* ms */));
1638 /*------------------------------------------------------------------------*
1639 * xhci_interrupt - XHCI interrupt handler
1640 *------------------------------------------------------------------------*/
1642 xhci_interrupt(struct xhci_softc *sc)
1647 USB_BUS_LOCK(&sc->sc_bus);
1649 status = XREAD4(sc, oper, XHCI_USBSTS);
1651 /* acknowledge interrupts, if any */
1653 XWRITE4(sc, oper, XHCI_USBSTS, status);
1654 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1657 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1659 /* force clearing of pending interrupts */
1660 if (temp & XHCI_IMAN_INTR_PEND)
1661 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1663 /* check for event(s) */
1664 xhci_interrupt_poll(sc);
1666 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1667 XHCI_STS_HSE | XHCI_STS_HCE)) {
1669 if (status & XHCI_STS_PCD) {
1673 if (status & XHCI_STS_HCH) {
1674 printf("%s: host controller halted\n",
1678 if (status & XHCI_STS_HSE) {
1679 printf("%s: host system error\n",
1683 if (status & XHCI_STS_HCE) {
1684 printf("%s: host controller error\n",
1688 USB_BUS_UNLOCK(&sc->sc_bus);
1691 /*------------------------------------------------------------------------*
1692 * xhci_timeout - XHCI timeout handler
1693 *------------------------------------------------------------------------*/
1695 xhci_timeout(void *arg)
1697 struct usb_xfer *xfer = arg;
1699 DPRINTF("xfer=%p\n", xfer);
1701 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1703 /* transfer is transferred */
1704 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1708 xhci_do_poll(struct usb_bus *bus)
1710 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1712 USB_BUS_LOCK(&sc->sc_bus);
1713 xhci_interrupt_poll(sc);
1714 USB_BUS_UNLOCK(&sc->sc_bus);
1718 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1720 struct usb_page_search buf_res;
1722 struct xhci_td *td_next;
1723 struct xhci_td *td_alt_next;
1724 struct xhci_td *td_first;
1725 uint32_t buf_offset;
1730 uint8_t shortpkt_old;
1736 shortpkt_old = temp->shortpkt;
1737 len_old = temp->len;
1744 td_next = td_first = temp->td_next;
1748 if (temp->len == 0) {
1753 /* send a Zero Length Packet, ZLP, last */
1760 average = temp->average;
1762 if (temp->len < average) {
1763 if (temp->len % temp->max_packet_size) {
1766 average = temp->len;
1770 if (td_next == NULL)
1771 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1776 td_next = td->obj_next;
1778 /* check if we are pre-computing */
1782 /* update remaining length */
1784 temp->len -= average;
1788 /* fill out current TD */
1794 /* update remaining length */
1796 temp->len -= average;
1798 /* reset TRB index */
1802 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1803 /* immediate data */
1808 td->td_trb[0].qwTrb0 = 0;
1810 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1811 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1814 dword = XHCI_TRB_2_BYTES_SET(8) |
1815 XHCI_TRB_2_TDSZ_SET(0) |
1816 XHCI_TRB_2_IRQ_SET(0);
1818 td->td_trb[0].dwTrb2 = htole32(dword);
1820 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1821 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1824 if (td->td_trb[0].qwTrb0 &
1825 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1826 if (td->td_trb[0].qwTrb0 &
1827 htole64(XHCI_TRB_0_DIR_IN_MASK))
1828 dword |= XHCI_TRB_3_TRT_IN;
1830 dword |= XHCI_TRB_3_TRT_OUT;
1833 td->td_trb[0].dwTrb3 = htole32(dword);
1835 xhci_dump_trb(&td->td_trb[x]);
1843 /* fill out buffer pointers */
1846 memset(&buf_res, 0, sizeof(buf_res));
1848 usbd_get_page(temp->pc, temp->offset +
1849 buf_offset, &buf_res);
1851 /* get length to end of page */
1852 if (buf_res.length > average)
1853 buf_res.length = average;
1855 /* check for maximum length */
1856 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1857 buf_res.length = XHCI_TD_PAGE_SIZE;
1859 npkt_off += buf_res.length;
1863 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1864 temp->max_packet_size;
1871 /* fill out TRB's */
1872 td->td_trb[x].qwTrb0 =
1873 htole64((uint64_t)buf_res.physaddr);
1876 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1877 XHCI_TRB_2_TDSZ_SET(npkt) |
1878 XHCI_TRB_2_IRQ_SET(0);
1880 td->td_trb[x].dwTrb2 = htole32(dword);
1882 switch (temp->trb_type) {
1883 case XHCI_TRB_TYPE_ISOCH:
1884 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1885 XHCI_TRB_3_TBC_SET(temp->tbc) |
1886 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1887 if (td != td_first) {
1888 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1889 } else if (temp->do_isoc_sync != 0) {
1890 temp->do_isoc_sync = 0;
1891 /* wait until "isoc_frame" */
1892 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1893 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1895 /* start data transfer at next interval */
1896 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1897 XHCI_TRB_3_ISO_SIA_BIT;
1899 if (temp->direction == UE_DIR_IN)
1900 dword |= XHCI_TRB_3_ISP_BIT;
1902 case XHCI_TRB_TYPE_DATA_STAGE:
1903 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1904 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1905 if (temp->direction == UE_DIR_IN)
1906 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1908 * Section 3.2.9 in the XHCI
1909 * specification about control
1910 * transfers says that we should use a
1911 * normal-TRB if there are more TRBs
1912 * extending the data-stage
1913 * TRB. Update the "trb_type".
1915 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1917 case XHCI_TRB_TYPE_STATUS_STAGE:
1918 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1919 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1920 if (temp->direction == UE_DIR_IN)
1921 dword |= XHCI_TRB_3_DIR_IN;
1923 default: /* XHCI_TRB_TYPE_NORMAL */
1924 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1925 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1926 if (temp->direction == UE_DIR_IN)
1927 dword |= XHCI_TRB_3_ISP_BIT;
1930 td->td_trb[x].dwTrb3 = htole32(dword);
1932 average -= buf_res.length;
1933 buf_offset += buf_res.length;
1935 xhci_dump_trb(&td->td_trb[x]);
1939 } while (average != 0);
1941 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1943 /* store number of data TRB's */
1947 DPRINTF("NTRB=%u\n", x);
1949 /* fill out link TRB */
1951 if (td_next != NULL) {
1952 /* link the current TD with the next one */
1953 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1954 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1956 /* this field will get updated later */
1957 DPRINTF("NOLINK\n");
1960 dword = XHCI_TRB_2_IRQ_SET(0);
1962 td->td_trb[x].dwTrb2 = htole32(dword);
1964 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1965 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1967 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1968 * frame only receives a single short packet event
1969 * by setting the CHAIN bit in the LINK field. In
1970 * addition some XHCI controllers have problems
1971 * sending a ZLP unless the CHAIN-BIT is set in
1974 XHCI_TRB_3_CHAIN_BIT;
1976 td->td_trb[x].dwTrb3 = htole32(dword);
1978 td->alt_next = td_alt_next;
1980 xhci_dump_trb(&td->td_trb[x]);
1982 usb_pc_cpu_flush(td->page_cache);
1988 /* set up alt next pointer, if any */
1989 if (temp->last_frame) {
1992 /* we use this field internally */
1993 td_alt_next = td_next;
1997 temp->shortpkt = shortpkt_old;
1998 temp->len = len_old;
2003 * Remove cycle bit from the first TRB if we are
2006 if (temp->step_td != 0) {
2007 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2008 usb_pc_cpu_flush(td_first->page_cache);
2011 /* clear TD SIZE to zero, hence this is the last TRB */
2012 /* remove chain bit because this is the last data TRB in the chain */
2013 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31));
2014 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2015 /* remove CHAIN-BIT from last LINK TRB */
2016 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2018 usb_pc_cpu_flush(td->page_cache);
2021 temp->td_next = td_next;
2025 xhci_setup_generic_chain(struct usb_xfer *xfer)
2027 struct xhci_std_temp temp;
2033 temp.do_isoc_sync = 0;
2037 temp.average = xfer->max_hc_frame_size;
2038 temp.max_packet_size = xfer->max_packet_size;
2039 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2041 temp.last_frame = 0;
2043 temp.multishort = xfer->flags_int.isochronous_xfr ||
2044 xfer->flags_int.control_xfr ||
2045 xfer->flags_int.short_frames_ok;
2047 /* toggle the DMA set we are using */
2048 xfer->flags_int.curr_dma_set ^= 1;
2050 /* get next DMA set */
2051 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2056 xfer->td_transfer_first = td;
2057 xfer->td_transfer_cache = td;
2059 if (xfer->flags_int.isochronous_xfr) {
2062 /* compute multiplier for ISOCHRONOUS transfers */
2063 mult = xfer->endpoint->ecomp ?
2064 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2066 /* check for USB 2.0 multiplier */
2068 mult = (xfer->endpoint->edesc->
2069 wMaxPacketSize[1] >> 3) & 3;
2077 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2079 DPRINTF("MFINDEX=0x%08x\n", x);
2081 switch (usbd_get_speed(xfer->xroot->udev)) {
2082 case USB_SPEED_FULL:
2084 temp.isoc_delta = 8; /* 1ms */
2085 x += temp.isoc_delta - 1;
2086 x &= ~(temp.isoc_delta - 1);
2089 shift = usbd_xfer_get_fps_shift(xfer);
2090 temp.isoc_delta = 1U << shift;
2091 x += temp.isoc_delta - 1;
2092 x &= ~(temp.isoc_delta - 1);
2093 /* simple frame load balancing */
2094 x += xfer->endpoint->usb_uframe;
2098 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2100 if ((xfer->endpoint->is_synced == 0) ||
2101 (y < (xfer->nframes << shift)) ||
2102 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2104 * If there is data underflow or the pipe
2105 * queue is empty we schedule the transfer a
2106 * few frames ahead of the current frame
2107 * position. Else two isochronous transfers
2110 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2111 xfer->endpoint->is_synced = 1;
2112 temp.do_isoc_sync = 1;
2114 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2117 /* compute isochronous completion time */
2119 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2121 xfer->isoc_time_complete =
2122 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2123 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2126 temp.isoc_frame = xfer->endpoint->isoc_next;
2127 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2129 xfer->endpoint->isoc_next += xfer->nframes << shift;
2131 } else if (xfer->flags_int.control_xfr) {
2133 /* check if we should prepend a setup message */
2135 if (xfer->flags_int.control_hdr) {
2137 temp.len = xfer->frlengths[0];
2138 temp.pc = xfer->frbuffers + 0;
2139 temp.shortpkt = temp.len ? 1 : 0;
2140 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2143 /* check for last frame */
2144 if (xfer->nframes == 1) {
2145 /* no STATUS stage yet, SETUP is last */
2146 if (xfer->flags_int.control_act)
2147 temp.last_frame = 1;
2150 xhci_setup_generic_chain_sub(&temp);
2154 temp.isoc_delta = 0;
2155 temp.isoc_frame = 0;
2156 temp.trb_type = xfer->flags_int.control_did_data ?
2157 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2161 temp.isoc_delta = 0;
2162 temp.isoc_frame = 0;
2163 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2166 if (x != xfer->nframes) {
2167 /* set up page_cache pointer */
2168 temp.pc = xfer->frbuffers + x;
2169 /* set endpoint direction */
2170 temp.direction = UE_GET_DIR(xfer->endpointno);
2173 while (x != xfer->nframes) {
2175 /* DATA0 / DATA1 message */
2177 temp.len = xfer->frlengths[x];
2178 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2179 x != 0 && temp.multishort == 0);
2183 if (x == xfer->nframes) {
2184 if (xfer->flags_int.control_xfr) {
2185 /* no STATUS stage yet, DATA is last */
2186 if (xfer->flags_int.control_act)
2187 temp.last_frame = 1;
2189 temp.last_frame = 1;
2192 if (temp.len == 0) {
2194 /* make sure that we send an USB packet */
2199 temp.tlbpc = mult - 1;
2201 } else if (xfer->flags_int.isochronous_xfr) {
2206 * Isochronous transfers don't have short
2207 * packet termination:
2212 /* isochronous transfers have a transfer limit */
2214 if (temp.len > xfer->max_frame_size)
2215 temp.len = xfer->max_frame_size;
2217 /* compute TD packet count */
2218 tdpc = (temp.len + xfer->max_packet_size - 1) /
2219 xfer->max_packet_size;
2221 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2222 temp.tlbpc = (tdpc % mult);
2224 if (temp.tlbpc == 0)
2225 temp.tlbpc = mult - 1;
2230 /* regular data transfer */
2232 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2235 xhci_setup_generic_chain_sub(&temp);
2237 if (xfer->flags_int.isochronous_xfr) {
2238 temp.offset += xfer->frlengths[x - 1];
2239 temp.isoc_frame += temp.isoc_delta;
2241 /* get next Page Cache pointer */
2242 temp.pc = xfer->frbuffers + x;
2246 /* check if we should append a status stage */
2248 if (xfer->flags_int.control_xfr &&
2249 !xfer->flags_int.control_act) {
2252 * Send a DATA1 message and invert the current
2253 * endpoint direction.
2255 if (xhcictlstep || temp.sc->sc_ctlstep) {
2257 * Some XHCI controllers will not delay the
2258 * status stage until the next SOF. Force this
2259 * behaviour to avoid failed control
2262 temp.step_td = (xfer->nframes != 0);
2266 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2270 temp.last_frame = 1;
2271 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2273 xhci_setup_generic_chain_sub(&temp);
2278 /* must have at least one frame! */
2280 xfer->td_transfer_last = td;
2282 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2286 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2288 struct usb_page_search buf_res;
2289 struct xhci_dev_ctx_addr *pdctxa;
2291 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2293 pdctxa = buf_res.buffer;
2295 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2297 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2299 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2303 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2305 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2306 struct usb_page_search buf_inp;
2307 struct xhci_input_dev_ctx *pinp;
2312 index = udev->controller_slot_id;
2314 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2316 pinp = buf_inp.buffer;
2319 mask &= XHCI_INCTX_NON_CTRL_MASK;
2320 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2321 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2324 * Some hardware requires that we drop the endpoint
2325 * context before adding it again:
2327 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2328 mask & XHCI_INCTX_NON_CTRL_MASK);
2330 /* Add new endpoint context */
2331 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2333 /* find most significant set bit */
2334 for (x = 31; x != 1; x--) {
2335 if (mask & (1 << x))
2342 /* figure out the maximum number of contexts */
2343 if (x > sc->sc_hw.devs[index].context_num)
2344 sc->sc_hw.devs[index].context_num = x;
2346 x = sc->sc_hw.devs[index].context_num;
2348 /* update number of contexts */
2349 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2350 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2351 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2352 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2354 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2359 xhci_configure_endpoint(struct usb_device *udev,
2360 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2361 uint16_t interval, uint8_t max_packet_count,
2362 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2363 uint16_t max_frame_size, uint8_t ep_mode)
2365 struct usb_page_search buf_inp;
2366 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2367 struct xhci_input_dev_ctx *pinp;
2368 uint64_t ring_addr = pepext->physaddr;
2374 index = udev->controller_slot_id;
2376 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2378 pinp = buf_inp.buffer;
2380 epno = edesc->bEndpointAddress;
2381 type = edesc->bmAttributes & UE_XFERTYPE;
2383 if (type == UE_CONTROL)
2386 epno = XHCI_EPNO2EPID(epno);
2389 return (USB_ERR_NO_PIPE); /* invalid */
2391 if (max_packet_count == 0)
2392 return (USB_ERR_BAD_BUFSIZE);
2397 return (USB_ERR_BAD_BUFSIZE);
2399 /* store endpoint mode */
2400 pepext->trb_ep_mode = ep_mode;
2401 /* store bMaxPacketSize for control endpoints */
2402 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2403 usb_pc_cpu_flush(pepext->page_cache);
2405 if (ep_mode == USB_EP_MODE_STREAMS) {
2406 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2407 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2408 XHCI_EPCTX_0_LSA_SET(1);
2410 ring_addr += sizeof(struct xhci_trb) *
2411 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2413 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2414 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2415 XHCI_EPCTX_0_LSA_SET(0);
2417 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2420 switch (udev->speed) {
2421 case USB_SPEED_FULL:
2434 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2436 case UE_ISOCHRONOUS:
2437 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2439 switch (udev->speed) {
2440 case USB_SPEED_SUPER:
2443 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2444 max_packet_count /= mult;
2454 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2457 XHCI_EPCTX_1_HID_SET(0) |
2458 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2459 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2462 * Always enable the "three strikes and you are gone" feature
2463 * except for ISOCHRONOUS endpoints. This is suggested by
2464 * section 4.3.3 in the XHCI specification about device slot
2467 if (type != UE_ISOCHRONOUS)
2468 temp |= XHCI_EPCTX_1_CERR_SET(3);
2472 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2474 case UE_ISOCHRONOUS:
2475 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2478 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2481 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2485 /* check for IN direction */
2487 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2489 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2490 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2492 switch (edesc->bmAttributes & UE_XFERTYPE) {
2494 case UE_ISOCHRONOUS:
2495 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2496 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2500 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2503 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2507 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2510 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2512 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2514 return (0); /* success */
2518 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2520 struct xhci_endpoint_ext *pepext;
2521 struct usb_endpoint_ss_comp_descriptor *ecomp;
2524 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2525 xfer->endpoint->edesc);
2527 ecomp = xfer->endpoint->ecomp;
2529 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2532 /* halt any transfers */
2533 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2535 /* compute start of TRB ring for stream "x" */
2536 temp = pepext->physaddr +
2537 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2538 XHCI_SCTX_0_SCT_SEC_TR_RING;
2540 /* make tree structure */
2541 pepext->trb[(XHCI_MAX_TRANSFERS *
2542 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2544 /* reserved fields */
2545 pepext->trb[(XHCI_MAX_TRANSFERS *
2546 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2547 pepext->trb[(XHCI_MAX_TRANSFERS *
2548 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2550 usb_pc_cpu_flush(pepext->page_cache);
2552 return (xhci_configure_endpoint(xfer->xroot->udev,
2553 xfer->endpoint->edesc, pepext,
2554 xfer->interval, xfer->max_packet_count,
2555 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2556 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2557 xfer->max_frame_size, xfer->endpoint->ep_mode));
2561 xhci_configure_device(struct usb_device *udev)
2563 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2564 struct usb_page_search buf_inp;
2565 struct usb_page_cache *pcinp;
2566 struct xhci_input_dev_ctx *pinp;
2567 struct usb_device *hubdev;
2575 index = udev->controller_slot_id;
2577 DPRINTF("index=%u\n", index);
2579 pcinp = &sc->sc_hw.devs[index].input_pc;
2581 usbd_get_page(pcinp, 0, &buf_inp);
2583 pinp = buf_inp.buffer;
2588 /* figure out route string and root HUB port number */
2590 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2592 if (hubdev->parent_hub == NULL)
2595 depth = hubdev->parent_hub->depth;
2598 * NOTE: HS/FS/LS devices and the SS root HUB can have
2599 * more than 15 ports
2602 rh_port = hubdev->port_no;
2611 route |= rh_port << (4 * (depth - 1));
2614 DPRINTF("Route=0x%08x\n", route);
2616 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2617 XHCI_SCTX_0_CTX_NUM_SET(
2618 sc->sc_hw.devs[index].context_num + 1);
2620 switch (udev->speed) {
2622 temp |= XHCI_SCTX_0_SPEED_SET(2);
2623 if (udev->parent_hs_hub != NULL &&
2624 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2626 DPRINTF("Device inherits MTT\n");
2627 temp |= XHCI_SCTX_0_MTT_SET(1);
2630 case USB_SPEED_HIGH:
2631 temp |= XHCI_SCTX_0_SPEED_SET(3);
2632 if (sc->sc_hw.devs[index].nports != 0 &&
2633 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2634 DPRINTF("HUB supports MTT\n");
2635 temp |= XHCI_SCTX_0_MTT_SET(1);
2638 case USB_SPEED_FULL:
2639 temp |= XHCI_SCTX_0_SPEED_SET(1);
2640 if (udev->parent_hs_hub != NULL &&
2641 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2643 DPRINTF("Device inherits MTT\n");
2644 temp |= XHCI_SCTX_0_MTT_SET(1);
2648 temp |= XHCI_SCTX_0_SPEED_SET(4);
2652 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2653 (udev->speed == USB_SPEED_SUPER ||
2654 udev->speed == USB_SPEED_HIGH);
2657 temp |= XHCI_SCTX_0_HUB_SET(1);
2659 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2661 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2664 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2665 sc->sc_hw.devs[index].nports);
2668 switch (udev->speed) {
2669 case USB_SPEED_SUPER:
2670 switch (sc->sc_hw.devs[index].state) {
2671 case XHCI_ST_ADDRESSED:
2672 case XHCI_ST_CONFIGURED:
2673 /* enable power save */
2674 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2677 /* disable power save */
2685 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2687 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2690 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2691 sc->sc_hw.devs[index].tt);
2694 hubdev = udev->parent_hs_hub;
2696 /* check if we should activate the transaction translator */
2697 switch (udev->speed) {
2698 case USB_SPEED_FULL:
2700 if (hubdev != NULL) {
2701 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2702 hubdev->controller_slot_id);
2703 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2711 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2714 * These fields should be initialized to zero, according to
2715 * XHCI section 6.2.2 - slot context:
2717 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2718 XHCI_SCTX_3_SLOT_STATE_SET(0);
2720 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2723 xhci_dump_device(sc, &pinp->ctx_slot);
2725 usb_pc_cpu_flush(pcinp);
2727 return (0); /* success */
2731 xhci_alloc_device_ext(struct usb_device *udev)
2733 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2734 struct usb_page_search buf_dev;
2735 struct usb_page_search buf_ep;
2736 struct xhci_trb *trb;
2737 struct usb_page_cache *pc;
2738 struct usb_page *pg;
2743 index = udev->controller_slot_id;
2745 pc = &sc->sc_hw.devs[index].device_pc;
2746 pg = &sc->sc_hw.devs[index].device_pg;
2748 /* need to initialize the page cache */
2749 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2751 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2752 (2 * sizeof(struct xhci_dev_ctx)) :
2753 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2756 usbd_get_page(pc, 0, &buf_dev);
2758 pc = &sc->sc_hw.devs[index].input_pc;
2759 pg = &sc->sc_hw.devs[index].input_pg;
2761 /* need to initialize the page cache */
2762 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2764 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2765 (2 * sizeof(struct xhci_input_dev_ctx)) :
2766 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2770 /* initialize all endpoint LINK TRBs */
2772 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2774 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2775 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2777 /* need to initialize the page cache */
2778 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2780 if (usb_pc_alloc_mem(pc, pg,
2781 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2785 /* lookup endpoint TRB ring */
2786 usbd_get_page(pc, 0, &buf_ep);
2788 /* get TRB pointer */
2789 trb = buf_ep.buffer;
2790 trb += XHCI_MAX_TRANSFERS - 1;
2792 /* get TRB start address */
2793 addr = buf_ep.physaddr;
2795 /* create LINK TRB */
2796 trb->qwTrb0 = htole64(addr);
2797 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2798 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2799 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2801 usb_pc_cpu_flush(pc);
2804 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2809 xhci_free_device_ext(udev);
2811 return (USB_ERR_NOMEM);
2815 xhci_free_device_ext(struct usb_device *udev)
2817 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2821 index = udev->controller_slot_id;
2822 xhci_set_slot_pointer(sc, index, 0);
2824 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2825 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2826 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2827 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2830 static struct xhci_endpoint_ext *
2831 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2833 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2834 struct xhci_endpoint_ext *pepext;
2835 struct usb_page_cache *pc;
2836 struct usb_page_search buf_ep;
2840 epno = edesc->bEndpointAddress;
2841 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2844 epno = XHCI_EPNO2EPID(epno);
2846 index = udev->controller_slot_id;
2848 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2850 usbd_get_page(pc, 0, &buf_ep);
2852 pepext = &sc->sc_hw.devs[index].endp[epno];
2853 pepext->page_cache = pc;
2854 pepext->trb = buf_ep.buffer;
2855 pepext->physaddr = buf_ep.physaddr;
2861 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2863 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2867 epno = xfer->endpointno;
2868 if (xfer->flags_int.control_xfr)
2871 epno = XHCI_EPNO2EPID(epno);
2872 index = xfer->xroot->udev->controller_slot_id;
2874 if (xfer->xroot->udev->flags.self_suspended == 0) {
2875 XWRITE4(sc, door, XHCI_DOORBELL(index),
2876 epno | XHCI_DB_SID_SET(xfer->stream_id));
2881 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2883 struct xhci_endpoint_ext *pepext;
2885 if (xfer->flags_int.bandwidth_reclaimed) {
2886 xfer->flags_int.bandwidth_reclaimed = 0;
2888 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2889 xfer->endpoint->edesc);
2891 pepext->trb_used[xfer->stream_id]--;
2893 pepext->xfer[xfer->qh_pos] = NULL;
2895 if (error && pepext->trb_running != 0) {
2896 pepext->trb_halted = 1;
2897 pepext->trb_running = 0;
2903 xhci_transfer_insert(struct usb_xfer *xfer)
2905 struct xhci_td *td_first;
2906 struct xhci_td *td_last;
2907 struct xhci_trb *trb_link;
2908 struct xhci_endpoint_ext *pepext;
2917 id = xfer->stream_id;
2919 /* check if already inserted */
2920 if (xfer->flags_int.bandwidth_reclaimed) {
2921 DPRINTFN(8, "Already in schedule\n");
2925 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2926 xfer->endpoint->edesc);
2928 td_first = xfer->td_transfer_first;
2929 td_last = xfer->td_transfer_last;
2930 addr = pepext->physaddr;
2932 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2935 /* single buffered */
2939 /* multi buffered */
2940 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2944 if (pepext->trb_used[id] >= trb_limit) {
2945 DPRINTFN(8, "Too many TDs queued.\n");
2946 return (USB_ERR_NOMEM);
2949 /* check if bMaxPacketSize changed */
2950 if (xfer->flags_int.control_xfr != 0 &&
2951 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2953 DPRINTFN(8, "Reconfigure control endpoint\n");
2955 /* force driver to reconfigure endpoint */
2956 pepext->trb_halted = 1;
2957 pepext->trb_running = 0;
2960 /* check for stopped condition, after putting transfer on interrupt queue */
2961 if (pepext->trb_running == 0) {
2962 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2964 DPRINTFN(8, "Not running\n");
2966 /* start configuration */
2967 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2968 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2972 pepext->trb_used[id]++;
2974 /* get current TRB index */
2975 i = pepext->trb_index[id];
2977 /* get next TRB index */
2980 /* the last entry of the ring is a hardcoded link TRB */
2981 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2984 /* store next TRB index, before stream ID offset is added */
2985 pepext->trb_index[id] = inext;
2987 /* offset for stream */
2988 i += id * XHCI_MAX_TRANSFERS;
2989 inext += id * XHCI_MAX_TRANSFERS;
2991 /* compute terminating return address */
2992 addr += (inext * sizeof(struct xhci_trb));
2994 /* compute link TRB pointer */
2995 trb_link = td_last->td_trb + td_last->ntrb;
2997 /* update next pointer of last link TRB */
2998 trb_link->qwTrb0 = htole64(addr);
2999 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3000 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
3001 XHCI_TRB_3_CYCLE_BIT |
3002 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3005 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
3007 usb_pc_cpu_flush(td_last->page_cache);
3009 /* write ahead chain end marker */
3011 pepext->trb[inext].qwTrb0 = 0;
3012 pepext->trb[inext].dwTrb2 = 0;
3013 pepext->trb[inext].dwTrb3 = 0;
3015 /* update next pointer of link TRB */
3017 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
3018 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3021 xhci_dump_trb(&pepext->trb[i]);
3023 usb_pc_cpu_flush(pepext->page_cache);
3025 /* toggle cycle bit which activates the transfer chain */
3027 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3028 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3030 usb_pc_cpu_flush(pepext->page_cache);
3032 DPRINTF("qh_pos = %u\n", i);
3034 pepext->xfer[i] = xfer;
3038 xfer->flags_int.bandwidth_reclaimed = 1;
3040 xhci_endpoint_doorbell(xfer);
3046 xhci_root_intr(struct xhci_softc *sc)
3050 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3052 /* clear any old interrupt data */
3053 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3055 for (i = 1; i <= sc->sc_noport; i++) {
3056 /* pick out CHANGE bits from the status register */
3057 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3058 XHCI_PS_CSC | XHCI_PS_PEC |
3059 XHCI_PS_OCC | XHCI_PS_WRC |
3060 XHCI_PS_PRC | XHCI_PS_PLC |
3062 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3063 DPRINTF("port %d changed\n", i);
3066 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3067 sizeof(sc->sc_hub_idata));
3070 /*------------------------------------------------------------------------*
3071 * xhci_device_done - XHCI done handler
3073 * NOTE: This function can be called two times in a row on
3074 * the same USB transfer. From close and from interrupt.
3075 *------------------------------------------------------------------------*/
3077 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3079 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3080 xfer, xfer->endpoint, error);
3082 /* remove transfer from HW queue */
3083 xhci_transfer_remove(xfer, error);
3085 /* dequeue transfer and start next transfer */
3086 usbd_transfer_done(xfer, error);
3089 /*------------------------------------------------------------------------*
3090 * XHCI data transfer support (generic type)
3091 *------------------------------------------------------------------------*/
3093 xhci_device_generic_open(struct usb_xfer *xfer)
3095 if (xfer->flags_int.isochronous_xfr) {
3096 switch (xfer->xroot->udev->speed) {
3097 case USB_SPEED_FULL:
3100 usb_hs_bandwidth_alloc(xfer);
3107 xhci_device_generic_close(struct usb_xfer *xfer)
3111 xhci_device_done(xfer, USB_ERR_CANCELLED);
3113 if (xfer->flags_int.isochronous_xfr) {
3114 switch (xfer->xroot->udev->speed) {
3115 case USB_SPEED_FULL:
3118 usb_hs_bandwidth_free(xfer);
3125 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3126 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3128 struct usb_xfer *xfer;
3130 /* check if there is a current transfer */
3131 xfer = ep->endpoint_q[stream_id].curr;
3136 * Check if the current transfer is started and then pickup
3137 * the next one, if any. Else wait for next start event due to
3138 * block on failure feature.
3140 if (!xfer->flags_int.bandwidth_reclaimed)
3143 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3146 * In case of enter we have to consider that the
3147 * transfer is queued by the USB core after the enter
3156 /* try to multi buffer */
3157 xhci_transfer_insert(xfer);
3161 xhci_device_generic_enter(struct usb_xfer *xfer)
3165 /* set up TD's and QH */
3166 xhci_setup_generic_chain(xfer);
3168 xhci_device_generic_multi_enter(xfer->endpoint,
3169 xfer->stream_id, xfer);
3173 xhci_device_generic_start(struct usb_xfer *xfer)
3177 /* try to insert xfer on HW queue */
3178 xhci_transfer_insert(xfer);
3180 /* try to multi buffer */
3181 xhci_device_generic_multi_enter(xfer->endpoint,
3182 xfer->stream_id, NULL);
3184 /* add transfer last on interrupt queue */
3185 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3187 /* start timeout, if any */
3188 if (xfer->timeout != 0)
3189 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3192 struct usb_pipe_methods xhci_device_generic_methods =
3194 .open = xhci_device_generic_open,
3195 .close = xhci_device_generic_close,
3196 .enter = xhci_device_generic_enter,
3197 .start = xhci_device_generic_start,
3200 /*------------------------------------------------------------------------*
3201 * xhci root HUB support
3202 *------------------------------------------------------------------------*
3203 * Simulate a hardware HUB by handling all the necessary requests.
3204 *------------------------------------------------------------------------*/
3206 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3209 struct usb_device_descriptor xhci_devd =
3211 .bLength = sizeof(xhci_devd),
3212 .bDescriptorType = UDESC_DEVICE, /* type */
3213 HSETW(.bcdUSB, 0x0300), /* USB version */
3214 .bDeviceClass = UDCLASS_HUB, /* class */
3215 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3216 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3217 .bMaxPacketSize = 9, /* max packet size */
3218 HSETW(.idVendor, 0x0000), /* vendor */
3219 HSETW(.idProduct, 0x0000), /* product */
3220 HSETW(.bcdDevice, 0x0100), /* device version */
3224 .bNumConfigurations = 1, /* # of configurations */
3228 struct xhci_bos_desc xhci_bosd = {
3230 .bLength = sizeof(xhci_bosd.bosd),
3231 .bDescriptorType = UDESC_BOS,
3232 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3233 .bNumDeviceCaps = 3,
3236 .bLength = sizeof(xhci_bosd.usb2extd),
3237 .bDescriptorType = 1,
3238 .bDevCapabilityType = 2,
3239 .bmAttributes[0] = 2,
3242 .bLength = sizeof(xhci_bosd.usbdcd),
3243 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3244 .bDevCapabilityType = 3,
3245 .bmAttributes = 0, /* XXX */
3246 HSETW(.wSpeedsSupported, 0x000C),
3247 .bFunctionalitySupport = 8,
3248 .bU1DevExitLat = 255, /* dummy - not used */
3249 .wU2DevExitLat = { 0x00, 0x08 },
3252 .bLength = sizeof(xhci_bosd.cidd),
3253 .bDescriptorType = 1,
3254 .bDevCapabilityType = 4,
3256 .bContainerID = 0, /* XXX */
3261 struct xhci_config_desc xhci_confd = {
3263 .bLength = sizeof(xhci_confd.confd),
3264 .bDescriptorType = UDESC_CONFIG,
3265 .wTotalLength[0] = sizeof(xhci_confd),
3267 .bConfigurationValue = 1,
3268 .iConfiguration = 0,
3269 .bmAttributes = UC_SELF_POWERED,
3270 .bMaxPower = 0 /* max power */
3273 .bLength = sizeof(xhci_confd.ifcd),
3274 .bDescriptorType = UDESC_INTERFACE,
3276 .bInterfaceClass = UICLASS_HUB,
3277 .bInterfaceSubClass = UISUBCLASS_HUB,
3278 .bInterfaceProtocol = 0,
3281 .bLength = sizeof(xhci_confd.endpd),
3282 .bDescriptorType = UDESC_ENDPOINT,
3283 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3284 .bmAttributes = UE_INTERRUPT,
3285 .wMaxPacketSize[0] = 2, /* max 15 ports */
3289 .bLength = sizeof(xhci_confd.endpcd),
3290 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3297 struct usb_hub_ss_descriptor xhci_hubd = {
3298 .bLength = sizeof(xhci_hubd),
3299 .bDescriptorType = UDESC_SS_HUB,
3303 xhci_roothub_exec(struct usb_device *udev,
3304 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3306 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3307 const char *str_ptr;
3318 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3321 ptr = (const void *)&sc->sc_hub_desc;
3325 value = UGETW(req->wValue);
3326 index = UGETW(req->wIndex);
3328 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3329 "wValue=0x%04x wIndex=0x%04x\n",
3330 req->bmRequestType, req->bRequest,
3331 UGETW(req->wLength), value, index);
3333 #define C(x,y) ((x) | ((y) << 8))
3334 switch (C(req->bRequest, req->bmRequestType)) {
3335 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3336 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3337 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3339 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3340 * for the integrated root hub.
3343 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3345 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3347 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3348 switch (value >> 8) {
3350 if ((value & 0xff) != 0) {
3351 err = USB_ERR_IOERROR;
3354 len = sizeof(xhci_devd);
3355 ptr = (const void *)&xhci_devd;
3359 if ((value & 0xff) != 0) {
3360 err = USB_ERR_IOERROR;
3363 len = sizeof(xhci_bosd);
3364 ptr = (const void *)&xhci_bosd;
3368 if ((value & 0xff) != 0) {
3369 err = USB_ERR_IOERROR;
3372 len = sizeof(xhci_confd);
3373 ptr = (const void *)&xhci_confd;
3377 switch (value & 0xff) {
3378 case 0: /* Language table */
3382 case 1: /* Vendor */
3383 str_ptr = sc->sc_vendor;
3386 case 2: /* Product */
3387 str_ptr = "XHCI root HUB";
3395 len = usb_make_str_desc(
3396 sc->sc_hub_desc.temp,
3397 sizeof(sc->sc_hub_desc.temp),
3402 err = USB_ERR_IOERROR;
3406 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3408 sc->sc_hub_desc.temp[0] = 0;
3410 case C(UR_GET_STATUS, UT_READ_DEVICE):
3412 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3414 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3415 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3417 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3419 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3420 if (value >= XHCI_MAX_DEVICES) {
3421 err = USB_ERR_IOERROR;
3425 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3426 if (value != 0 && value != 1) {
3427 err = USB_ERR_IOERROR;
3430 sc->sc_conf = value;
3432 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3434 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3435 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3436 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3437 err = USB_ERR_IOERROR;
3439 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3441 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3444 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3446 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3447 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3450 (index > sc->sc_noport)) {
3451 err = USB_ERR_IOERROR;
3454 port = XHCI_PORTSC(index);
3456 v = XREAD4(sc, oper, port);
3457 i = XHCI_PS_PLS_GET(v);
3458 v &= ~XHCI_PS_CLEAR;
3461 case UHF_C_BH_PORT_RESET:
3462 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3464 case UHF_C_PORT_CONFIG_ERROR:
3465 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3467 case UHF_C_PORT_SUSPEND:
3468 case UHF_C_PORT_LINK_STATE:
3469 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3471 case UHF_C_PORT_CONNECTION:
3472 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3474 case UHF_C_PORT_ENABLE:
3475 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3477 case UHF_C_PORT_OVER_CURRENT:
3478 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3480 case UHF_C_PORT_RESET:
3481 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3483 case UHF_PORT_ENABLE:
3484 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3486 case UHF_PORT_POWER:
3487 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3489 case UHF_PORT_INDICATOR:
3490 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3492 case UHF_PORT_SUSPEND:
3496 XWRITE4(sc, oper, port, v |
3497 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3500 /* wait 20ms for resume sequence to complete */
3501 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3504 XWRITE4(sc, oper, port, v |
3505 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3508 err = USB_ERR_IOERROR;
3513 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3514 if ((value & 0xff) != 0) {
3515 err = USB_ERR_IOERROR;
3519 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3521 sc->sc_hub_desc.hubd = xhci_hubd;
3523 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3525 if (XHCI_HCS0_PPC(v))
3526 i = UHD_PWR_INDIVIDUAL;
3530 if (XHCI_HCS0_PIND(v))
3533 i |= UHD_OC_INDIVIDUAL;
3535 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3537 /* see XHCI section 5.4.9: */
3538 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3540 for (j = 1; j <= sc->sc_noport; j++) {
3542 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3543 if (v & XHCI_PS_DR) {
3544 sc->sc_hub_desc.hubd.
3545 DeviceRemovable[j / 8] |= 1U << (j % 8);
3548 len = sc->sc_hub_desc.hubd.bLength;
3551 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3553 memset(sc->sc_hub_desc.temp, 0, 16);
3556 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3557 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3560 (index > sc->sc_noport)) {
3561 err = USB_ERR_IOERROR;
3565 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3567 DPRINTFN(9, "port status=0x%08x\n", v);
3569 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3571 switch (XHCI_PS_SPEED_GET(v)) {
3573 i |= UPS_HIGH_SPEED;
3582 i |= UPS_OTHER_SPEED;
3586 if (v & XHCI_PS_CCS)
3587 i |= UPS_CURRENT_CONNECT_STATUS;
3588 if (v & XHCI_PS_PED)
3589 i |= UPS_PORT_ENABLED;
3590 if (v & XHCI_PS_OCA)
3591 i |= UPS_OVERCURRENT_INDICATOR;
3594 if (v & XHCI_PS_PP) {
3596 * The USB 3.0 RH is using the
3597 * USB 2.0's power bit
3599 i |= UPS_PORT_POWER;
3601 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3604 if (v & XHCI_PS_CSC)
3605 i |= UPS_C_CONNECT_STATUS;
3606 if (v & XHCI_PS_PEC)
3607 i |= UPS_C_PORT_ENABLED;
3608 if (v & XHCI_PS_OCC)
3609 i |= UPS_C_OVERCURRENT_INDICATOR;
3610 if (v & XHCI_PS_WRC)
3611 i |= UPS_C_BH_PORT_RESET;
3612 if (v & XHCI_PS_PRC)
3613 i |= UPS_C_PORT_RESET;
3614 if (v & XHCI_PS_PLC)
3615 i |= UPS_C_PORT_LINK_STATE;
3616 if (v & XHCI_PS_CEC)
3617 i |= UPS_C_PORT_CONFIG_ERROR;
3619 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3620 len = sizeof(sc->sc_hub_desc.ps);
3623 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3624 err = USB_ERR_IOERROR;
3627 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3630 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3636 (index > sc->sc_noport)) {
3637 err = USB_ERR_IOERROR;
3641 port = XHCI_PORTSC(index);
3642 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3645 case UHF_PORT_U1_TIMEOUT:
3646 if (XHCI_PS_SPEED_GET(v) != 4) {
3647 err = USB_ERR_IOERROR;
3650 port = XHCI_PORTPMSC(index);
3651 v = XREAD4(sc, oper, port);
3652 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3653 v |= XHCI_PM3_U1TO_SET(i);
3654 XWRITE4(sc, oper, port, v);
3656 case UHF_PORT_U2_TIMEOUT:
3657 if (XHCI_PS_SPEED_GET(v) != 4) {
3658 err = USB_ERR_IOERROR;
3661 port = XHCI_PORTPMSC(index);
3662 v = XREAD4(sc, oper, port);
3663 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3664 v |= XHCI_PM3_U2TO_SET(i);
3665 XWRITE4(sc, oper, port, v);
3667 case UHF_BH_PORT_RESET:
3668 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3670 case UHF_PORT_LINK_STATE:
3671 XWRITE4(sc, oper, port, v |
3672 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3673 /* 4ms settle time */
3674 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3676 case UHF_PORT_ENABLE:
3677 DPRINTFN(3, "set port enable %d\n", index);
3679 case UHF_PORT_SUSPEND:
3680 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3681 j = XHCI_PS_SPEED_GET(v);
3682 if ((j < 1) || (j > 3)) {
3683 /* non-supported speed */
3684 err = USB_ERR_IOERROR;
3687 XWRITE4(sc, oper, port, v |
3688 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3690 case UHF_PORT_RESET:
3691 DPRINTFN(6, "reset port %d\n", index);
3692 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3694 case UHF_PORT_POWER:
3695 DPRINTFN(3, "set port power %d\n", index);
3696 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3699 DPRINTFN(3, "set port test %d\n", index);
3701 case UHF_PORT_INDICATOR:
3702 DPRINTFN(3, "set port indicator %d\n", index);
3704 v &= ~XHCI_PS_PIC_SET(3);
3705 v |= XHCI_PS_PIC_SET(1);
3707 XWRITE4(sc, oper, port, v);
3710 err = USB_ERR_IOERROR;
3715 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3716 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3717 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3718 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3721 err = USB_ERR_IOERROR;
3731 xhci_xfer_setup(struct usb_setup_params *parm)
3733 struct usb_page_search page_info;
3734 struct usb_page_cache *pc;
3735 struct xhci_softc *sc;
3736 struct usb_xfer *xfer;
3741 sc = XHCI_BUS2SC(parm->udev->bus);
3742 xfer = parm->curr_xfer;
3745 * The proof for the "ntd" formula is illustrated like this:
3747 * +------------------------------------+
3751 * | | xxx | x | frm 0 |
3753 * | | xxx | xx | frm 1 |
3756 * +------------------------------------+
3758 * "xxx" means a completely full USB transfer descriptor
3760 * "x" and "xx" means a short USB packet
3762 * For the remainder of an USB transfer modulo
3763 * "max_data_length" we need two USB transfer descriptors.
3764 * One to transfer the remaining data and one to finalise with
3765 * a zero length packet in case the "force_short_xfer" flag is
3766 * set. We only need two USB transfer descriptors in the case
3767 * where the transfer length of the first one is a factor of
3768 * "max_frame_size". The rest of the needed USB transfer
3769 * descriptors is given by the buffer size divided by the
3770 * maximum data payload.
3772 parm->hc_max_packet_size = 0x400;
3773 parm->hc_max_packet_count = 16 * 3;
3774 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3776 xfer->flags_int.bdma_enable = 1;
3778 usbd_transfer_setup_sub(parm);
3780 if (xfer->flags_int.isochronous_xfr) {
3781 ntd = ((1 * xfer->nframes)
3782 + (xfer->max_data_length / xfer->max_hc_frame_size));
3783 } else if (xfer->flags_int.control_xfr) {
3784 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3785 + (xfer->max_data_length / xfer->max_hc_frame_size));
3787 ntd = ((2 * xfer->nframes)
3788 + (xfer->max_data_length / xfer->max_hc_frame_size));
3797 * Allocate queue heads and transfer descriptors
3801 if (usbd_transfer_setup_sub_malloc(
3802 parm, &pc, sizeof(struct xhci_td),
3803 XHCI_TD_ALIGN, ntd)) {
3804 parm->err = USB_ERR_NOMEM;
3808 for (n = 0; n != ntd; n++) {
3811 usbd_get_page(pc + n, 0, &page_info);
3813 td = page_info.buffer;
3816 td->td_self = page_info.physaddr;
3817 td->obj_next = last_obj;
3818 td->page_cache = pc + n;
3822 usb_pc_cpu_flush(pc + n);
3825 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3827 if (!xfer->flags_int.curr_dma_set) {
3828 xfer->flags_int.curr_dma_set = 1;
3834 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3836 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3837 struct usb_page_search buf_inp;
3838 struct usb_device *udev;
3839 struct xhci_endpoint_ext *pepext;
3840 struct usb_endpoint_descriptor *edesc;
3841 struct usb_page_cache *pcinp;
3843 usb_stream_t stream_id;
3848 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3849 xfer->endpoint->edesc);
3851 udev = xfer->xroot->udev;
3852 index = udev->controller_slot_id;
3854 pcinp = &sc->sc_hw.devs[index].input_pc;
3856 usbd_get_page(pcinp, 0, &buf_inp);
3858 edesc = xfer->endpoint->edesc;
3860 epno = edesc->bEndpointAddress;
3861 stream_id = xfer->stream_id;
3863 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3866 epno = XHCI_EPNO2EPID(epno);
3869 return (USB_ERR_NO_PIPE); /* invalid */
3873 /* configure endpoint */
3875 err = xhci_configure_endpoint_by_xfer(xfer);
3878 XHCI_CMD_UNLOCK(sc);
3883 * Get the endpoint into the stopped state according to the
3884 * endpoint context state diagram in the XHCI specification:
3887 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3890 DPRINTF("Could not stop endpoint %u\n", epno);
3892 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3895 DPRINTF("Could not reset endpoint %u\n", epno);
3897 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3898 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3899 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3900 stream_id, epno, index);
3903 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3906 * Get the endpoint into the running state according to the
3907 * endpoint context state diagram in the XHCI specification:
3910 mask = (1U << epno);
3911 xhci_configure_mask(udev, mask | 1U, 0);
3913 if (!(sc->sc_hw.devs[index].ep_configured & mask)) {
3914 sc->sc_hw.devs[index].ep_configured |= mask;
3915 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3917 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3921 DPRINTF("Could not configure "
3922 "endpoint %u at slot %u.\n", epno, index);
3924 XHCI_CMD_UNLOCK(sc);
3930 xhci_xfer_unsetup(struct usb_xfer *xfer)
3936 xhci_start_dma_delay(struct usb_xfer *xfer)
3938 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3940 /* put transfer on interrupt queue (again) */
3941 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3943 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3944 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3948 xhci_configure_msg(struct usb_proc_msg *pm)
3950 struct xhci_softc *sc;
3951 struct xhci_endpoint_ext *pepext;
3952 struct usb_xfer *xfer;
3954 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3957 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3959 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3960 xfer->endpoint->edesc);
3962 if ((pepext->trb_halted != 0) ||
3963 (pepext->trb_running == 0)) {
3967 /* clear halted and running */
3968 pepext->trb_halted = 0;
3969 pepext->trb_running = 0;
3971 /* nuke remaining buffered transfers */
3973 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3974 XHCI_MAX_STREAMS); i++) {
3976 * NOTE: We need to use the timeout
3977 * error code here else existing
3978 * isochronous clients can get
3981 if (pepext->xfer[i] != NULL) {
3982 xhci_device_done(pepext->xfer[i],
3988 * NOTE: The USB transfer cannot vanish in
3992 USB_BUS_UNLOCK(&sc->sc_bus);
3994 xhci_configure_reset_endpoint(xfer);
3996 USB_BUS_LOCK(&sc->sc_bus);
3998 /* check if halted is still cleared */
3999 if (pepext->trb_halted == 0) {
4000 pepext->trb_running = 1;
4001 memset(pepext->trb_index, 0,
4002 sizeof(pepext->trb_index));
4007 if (xfer->flags_int.did_dma_delay) {
4009 /* remove transfer from interrupt queue (again) */
4010 usbd_transfer_dequeue(xfer);
4012 /* we are finally done */
4013 usb_dma_delay_done_cb(xfer);
4015 /* queue changed - restart */
4020 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4022 /* try to insert xfer on HW queue */
4023 xhci_transfer_insert(xfer);
4025 /* try to multi buffer */
4026 xhci_device_generic_multi_enter(xfer->endpoint,
4027 xfer->stream_id, NULL);
4032 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4033 struct usb_endpoint *ep)
4035 struct xhci_endpoint_ext *pepext;
4037 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4038 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4040 if (udev->parent_hub == NULL) {
4041 /* root HUB has special endpoint handling */
4045 ep->methods = &xhci_device_generic_methods;
4047 pepext = xhci_get_endpoint_ext(udev, edesc);
4049 USB_BUS_LOCK(udev->bus);
4050 pepext->trb_halted = 1;
4051 pepext->trb_running = 0;
4052 USB_BUS_UNLOCK(udev->bus);
4056 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4062 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4064 struct xhci_endpoint_ext *pepext;
4068 if (udev->flags.usb_mode != USB_MODE_HOST) {
4072 if (udev->parent_hub == NULL) {
4073 /* root HUB has special endpoint handling */
4077 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4079 USB_BUS_LOCK(udev->bus);
4080 pepext->trb_halted = 1;
4081 pepext->trb_running = 0;
4082 USB_BUS_UNLOCK(udev->bus);
4086 xhci_device_init(struct usb_device *udev)
4088 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4092 /* no init for root HUB */
4093 if (udev->parent_hub == NULL)
4098 /* set invalid default */
4100 udev->controller_slot_id = sc->sc_noslot + 1;
4102 /* try to get a new slot ID from the XHCI */
4104 err = xhci_cmd_enable_slot(sc, &temp);
4107 XHCI_CMD_UNLOCK(sc);
4111 if (temp > sc->sc_noslot) {
4112 XHCI_CMD_UNLOCK(sc);
4113 return (USB_ERR_BAD_ADDRESS);
4116 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4117 DPRINTF("slot %u already allocated.\n", temp);
4118 XHCI_CMD_UNLOCK(sc);
4119 return (USB_ERR_BAD_ADDRESS);
4122 /* store slot ID for later reference */
4124 udev->controller_slot_id = temp;
4126 /* reset data structure */
4128 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4130 /* set mark slot allocated */
4132 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4134 err = xhci_alloc_device_ext(udev);
4136 XHCI_CMD_UNLOCK(sc);
4138 /* get device into default state */
4141 err = xhci_set_address(udev, NULL, 0);
4147 xhci_device_uninit(struct usb_device *udev)
4149 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4152 /* no init for root HUB */
4153 if (udev->parent_hub == NULL)
4158 index = udev->controller_slot_id;
4160 if (index <= sc->sc_noslot) {
4161 xhci_cmd_disable_slot(sc, index);
4162 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4164 /* free device extension */
4165 xhci_free_device_ext(udev);
4168 XHCI_CMD_UNLOCK(sc);
4172 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4175 * Wait until the hardware has finished any possible use of
4176 * the transfer descriptor(s)
4178 *pus = 2048; /* microseconds */
4182 xhci_device_resume(struct usb_device *udev)
4184 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4191 /* check for root HUB */
4192 if (udev->parent_hub == NULL)
4195 index = udev->controller_slot_id;
4199 /* blindly resume all endpoints */
4201 USB_BUS_LOCK(udev->bus);
4203 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4204 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4205 XWRITE4(sc, door, XHCI_DOORBELL(index),
4206 n | XHCI_DB_SID_SET(p));
4210 USB_BUS_UNLOCK(udev->bus);
4212 XHCI_CMD_UNLOCK(sc);
4216 xhci_device_suspend(struct usb_device *udev)
4218 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4225 /* check for root HUB */
4226 if (udev->parent_hub == NULL)
4229 index = udev->controller_slot_id;
4233 /* blindly suspend all endpoints */
4235 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4236 err = xhci_cmd_stop_ep(sc, 1, n, index);
4238 DPRINTF("Failed to suspend endpoint "
4239 "%u on slot %u (ignored).\n", n, index);
4243 XHCI_CMD_UNLOCK(sc);
4247 xhci_set_hw_power(struct usb_bus *bus)
4253 xhci_device_state_change(struct usb_device *udev)
4255 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4256 struct usb_page_search buf_inp;
4260 /* check for root HUB */
4261 if (udev->parent_hub == NULL)
4264 index = udev->controller_slot_id;
4268 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4269 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4270 &sc->sc_hw.devs[index].tt);
4272 sc->sc_hw.devs[index].nports = 0;
4277 switch (usb_get_device_state(udev)) {
4278 case USB_STATE_POWERED:
4279 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4282 /* set default state */
4283 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4284 sc->sc_hw.devs[index].ep_configured = 3U;
4286 /* reset number of contexts */
4287 sc->sc_hw.devs[index].context_num = 0;
4289 err = xhci_cmd_reset_dev(sc, index);
4292 DPRINTF("Device reset failed "
4293 "for slot %u.\n", index);
4297 case USB_STATE_ADDRESSED:
4298 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4301 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4302 sc->sc_hw.devs[index].ep_configured = 3U;
4304 /* set configure mask to slot only */
4305 xhci_configure_mask(udev, 1, 0);
4307 /* deconfigure all endpoints, except EP0 */
4308 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4311 DPRINTF("Failed to deconfigure "
4312 "slot %u.\n", index);
4316 case USB_STATE_CONFIGURED:
4317 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) {
4318 /* deconfigure all endpoints, except EP0 */
4319 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4322 DPRINTF("Failed to deconfigure "
4323 "slot %u.\n", index);
4327 /* set configured state */
4328 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4329 sc->sc_hw.devs[index].ep_configured = 3U;
4331 /* reset number of contexts */
4332 sc->sc_hw.devs[index].context_num = 0;
4334 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4336 xhci_configure_mask(udev, 3, 0);
4338 err = xhci_configure_device(udev);
4340 DPRINTF("Could not configure device "
4341 "at slot %u.\n", index);
4344 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4346 DPRINTF("Could not evaluate device "
4347 "context at slot %u.\n", index);
4354 XHCI_CMD_UNLOCK(sc);
4358 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4362 case USB_EP_MODE_DEFAULT:
4364 case USB_EP_MODE_STREAMS:
4365 if (xhcistreams == 0 ||
4366 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4367 udev->speed != USB_SPEED_SUPER)
4368 return (USB_ERR_INVAL);
4371 return (USB_ERR_INVAL);
4375 struct usb_bus_methods xhci_bus_methods = {
4376 .endpoint_init = xhci_ep_init,
4377 .endpoint_uninit = xhci_ep_uninit,
4378 .xfer_setup = xhci_xfer_setup,
4379 .xfer_unsetup = xhci_xfer_unsetup,
4380 .get_dma_delay = xhci_get_dma_delay,
4381 .device_init = xhci_device_init,
4382 .device_uninit = xhci_device_uninit,
4383 .device_resume = xhci_device_resume,
4384 .device_suspend = xhci_device_suspend,
4385 .set_hw_power = xhci_set_hw_power,
4386 .roothub_exec = xhci_roothub_exec,
4387 .xfer_poll = xhci_do_poll,
4388 .start_dma_delay = xhci_start_dma_delay,
4389 .set_address = xhci_set_address,
4390 .clear_stall = xhci_ep_clear_stall,
4391 .device_state_change = xhci_device_state_change,
4392 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4393 .set_endpoint_mode = xhci_set_endpoint_mode,