sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  29  *
  30  * The XHCI 1.0 spec can be found at
  31  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  32  * and the USB 3.0 spec at
  33  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  34  */
  35
  36 /*
  37  * A few words about the design implementation: This driver emulates
  38  * the concept about TDs which is found in EHCI specification. This
  39  * way we achieve that the USB controller drivers look similar to
  40  * eachother which makes it easier to understand the code.
  41  */
  42
  43 #ifdef USB_GLOBAL_INCLUDE_FILE
  44 #include USB_GLOBAL_INCLUDE_FILE
  45 #else
  46 #include <sys/stdint.h>
  47 #include <sys/stddef.h>
  48 #include <sys/param.h>
  49 #include <sys/queue.h>
  50 #include <sys/types.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/bus.h>
  54 #include <sys/module.h>
  55 #include <sys/lock.h>
  56 #include <sys/mutex.h>
  57 #include <sys/condvar.h>
  58 #include <sys/sysctl.h>
  59 #include <sys/sx.h>
  60 #include <sys/unistd.h>
  61 #include <sys/callout.h>
  62 #include <sys/malloc.h>
  63 #include <sys/priv.h>
  64
  65 #include <dev/usb/usb.h>
  66 #include <dev/usb/usbdi.h>
  67
  68 #define USB_DEBUG_VAR xhcidebug
  69
  70 #include <dev/usb/usb_core.h>
  71 #include <dev/usb/usb_debug.h>
  72 #include <dev/usb/usb_busdma.h>
  73 #include <dev/usb/usb_process.h>
  74 #include <dev/usb/usb_transfer.h>
  75 #include <dev/usb/usb_device.h>
  76 #include <dev/usb/usb_hub.h>
  77 #include <dev/usb/usb_util.h>
  78
  79 #include <dev/usb/usb_controller.h>
  80 #include <dev/usb/usb_bus.h>
  81 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  82
  83 #include <dev/usb/controller/xhci.h>
  84 #include <dev/usb/controller/xhcireg.h>
  85
  86 #define XHCI_BUS2SC(bus) \
  87    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  88     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  89
  90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91
  92 static int xhcistreams;
  93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
  94     &xhcistreams, 0, "Set to enable streams mode support");
  95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
  96
  97 #ifdef USB_DEBUG
  98 static int xhcidebug;
  99 static int xhciroute;
 100 static int xhcipolling;
 101
 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
 103     &xhcidebug, 0, "Debug level");
 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
 106     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
 109     &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 111 #else
 112 #define xhciroute 0
 113 #endif
 114
 115 #define XHCI_INTR_ENDPT 1
 116
 117 struct xhci_std_temp {
 118         struct xhci_softc       *sc;
 119         struct usb_page_cache   *pc;
 120         struct xhci_td          *td;
 121         struct xhci_td          *td_next;
 122         uint32_t                len;
 123         uint32_t                offset;
 124         uint32_t                max_packet_size;
 125         uint32_t                average;
 126         uint16_t                isoc_delta;
 127         uint16_t                isoc_frame;
 128         uint8_t                 shortpkt;
 129         uint8_t                 multishort;
 130         uint8_t                 last_frame;
 131         uint8_t                 trb_type;
 132         uint8_t                 direction;
 133         uint8_t                 tbc;
 134         uint8_t                 tlbpc;
 135         uint8_t                 step_td;
 136         uint8_t                 do_isoc_sync;
 137 };
 138
 139 static void     xhci_do_poll(struct usb_bus *);
 140 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 141 static void     xhci_root_intr(struct xhci_softc *);
 142 static void     xhci_free_device_ext(struct usb_device *);
 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 144                     struct usb_endpoint_descriptor *);
 145 static usb_proc_callback_t xhci_configure_msg;
 146 static usb_error_t xhci_configure_device(struct usb_device *);
 147 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 148                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 149                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 150                    uint8_t);
 151 static usb_error_t xhci_configure_mask(struct usb_device *,
 152                     uint32_t, uint8_t);
 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 154                     uint64_t, uint8_t);
 155 static void xhci_endpoint_doorbell(struct usb_xfer *);
 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 159 #ifdef USB_DEBUG
 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 161 #endif
 162
 163 extern struct usb_bus_methods xhci_bus_methods;
 164
 165 #ifdef USB_DEBUG
 166 static void
 167 xhci_dump_trb(struct xhci_trb *trb)
 168 {
 169         DPRINTFN(5, "trb = %p\n", trb);
 170         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 171         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 172         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 173 }
 174
 175 static void
 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 177 {
 178         DPRINTFN(5, "pep = %p\n", pep);
 179         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 180         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 181         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 182         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 183         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 184         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 185         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 186 }
 187
 188 static void
 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 190 {
 191         DPRINTFN(5, "psl = %p\n", psl);
 192         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 193         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 194         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 195         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 196 }
 197 #endif
 198
 199 uint8_t
 200 xhci_use_polling(void)
 201 {
 202 #ifdef USB_DEBUG
 203         return (xhcipolling != 0);
 204 #else
 205         return (0);
 206 #endif
 207 }
 208
 209 static void
 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 211 {
 212         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 213         uint8_t i;
 214
 215         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 216            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 217
 218         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 219            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 220
 221         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 222                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 223                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 224         }
 225 }
 226
 227 static void
 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 229 {
 230         if (sc->sc_ctx_is_64_byte) {
 231                 uint32_t offset;
 232                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 233                 /* all contexts are initially 32-bytes */
 234                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 235                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 236         }
 237         *ptr = htole32(val);
 238 }
 239
 240 static uint32_t
 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 242 {
 243         if (sc->sc_ctx_is_64_byte) {
 244                 uint32_t offset;
 245                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 246                 /* all contexts are initially 32-bytes */
 247                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 248                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 249         }
 250         return (le32toh(*ptr));
 251 }
 252
 253 static void
 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 255 {
 256         if (sc->sc_ctx_is_64_byte) {
 257                 uint32_t offset;
 258                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 259                 /* all contexts are initially 32-bytes */
 260                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 261                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 262         }
 263         *ptr = htole64(val);
 264 }
 265
 266 #ifdef USB_DEBUG
 267 static uint64_t
 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 269 {
 270         if (sc->sc_ctx_is_64_byte) {
 271                 uint32_t offset;
 272                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 273                 /* all contexts are initially 32-bytes */
 274                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 275                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 276         }
 277         return (le64toh(*ptr));
 278 }
 279 #endif
 280
 281 static int
 282 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 283 {
 284         struct usb_page_search buf_res;
 285         struct xhci_hw_root *phwr;
 286         uint64_t addr;
 287         uint32_t temp;
 288
 289         DPRINTF("\n");
 290
 291         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 292         if (temp & XHCI_CRCR_LO_CRR) {
 293                 DPRINTF("Command ring running\n");
 294                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 295
 296                 /*
 297                  * Try to abort the last command as per section
 298                  * 4.6.1.2 "Aborting a Command" of the XHCI
 299                  * specification:
 300                  */
 301
 302                 /* stop and cancel */
 303                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 304                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 305
 306                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 307                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 308
 309                 /* wait 250ms */
 310                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 311
 312                 /* check if command ring is still running */
 313                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 314                 if (temp & XHCI_CRCR_LO_CRR) {
 315                         DPRINTF("Comand ring still running\n");
 316                         return (USB_ERR_IOERROR);
 317                 }
 318         }
 319
 320         /* reset command ring */
 321         sc->sc_command_ccs = 1;
 322         sc->sc_command_idx = 0;
 323
 324         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 325
 326         /* setup command ring control base address */
 327         addr = buf_res.physaddr;
 328         phwr = buf_res.buffer;
 329         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 330
 331         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 332
 333         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 334         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 335
 336         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 337
 338         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 339         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 340
 341         return (0);
 342 }
 343
 344 usb_error_t
 345 xhci_start_controller(struct xhci_softc *sc)
 346 {
 347         struct usb_page_search buf_res;
 348         struct xhci_hw_root *phwr;
 349         struct xhci_dev_ctx_addr *pdctxa;
 350         uint64_t addr;
 351         uint32_t temp;
 352         uint16_t i;
 353
 354         DPRINTF("\n");
 355
 356         sc->sc_capa_off = 0;
 357         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 358         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 359         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 360
 361         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 362         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 363         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 364
 365         sc->sc_event_ccs = 1;
 366         sc->sc_event_idx = 0;
 367         sc->sc_command_ccs = 1;
 368         sc->sc_command_idx = 0;
 369
 370         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 371
 372         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 373
 374         DPRINTF("HCS0 = 0x%08x\n", temp);
 375
 376         if (XHCI_HCS0_CSZ(temp)) {
 377                 sc->sc_ctx_is_64_byte = 1;
 378                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 379         } else {
 380                 sc->sc_ctx_is_64_byte = 0;
 381                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 382         }
 383
 384         /* Reset controller */
 385         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 386
 387         for (i = 0; i != 100; i++) {
 388                 usb_pause_mtx(NULL, hz / 100);
 389                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 390                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 391                 if (!temp)
 392                         break;
 393         }
 394
 395         if (temp) {
 396                 device_printf(sc->sc_bus.parent, "Controller "
 397                     "reset timeout.\n");
 398                 return (USB_ERR_IOERROR);
 399         }
 400
 401         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 402                 device_printf(sc->sc_bus.parent, "Controller does "
 403                     "not support 4K page size.\n");
 404                 return (USB_ERR_IOERROR);
 405         }
 406
 407         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 408
 409         i = XHCI_HCS1_N_PORTS(temp);
 410
 411         if (i == 0) {
 412                 device_printf(sc->sc_bus.parent, "Invalid number "
 413                     "of ports: %u\n", i);
 414                 return (USB_ERR_IOERROR);
 415         }
 416
 417         sc->sc_noport = i;
 418         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 419
 420         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 421                 sc->sc_noslot = XHCI_MAX_DEVICES;
 422
 423         /* setup number of device slots */
 424
 425         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 426             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 427
 428         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 429
 430         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 431
 432         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 433
 434         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 435
 436         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 437                 device_printf(sc->sc_bus.parent, "XHCI request "
 438                     "too many scratchpads\n");
 439                 return (USB_ERR_NOMEM);
 440         }
 441
 442         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 443
 444         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 445
 446         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 447             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 448
 449         temp = XREAD4(sc, oper, XHCI_USBSTS);
 450
 451         /* clear interrupts */
 452         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 453         /* disable all device notifications */
 454         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 455
 456         /* setup device context base address */
 457         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 458         pdctxa = buf_res.buffer;
 459         memset(pdctxa, 0, sizeof(*pdctxa));
 460
 461         addr = buf_res.physaddr;
 462         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 463
 464         /* slot 0 points to the table of scratchpad pointers */
 465         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 466
 467         for (i = 0; i != sc->sc_noscratch; i++) {
 468                 struct usb_page_search buf_scp;
 469                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 470                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 471         }
 472
 473         addr = buf_res.physaddr;
 474
 475         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 476         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 477         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 478         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 479
 480         /* Setup event table size */
 481
 482         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 483
 484         DPRINTF("HCS2=0x%08x\n", temp);
 485
 486         temp = XHCI_HCS2_ERST_MAX(temp);
 487         temp = 1U << temp;
 488         if (temp > XHCI_MAX_RSEG)
 489                 temp = XHCI_MAX_RSEG;
 490
 491         sc->sc_erst_max = temp;
 492
 493         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 494             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 495
 496         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 497
 498         /* Check if we should use the default IMOD value */
 499         if (sc->sc_imod_default == 0)
 500                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 501
 502         /* Setup interrupt rate */
 503         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 504
 505         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 506
 507         phwr = buf_res.buffer;
 508         addr = buf_res.physaddr;
 509         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 510
 511         /* reset hardware root structure */
 512         memset(phwr, 0, sizeof(*phwr));
 513
 514         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 515         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 516
 517         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 518
 519         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 520         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 521
 522         addr = (uint64_t)buf_res.physaddr;
 523
 524         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 525
 526         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 527         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 528
 529         /* Setup interrupter registers */
 530
 531         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 532         temp |= XHCI_IMAN_INTR_ENA;
 533         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 534
 535         /* setup command ring control base address */
 536         addr = buf_res.physaddr;
 537         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 538
 539         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 540
 541         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 542         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 543
 544         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 545
 546         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 547
 548         /* Go! */
 549         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 550             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 551
 552         for (i = 0; i != 100; i++) {
 553                 usb_pause_mtx(NULL, hz / 100);
 554                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 555                 if (!temp)
 556                         break;
 557         }
 558         if (temp) {
 559                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 560                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 561                 return (USB_ERR_IOERROR);
 562         }
 563
 564         /* catch any lost interrupts */
 565         xhci_do_poll(&sc->sc_bus);
 566
 567         if (sc->sc_port_route != NULL) {
 568                 /* Route all ports to the XHCI by default */
 569                 sc->sc_port_route(sc->sc_bus.parent,
 570                     ~xhciroute, xhciroute);
 571         }
 572         return (0);
 573 }
 574
 575 usb_error_t
 576 xhci_halt_controller(struct xhci_softc *sc)
 577 {
 578         uint32_t temp;
 579         uint16_t i;
 580
 581         DPRINTF("\n");
 582
 583         sc->sc_capa_off = 0;
 584         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 585         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 586         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 587
 588         /* Halt controller */
 589         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 590
 591         for (i = 0; i != 100; i++) {
 592                 usb_pause_mtx(NULL, hz / 100);
 593                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 594                 if (temp)
 595                         break;
 596         }
 597
 598         if (!temp) {
 599                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 600                 return (USB_ERR_IOERROR);
 601         }
 602         return (0);
 603 }
 604
 605 usb_error_t
 606 xhci_init(struct xhci_softc *sc, device_t self)
 607 {
 608         /* initialise some bus fields */
 609         sc->sc_bus.parent = self;
 610
 611         /* set the bus revision */
 612         sc->sc_bus.usbrev = USB_REV_3_0;
 613
 614         /* set up the bus struct */
 615         sc->sc_bus.methods = &xhci_bus_methods;
 616
 617         /* setup devices array */
 618         sc->sc_bus.devices = sc->sc_devices;
 619         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 620
 621         /* set default cycle state in case of early interrupts */
 622         sc->sc_event_ccs = 1;
 623         sc->sc_command_ccs = 1;
 624
 625         /* setup command queue mutex and condition varible */
 626         cv_init(&sc->sc_cmd_cv, "CMDQ");
 627         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 628
 629         /* get all DMA memory */
 630         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 631             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 632                 return (ENOMEM);
 633         }
 634
 635         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 636         sc->sc_config_msg[0].bus = &sc->sc_bus;
 637         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 638         sc->sc_config_msg[1].bus = &sc->sc_bus;
 639
 640         return (0);
 641 }
 642
 643 void
 644 xhci_uninit(struct xhci_softc *sc)
 645 {
 646         /*
 647          * NOTE: At this point the control transfer process is gone
 648          * and "xhci_configure_msg" is no longer called. Consequently
 649          * waiting for the configuration messages to complete is not
 650          * needed.
 651          */
 652         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 653
 654         cv_destroy(&sc->sc_cmd_cv);
 655         sx_destroy(&sc->sc_cmd_sx);
 656 }
 657
 658 static void
 659 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 660 {
 661         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 662
 663         switch (state) {
 664         case USB_HW_POWER_SUSPEND:
 665                 DPRINTF("Stopping the XHCI\n");
 666                 xhci_halt_controller(sc);
 667                 break;
 668         case USB_HW_POWER_SHUTDOWN:
 669                 DPRINTF("Stopping the XHCI\n");
 670                 xhci_halt_controller(sc);
 671                 break;
 672         case USB_HW_POWER_RESUME:
 673                 DPRINTF("Starting the XHCI\n");
 674                 xhci_start_controller(sc);
 675                 break;
 676         default:
 677                 break;
 678         }
 679 }
 680
 681 static usb_error_t
 682 xhci_generic_done_sub(struct usb_xfer *xfer)
 683 {
 684         struct xhci_td *td;
 685         struct xhci_td *td_alt_next;
 686         uint32_t len;
 687         uint8_t status;
 688
 689         td = xfer->td_transfer_cache;
 690         td_alt_next = td->alt_next;
 691
 692         if (xfer->aframes != xfer->nframes)
 693                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 694
 695         while (1) {
 696
 697                 usb_pc_cpu_invalidate(td->page_cache);
 698
 699                 status = td->status;
 700                 len = td->remainder;
 701
 702                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 703                     xfer, (unsigned int)xfer->aframes,
 704                     (unsigned int)xfer->nframes,
 705                     (unsigned int)len, (unsigned int)td->len,
 706                     (unsigned int)status);
 707
 708                 /*
 709                  * Verify the status length and
 710                  * add the length to "frlengths[]":
 711                  */
 712                 if (len > td->len) {
 713                         /* should not happen */
 714                         DPRINTF("Invalid status length, "
 715                             "0x%04x/0x%04x bytes\n", len, td->len);
 716                         status = XHCI_TRB_ERROR_LENGTH;
 717                 } else if (xfer->aframes != xfer->nframes) {
 718                         xfer->frlengths[xfer->aframes] += td->len - len;
 719                 }
 720                 /* Check for last transfer */
 721                 if (((void *)td) == xfer->td_transfer_last) {
 722                         td = NULL;
 723                         break;
 724                 }
 725                 /* Check for transfer error */
 726                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 727                     status != XHCI_TRB_ERROR_SUCCESS) {
 728                         /* the transfer is finished */
 729                         td = NULL;
 730                         break;
 731                 }
 732                 /* Check for short transfer */
 733                 if (len > 0) {
 734                         if (xfer->flags_int.short_frames_ok ||
 735                             xfer->flags_int.isochronous_xfr ||
 736                             xfer->flags_int.control_xfr) {
 737                                 /* follow alt next */
 738                                 td = td->alt_next;
 739                         } else {
 740                                 /* the transfer is finished */
 741                                 td = NULL;
 742                         }
 743                         break;
 744                 }
 745                 td = td->obj_next;
 746
 747                 if (td->alt_next != td_alt_next) {
 748                         /* this USB frame is complete */
 749                         break;
 750                 }
 751         }
 752
 753         /* update transfer cache */
 754
 755         xfer->td_transfer_cache = td;
 756
 757         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 758             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 759             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 760             USB_ERR_NORMAL_COMPLETION);
 761 }
 762
 763 static void
 764 xhci_generic_done(struct usb_xfer *xfer)
 765 {
 766         usb_error_t err = 0;
 767
 768         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 769             xfer, xfer->endpoint);
 770
 771         /* reset scanner */
 772
 773         xfer->td_transfer_cache = xfer->td_transfer_first;
 774
 775         if (xfer->flags_int.control_xfr) {
 776
 777                 if (xfer->flags_int.control_hdr)
 778                         err = xhci_generic_done_sub(xfer);
 779
 780                 xfer->aframes = 1;
 781
 782                 if (xfer->td_transfer_cache == NULL)
 783                         goto done;
 784         }
 785
 786         while (xfer->aframes != xfer->nframes) {
 787
 788                 err = xhci_generic_done_sub(xfer);
 789                 xfer->aframes++;
 790
 791                 if (xfer->td_transfer_cache == NULL)
 792                         goto done;
 793         }
 794
 795         if (xfer->flags_int.control_xfr &&
 796             !xfer->flags_int.control_act)
 797                 err = xhci_generic_done_sub(xfer);
 798 done:
 799         /* transfer is complete */
 800         xhci_device_done(xfer, err);
 801 }
 802
 803 static void
 804 xhci_activate_transfer(struct usb_xfer *xfer)
 805 {
 806         struct xhci_td *td;
 807
 808         td = xfer->td_transfer_cache;
 809
 810         usb_pc_cpu_invalidate(td->page_cache);
 811
 812         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 813
 814                 /* activate the transfer */
 815
 816                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 817                 usb_pc_cpu_flush(td->page_cache);
 818
 819                 xhci_endpoint_doorbell(xfer);
 820         }
 821 }
 822
 823 static void
 824 xhci_skip_transfer(struct usb_xfer *xfer)
 825 {
 826         struct xhci_td *td;
 827         struct xhci_td *td_last;
 828
 829         td = xfer->td_transfer_cache;
 830         td_last = xfer->td_transfer_last;
 831
 832         td = td->alt_next;
 833
 834         usb_pc_cpu_invalidate(td->page_cache);
 835
 836         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 837
 838                 usb_pc_cpu_invalidate(td_last->page_cache);
 839
 840                 /* copy LINK TRB to current waiting location */
 841
 842                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 843                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 844                 usb_pc_cpu_flush(td->page_cache);
 845
 846                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 847                 usb_pc_cpu_flush(td->page_cache);
 848
 849                 xhci_endpoint_doorbell(xfer);
 850         }
 851 }
 852
 853 /*------------------------------------------------------------------------*
 854  *      xhci_check_transfer
 855  *------------------------------------------------------------------------*/
 856 static void
 857 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 858 {
 859         struct xhci_endpoint_ext *pepext;
 860         int64_t offset;
 861         uint64_t td_event;
 862         uint32_t temp;
 863         uint32_t remainder;
 864         uint16_t stream_id;
 865         uint16_t i;
 866         uint8_t status;
 867         uint8_t halted;
 868         uint8_t epno;
 869         uint8_t index;
 870
 871         /* decode TRB */
 872         td_event = le64toh(trb->qwTrb0);
 873         temp = le32toh(trb->dwTrb2);
 874
 875         remainder = XHCI_TRB_2_REM_GET(temp);
 876         status = XHCI_TRB_2_ERROR_GET(temp);
 877         stream_id = XHCI_TRB_2_STREAM_GET(temp);
 878
 879         temp = le32toh(trb->dwTrb3);
 880         epno = XHCI_TRB_3_EP_GET(temp);
 881         index = XHCI_TRB_3_SLOT_GET(temp);
 882
 883         /* check if error means halted */
 884         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 885             status != XHCI_TRB_ERROR_SUCCESS);
 886
 887         DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
 888             index, epno, stream_id, remainder, status);
 889
 890         if (index > sc->sc_noslot) {
 891                 DPRINTF("Invalid slot.\n");
 892                 return;
 893         }
 894
 895         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 896                 DPRINTF("Invalid endpoint.\n");
 897                 return;
 898         }
 899
 900         pepext = &sc->sc_hw.devs[index].endp[epno];
 901
 902         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
 903                 stream_id = 0;
 904                 DPRINTF("stream_id=0\n");
 905         } else if (stream_id >= XHCI_MAX_STREAMS) {
 906                 DPRINTF("Invalid stream ID.\n");
 907                 return;
 908         }
 909
 910         /* try to find the USB transfer that generated the event */
 911         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 912                 struct usb_xfer *xfer;
 913                 struct xhci_td *td;
 914
 915                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 916                 if (xfer == NULL)
 917                         continue;
 918
 919                 td = xfer->td_transfer_cache;
 920
 921                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 922                         (long long)td_event,
 923                         (long long)td->td_self,
 924                         (long long)td->td_self + sizeof(td->td_trb));
 925
 926                 /*
 927                  * NOTE: Some XHCI implementations might not trigger
 928                  * an event on the last LINK TRB so we need to
 929                  * consider both the last and second last event
 930                  * address as conditions for a successful transfer.
 931                  *
 932                  * NOTE: We assume that the XHCI will only trigger one
 933                  * event per chain of TRBs.
 934                  */
 935
 936                 offset = td_event - td->td_self;
 937
 938                 if (offset >= 0 &&
 939                     offset < (int64_t)sizeof(td->td_trb)) {
 940
 941                         usb_pc_cpu_invalidate(td->page_cache);
 942
 943                         /* compute rest of remainder, if any */
 944                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 945                                 temp = le32toh(td->td_trb[i].dwTrb2);
 946                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 947                         }
 948
 949                         DPRINTFN(5, "New remainder: %u\n", remainder);
 950
 951                         /* clear isochronous transfer errors */
 952                         if (xfer->flags_int.isochronous_xfr) {
 953                                 if (halted) {
 954                                         halted = 0;
 955                                         status = XHCI_TRB_ERROR_SUCCESS;
 956                                         remainder = td->len;
 957                                 }
 958                         }
 959
 960                         /* "td->remainder" is verified later */
 961                         td->remainder = remainder;
 962                         td->status = status;
 963
 964                         usb_pc_cpu_flush(td->page_cache);
 965
 966                         /*
 967                          * 1) Last transfer descriptor makes the
 968                          * transfer done
 969                          */
 970                         if (((void *)td) == xfer->td_transfer_last) {
 971                                 DPRINTF("TD is last\n");
 972                                 xhci_generic_done(xfer);
 973                                 break;
 974                         }
 975
 976                         /*
 977                          * 2) Any kind of error makes the transfer
 978                          * done
 979                          */
 980                         if (halted) {
 981                                 DPRINTF("TD has I/O error\n");
 982                                 xhci_generic_done(xfer);
 983                                 break;
 984                         }
 985
 986                         /*
 987                          * 3) If there is no alternate next transfer,
 988                          * a short packet also makes the transfer done
 989                          */
 990                         if (td->remainder > 0) {
 991                                 if (td->alt_next == NULL) {
 992                                         DPRINTF(
 993                                             "short TD has no alternate next\n");
 994                                         xhci_generic_done(xfer);
 995                                         break;
 996                                 }
 997                                 DPRINTF("TD has short pkt\n");
 998                                 if (xfer->flags_int.short_frames_ok ||
 999                                     xfer->flags_int.isochronous_xfr ||
1000                                     xfer->flags_int.control_xfr) {
1001                                         /* follow the alt next */
1002                                         xfer->td_transfer_cache = td->alt_next;
1003                                         xhci_activate_transfer(xfer);
1004                                         break;
1005                                 }
1006                                 xhci_skip_transfer(xfer);
1007                                 xhci_generic_done(xfer);
1008                                 break;
1009                         }
1010
1011                         /*
1012                          * 4) Transfer complete - go to next TD
1013                          */
1014                         DPRINTF("Following next TD\n");
1015                         xfer->td_transfer_cache = td->obj_next;
1016                         xhci_activate_transfer(xfer);
1017                         break;          /* there should only be one match */
1018                 }
1019         }
1020 }
1021
1022 static int
1023 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1024 {
1025         if (sc->sc_cmd_addr == trb->qwTrb0) {
1026                 DPRINTF("Received command event\n");
1027                 sc->sc_cmd_result[0] = trb->dwTrb2;
1028                 sc->sc_cmd_result[1] = trb->dwTrb3;
1029                 cv_signal(&sc->sc_cmd_cv);
1030                 return (1);     /* command match */
1031         }
1032         return (0);
1033 }
1034
1035 static int
1036 xhci_interrupt_poll(struct xhci_softc *sc)
1037 {
1038         struct usb_page_search buf_res;
1039         struct xhci_hw_root *phwr;
1040         uint64_t addr;
1041         uint32_t temp;
1042         int retval = 0;
1043         uint16_t i;
1044         uint8_t event;
1045         uint8_t j;
1046         uint8_t k;
1047         uint8_t t;
1048
1049         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1050
1051         phwr = buf_res.buffer;
1052
1053         /* Receive any events */
1054
1055         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1056
1057         i = sc->sc_event_idx;
1058         j = sc->sc_event_ccs;
1059         t = 2;
1060
1061         while (1) {
1062
1063                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1064
1065                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1066
1067                 if (j != k)
1068                         break;
1069
1070                 event = XHCI_TRB_3_TYPE_GET(temp);
1071
1072                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1073                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1074                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1075                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1076
1077                 switch (event) {
1078                 case XHCI_TRB_EVENT_TRANSFER:
1079                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1080                         break;
1081                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1082                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1083                         break;
1084                 default:
1085                         DPRINTF("Unhandled event = %u\n", event);
1086                         break;
1087                 }
1088
1089                 i++;
1090
1091                 if (i == XHCI_MAX_EVENTS) {
1092                         i = 0;
1093                         j ^= 1;
1094
1095                         /* check for timeout */
1096                         if (!--t)
1097                                 break;
1098                 }
1099         }
1100
1101         sc->sc_event_idx = i;
1102         sc->sc_event_ccs = j;
1103
1104         /*
1105          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1106          * latched. That means to activate the register we need to
1107          * write both the low and high double word of the 64-bit
1108          * register.
1109          */
1110
1111         addr = (uint32_t)buf_res.physaddr;
1112         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1113
1114         /* try to clear busy bit */
1115         addr |= XHCI_ERDP_LO_BUSY;
1116
1117         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1118         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1119
1120         return (retval);
1121 }
1122
1123 static usb_error_t
1124 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1125     uint16_t timeout_ms)
1126 {
1127         struct usb_page_search buf_res;
1128         struct xhci_hw_root *phwr;
1129         uint64_t addr;
1130         uint32_t temp;
1131         uint8_t i;
1132         uint8_t j;
1133         uint8_t timeout = 0;
1134         int err;
1135
1136         XHCI_CMD_ASSERT_LOCKED(sc);
1137
1138         /* get hardware root structure */
1139
1140         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1141
1142         phwr = buf_res.buffer;
1143
1144         /* Queue command */
1145
1146         USB_BUS_LOCK(&sc->sc_bus);
1147 retry:
1148         i = sc->sc_command_idx;
1149         j = sc->sc_command_ccs;
1150
1151         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1152             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1153             (long long)le64toh(trb->qwTrb0),
1154             (long)le32toh(trb->dwTrb2),
1155             (long)le32toh(trb->dwTrb3));
1156
1157         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1158         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1159
1160         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1161
1162         temp = trb->dwTrb3;
1163
1164         if (j)
1165                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1166         else
1167                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1168
1169         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1170
1171         phwr->hwr_commands[i].dwTrb3 = temp;
1172
1173         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1174
1175         addr = buf_res.physaddr;
1176         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1177
1178         sc->sc_cmd_addr = htole64(addr);
1179
1180         i++;
1181
1182         if (i == (XHCI_MAX_COMMANDS - 1)) {
1183
1184                 if (j) {
1185                         temp = htole32(XHCI_TRB_3_TC_BIT |
1186                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1187                             XHCI_TRB_3_CYCLE_BIT);
1188                 } else {
1189                         temp = htole32(XHCI_TRB_3_TC_BIT |
1190                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1191                 }
1192
1193                 phwr->hwr_commands[i].dwTrb3 = temp;
1194
1195                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1196
1197                 i = 0;
1198                 j ^= 1;
1199         }
1200
1201         sc->sc_command_idx = i;
1202         sc->sc_command_ccs = j;
1203
1204         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1205
1206         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1207             USB_MS_TO_TICKS(timeout_ms));
1208
1209         /*
1210          * In some error cases event interrupts are not generated.
1211          * Poll one time to see if the command has completed.
1212          */
1213         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1214                 DPRINTF("Command was completed when polling\n");
1215                 err = 0;
1216         }
1217         if (err != 0) {
1218                 DPRINTF("Command timeout!\n");
1219                 /*
1220                  * After some weeks of continuous operation, it has
1221                  * been observed that the ASMedia Technology, ASM1042
1222                  * SuperSpeed USB Host Controller can suddenly stop
1223                  * accepting commands via the command queue. Try to
1224                  * first reset the command queue. If that fails do a
1225                  * host controller reset.
1226                  */
1227                 if (timeout == 0 &&
1228                     xhci_reset_command_queue_locked(sc) == 0) {
1229                         temp = le32toh(trb->dwTrb3);
1230
1231                         /*
1232                          * Avoid infinite XHCI reset loops if the set
1233                          * address command fails to respond due to a
1234                          * non-enumerating device:
1235                          */
1236                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1237                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1238                                 DPRINTF("Set address timeout\n");
1239                         } else {
1240                                 timeout = 1;
1241                                 goto retry;
1242                         }
1243                 } else {
1244                         DPRINTF("Controller reset!\n");
1245                         usb_bus_reset_async_locked(&sc->sc_bus);
1246                 }
1247                 err = USB_ERR_TIMEOUT;
1248                 trb->dwTrb2 = 0;
1249                 trb->dwTrb3 = 0;
1250         } else {
1251                 temp = le32toh(sc->sc_cmd_result[0]);
1252                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1253                         err = USB_ERR_IOERROR;
1254
1255                 trb->dwTrb2 = sc->sc_cmd_result[0];
1256                 trb->dwTrb3 = sc->sc_cmd_result[1];
1257         }
1258
1259         USB_BUS_UNLOCK(&sc->sc_bus);
1260
1261         return (err);
1262 }
1263
1264 #if 0
1265 static usb_error_t
1266 xhci_cmd_nop(struct xhci_softc *sc)
1267 {
1268         struct xhci_trb trb;
1269         uint32_t temp;
1270
1271         DPRINTF("\n");
1272
1273         trb.qwTrb0 = 0;
1274         trb.dwTrb2 = 0;
1275         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1276
1277         trb.dwTrb3 = htole32(temp);
1278
1279         return (xhci_do_command(sc, &trb, 100 /* ms */));
1280 }
1281 #endif
1282
1283 static usb_error_t
1284 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1285 {
1286         struct xhci_trb trb;
1287         uint32_t temp;
1288         usb_error_t err;
1289
1290         DPRINTF("\n");
1291
1292         trb.qwTrb0 = 0;
1293         trb.dwTrb2 = 0;
1294         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1295
1296         err = xhci_do_command(sc, &trb, 100 /* ms */);
1297         if (err)
1298                 goto done;
1299
1300         temp = le32toh(trb.dwTrb3);
1301
1302         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1303
1304 done:
1305         return (err);
1306 }
1307
1308 static usb_error_t
1309 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1310 {
1311         struct xhci_trb trb;
1312         uint32_t temp;
1313
1314         DPRINTF("\n");
1315
1316         trb.qwTrb0 = 0;
1317         trb.dwTrb2 = 0;
1318         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1319             XHCI_TRB_3_SLOT_SET(slot_id);
1320
1321         trb.dwTrb3 = htole32(temp);
1322
1323         return (xhci_do_command(sc, &trb, 100 /* ms */));
1324 }
1325
1326 static usb_error_t
1327 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1328     uint8_t bsr, uint8_t slot_id)
1329 {
1330         struct xhci_trb trb;
1331         uint32_t temp;
1332
1333         DPRINTF("\n");
1334
1335         trb.qwTrb0 = htole64(input_ctx);
1336         trb.dwTrb2 = 0;
1337         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1338             XHCI_TRB_3_SLOT_SET(slot_id);
1339
1340         if (bsr)
1341                 temp |= XHCI_TRB_3_BSR_BIT;
1342
1343         trb.dwTrb3 = htole32(temp);
1344
1345         return (xhci_do_command(sc, &trb, 500 /* ms */));
1346 }
1347
1348 static usb_error_t
1349 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1350 {
1351         struct usb_page_search buf_inp;
1352         struct usb_page_search buf_dev;
1353         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1354         struct xhci_hw_dev *hdev;
1355         struct xhci_dev_ctx *pdev;
1356         struct xhci_endpoint_ext *pepext;
1357         uint32_t temp;
1358         uint16_t mps;
1359         usb_error_t err;
1360         uint8_t index;
1361
1362         /* the root HUB case is not handled here */
1363         if (udev->parent_hub == NULL)
1364                 return (USB_ERR_INVAL);
1365
1366         index = udev->controller_slot_id;
1367
1368         hdev =  &sc->sc_hw.devs[index];
1369
1370         if (mtx != NULL)
1371                 mtx_unlock(mtx);
1372
1373         XHCI_CMD_LOCK(sc);
1374
1375         switch (hdev->state) {
1376         case XHCI_ST_DEFAULT:
1377         case XHCI_ST_ENABLED:
1378
1379                 hdev->state = XHCI_ST_ENABLED;
1380
1381                 /* set configure mask to slot and EP0 */
1382                 xhci_configure_mask(udev, 3, 0);
1383
1384                 /* configure input slot context structure */
1385                 err = xhci_configure_device(udev);
1386
1387                 if (err != 0) {
1388                         DPRINTF("Could not configure device\n");
1389                         break;
1390                 }
1391
1392                 /* configure input endpoint context structure */
1393                 switch (udev->speed) {
1394                 case USB_SPEED_LOW:
1395                 case USB_SPEED_FULL:
1396                         mps = 8;
1397                         break;
1398                 case USB_SPEED_HIGH:
1399                         mps = 64;
1400                         break;
1401                 default:
1402                         mps = 512;
1403                         break;
1404                 }
1405
1406                 pepext = xhci_get_endpoint_ext(udev,
1407                     &udev->ctrl_ep_desc);
1408                 err = xhci_configure_endpoint(udev,
1409                     &udev->ctrl_ep_desc, pepext,
1410                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1411
1412                 if (err != 0) {
1413                         DPRINTF("Could not configure default endpoint\n");
1414                         break;
1415                 }
1416
1417                 /* execute set address command */
1418                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1419
1420                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1421                     (address == 0), index);
1422
1423                 if (err != 0) {
1424                         temp = le32toh(sc->sc_cmd_result[0]);
1425                         if (address == 0 && sc->sc_port_route != NULL &&
1426                             XHCI_TRB_2_ERROR_GET(temp) ==
1427                             XHCI_TRB_ERROR_PARAMETER) {
1428                                 /* LynxPoint XHCI - ports are not switchable */
1429                                 /* Un-route all ports from the XHCI */
1430                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1431                         }
1432                         DPRINTF("Could not set address "
1433                             "for slot %u.\n", index);
1434                         if (address != 0)
1435                                 break;
1436                 }
1437
1438                 /* update device address to new value */
1439
1440                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1441                 pdev = buf_dev.buffer;
1442                 usb_pc_cpu_invalidate(&hdev->device_pc);
1443
1444                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1445                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1446
1447                 /* update device state to new value */
1448
1449                 if (address != 0)
1450                         hdev->state = XHCI_ST_ADDRESSED;
1451                 else
1452                         hdev->state = XHCI_ST_DEFAULT;
1453                 break;
1454
1455         default:
1456                 DPRINTF("Wrong state for set address.\n");
1457                 err = USB_ERR_IOERROR;
1458                 break;
1459         }
1460         XHCI_CMD_UNLOCK(sc);
1461
1462         if (mtx != NULL)
1463                 mtx_lock(mtx);
1464
1465         return (err);
1466 }
1467
1468 static usb_error_t
1469 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1470     uint8_t deconfigure, uint8_t slot_id)
1471 {
1472         struct xhci_trb trb;
1473         uint32_t temp;
1474
1475         DPRINTF("\n");
1476
1477         trb.qwTrb0 = htole64(input_ctx);
1478         trb.dwTrb2 = 0;
1479         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1480             XHCI_TRB_3_SLOT_SET(slot_id);
1481
1482         if (deconfigure)
1483                 temp |= XHCI_TRB_3_DCEP_BIT;
1484
1485         trb.dwTrb3 = htole32(temp);
1486
1487         return (xhci_do_command(sc, &trb, 100 /* ms */));
1488 }
1489
1490 static usb_error_t
1491 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1492     uint8_t slot_id)
1493 {
1494         struct xhci_trb trb;
1495         uint32_t temp;
1496
1497         DPRINTF("\n");
1498
1499         trb.qwTrb0 = htole64(input_ctx);
1500         trb.dwTrb2 = 0;
1501         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1502             XHCI_TRB_3_SLOT_SET(slot_id);
1503         trb.dwTrb3 = htole32(temp);
1504
1505         return (xhci_do_command(sc, &trb, 100 /* ms */));
1506 }
1507
1508 static usb_error_t
1509 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1510     uint8_t ep_id, uint8_t slot_id)
1511 {
1512         struct xhci_trb trb;
1513         uint32_t temp;
1514
1515         DPRINTF("\n");
1516
1517         trb.qwTrb0 = 0;
1518         trb.dwTrb2 = 0;
1519         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1520             XHCI_TRB_3_SLOT_SET(slot_id) |
1521             XHCI_TRB_3_EP_SET(ep_id);
1522
1523         if (preserve)
1524                 temp |= XHCI_TRB_3_PRSV_BIT;
1525
1526         trb.dwTrb3 = htole32(temp);
1527
1528         return (xhci_do_command(sc, &trb, 100 /* ms */));
1529 }
1530
1531 static usb_error_t
1532 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1533     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1534 {
1535         struct xhci_trb trb;
1536         uint32_t temp;
1537
1538         DPRINTF("\n");
1539
1540         trb.qwTrb0 = htole64(dequeue_ptr);
1541
1542         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1543         trb.dwTrb2 = htole32(temp);
1544
1545         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1546             XHCI_TRB_3_SLOT_SET(slot_id) |
1547             XHCI_TRB_3_EP_SET(ep_id);
1548         trb.dwTrb3 = htole32(temp);
1549
1550         return (xhci_do_command(sc, &trb, 100 /* ms */));
1551 }
1552
1553 static usb_error_t
1554 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1555     uint8_t ep_id, uint8_t slot_id)
1556 {
1557         struct xhci_trb trb;
1558         uint32_t temp;
1559
1560         DPRINTF("\n");
1561
1562         trb.qwTrb0 = 0;
1563         trb.dwTrb2 = 0;
1564         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1565             XHCI_TRB_3_SLOT_SET(slot_id) |
1566             XHCI_TRB_3_EP_SET(ep_id);
1567
1568         if (suspend)
1569                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1570
1571         trb.dwTrb3 = htole32(temp);
1572
1573         return (xhci_do_command(sc, &trb, 100 /* ms */));
1574 }
1575
1576 static usb_error_t
1577 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1578 {
1579         struct xhci_trb trb;
1580         uint32_t temp;
1581
1582         DPRINTF("\n");
1583
1584         trb.qwTrb0 = 0;
1585         trb.dwTrb2 = 0;
1586         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1587             XHCI_TRB_3_SLOT_SET(slot_id);
1588
1589         trb.dwTrb3 = htole32(temp);
1590
1591         return (xhci_do_command(sc, &trb, 100 /* ms */));
1592 }
1593
1594 /*------------------------------------------------------------------------*
1595  *      xhci_interrupt - XHCI interrupt handler
1596  *------------------------------------------------------------------------*/
1597 void
1598 xhci_interrupt(struct xhci_softc *sc)
1599 {
1600         uint32_t status;
1601         uint32_t temp;
1602
1603         USB_BUS_LOCK(&sc->sc_bus);
1604
1605         status = XREAD4(sc, oper, XHCI_USBSTS);
1606
1607         /* acknowledge interrupts, if any */
1608         if (status != 0) {
1609                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1610                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1611         }
1612
1613         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1614
1615         /* force clearing of pending interrupts */
1616         if (temp & XHCI_IMAN_INTR_PEND)
1617                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1618
1619         /* check for event(s) */
1620         xhci_interrupt_poll(sc);
1621
1622         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1623             XHCI_STS_HSE | XHCI_STS_HCE)) {
1624
1625                 if (status & XHCI_STS_PCD) {
1626                         xhci_root_intr(sc);
1627                 }
1628
1629                 if (status & XHCI_STS_HCH) {
1630                         printf("%s: host controller halted\n",
1631                             __FUNCTION__);
1632                 }
1633
1634                 if (status & XHCI_STS_HSE) {
1635                         printf("%s: host system error\n",
1636                             __FUNCTION__);
1637                 }
1638
1639                 if (status & XHCI_STS_HCE) {
1640                         printf("%s: host controller error\n",
1641                            __FUNCTION__);
1642                 }
1643         }
1644         USB_BUS_UNLOCK(&sc->sc_bus);
1645 }
1646
1647 /*------------------------------------------------------------------------*
1648  *      xhci_timeout - XHCI timeout handler
1649  *------------------------------------------------------------------------*/
1650 static void
1651 xhci_timeout(void *arg)
1652 {
1653         struct usb_xfer *xfer = arg;
1654
1655         DPRINTF("xfer=%p\n", xfer);
1656
1657         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1658
1659         /* transfer is transferred */
1660         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1661 }
1662
1663 static void
1664 xhci_do_poll(struct usb_bus *bus)
1665 {
1666         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1667
1668         USB_BUS_LOCK(&sc->sc_bus);
1669         xhci_interrupt_poll(sc);
1670         USB_BUS_UNLOCK(&sc->sc_bus);
1671 }
1672
1673 static void
1674 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1675 {
1676         struct usb_page_search buf_res;
1677         struct xhci_td *td;
1678         struct xhci_td *td_next;
1679         struct xhci_td *td_alt_next;
1680         struct xhci_td *td_first;
1681         uint32_t buf_offset;
1682         uint32_t average;
1683         uint32_t len_old;
1684         uint32_t npkt_off;
1685         uint32_t dword;
1686         uint8_t shortpkt_old;
1687         uint8_t precompute;
1688         uint8_t x;
1689
1690         td_alt_next = NULL;
1691         buf_offset = 0;
1692         shortpkt_old = temp->shortpkt;
1693         len_old = temp->len;
1694         npkt_off = 0;
1695         precompute = 1;
1696
1697 restart:
1698
1699         td = temp->td;
1700         td_next = td_first = temp->td_next;
1701
1702         while (1) {
1703
1704                 if (temp->len == 0) {
1705
1706                         if (temp->shortpkt)
1707                                 break;
1708
1709                         /* send a Zero Length Packet, ZLP, last */
1710
1711                         temp->shortpkt = 1;
1712                         average = 0;
1713
1714                 } else {
1715
1716                         average = temp->average;
1717
1718                         if (temp->len < average) {
1719                                 if (temp->len % temp->max_packet_size) {
1720                                         temp->shortpkt = 1;
1721                                 }
1722                                 average = temp->len;
1723                         }
1724                 }
1725
1726                 if (td_next == NULL)
1727                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1728
1729                 /* get next TD */
1730
1731                 td = td_next;
1732                 td_next = td->obj_next;
1733
1734                 /* check if we are pre-computing */
1735
1736                 if (precompute) {
1737
1738                         /* update remaining length */
1739
1740                         temp->len -= average;
1741
1742                         continue;
1743                 }
1744                 /* fill out current TD */
1745
1746                 td->len = average;
1747                 td->remainder = 0;
1748                 td->status = 0;
1749
1750                 /* update remaining length */
1751
1752                 temp->len -= average;
1753
1754                 /* reset TRB index */
1755
1756                 x = 0;
1757
1758                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1759                         /* immediate data */
1760
1761                         if (average > 8)
1762                                 average = 8;
1763
1764                         td->td_trb[0].qwTrb0 = 0;
1765
1766                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1767                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1768                            average);
1769
1770                         dword = XHCI_TRB_2_BYTES_SET(8) |
1771                             XHCI_TRB_2_TDSZ_SET(0) |
1772                             XHCI_TRB_2_IRQ_SET(0);
1773
1774                         td->td_trb[0].dwTrb2 = htole32(dword);
1775
1776                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1777                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1778
1779                         /* check wLength */
1780                         if (td->td_trb[0].qwTrb0 &
1781                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1782                                 if (td->td_trb[0].qwTrb0 &
1783                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1784                                         dword |= XHCI_TRB_3_TRT_IN;
1785                                 else
1786                                         dword |= XHCI_TRB_3_TRT_OUT;
1787                         }
1788
1789                         td->td_trb[0].dwTrb3 = htole32(dword);
1790 #ifdef USB_DEBUG
1791                         xhci_dump_trb(&td->td_trb[x]);
1792 #endif
1793                         x++;
1794
1795                 } else do {
1796
1797                         uint32_t npkt;
1798
1799                         /* fill out buffer pointers */
1800
1801                         if (average == 0) {
1802                                 memset(&buf_res, 0, sizeof(buf_res));
1803                         } else {
1804                                 usbd_get_page(temp->pc, temp->offset +
1805                                     buf_offset, &buf_res);
1806
1807                                 /* get length to end of page */
1808                                 if (buf_res.length > average)
1809                                         buf_res.length = average;
1810
1811                                 /* check for maximum length */
1812                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1813                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1814
1815                                 npkt_off += buf_res.length;
1816                         }
1817
1818                         /* setup npkt */
1819                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1820                             temp->max_packet_size;
1821
1822                         if (npkt == 0)
1823                                 npkt = 1;
1824                         else if (npkt > 31)
1825                                 npkt = 31;
1826
1827                         /* fill out TRB's */
1828                         td->td_trb[x].qwTrb0 =
1829                             htole64((uint64_t)buf_res.physaddr);
1830
1831                         dword =
1832                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1833                           XHCI_TRB_2_TDSZ_SET(npkt) |
1834                           XHCI_TRB_2_IRQ_SET(0);
1835
1836                         td->td_trb[x].dwTrb2 = htole32(dword);
1837
1838                         switch (temp->trb_type) {
1839                         case XHCI_TRB_TYPE_ISOCH:
1840                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1841                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1842                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1843                                 if (td != td_first) {
1844                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1845                                 } else if (temp->do_isoc_sync != 0) {
1846                                         temp->do_isoc_sync = 0;
1847                                         /* wait until "isoc_frame" */
1848                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1849                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1850                                 } else {
1851                                         /* start data transfer at next interval */
1852                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1853                                             XHCI_TRB_3_ISO_SIA_BIT;
1854                                 }
1855                                 if (temp->direction == UE_DIR_IN)
1856                                         dword |= XHCI_TRB_3_ISP_BIT;
1857                                 break;
1858                         case XHCI_TRB_TYPE_DATA_STAGE:
1859                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1860                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1861                                 if (temp->direction == UE_DIR_IN)
1862                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1863                                 break;
1864                         case XHCI_TRB_TYPE_STATUS_STAGE:
1865                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1866                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1867                                 if (temp->direction == UE_DIR_IN)
1868                                         dword |= XHCI_TRB_3_DIR_IN;
1869                                 break;
1870                         default:        /* XHCI_TRB_TYPE_NORMAL */
1871                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1872                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1873                                 if (temp->direction == UE_DIR_IN)
1874                                         dword |= XHCI_TRB_3_ISP_BIT;
1875                                 break;
1876                         }
1877                         td->td_trb[x].dwTrb3 = htole32(dword);
1878
1879                         average -= buf_res.length;
1880                         buf_offset += buf_res.length;
1881 #ifdef USB_DEBUG
1882                         xhci_dump_trb(&td->td_trb[x]);
1883 #endif
1884                         x++;
1885
1886                 } while (average != 0);
1887
1888                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1889
1890                 /* store number of data TRB's */
1891
1892                 td->ntrb = x;
1893
1894                 DPRINTF("NTRB=%u\n", x);
1895
1896                 /* fill out link TRB */
1897
1898                 if (td_next != NULL) {
1899                         /* link the current TD with the next one */
1900                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1901                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1902                 } else {
1903                         /* this field will get updated later */
1904                         DPRINTF("NOLINK\n");
1905                 }
1906
1907                 dword = XHCI_TRB_2_IRQ_SET(0);
1908
1909                 td->td_trb[x].dwTrb2 = htole32(dword);
1910
1911                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1912                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1913                     /*
1914                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1915                      * frame only receives a single short packet event
1916                      * by setting the CHAIN bit in the LINK field. In
1917                      * addition some XHCI controllers have problems
1918                      * sending a ZLP unless the CHAIN-BIT is set in
1919                      * the LINK TRB.
1920                      */
1921                     XHCI_TRB_3_CHAIN_BIT;
1922
1923                 td->td_trb[x].dwTrb3 = htole32(dword);
1924
1925                 td->alt_next = td_alt_next;
1926 #ifdef USB_DEBUG
1927                 xhci_dump_trb(&td->td_trb[x]);
1928 #endif
1929                 usb_pc_cpu_flush(td->page_cache);
1930         }
1931
1932         if (precompute) {
1933                 precompute = 0;
1934
1935                 /* setup alt next pointer, if any */
1936                 if (temp->last_frame) {
1937                         td_alt_next = NULL;
1938                 } else {
1939                         /* we use this field internally */
1940                         td_alt_next = td_next;
1941                 }
1942
1943                 /* restore */
1944                 temp->shortpkt = shortpkt_old;
1945                 temp->len = len_old;
1946                 goto restart;
1947         }
1948
1949         /*
1950          * Remove cycle bit from the first TRB if we are
1951          * stepping them:
1952          */
1953         if (temp->step_td != 0) {
1954                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1955                 usb_pc_cpu_flush(td_first->page_cache);
1956         }
1957
1958         /* clear TD SIZE to zero, hence this is the last TRB */
1959         /* remove chain bit because this is the last data TRB in the chain */
1960         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1961         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1962         /* remove CHAIN-BIT from last LINK TRB */
1963         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1964
1965         usb_pc_cpu_flush(td->page_cache);
1966
1967         temp->td = td;
1968         temp->td_next = td_next;
1969 }
1970
1971 static void
1972 xhci_setup_generic_chain(struct usb_xfer *xfer)
1973 {
1974         struct xhci_std_temp temp;
1975         struct xhci_td *td;
1976         uint32_t x;
1977         uint32_t y;
1978         uint8_t mult;
1979
1980         temp.do_isoc_sync = 0;
1981         temp.step_td = 0;
1982         temp.tbc = 0;
1983         temp.tlbpc = 0;
1984         temp.average = xfer->max_hc_frame_size;
1985         temp.max_packet_size = xfer->max_packet_size;
1986         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1987         temp.pc = NULL;
1988         temp.last_frame = 0;
1989         temp.offset = 0;
1990         temp.multishort = xfer->flags_int.isochronous_xfr ||
1991             xfer->flags_int.control_xfr ||
1992             xfer->flags_int.short_frames_ok;
1993
1994         /* toggle the DMA set we are using */
1995         xfer->flags_int.curr_dma_set ^= 1;
1996
1997         /* get next DMA set */
1998         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1999
2000         temp.td = NULL;
2001         temp.td_next = td;
2002
2003         xfer->td_transfer_first = td;
2004         xfer->td_transfer_cache = td;
2005
2006         if (xfer->flags_int.isochronous_xfr) {
2007                 uint8_t shift;
2008
2009                 /* compute multiplier for ISOCHRONOUS transfers */
2010                 mult = xfer->endpoint->ecomp ?
2011                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2012                     : 0;
2013                 /* check for USB 2.0 multiplier */
2014                 if (mult == 0) {
2015                         mult = (xfer->endpoint->edesc->
2016                             wMaxPacketSize[1] >> 3) & 3;
2017                 }
2018                 /* range check */
2019                 if (mult > 2)
2020                         mult = 3;
2021                 else
2022                         mult++;
2023
2024                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2025
2026                 DPRINTF("MFINDEX=0x%08x\n", x);
2027
2028                 switch (usbd_get_speed(xfer->xroot->udev)) {
2029                 case USB_SPEED_FULL:
2030                         shift = 3;
2031                         temp.isoc_delta = 8;    /* 1ms */
2032                         x += temp.isoc_delta - 1;
2033                         x &= ~(temp.isoc_delta - 1);
2034                         break;
2035                 default:
2036                         shift = usbd_xfer_get_fps_shift(xfer);
2037                         temp.isoc_delta = 1U << shift;
2038                         x += temp.isoc_delta - 1;
2039                         x &= ~(temp.isoc_delta - 1);
2040                         /* simple frame load balancing */
2041                         x += xfer->endpoint->usb_uframe;
2042                         break;
2043                 }
2044
2045                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2046
2047                 if ((xfer->endpoint->is_synced == 0) ||
2048                     (y < (xfer->nframes << shift)) ||
2049                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2050                         /*
2051                          * If there is data underflow or the pipe
2052                          * queue is empty we schedule the transfer a
2053                          * few frames ahead of the current frame
2054                          * position. Else two isochronous transfers
2055                          * might overlap.
2056                          */
2057                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2058                         xfer->endpoint->is_synced = 1;
2059                         temp.do_isoc_sync = 1;
2060
2061                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2062                 }
2063
2064                 /* compute isochronous completion time */
2065
2066                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2067
2068                 xfer->isoc_time_complete =
2069                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2070                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2071
2072                 x = 0;
2073                 temp.isoc_frame = xfer->endpoint->isoc_next;
2074                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2075
2076                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2077
2078         } else if (xfer->flags_int.control_xfr) {
2079
2080                 /* check if we should prepend a setup message */
2081
2082                 if (xfer->flags_int.control_hdr) {
2083
2084                         temp.len = xfer->frlengths[0];
2085                         temp.pc = xfer->frbuffers + 0;
2086                         temp.shortpkt = temp.len ? 1 : 0;
2087                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2088                         temp.direction = 0;
2089
2090                         /* check for last frame */
2091                         if (xfer->nframes == 1) {
2092                                 /* no STATUS stage yet, SETUP is last */
2093                                 if (xfer->flags_int.control_act)
2094                                         temp.last_frame = 1;
2095                         }
2096
2097                         xhci_setup_generic_chain_sub(&temp);
2098                 }
2099                 x = 1;
2100                 mult = 1;
2101                 temp.isoc_delta = 0;
2102                 temp.isoc_frame = 0;
2103                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2104         } else {
2105                 x = 0;
2106                 mult = 1;
2107                 temp.isoc_delta = 0;
2108                 temp.isoc_frame = 0;
2109                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2110         }
2111
2112         if (x != xfer->nframes) {
2113                 /* setup page_cache pointer */
2114                 temp.pc = xfer->frbuffers + x;
2115                 /* set endpoint direction */
2116                 temp.direction = UE_GET_DIR(xfer->endpointno);
2117         }
2118
2119         while (x != xfer->nframes) {
2120
2121                 /* DATA0 / DATA1 message */
2122
2123                 temp.len = xfer->frlengths[x];
2124                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2125                     x != 0 && temp.multishort == 0);
2126
2127                 x++;
2128
2129                 if (x == xfer->nframes) {
2130                         if (xfer->flags_int.control_xfr) {
2131                                 /* no STATUS stage yet, DATA is last */
2132                                 if (xfer->flags_int.control_act)
2133                                         temp.last_frame = 1;
2134                         } else {
2135                                 temp.last_frame = 1;
2136                         }
2137                 }
2138                 if (temp.len == 0) {
2139
2140                         /* make sure that we send an USB packet */
2141
2142                         temp.shortpkt = 0;
2143
2144                         temp.tbc = 0;
2145                         temp.tlbpc = mult - 1;
2146
2147                 } else if (xfer->flags_int.isochronous_xfr) {
2148
2149                         uint8_t tdpc;
2150
2151                         /*
2152                          * Isochronous transfers don't have short
2153                          * packet termination:
2154                          */
2155
2156                         temp.shortpkt = 1;
2157
2158                         /* isochronous transfers have a transfer limit */
2159
2160                         if (temp.len > xfer->max_frame_size)
2161                                 temp.len = xfer->max_frame_size;
2162
2163                         /* compute TD packet count */
2164                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2165                             xfer->max_packet_size;
2166
2167                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2168                         temp.tlbpc = (tdpc % mult);
2169
2170                         if (temp.tlbpc == 0)
2171                                 temp.tlbpc = mult - 1;
2172                         else
2173                                 temp.tlbpc--;
2174                 } else {
2175
2176                         /* regular data transfer */
2177
2178                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2179                 }
2180
2181                 xhci_setup_generic_chain_sub(&temp);
2182
2183                 if (xfer->flags_int.isochronous_xfr) {
2184                         temp.offset += xfer->frlengths[x - 1];
2185                         temp.isoc_frame += temp.isoc_delta;
2186                 } else {
2187                         /* get next Page Cache pointer */
2188                         temp.pc = xfer->frbuffers + x;
2189                 }
2190         }
2191
2192         /* check if we should append a status stage */
2193
2194         if (xfer->flags_int.control_xfr &&
2195             !xfer->flags_int.control_act) {
2196
2197                 /*
2198                  * Send a DATA1 message and invert the current
2199                  * endpoint direction.
2200                  */
2201                 temp.step_td = (xfer->nframes != 0);
2202                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2203                 temp.len = 0;
2204                 temp.pc = NULL;
2205                 temp.shortpkt = 0;
2206                 temp.last_frame = 1;
2207                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2208
2209                 xhci_setup_generic_chain_sub(&temp);
2210         }
2211
2212         td = temp.td;
2213
2214         /* must have at least one frame! */
2215
2216         xfer->td_transfer_last = td;
2217
2218         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2219 }
2220
2221 static void
2222 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2223 {
2224         struct usb_page_search buf_res;
2225         struct xhci_dev_ctx_addr *pdctxa;
2226
2227         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2228
2229         pdctxa = buf_res.buffer;
2230
2231         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2232
2233         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2234
2235         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2236 }
2237
2238 static usb_error_t
2239 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2240 {
2241         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2242         struct usb_page_search buf_inp;
2243         struct xhci_input_dev_ctx *pinp;
2244         uint32_t temp;
2245         uint8_t index;
2246         uint8_t x;
2247
2248         index = udev->controller_slot_id;
2249
2250         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2251
2252         pinp = buf_inp.buffer;
2253
2254         if (drop) {
2255                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2256                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2257                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2258         } else {
2259                 /*
2260                  * Some hardware requires that we drop the endpoint
2261                  * context before adding it again:
2262                  */
2263                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2264                     mask & XHCI_INCTX_NON_CTRL_MASK);
2265
2266                 /* Add new endpoint context */
2267                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2268
2269                 /* find most significant set bit */
2270                 for (x = 31; x != 1; x--) {
2271                         if (mask & (1 << x))
2272                                 break;
2273                 }
2274
2275                 /* adjust */
2276                 x--;
2277
2278                 /* figure out the maximum number of contexts */
2279                 if (x > sc->sc_hw.devs[index].context_num)
2280                         sc->sc_hw.devs[index].context_num = x;
2281                 else
2282                         x = sc->sc_hw.devs[index].context_num;
2283
2284                 /* update number of contexts */
2285                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2286                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2287                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2288                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2289         }
2290         return (0);
2291 }
2292
2293 static usb_error_t
2294 xhci_configure_endpoint(struct usb_device *udev,
2295     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2296     uint16_t interval, uint8_t max_packet_count,
2297     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2298     uint16_t max_frame_size, uint8_t ep_mode)
2299 {
2300         struct usb_page_search buf_inp;
2301         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2302         struct xhci_input_dev_ctx *pinp;
2303         uint64_t ring_addr = pepext->physaddr;
2304         uint32_t temp;
2305         uint8_t index;
2306         uint8_t epno;
2307         uint8_t type;
2308
2309         index = udev->controller_slot_id;
2310
2311         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2312
2313         pinp = buf_inp.buffer;
2314
2315         epno = edesc->bEndpointAddress;
2316         type = edesc->bmAttributes & UE_XFERTYPE;
2317
2318         if (type == UE_CONTROL)
2319                 epno |= UE_DIR_IN;
2320
2321         epno = XHCI_EPNO2EPID(epno);
2322
2323         if (epno == 0)
2324                 return (USB_ERR_NO_PIPE);               /* invalid */
2325
2326         if (max_packet_count == 0)
2327                 return (USB_ERR_BAD_BUFSIZE);
2328
2329         max_packet_count--;
2330
2331         if (mult == 0)
2332                 return (USB_ERR_BAD_BUFSIZE);
2333
2334         /* store endpoint mode */
2335         pepext->trb_ep_mode = ep_mode;
2336         usb_pc_cpu_flush(pepext->page_cache);
2337
2338         if (ep_mode == USB_EP_MODE_STREAMS) {
2339                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2340                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2341                     XHCI_EPCTX_0_LSA_SET(1);
2342
2343                 ring_addr += sizeof(struct xhci_trb) *
2344                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2345         } else {
2346                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2347                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2348                     XHCI_EPCTX_0_LSA_SET(0);
2349
2350                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2351         }
2352
2353         switch (udev->speed) {
2354         case USB_SPEED_FULL:
2355         case USB_SPEED_LOW:
2356                 /* 1ms -> 125us */
2357                 fps_shift += 3;
2358                 break;
2359         default:
2360                 break;
2361         }
2362
2363         switch (type) {
2364         case UE_INTERRUPT:
2365                 if (fps_shift > 3)
2366                         fps_shift--;
2367                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2368                 break;
2369         case UE_ISOCHRONOUS:
2370                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2371
2372                 switch (udev->speed) {
2373                 case USB_SPEED_SUPER:
2374                         if (mult > 3)
2375                                 mult = 3;
2376                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2377                         max_packet_count /= mult;
2378                         break;
2379                 default:
2380                         break;
2381                 }
2382                 break;
2383         default:
2384                 break;
2385         }
2386
2387         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2388
2389         temp =
2390             XHCI_EPCTX_1_HID_SET(0) |
2391             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2392             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2393
2394         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2395                 if (type != UE_ISOCHRONOUS)
2396                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2397         }
2398
2399         switch (type) {
2400         case UE_CONTROL:
2401                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2402                 break;
2403         case UE_ISOCHRONOUS:
2404                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2405                 break;
2406         case UE_BULK:
2407                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2408                 break;
2409         default:
2410                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2411                 break;
2412         }
2413
2414         /* check for IN direction */
2415         if (epno & 1)
2416                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2417
2418         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2419         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2420
2421         switch (edesc->bmAttributes & UE_XFERTYPE) {
2422         case UE_INTERRUPT:
2423         case UE_ISOCHRONOUS:
2424                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2425                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2426                     max_frame_size));
2427                 break;
2428         case UE_CONTROL:
2429                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2430                 break;
2431         default:
2432                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2433                 break;
2434         }
2435
2436         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2437
2438 #ifdef USB_DEBUG
2439         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2440 #endif
2441         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2442
2443         return (0);             /* success */
2444 }
2445
2446 static usb_error_t
2447 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2448 {
2449         struct xhci_endpoint_ext *pepext;
2450         struct usb_endpoint_ss_comp_descriptor *ecomp;
2451         usb_stream_t x;
2452
2453         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2454             xfer->endpoint->edesc);
2455
2456         ecomp = xfer->endpoint->ecomp;
2457
2458         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2459                 uint64_t temp;
2460
2461                 /* halt any transfers */
2462                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2463
2464                 /* compute start of TRB ring for stream "x" */
2465                 temp = pepext->physaddr +
2466                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2467                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2468
2469                 /* make tree structure */
2470                 pepext->trb[(XHCI_MAX_TRANSFERS *
2471                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2472
2473                 /* reserved fields */
2474                 pepext->trb[(XHCI_MAX_TRANSFERS *
2475                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2476                 pepext->trb[(XHCI_MAX_TRANSFERS *
2477                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2478         }
2479         usb_pc_cpu_flush(pepext->page_cache);
2480
2481         return (xhci_configure_endpoint(xfer->xroot->udev,
2482             xfer->endpoint->edesc, pepext,
2483             xfer->interval, xfer->max_packet_count,
2484             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2485             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2486             xfer->max_frame_size, xfer->endpoint->ep_mode));
2487 }
2488
2489 static usb_error_t
2490 xhci_configure_device(struct usb_device *udev)
2491 {
2492         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2493         struct usb_page_search buf_inp;
2494         struct usb_page_cache *pcinp;
2495         struct xhci_input_dev_ctx *pinp;
2496         struct usb_device *hubdev;
2497         uint32_t temp;
2498         uint32_t route;
2499         uint32_t rh_port;
2500         uint8_t is_hub;
2501         uint8_t index;
2502         uint8_t depth;
2503
2504         index = udev->controller_slot_id;
2505
2506         DPRINTF("index=%u\n", index);
2507
2508         pcinp = &sc->sc_hw.devs[index].input_pc;
2509
2510         usbd_get_page(pcinp, 0, &buf_inp);
2511
2512         pinp = buf_inp.buffer;
2513
2514         rh_port = 0;
2515         route = 0;
2516
2517         /* figure out route string and root HUB port number */
2518
2519         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2520
2521                 if (hubdev->parent_hub == NULL)
2522                         break;
2523
2524                 depth = hubdev->parent_hub->depth;
2525
2526                 /*
2527                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2528                  * more than 15 ports
2529                  */
2530
2531                 rh_port = hubdev->port_no;
2532
2533                 if (depth == 0)
2534                         break;
2535
2536                 if (rh_port > 15)
2537                         rh_port = 15;
2538
2539                 if (depth < 6)
2540                         route |= rh_port << (4 * (depth - 1));
2541         }
2542
2543         DPRINTF("Route=0x%08x\n", route);
2544
2545         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2546             XHCI_SCTX_0_CTX_NUM_SET(
2547             sc->sc_hw.devs[index].context_num + 1);
2548
2549         switch (udev->speed) {
2550         case USB_SPEED_LOW:
2551                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2552                 if (udev->parent_hs_hub != NULL &&
2553                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2554                     UDPROTO_HSHUBMTT) {
2555                         DPRINTF("Device inherits MTT\n");
2556                         temp |= XHCI_SCTX_0_MTT_SET(1);
2557                 }
2558                 break;
2559         case USB_SPEED_HIGH:
2560                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2561                 if (sc->sc_hw.devs[index].nports != 0 &&
2562                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2563                         DPRINTF("HUB supports MTT\n");
2564                         temp |= XHCI_SCTX_0_MTT_SET(1);
2565                 }
2566                 break;
2567         case USB_SPEED_FULL:
2568                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2569                 if (udev->parent_hs_hub != NULL &&
2570                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2571                     UDPROTO_HSHUBMTT) {
2572                         DPRINTF("Device inherits MTT\n");
2573                         temp |= XHCI_SCTX_0_MTT_SET(1);
2574                 }
2575                 break;
2576         default:
2577                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2578                 break;
2579         }
2580
2581         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2582             (udev->speed == USB_SPEED_SUPER ||
2583             udev->speed == USB_SPEED_HIGH);
2584
2585         if (is_hub)
2586                 temp |= XHCI_SCTX_0_HUB_SET(1);
2587
2588         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2589
2590         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2591
2592         if (is_hub) {
2593                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2594                     sc->sc_hw.devs[index].nports);
2595         }
2596
2597         switch (udev->speed) {
2598         case USB_SPEED_SUPER:
2599                 switch (sc->sc_hw.devs[index].state) {
2600                 case XHCI_ST_ADDRESSED:
2601                 case XHCI_ST_CONFIGURED:
2602                         /* enable power save */
2603                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2604                         break;
2605                 default:
2606                         /* disable power save */
2607                         break;
2608                 }
2609                 break;
2610         default:
2611                 break;
2612         }
2613
2614         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2615
2616         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2617
2618         if (is_hub) {
2619                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2620                     sc->sc_hw.devs[index].tt);
2621         }
2622
2623         hubdev = udev->parent_hs_hub;
2624
2625         /* check if we should activate the transaction translator */
2626         switch (udev->speed) {
2627         case USB_SPEED_FULL:
2628         case USB_SPEED_LOW:
2629                 if (hubdev != NULL) {
2630                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2631                             hubdev->controller_slot_id);
2632                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2633                             udev->hs_port_no);
2634                 }
2635                 break;
2636         default:
2637                 break;
2638         }
2639
2640         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2641
2642         /*
2643          * These fields should be initialized to zero, according to
2644          * XHCI section 6.2.2 - slot context:
2645          */
2646         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2647             XHCI_SCTX_3_SLOT_STATE_SET(0);
2648
2649         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2650
2651 #ifdef USB_DEBUG
2652         xhci_dump_device(sc, &pinp->ctx_slot);
2653 #endif
2654         usb_pc_cpu_flush(pcinp);
2655
2656         return (0);             /* success */
2657 }
2658
2659 static usb_error_t
2660 xhci_alloc_device_ext(struct usb_device *udev)
2661 {
2662         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2663         struct usb_page_search buf_dev;
2664         struct usb_page_search buf_ep;
2665         struct xhci_trb *trb;
2666         struct usb_page_cache *pc;
2667         struct usb_page *pg;
2668         uint64_t addr;
2669         uint8_t index;
2670         uint8_t i;
2671
2672         index = udev->controller_slot_id;
2673
2674         pc = &sc->sc_hw.devs[index].device_pc;
2675         pg = &sc->sc_hw.devs[index].device_pg;
2676
2677         /* need to initialize the page cache */
2678         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2679
2680         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2681             (2 * sizeof(struct xhci_dev_ctx)) :
2682             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2683                 goto error;
2684
2685         usbd_get_page(pc, 0, &buf_dev);
2686
2687         pc = &sc->sc_hw.devs[index].input_pc;
2688         pg = &sc->sc_hw.devs[index].input_pg;
2689
2690         /* need to initialize the page cache */
2691         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2692
2693         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2694             (2 * sizeof(struct xhci_input_dev_ctx)) :
2695             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2696                 goto error;
2697         }
2698
2699         /* initialise all endpoint LINK TRBs */
2700
2701         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2702
2703                 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2704                 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2705
2706                 /* need to initialize the page cache */
2707                 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2708
2709                 if (usb_pc_alloc_mem(pc, pg,
2710                     sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2711                         goto error;
2712                 }
2713
2714                 /* lookup endpoint TRB ring */
2715                 usbd_get_page(pc, 0, &buf_ep);
2716
2717                 /* get TRB pointer */
2718                 trb = buf_ep.buffer;
2719                 trb += XHCI_MAX_TRANSFERS - 1;
2720
2721                 /* get TRB start address */
2722                 addr = buf_ep.physaddr;
2723
2724                 /* create LINK TRB */
2725                 trb->qwTrb0 = htole64(addr);
2726                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2727                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2728                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2729
2730                 usb_pc_cpu_flush(pc);
2731         }
2732
2733         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2734
2735         return (0);
2736
2737 error:
2738         xhci_free_device_ext(udev);
2739
2740         return (USB_ERR_NOMEM);
2741 }
2742
2743 static void
2744 xhci_free_device_ext(struct usb_device *udev)
2745 {
2746         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2747         uint8_t index;
2748         uint8_t i;
2749
2750         index = udev->controller_slot_id;
2751         xhci_set_slot_pointer(sc, index, 0);
2752
2753         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2754         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2755         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2756                 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2757 }
2758
2759 static struct xhci_endpoint_ext *
2760 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2761 {
2762         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2763         struct xhci_endpoint_ext *pepext;
2764         struct usb_page_cache *pc;
2765         struct usb_page_search buf_ep;
2766         uint8_t epno;
2767         uint8_t index;
2768
2769         epno = edesc->bEndpointAddress;
2770         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2771                 epno |= UE_DIR_IN;
2772
2773         epno = XHCI_EPNO2EPID(epno);
2774
2775         index = udev->controller_slot_id;
2776
2777         pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2778
2779         usbd_get_page(pc, 0, &buf_ep);
2780
2781         pepext = &sc->sc_hw.devs[index].endp[epno];
2782         pepext->page_cache = pc;
2783         pepext->trb = buf_ep.buffer;
2784         pepext->physaddr = buf_ep.physaddr;
2785
2786         return (pepext);
2787 }
2788
2789 static void
2790 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2791 {
2792         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2793         uint8_t epno;
2794         uint8_t index;
2795
2796         epno = xfer->endpointno;
2797         if (xfer->flags_int.control_xfr)
2798                 epno |= UE_DIR_IN;
2799
2800         epno = XHCI_EPNO2EPID(epno);
2801         index = xfer->xroot->udev->controller_slot_id;
2802
2803         if (xfer->xroot->udev->flags.self_suspended == 0) {
2804                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2805                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2806         }
2807 }
2808
2809 static void
2810 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2811 {
2812         struct xhci_endpoint_ext *pepext;
2813
2814         if (xfer->flags_int.bandwidth_reclaimed) {
2815                 xfer->flags_int.bandwidth_reclaimed = 0;
2816
2817                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2818                     xfer->endpoint->edesc);
2819
2820                 pepext->trb_used[xfer->stream_id]--;
2821
2822                 pepext->xfer[xfer->qh_pos] = NULL;
2823
2824                 if (error && pepext->trb_running != 0) {
2825                         pepext->trb_halted = 1;
2826                         pepext->trb_running = 0;
2827                 }
2828         }
2829 }
2830
2831 static usb_error_t
2832 xhci_transfer_insert(struct usb_xfer *xfer)
2833 {
2834         struct xhci_td *td_first;
2835         struct xhci_td *td_last;
2836         struct xhci_trb *trb_link;
2837         struct xhci_endpoint_ext *pepext;
2838         uint64_t addr;
2839         usb_stream_t id;
2840         uint8_t i;
2841         uint8_t inext;
2842         uint8_t trb_limit;
2843
2844         DPRINTFN(8, "\n");
2845
2846         id = xfer->stream_id;
2847
2848         /* check if already inserted */
2849         if (xfer->flags_int.bandwidth_reclaimed) {
2850                 DPRINTFN(8, "Already in schedule\n");
2851                 return (0);
2852         }
2853
2854         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2855             xfer->endpoint->edesc);
2856
2857         td_first = xfer->td_transfer_first;
2858         td_last = xfer->td_transfer_last;
2859         addr = pepext->physaddr;
2860
2861         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2862         case UE_CONTROL:
2863         case UE_INTERRUPT:
2864                 /* single buffered */
2865                 trb_limit = 1;
2866                 break;
2867         default:
2868                 /* multi buffered */
2869                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2870                 break;
2871         }
2872
2873         if (pepext->trb_used[id] >= trb_limit) {
2874                 DPRINTFN(8, "Too many TDs queued.\n");
2875                 return (USB_ERR_NOMEM);
2876         }
2877
2878         /* check for stopped condition, after putting transfer on interrupt queue */
2879         if (pepext->trb_running == 0) {
2880                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2881
2882                 DPRINTFN(8, "Not running\n");
2883
2884                 /* start configuration */
2885                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2886                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2887                 return (0);
2888         }
2889
2890         pepext->trb_used[id]++;
2891
2892         /* get current TRB index */
2893         i = pepext->trb_index[id];
2894
2895         /* get next TRB index */
2896         inext = (i + 1);
2897
2898         /* the last entry of the ring is a hardcoded link TRB */
2899         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2900                 inext = 0;
2901
2902         /* store next TRB index, before stream ID offset is added */
2903         pepext->trb_index[id] = inext;
2904
2905         /* offset for stream */
2906         i += id * XHCI_MAX_TRANSFERS;
2907         inext += id * XHCI_MAX_TRANSFERS;
2908
2909         /* compute terminating return address */
2910         addr += (inext * sizeof(struct xhci_trb));
2911
2912         /* compute link TRB pointer */
2913         trb_link = td_last->td_trb + td_last->ntrb;
2914
2915         /* update next pointer of last link TRB */
2916         trb_link->qwTrb0 = htole64(addr);
2917         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2918         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2919             XHCI_TRB_3_CYCLE_BIT |
2920             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2921
2922 #ifdef USB_DEBUG
2923         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2924 #endif
2925         usb_pc_cpu_flush(td_last->page_cache);
2926
2927         /* write ahead chain end marker */
2928
2929         pepext->trb[inext].qwTrb0 = 0;
2930         pepext->trb[inext].dwTrb2 = 0;
2931         pepext->trb[inext].dwTrb3 = 0;
2932
2933         /* update next pointer of link TRB */
2934
2935         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2936         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2937
2938 #ifdef USB_DEBUG
2939         xhci_dump_trb(&pepext->trb[i]);
2940 #endif
2941         usb_pc_cpu_flush(pepext->page_cache);
2942
2943         /* toggle cycle bit which activates the transfer chain */
2944
2945         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2946             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2947
2948         usb_pc_cpu_flush(pepext->page_cache);
2949
2950         DPRINTF("qh_pos = %u\n", i);
2951
2952         pepext->xfer[i] = xfer;
2953
2954         xfer->qh_pos = i;
2955
2956         xfer->flags_int.bandwidth_reclaimed = 1;
2957
2958         xhci_endpoint_doorbell(xfer);
2959
2960         return (0);
2961 }
2962
2963 static void
2964 xhci_root_intr(struct xhci_softc *sc)
2965 {
2966         uint16_t i;
2967
2968         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2969
2970         /* clear any old interrupt data */
2971         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2972
2973         for (i = 1; i <= sc->sc_noport; i++) {
2974                 /* pick out CHANGE bits from the status register */
2975                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2976                     XHCI_PS_CSC | XHCI_PS_PEC |
2977                     XHCI_PS_OCC | XHCI_PS_WRC |
2978                     XHCI_PS_PRC | XHCI_PS_PLC |
2979                     XHCI_PS_CEC)) {
2980                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2981                         DPRINTF("port %d changed\n", i);
2982                 }
2983         }
2984         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2985             sizeof(sc->sc_hub_idata));
2986 }
2987
2988 /*------------------------------------------------------------------------*
2989  *      xhci_device_done - XHCI done handler
2990  *
2991  * NOTE: This function can be called two times in a row on
2992  * the same USB transfer. From close and from interrupt.
2993  *------------------------------------------------------------------------*/
2994 static void
2995 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2996 {
2997         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2998             xfer, xfer->endpoint, error);
2999
3000         /* remove transfer from HW queue */
3001         xhci_transfer_remove(xfer, error);
3002
3003         /* dequeue transfer and start next transfer */
3004         usbd_transfer_done(xfer, error);
3005 }
3006
3007 /*------------------------------------------------------------------------*
3008  * XHCI data transfer support (generic type)
3009  *------------------------------------------------------------------------*/
3010 static void
3011 xhci_device_generic_open(struct usb_xfer *xfer)
3012 {
3013         if (xfer->flags_int.isochronous_xfr) {
3014                 switch (xfer->xroot->udev->speed) {
3015                 case USB_SPEED_FULL:
3016                         break;
3017                 default:
3018                         usb_hs_bandwidth_alloc(xfer);
3019                         break;
3020                 }
3021         }
3022 }
3023
3024 static void
3025 xhci_device_generic_close(struct usb_xfer *xfer)
3026 {
3027         DPRINTF("\n");
3028
3029         xhci_device_done(xfer, USB_ERR_CANCELLED);
3030
3031         if (xfer->flags_int.isochronous_xfr) {
3032                 switch (xfer->xroot->udev->speed) {
3033                 case USB_SPEED_FULL:
3034                         break;
3035                 default:
3036                         usb_hs_bandwidth_free(xfer);
3037                         break;
3038                 }
3039         }
3040 }
3041
3042 static void
3043 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3044     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3045 {
3046         struct usb_xfer *xfer;
3047
3048         /* check if there is a current transfer */
3049         xfer = ep->endpoint_q[stream_id].curr;
3050         if (xfer == NULL)
3051                 return;
3052
3053         /*
3054          * Check if the current transfer is started and then pickup
3055          * the next one, if any. Else wait for next start event due to
3056          * block on failure feature.
3057          */
3058         if (!xfer->flags_int.bandwidth_reclaimed)
3059                 return;
3060
3061         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3062         if (xfer == NULL) {
3063                 /*
3064                  * In case of enter we have to consider that the
3065                  * transfer is queued by the USB core after the enter
3066                  * method is called.
3067                  */
3068                 xfer = enter_xfer;
3069
3070                 if (xfer == NULL)
3071                         return;
3072         }
3073
3074         /* try to multi buffer */
3075         xhci_transfer_insert(xfer);
3076 }
3077
3078 static void
3079 xhci_device_generic_enter(struct usb_xfer *xfer)
3080 {
3081         DPRINTF("\n");
3082
3083         /* setup TD's and QH */
3084         xhci_setup_generic_chain(xfer);
3085
3086         xhci_device_generic_multi_enter(xfer->endpoint,
3087             xfer->stream_id, xfer);
3088 }
3089
3090 static void
3091 xhci_device_generic_start(struct usb_xfer *xfer)
3092 {
3093         DPRINTF("\n");
3094
3095         /* try to insert xfer on HW queue */
3096         xhci_transfer_insert(xfer);
3097
3098         /* try to multi buffer */
3099         xhci_device_generic_multi_enter(xfer->endpoint,
3100             xfer->stream_id, NULL);
3101
3102         /* add transfer last on interrupt queue */
3103         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3104
3105         /* start timeout, if any */
3106         if (xfer->timeout != 0)
3107                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3108 }
3109
3110 struct usb_pipe_methods xhci_device_generic_methods =
3111 {
3112         .open = xhci_device_generic_open,
3113         .close = xhci_device_generic_close,
3114         .enter = xhci_device_generic_enter,
3115         .start = xhci_device_generic_start,
3116 };
3117
3118 /*------------------------------------------------------------------------*
3119  * xhci root HUB support
3120  *------------------------------------------------------------------------*
3121  * Simulate a hardware HUB by handling all the necessary requests.
3122  *------------------------------------------------------------------------*/
3123
3124 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3125
3126 static const
3127 struct usb_device_descriptor xhci_devd =
3128 {
3129         .bLength = sizeof(xhci_devd),
3130         .bDescriptorType = UDESC_DEVICE,        /* type */
3131         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3132         .bDeviceClass = UDCLASS_HUB,            /* class */
3133         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3134         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3135         .bMaxPacketSize = 9,                    /* max packet size */
3136         HSETW(.idVendor, 0x0000),               /* vendor */
3137         HSETW(.idProduct, 0x0000),              /* product */
3138         HSETW(.bcdDevice, 0x0100),              /* device version */
3139         .iManufacturer = 1,
3140         .iProduct = 2,
3141         .iSerialNumber = 0,
3142         .bNumConfigurations = 1,                /* # of configurations */
3143 };
3144
3145 static const
3146 struct xhci_bos_desc xhci_bosd = {
3147         .bosd = {
3148                 .bLength = sizeof(xhci_bosd.bosd),
3149                 .bDescriptorType = UDESC_BOS,
3150                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3151                 .bNumDeviceCaps = 3,
3152         },
3153         .usb2extd = {
3154                 .bLength = sizeof(xhci_bosd.usb2extd),
3155                 .bDescriptorType = 1,
3156                 .bDevCapabilityType = 2,
3157                 .bmAttributes[0] = 2,
3158         },
3159         .usbdcd = {
3160                 .bLength = sizeof(xhci_bosd.usbdcd),
3161                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3162                 .bDevCapabilityType = 3,
3163                 .bmAttributes = 0, /* XXX */
3164                 HSETW(.wSpeedsSupported, 0x000C),
3165                 .bFunctionalitySupport = 8,
3166                 .bU1DevExitLat = 255,   /* dummy - not used */
3167                 .wU2DevExitLat = { 0x00, 0x08 },
3168         },
3169         .cidd = {
3170                 .bLength = sizeof(xhci_bosd.cidd),
3171                 .bDescriptorType = 1,
3172                 .bDevCapabilityType = 4,
3173                 .bReserved = 0,
3174                 .bContainerID = 0, /* XXX */
3175         },
3176 };
3177
3178 static const
3179 struct xhci_config_desc xhci_confd = {
3180         .confd = {
3181                 .bLength = sizeof(xhci_confd.confd),
3182                 .bDescriptorType = UDESC_CONFIG,
3183                 .wTotalLength[0] = sizeof(xhci_confd),
3184                 .bNumInterface = 1,
3185                 .bConfigurationValue = 1,
3186                 .iConfiguration = 0,
3187                 .bmAttributes = UC_SELF_POWERED,
3188                 .bMaxPower = 0          /* max power */
3189         },
3190         .ifcd = {
3191                 .bLength = sizeof(xhci_confd.ifcd),
3192                 .bDescriptorType = UDESC_INTERFACE,
3193                 .bNumEndpoints = 1,
3194                 .bInterfaceClass = UICLASS_HUB,
3195                 .bInterfaceSubClass = UISUBCLASS_HUB,
3196                 .bInterfaceProtocol = 0,
3197         },
3198         .endpd = {
3199                 .bLength = sizeof(xhci_confd.endpd),
3200                 .bDescriptorType = UDESC_ENDPOINT,
3201                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3202                 .bmAttributes = UE_INTERRUPT,
3203                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3204                 .bInterval = 255,
3205         },
3206         .endpcd = {
3207                 .bLength = sizeof(xhci_confd.endpcd),
3208                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3209                 .bMaxBurst = 0,
3210                 .bmAttributes = 0,
3211         },
3212 };
3213
3214 static const
3215 struct usb_hub_ss_descriptor xhci_hubd = {
3216         .bLength = sizeof(xhci_hubd),
3217         .bDescriptorType = UDESC_SS_HUB,
3218 };
3219
3220 static usb_error_t
3221 xhci_roothub_exec(struct usb_device *udev,
3222     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3223 {
3224         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3225         const char *str_ptr;
3226         const void *ptr;
3227         uint32_t port;
3228         uint32_t v;
3229         uint16_t len;
3230         uint16_t i;
3231         uint16_t value;
3232         uint16_t index;
3233         uint8_t j;
3234         usb_error_t err;
3235
3236         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3237
3238         /* buffer reset */
3239         ptr = (const void *)&sc->sc_hub_desc;
3240         len = 0;
3241         err = 0;
3242
3243         value = UGETW(req->wValue);
3244         index = UGETW(req->wIndex);
3245
3246         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3247             "wValue=0x%04x wIndex=0x%04x\n",
3248             req->bmRequestType, req->bRequest,
3249             UGETW(req->wLength), value, index);
3250
3251 #define C(x,y) ((x) | ((y) << 8))
3252         switch (C(req->bRequest, req->bmRequestType)) {
3253         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3254         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3255         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3256                 /*
3257                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3258                  * for the integrated root hub.
3259                  */
3260                 break;
3261         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3262                 len = 1;
3263                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3264                 break;
3265         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3266                 switch (value >> 8) {
3267                 case UDESC_DEVICE:
3268                         if ((value & 0xff) != 0) {
3269                                 err = USB_ERR_IOERROR;
3270                                 goto done;
3271                         }
3272                         len = sizeof(xhci_devd);
3273                         ptr = (const void *)&xhci_devd;
3274                         break;
3275
3276                 case UDESC_BOS:
3277                         if ((value & 0xff) != 0) {
3278                                 err = USB_ERR_IOERROR;
3279                                 goto done;
3280                         }
3281                         len = sizeof(xhci_bosd);
3282                         ptr = (const void *)&xhci_bosd;
3283                         break;
3284
3285                 case UDESC_CONFIG:
3286                         if ((value & 0xff) != 0) {
3287                                 err = USB_ERR_IOERROR;
3288                                 goto done;
3289                         }
3290                         len = sizeof(xhci_confd);
3291                         ptr = (const void *)&xhci_confd;
3292                         break;
3293
3294                 case UDESC_STRING:
3295                         switch (value & 0xff) {
3296                         case 0: /* Language table */
3297                                 str_ptr = "\001";
3298                                 break;
3299
3300                         case 1: /* Vendor */
3301                                 str_ptr = sc->sc_vendor;
3302                                 break;
3303
3304                         case 2: /* Product */
3305                                 str_ptr = "XHCI root HUB";
3306                                 break;
3307
3308                         default:
3309                                 str_ptr = "";
3310                                 break;
3311                         }
3312
3313                         len = usb_make_str_desc(
3314                             sc->sc_hub_desc.temp,
3315                             sizeof(sc->sc_hub_desc.temp),
3316                             str_ptr);
3317                         break;
3318
3319                 default:
3320                         err = USB_ERR_IOERROR;
3321                         goto done;
3322                 }
3323                 break;
3324         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3325                 len = 1;
3326                 sc->sc_hub_desc.temp[0] = 0;
3327                 break;
3328         case C(UR_GET_STATUS, UT_READ_DEVICE):
3329                 len = 2;
3330                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3331                 break;
3332         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3333         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3334                 len = 2;
3335                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3336                 break;
3337         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3338                 if (value >= XHCI_MAX_DEVICES) {
3339                         err = USB_ERR_IOERROR;
3340                         goto done;
3341                 }
3342                 break;
3343         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3344                 if (value != 0 && value != 1) {
3345                         err = USB_ERR_IOERROR;
3346                         goto done;
3347                 }
3348                 sc->sc_conf = value;
3349                 break;
3350         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3351                 break;
3352         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3353         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3354         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3355                 err = USB_ERR_IOERROR;
3356                 goto done;
3357         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3358                 break;
3359         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3360                 break;
3361                 /* Hub requests */
3362         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3363                 break;
3364         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3365                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3366
3367                 if ((index < 1) ||
3368                     (index > sc->sc_noport)) {
3369                         err = USB_ERR_IOERROR;
3370                         goto done;
3371                 }
3372                 port = XHCI_PORTSC(index);
3373
3374                 v = XREAD4(sc, oper, port);
3375                 i = XHCI_PS_PLS_GET(v);
3376                 v &= ~XHCI_PS_CLEAR;
3377
3378                 switch (value) {
3379                 case UHF_C_BH_PORT_RESET:
3380                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3381                         break;
3382                 case UHF_C_PORT_CONFIG_ERROR:
3383                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3384                         break;
3385                 case UHF_C_PORT_SUSPEND:
3386                 case UHF_C_PORT_LINK_STATE:
3387                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3388                         break;
3389                 case UHF_C_PORT_CONNECTION:
3390                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3391                         break;
3392                 case UHF_C_PORT_ENABLE:
3393                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3394                         break;
3395                 case UHF_C_PORT_OVER_CURRENT:
3396                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3397                         break;
3398                 case UHF_C_PORT_RESET:
3399                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3400                         break;
3401                 case UHF_PORT_ENABLE:
3402                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3403                         break;
3404                 case UHF_PORT_POWER:
3405                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3406                         break;
3407                 case UHF_PORT_INDICATOR:
3408                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3409                         break;
3410                 case UHF_PORT_SUSPEND:
3411
3412                         /* U3 -> U15 */
3413                         if (i == 3) {
3414                                 XWRITE4(sc, oper, port, v |
3415                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3416                         }
3417
3418                         /* wait 20ms for resume sequence to complete */
3419                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3420
3421                         /* U0 */
3422                         XWRITE4(sc, oper, port, v |
3423                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3424                         break;
3425                 default:
3426                         err = USB_ERR_IOERROR;
3427                         goto done;
3428                 }
3429                 break;
3430
3431         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3432                 if ((value & 0xff) != 0) {
3433                         err = USB_ERR_IOERROR;
3434                         goto done;
3435                 }
3436
3437                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3438
3439                 sc->sc_hub_desc.hubd = xhci_hubd;
3440
3441                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3442
3443                 if (XHCI_HCS0_PPC(v))
3444                         i = UHD_PWR_INDIVIDUAL;
3445                 else
3446                         i = UHD_PWR_GANGED;
3447
3448                 if (XHCI_HCS0_PIND(v))
3449                         i |= UHD_PORT_IND;
3450
3451                 i |= UHD_OC_INDIVIDUAL;
3452
3453                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3454
3455                 /* see XHCI section 5.4.9: */
3456                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3457
3458                 for (j = 1; j <= sc->sc_noport; j++) {
3459
3460                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3461                         if (v & XHCI_PS_DR) {
3462                                 sc->sc_hub_desc.hubd.
3463                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3464                         }
3465                 }
3466                 len = sc->sc_hub_desc.hubd.bLength;
3467                 break;
3468
3469         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3470                 len = 16;
3471                 memset(sc->sc_hub_desc.temp, 0, 16);
3472                 break;
3473
3474         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3475                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3476
3477                 if ((index < 1) ||
3478                     (index > sc->sc_noport)) {
3479                         err = USB_ERR_IOERROR;
3480                         goto done;
3481                 }
3482
3483                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3484
3485                 DPRINTFN(9, "port status=0x%08x\n", v);
3486
3487                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3488
3489                 switch (XHCI_PS_SPEED_GET(v)) {
3490                 case 3:
3491                         i |= UPS_HIGH_SPEED;
3492                         break;
3493                 case 2:
3494                         i |= UPS_LOW_SPEED;
3495                         break;
3496                 case 1:
3497                         /* FULL speed */
3498                         break;
3499                 default:
3500                         i |= UPS_OTHER_SPEED;
3501                         break;
3502                 }
3503
3504                 if (v & XHCI_PS_CCS)
3505                         i |= UPS_CURRENT_CONNECT_STATUS;
3506                 if (v & XHCI_PS_PED)
3507                         i |= UPS_PORT_ENABLED;
3508                 if (v & XHCI_PS_OCA)
3509                         i |= UPS_OVERCURRENT_INDICATOR;
3510                 if (v & XHCI_PS_PR)
3511                         i |= UPS_RESET;
3512                 if (v & XHCI_PS_PP) {
3513                         /*
3514                          * The USB 3.0 RH is using the
3515                          * USB 2.0's power bit
3516                          */
3517                         i |= UPS_PORT_POWER;
3518                 }
3519                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3520
3521                 i = 0;
3522                 if (v & XHCI_PS_CSC)
3523                         i |= UPS_C_CONNECT_STATUS;
3524                 if (v & XHCI_PS_PEC)
3525                         i |= UPS_C_PORT_ENABLED;
3526                 if (v & XHCI_PS_OCC)
3527                         i |= UPS_C_OVERCURRENT_INDICATOR;
3528                 if (v & XHCI_PS_WRC)
3529                         i |= UPS_C_BH_PORT_RESET;
3530                 if (v & XHCI_PS_PRC)
3531                         i |= UPS_C_PORT_RESET;
3532                 if (v & XHCI_PS_PLC)
3533                         i |= UPS_C_PORT_LINK_STATE;
3534                 if (v & XHCI_PS_CEC)
3535                         i |= UPS_C_PORT_CONFIG_ERROR;
3536
3537                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3538                 len = sizeof(sc->sc_hub_desc.ps);
3539                 break;
3540
3541         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3542                 err = USB_ERR_IOERROR;
3543                 goto done;
3544
3545         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3546                 break;
3547
3548         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3549
3550                 i = index >> 8;
3551                 index &= 0x00FF;
3552
3553                 if ((index < 1) ||
3554                     (index > sc->sc_noport)) {
3555                         err = USB_ERR_IOERROR;
3556                         goto done;
3557                 }
3558
3559                 port = XHCI_PORTSC(index);
3560                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3561
3562                 switch (value) {
3563                 case UHF_PORT_U1_TIMEOUT:
3564                         if (XHCI_PS_SPEED_GET(v) != 4) {
3565                                 err = USB_ERR_IOERROR;
3566                                 goto done;
3567                         }
3568                         port = XHCI_PORTPMSC(index);
3569                         v = XREAD4(sc, oper, port);
3570                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3571                         v |= XHCI_PM3_U1TO_SET(i);
3572                         XWRITE4(sc, oper, port, v);
3573                         break;
3574                 case UHF_PORT_U2_TIMEOUT:
3575                         if (XHCI_PS_SPEED_GET(v) != 4) {
3576                                 err = USB_ERR_IOERROR;
3577                                 goto done;
3578                         }
3579                         port = XHCI_PORTPMSC(index);
3580                         v = XREAD4(sc, oper, port);
3581                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3582                         v |= XHCI_PM3_U2TO_SET(i);
3583                         XWRITE4(sc, oper, port, v);
3584                         break;
3585                 case UHF_BH_PORT_RESET:
3586                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3587                         break;
3588                 case UHF_PORT_LINK_STATE:
3589                         XWRITE4(sc, oper, port, v |
3590                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3591                         /* 4ms settle time */
3592                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3593                         break;
3594                 case UHF_PORT_ENABLE:
3595                         DPRINTFN(3, "set port enable %d\n", index);
3596                         break;
3597                 case UHF_PORT_SUSPEND:
3598                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3599                         j = XHCI_PS_SPEED_GET(v);
3600                         if ((j < 1) || (j > 3)) {
3601                                 /* non-supported speed */
3602                                 err = USB_ERR_IOERROR;
3603                                 goto done;
3604                         }
3605                         XWRITE4(sc, oper, port, v |
3606                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3607                         break;
3608                 case UHF_PORT_RESET:
3609                         DPRINTFN(6, "reset port %d\n", index);
3610                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3611                         break;
3612                 case UHF_PORT_POWER:
3613                         DPRINTFN(3, "set port power %d\n", index);
3614                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3615                         break;
3616                 case UHF_PORT_TEST:
3617                         DPRINTFN(3, "set port test %d\n", index);
3618                         break;
3619                 case UHF_PORT_INDICATOR:
3620                         DPRINTFN(3, "set port indicator %d\n", index);
3621
3622                         v &= ~XHCI_PS_PIC_SET(3);
3623                         v |= XHCI_PS_PIC_SET(1);
3624
3625                         XWRITE4(sc, oper, port, v);
3626                         break;
3627                 default:
3628                         err = USB_ERR_IOERROR;
3629                         goto done;
3630                 }
3631                 break;
3632
3633         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3634         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3635         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3636         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3637                 break;
3638         default:
3639                 err = USB_ERR_IOERROR;
3640                 goto done;
3641         }
3642 done:
3643         *plength = len;
3644         *pptr = ptr;
3645         return (err);
3646 }
3647
3648 static void
3649 xhci_xfer_setup(struct usb_setup_params *parm)
3650 {
3651         struct usb_page_search page_info;
3652         struct usb_page_cache *pc;
3653         struct xhci_softc *sc;
3654         struct usb_xfer *xfer;
3655         void *last_obj;
3656         uint32_t ntd;
3657         uint32_t n;
3658
3659         sc = XHCI_BUS2SC(parm->udev->bus);
3660         xfer = parm->curr_xfer;
3661
3662         /*
3663          * The proof for the "ntd" formula is illustrated like this:
3664          *
3665          * +------------------------------------+
3666          * |                                    |
3667          * |         |remainder ->              |
3668          * |   +-----+---+                      |
3669          * |   | xxx | x | frm 0                |
3670          * |   +-----+---++                     |
3671          * |   | xxx | xx | frm 1               |
3672          * |   +-----+----+                     |
3673          * |            ...                     |
3674          * +------------------------------------+
3675          *
3676          * "xxx" means a completely full USB transfer descriptor
3677          *
3678          * "x" and "xx" means a short USB packet
3679          *
3680          * For the remainder of an USB transfer modulo
3681          * "max_data_length" we need two USB transfer descriptors.
3682          * One to transfer the remaining data and one to finalise with
3683          * a zero length packet in case the "force_short_xfer" flag is
3684          * set. We only need two USB transfer descriptors in the case
3685          * where the transfer length of the first one is a factor of
3686          * "max_frame_size". The rest of the needed USB transfer
3687          * descriptors is given by the buffer size divided by the
3688          * maximum data payload.
3689          */
3690         parm->hc_max_packet_size = 0x400;
3691         parm->hc_max_packet_count = 16 * 3;
3692         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3693
3694         xfer->flags_int.bdma_enable = 1;
3695
3696         usbd_transfer_setup_sub(parm);
3697
3698         if (xfer->flags_int.isochronous_xfr) {
3699                 ntd = ((1 * xfer->nframes)
3700                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3701         } else if (xfer->flags_int.control_xfr) {
3702                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3703                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3704         } else {
3705                 ntd = ((2 * xfer->nframes)
3706                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3707         }
3708
3709 alloc_dma_set:
3710
3711         if (parm->err)
3712                 return;
3713
3714         /*
3715          * Allocate queue heads and transfer descriptors
3716          */
3717         last_obj = NULL;
3718
3719         if (usbd_transfer_setup_sub_malloc(
3720             parm, &pc, sizeof(struct xhci_td),
3721             XHCI_TD_ALIGN, ntd)) {
3722                 parm->err = USB_ERR_NOMEM;
3723                 return;
3724         }
3725         if (parm->buf) {
3726                 for (n = 0; n != ntd; n++) {
3727                         struct xhci_td *td;
3728
3729                         usbd_get_page(pc + n, 0, &page_info);
3730
3731                         td = page_info.buffer;
3732
3733                         /* init TD */
3734                         td->td_self = page_info.physaddr;
3735                         td->obj_next = last_obj;
3736                         td->page_cache = pc + n;
3737
3738                         last_obj = td;
3739
3740                         usb_pc_cpu_flush(pc + n);
3741                 }
3742         }
3743         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3744
3745         if (!xfer->flags_int.curr_dma_set) {
3746                 xfer->flags_int.curr_dma_set = 1;
3747                 goto alloc_dma_set;
3748         }
3749 }
3750
3751 static usb_error_t
3752 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3753 {
3754         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3755         struct usb_page_search buf_inp;
3756         struct usb_device *udev;
3757         struct xhci_endpoint_ext *pepext;
3758         struct usb_endpoint_descriptor *edesc;
3759         struct usb_page_cache *pcinp;
3760         usb_error_t err;
3761         usb_stream_t stream_id;
3762         uint8_t index;
3763         uint8_t epno;
3764
3765         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3766             xfer->endpoint->edesc);
3767
3768         udev = xfer->xroot->udev;
3769         index = udev->controller_slot_id;
3770
3771         pcinp = &sc->sc_hw.devs[index].input_pc;
3772
3773         usbd_get_page(pcinp, 0, &buf_inp);
3774
3775         edesc = xfer->endpoint->edesc;
3776
3777         epno = edesc->bEndpointAddress;
3778         stream_id = xfer->stream_id;
3779
3780         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3781                 epno |= UE_DIR_IN;
3782
3783         epno = XHCI_EPNO2EPID(epno);
3784
3785         if (epno == 0)
3786                 return (USB_ERR_NO_PIPE);               /* invalid */
3787
3788         XHCI_CMD_LOCK(sc);
3789
3790         /* configure endpoint */
3791
3792         err = xhci_configure_endpoint_by_xfer(xfer);
3793
3794         if (err != 0) {
3795                 XHCI_CMD_UNLOCK(sc);
3796                 return (err);
3797         }
3798
3799         /*
3800          * Get the endpoint into the stopped state according to the
3801          * endpoint context state diagram in the XHCI specification:
3802          */
3803
3804         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3805
3806         if (err != 0)
3807                 DPRINTF("Could not stop endpoint %u\n", epno);
3808
3809         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3810
3811         if (err != 0)
3812                 DPRINTF("Could not reset endpoint %u\n", epno);
3813
3814         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3815             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3816             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3817             stream_id, epno, index);
3818
3819         if (err != 0)
3820                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3821
3822         /*
3823          * Get the endpoint into the running state according to the
3824          * endpoint context state diagram in the XHCI specification:
3825          */
3826
3827         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3828
3829         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3830
3831         if (err != 0)
3832                 DPRINTF("Could not configure endpoint %u\n", epno);
3833
3834         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3835
3836         if (err != 0)
3837                 DPRINTF("Could not configure endpoint %u\n", epno);
3838
3839         XHCI_CMD_UNLOCK(sc);
3840
3841         return (0);
3842 }
3843
3844 static void
3845 xhci_xfer_unsetup(struct usb_xfer *xfer)
3846 {
3847         return;
3848 }
3849
3850 static void
3851 xhci_start_dma_delay(struct usb_xfer *xfer)
3852 {
3853         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3854
3855         /* put transfer on interrupt queue (again) */
3856         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3857
3858         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3859             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3860 }
3861
3862 static void
3863 xhci_configure_msg(struct usb_proc_msg *pm)
3864 {
3865         struct xhci_softc *sc;
3866         struct xhci_endpoint_ext *pepext;
3867         struct usb_xfer *xfer;
3868
3869         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3870
3871 restart:
3872         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3873
3874                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3875                     xfer->endpoint->edesc);
3876
3877                 if ((pepext->trb_halted != 0) ||
3878                     (pepext->trb_running == 0)) {
3879
3880                         uint16_t i;
3881
3882                         /* clear halted and running */
3883                         pepext->trb_halted = 0;
3884                         pepext->trb_running = 0;
3885
3886                         /* nuke remaining buffered transfers */
3887
3888                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3889                             XHCI_MAX_STREAMS); i++) {
3890                                 /*
3891                                  * NOTE: We need to use the timeout
3892                                  * error code here else existing
3893                                  * isochronous clients can get
3894                                  * confused:
3895                                  */
3896                                 if (pepext->xfer[i] != NULL) {
3897                                         xhci_device_done(pepext->xfer[i],
3898                                             USB_ERR_TIMEOUT);
3899                                 }
3900                         }
3901
3902                         /*
3903                          * NOTE: The USB transfer cannot vanish in
3904                          * this state!
3905                          */
3906
3907                         USB_BUS_UNLOCK(&sc->sc_bus);
3908
3909                         xhci_configure_reset_endpoint(xfer);
3910
3911                         USB_BUS_LOCK(&sc->sc_bus);
3912
3913                         /* check if halted is still cleared */
3914                         if (pepext->trb_halted == 0) {
3915                                 pepext->trb_running = 1;
3916                                 memset(pepext->trb_index, 0,
3917                                     sizeof(pepext->trb_index));
3918                         }
3919                         goto restart;
3920                 }
3921
3922                 if (xfer->flags_int.did_dma_delay) {
3923
3924                         /* remove transfer from interrupt queue (again) */
3925                         usbd_transfer_dequeue(xfer);
3926
3927                         /* we are finally done */
3928                         usb_dma_delay_done_cb(xfer);
3929
3930                         /* queue changed - restart */
3931                         goto restart;
3932                 }
3933         }
3934
3935         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3936
3937                 /* try to insert xfer on HW queue */
3938                 xhci_transfer_insert(xfer);
3939
3940                 /* try to multi buffer */
3941                 xhci_device_generic_multi_enter(xfer->endpoint,
3942                     xfer->stream_id, NULL);
3943         }
3944 }
3945
3946 static void
3947 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3948     struct usb_endpoint *ep)
3949 {
3950         struct xhci_endpoint_ext *pepext;
3951
3952         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3953             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3954
3955         if (udev->parent_hub == NULL) {
3956                 /* root HUB has special endpoint handling */
3957                 return;
3958         }
3959
3960         ep->methods = &xhci_device_generic_methods;
3961
3962         pepext = xhci_get_endpoint_ext(udev, edesc);
3963
3964         USB_BUS_LOCK(udev->bus);
3965         pepext->trb_halted = 1;
3966         pepext->trb_running = 0;
3967         USB_BUS_UNLOCK(udev->bus);
3968 }
3969
3970 static void
3971 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3972 {
3973
3974 }
3975
3976 static void
3977 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3978 {
3979         struct xhci_endpoint_ext *pepext;
3980
3981         DPRINTF("\n");
3982
3983         if (udev->flags.usb_mode != USB_MODE_HOST) {
3984                 /* not supported */
3985                 return;
3986         }
3987         if (udev->parent_hub == NULL) {
3988                 /* root HUB has special endpoint handling */
3989                 return;
3990         }
3991
3992         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3993
3994         USB_BUS_LOCK(udev->bus);
3995         pepext->trb_halted = 1;
3996         pepext->trb_running = 0;
3997         USB_BUS_UNLOCK(udev->bus);
3998 }
3999
4000 static usb_error_t
4001 xhci_device_init(struct usb_device *udev)
4002 {
4003         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4004         usb_error_t err;
4005         uint8_t temp;
4006
4007         /* no init for root HUB */
4008         if (udev->parent_hub == NULL)
4009                 return (0);
4010
4011         XHCI_CMD_LOCK(sc);
4012
4013         /* set invalid default */
4014
4015         udev->controller_slot_id = sc->sc_noslot + 1;
4016
4017         /* try to get a new slot ID from the XHCI */
4018
4019         err = xhci_cmd_enable_slot(sc, &temp);
4020
4021         if (err) {
4022                 XHCI_CMD_UNLOCK(sc);
4023                 return (err);
4024         }
4025
4026         if (temp > sc->sc_noslot) {
4027                 XHCI_CMD_UNLOCK(sc);
4028                 return (USB_ERR_BAD_ADDRESS);
4029         }
4030
4031         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4032                 DPRINTF("slot %u already allocated.\n", temp);
4033                 XHCI_CMD_UNLOCK(sc);
4034                 return (USB_ERR_BAD_ADDRESS);
4035         }
4036
4037         /* store slot ID for later reference */
4038
4039         udev->controller_slot_id = temp;
4040
4041         /* reset data structure */
4042
4043         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4044
4045         /* set mark slot allocated */
4046
4047         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4048
4049         err = xhci_alloc_device_ext(udev);
4050
4051         XHCI_CMD_UNLOCK(sc);
4052
4053         /* get device into default state */
4054
4055         if (err == 0)
4056                 err = xhci_set_address(udev, NULL, 0);
4057
4058         return (err);
4059 }
4060
4061 static void
4062 xhci_device_uninit(struct usb_device *udev)
4063 {
4064         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4065         uint8_t index;
4066
4067         /* no init for root HUB */
4068         if (udev->parent_hub == NULL)
4069                 return;
4070
4071         XHCI_CMD_LOCK(sc);
4072
4073         index = udev->controller_slot_id;
4074
4075         if (index <= sc->sc_noslot) {
4076                 xhci_cmd_disable_slot(sc, index);
4077                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4078
4079                 /* free device extension */
4080                 xhci_free_device_ext(udev);
4081         }
4082
4083         XHCI_CMD_UNLOCK(sc);
4084 }
4085
4086 static void
4087 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4088 {
4089         /*
4090          * Wait until the hardware has finished any possible use of
4091          * the transfer descriptor(s)
4092          */
4093         *pus = 2048;                    /* microseconds */
4094 }
4095
4096 static void
4097 xhci_device_resume(struct usb_device *udev)
4098 {
4099         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4100         uint8_t index;
4101         uint8_t n;
4102         uint8_t p;
4103
4104         DPRINTF("\n");
4105
4106         /* check for root HUB */
4107         if (udev->parent_hub == NULL)
4108                 return;
4109
4110         index = udev->controller_slot_id;
4111
4112         XHCI_CMD_LOCK(sc);
4113
4114         /* blindly resume all endpoints */
4115
4116         USB_BUS_LOCK(udev->bus);
4117
4118         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4119                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4120                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4121                             n | XHCI_DB_SID_SET(p));
4122                 }
4123         }
4124
4125         USB_BUS_UNLOCK(udev->bus);
4126
4127         XHCI_CMD_UNLOCK(sc);
4128 }
4129
4130 static void
4131 xhci_device_suspend(struct usb_device *udev)
4132 {
4133         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4134         uint8_t index;
4135         uint8_t n;
4136         usb_error_t err;
4137
4138         DPRINTF("\n");
4139
4140         /* check for root HUB */
4141         if (udev->parent_hub == NULL)
4142                 return;
4143
4144         index = udev->controller_slot_id;
4145
4146         XHCI_CMD_LOCK(sc);
4147
4148         /* blindly suspend all endpoints */
4149
4150         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4151                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4152                 if (err != 0) {
4153                         DPRINTF("Failed to suspend endpoint "
4154                             "%u on slot %u (ignored).\n", n, index);
4155                 }
4156         }
4157
4158         XHCI_CMD_UNLOCK(sc);
4159 }
4160
4161 static void
4162 xhci_set_hw_power(struct usb_bus *bus)
4163 {
4164         DPRINTF("\n");
4165 }
4166
4167 static void
4168 xhci_device_state_change(struct usb_device *udev)
4169 {
4170         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4171         struct usb_page_search buf_inp;
4172         usb_error_t err;
4173         uint8_t index;
4174
4175         /* check for root HUB */
4176         if (udev->parent_hub == NULL)
4177                 return;
4178
4179         index = udev->controller_slot_id;
4180
4181         DPRINTF("\n");
4182
4183         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4184                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4185                     &sc->sc_hw.devs[index].tt);
4186                 if (err != 0)
4187                         sc->sc_hw.devs[index].nports = 0;
4188         }
4189
4190         XHCI_CMD_LOCK(sc);
4191
4192         switch (usb_get_device_state(udev)) {
4193         case USB_STATE_POWERED:
4194                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4195                         break;
4196
4197                 /* set default state */
4198                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4199
4200                 /* reset number of contexts */
4201                 sc->sc_hw.devs[index].context_num = 0;
4202
4203                 err = xhci_cmd_reset_dev(sc, index);
4204
4205                 if (err != 0) {
4206                         DPRINTF("Device reset failed "
4207                             "for slot %u.\n", index);
4208                 }
4209                 break;
4210
4211         case USB_STATE_ADDRESSED:
4212                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4213                         break;
4214
4215                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4216
4217                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4218
4219                 if (err) {
4220                         DPRINTF("Failed to deconfigure "
4221                             "slot %u.\n", index);
4222                 }
4223                 break;
4224
4225         case USB_STATE_CONFIGURED:
4226                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4227                         break;
4228
4229                 /* set configured state */
4230                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4231
4232                 /* reset number of contexts */
4233                 sc->sc_hw.devs[index].context_num = 0;
4234
4235                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4236
4237                 xhci_configure_mask(udev, 3, 0);
4238
4239                 err = xhci_configure_device(udev);
4240                 if (err != 0) {
4241                         DPRINTF("Could not configure device "
4242                             "at slot %u.\n", index);
4243                 }
4244
4245                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4246                 if (err != 0) {
4247                         DPRINTF("Could not evaluate device "
4248                             "context at slot %u.\n", index);
4249                 }
4250                 break;
4251
4252         default:
4253                 break;
4254         }
4255         XHCI_CMD_UNLOCK(sc);
4256 }
4257
4258 static usb_error_t
4259 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4260     uint8_t ep_mode)
4261 {
4262         switch (ep_mode) {
4263         case USB_EP_MODE_DEFAULT:
4264                 return (0);
4265         case USB_EP_MODE_STREAMS:
4266                 if (xhcistreams == 0 ||
4267                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4268                     udev->speed != USB_SPEED_SUPER)
4269                         return (USB_ERR_INVAL);
4270                 return (0);
4271         default:
4272                 return (USB_ERR_INVAL);
4273         }
4274 }
4275
4276 struct usb_bus_methods xhci_bus_methods = {
4277         .endpoint_init = xhci_ep_init,
4278         .endpoint_uninit = xhci_ep_uninit,
4279         .xfer_setup = xhci_xfer_setup,
4280         .xfer_unsetup = xhci_xfer_unsetup,
4281         .get_dma_delay = xhci_get_dma_delay,
4282         .device_init = xhci_device_init,
4283         .device_uninit = xhci_device_uninit,
4284         .device_resume = xhci_device_resume,
4285         .device_suspend = xhci_device_suspend,
4286         .set_hw_power = xhci_set_hw_power,
4287         .roothub_exec = xhci_roothub_exec,
4288         .xfer_poll = xhci_do_poll,
4289         .start_dma_delay = xhci_start_dma_delay,
4290         .set_address = xhci_set_address,
4291         .clear_stall = xhci_ep_clear_stall,
4292         .device_state_change = xhci_device_state_change,
4293         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4294         .set_endpoint_mode = xhci_set_endpoint_mode,
4295 };