sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  29  *
  30  * The XHCI 1.0 spec can be found at
  31  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  32  * and the USB 3.0 spec at
  33  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  34  */
  35
  36 /*
  37  * A few words about the design implementation: This driver emulates
  38  * the concept about TDs which is found in EHCI specification. This
  39  * way we achieve that the USB controller drivers look similar to
  40  * eachother which makes it easier to understand the code.
  41  */
  42
  43 #ifdef USB_GLOBAL_INCLUDE_FILE
  44 #include USB_GLOBAL_INCLUDE_FILE
  45 #else
  46 #include <sys/stdint.h>
  47 #include <sys/stddef.h>
  48 #include <sys/param.h>
  49 #include <sys/queue.h>
  50 #include <sys/types.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/bus.h>
  54 #include <sys/module.h>
  55 #include <sys/lock.h>
  56 #include <sys/mutex.h>
  57 #include <sys/condvar.h>
  58 #include <sys/sysctl.h>
  59 #include <sys/sx.h>
  60 #include <sys/unistd.h>
  61 #include <sys/callout.h>
  62 #include <sys/malloc.h>
  63 #include <sys/priv.h>
  64
  65 #include <dev/usb/usb.h>
  66 #include <dev/usb/usbdi.h>
  67
  68 #define USB_DEBUG_VAR xhcidebug
  69
  70 #include <dev/usb/usb_core.h>
  71 #include <dev/usb/usb_debug.h>
  72 #include <dev/usb/usb_busdma.h>
  73 #include <dev/usb/usb_process.h>
  74 #include <dev/usb/usb_transfer.h>
  75 #include <dev/usb/usb_device.h>
  76 #include <dev/usb/usb_hub.h>
  77 #include <dev/usb/usb_util.h>
  78
  79 #include <dev/usb/usb_controller.h>
  80 #include <dev/usb/usb_bus.h>
  81 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  82
  83 #include <dev/usb/controller/xhci.h>
  84 #include <dev/usb/controller/xhcireg.h>
  85
  86 #define XHCI_BUS2SC(bus) \
  87    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  88     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  89
  90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91
  92 static int xhcistreams;
  93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
  94     &xhcistreams, 0, "Set to enable streams mode support");
  95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
  96
  97 #ifdef USB_DEBUG
  98 static int xhcidebug;
  99 static int xhciroute;
 100 static int xhcipolling;
 101 static int xhcidma32;
 102
 103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
 104     &xhcidebug, 0, "Debug level");
 105 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
 106 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
 107     &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
 108 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
 109 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
 110     &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
 111 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 112 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
 113     &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
 114 TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32);
 115 #else
 116 #define xhciroute 0
 117 #define xhcidma32 0
 118 #endif
 119
 120 #define XHCI_INTR_ENDPT 1
 121
 122 struct xhci_std_temp {
 123         struct xhci_softc       *sc;
 124         struct usb_page_cache   *pc;
 125         struct xhci_td          *td;
 126         struct xhci_td          *td_next;
 127         uint32_t                len;
 128         uint32_t                offset;
 129         uint32_t                max_packet_size;
 130         uint32_t                average;
 131         uint16_t                isoc_delta;
 132         uint16_t                isoc_frame;
 133         uint8_t                 shortpkt;
 134         uint8_t                 multishort;
 135         uint8_t                 last_frame;
 136         uint8_t                 trb_type;
 137         uint8_t                 direction;
 138         uint8_t                 tbc;
 139         uint8_t                 tlbpc;
 140         uint8_t                 step_td;
 141         uint8_t                 do_isoc_sync;
 142 };
 143
 144 static void     xhci_do_poll(struct usb_bus *);
 145 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 146 static void     xhci_root_intr(struct xhci_softc *);
 147 static void     xhci_free_device_ext(struct usb_device *);
 148 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 149                     struct usb_endpoint_descriptor *);
 150 static usb_proc_callback_t xhci_configure_msg;
 151 static usb_error_t xhci_configure_device(struct usb_device *);
 152 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 153                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 154                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 155                    uint8_t);
 156 static usb_error_t xhci_configure_mask(struct usb_device *,
 157                     uint32_t, uint8_t);
 158 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 159                     uint64_t, uint8_t);
 160 static void xhci_endpoint_doorbell(struct usb_xfer *);
 161 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 162 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 163 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 164 #ifdef USB_DEBUG
 165 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 166 #endif
 167
 168 extern struct usb_bus_methods xhci_bus_methods;
 169
 170 #ifdef USB_DEBUG
 171 static void
 172 xhci_dump_trb(struct xhci_trb *trb)
 173 {
 174         DPRINTFN(5, "trb = %p\n", trb);
 175         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 176         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 177         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 178 }
 179
 180 static void
 181 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 182 {
 183         DPRINTFN(5, "pep = %p\n", pep);
 184         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 185         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 186         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 187         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 188         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 189         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 190         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 191 }
 192
 193 static void
 194 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 195 {
 196         DPRINTFN(5, "psl = %p\n", psl);
 197         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 198         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 199         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 200         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 201 }
 202 #endif
 203
 204 uint8_t
 205 xhci_use_polling(void)
 206 {
 207 #ifdef USB_DEBUG
 208         return (xhcipolling != 0);
 209 #else
 210         return (0);
 211 #endif
 212 }
 213
 214 static void
 215 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 216 {
 217         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 218         uint16_t i;
 219
 220         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 221            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 222
 223         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 224            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 225
 226         for (i = 0; i != sc->sc_noscratch; i++) {
 227                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 228                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 229         }
 230 }
 231
 232 static void
 233 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 234 {
 235         if (sc->sc_ctx_is_64_byte) {
 236                 uint32_t offset;
 237                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 238                 /* all contexts are initially 32-bytes */
 239                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 240                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 241         }
 242         *ptr = htole32(val);
 243 }
 244
 245 static uint32_t
 246 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 247 {
 248         if (sc->sc_ctx_is_64_byte) {
 249                 uint32_t offset;
 250                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 251                 /* all contexts are initially 32-bytes */
 252                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 253                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 254         }
 255         return (le32toh(*ptr));
 256 }
 257
 258 static void
 259 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 260 {
 261         if (sc->sc_ctx_is_64_byte) {
 262                 uint32_t offset;
 263                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 264                 /* all contexts are initially 32-bytes */
 265                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 266                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 267         }
 268         *ptr = htole64(val);
 269 }
 270
 271 #ifdef USB_DEBUG
 272 static uint64_t
 273 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 274 {
 275         if (sc->sc_ctx_is_64_byte) {
 276                 uint32_t offset;
 277                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 278                 /* all contexts are initially 32-bytes */
 279                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 280                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 281         }
 282         return (le64toh(*ptr));
 283 }
 284 #endif
 285
 286 static int
 287 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 288 {
 289         struct usb_page_search buf_res;
 290         struct xhci_hw_root *phwr;
 291         uint64_t addr;
 292         uint32_t temp;
 293
 294         DPRINTF("\n");
 295
 296         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 297         if (temp & XHCI_CRCR_LO_CRR) {
 298                 DPRINTF("Command ring running\n");
 299                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 300
 301                 /*
 302                  * Try to abort the last command as per section
 303                  * 4.6.1.2 "Aborting a Command" of the XHCI
 304                  * specification:
 305                  */
 306
 307                 /* stop and cancel */
 308                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 309                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 310
 311                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 312                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 313
 314                 /* wait 250ms */
 315                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 316
 317                 /* check if command ring is still running */
 318                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 319                 if (temp & XHCI_CRCR_LO_CRR) {
 320                         DPRINTF("Comand ring still running\n");
 321                         return (USB_ERR_IOERROR);
 322                 }
 323         }
 324
 325         /* reset command ring */
 326         sc->sc_command_ccs = 1;
 327         sc->sc_command_idx = 0;
 328
 329         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 330
 331         /* set up command ring control base address */
 332         addr = buf_res.physaddr;
 333         phwr = buf_res.buffer;
 334         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 335
 336         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 337
 338         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 339         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 340
 341         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 342
 343         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 344         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 345
 346         return (0);
 347 }
 348
 349 usb_error_t
 350 xhci_start_controller(struct xhci_softc *sc)
 351 {
 352         struct usb_page_search buf_res;
 353         struct xhci_hw_root *phwr;
 354         struct xhci_dev_ctx_addr *pdctxa;
 355         uint64_t addr;
 356         uint32_t temp;
 357         uint16_t i;
 358
 359         DPRINTF("\n");
 360
 361         sc->sc_event_ccs = 1;
 362         sc->sc_event_idx = 0;
 363         sc->sc_command_ccs = 1;
 364         sc->sc_command_idx = 0;
 365
 366         /* Reset controller */
 367         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 368
 369         for (i = 0; i != 100; i++) {
 370                 usb_pause_mtx(NULL, hz / 100);
 371                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 372                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 373                 if (!temp)
 374                         break;
 375         }
 376
 377         if (temp) {
 378                 device_printf(sc->sc_bus.parent, "Controller "
 379                     "reset timeout.\n");
 380                 return (USB_ERR_IOERROR);
 381         }
 382
 383         /* set up number of device slots */
 384         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 385             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 386
 387         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 388
 389         temp = XREAD4(sc, oper, XHCI_USBSTS);
 390
 391         /* clear interrupts */
 392         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 393         /* disable all device notifications */
 394         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 395
 396         /* set up device context base address */
 397         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 398         pdctxa = buf_res.buffer;
 399         memset(pdctxa, 0, sizeof(*pdctxa));
 400
 401         addr = buf_res.physaddr;
 402         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 403
 404         /* slot 0 points to the table of scratchpad pointers */
 405         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 406
 407         for (i = 0; i != sc->sc_noscratch; i++) {
 408                 struct usb_page_search buf_scp;
 409                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 410                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 411         }
 412
 413         addr = buf_res.physaddr;
 414
 415         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 416         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 417         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 418         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 419
 420         /* set up event table size */
 421         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 422             XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
 423
 424         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
 425
 426         /* set up interrupt rate */
 427         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 428
 429         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 430
 431         phwr = buf_res.buffer;
 432         addr = buf_res.physaddr;
 433         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 434
 435         /* reset hardware root structure */
 436         memset(phwr, 0, sizeof(*phwr));
 437
 438         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 439         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 440
 441         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 442
 443         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 444         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 445
 446         addr = buf_res.physaddr;
 447
 448         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 449
 450         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 451         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 452
 453         /* set up interrupter registers */
 454         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 455         temp |= XHCI_IMAN_INTR_ENA;
 456         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 457
 458         /* set up command ring control base address */
 459         addr = buf_res.physaddr;
 460         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 461
 462         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 463
 464         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 465         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 466
 467         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 468
 469         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 470
 471         /* Go! */
 472         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 473             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 474
 475         for (i = 0; i != 100; i++) {
 476                 usb_pause_mtx(NULL, hz / 100);
 477                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 478                 if (!temp)
 479                         break;
 480         }
 481         if (temp) {
 482                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 483                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 484                 return (USB_ERR_IOERROR);
 485         }
 486
 487         /* catch any lost interrupts */
 488         xhci_do_poll(&sc->sc_bus);
 489
 490         if (sc->sc_port_route != NULL) {
 491                 /* Route all ports to the XHCI by default */
 492                 sc->sc_port_route(sc->sc_bus.parent,
 493                     ~xhciroute, xhciroute);
 494         }
 495         return (0);
 496 }
 497
 498 usb_error_t
 499 xhci_halt_controller(struct xhci_softc *sc)
 500 {
 501         uint32_t temp;
 502         uint16_t i;
 503
 504         DPRINTF("\n");
 505
 506         sc->sc_capa_off = 0;
 507         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 508         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 509         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 510
 511         /* Halt controller */
 512         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 513
 514         for (i = 0; i != 100; i++) {
 515                 usb_pause_mtx(NULL, hz / 100);
 516                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 517                 if (temp)
 518                         break;
 519         }
 520
 521         if (!temp) {
 522                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 523                 return (USB_ERR_IOERROR);
 524         }
 525         return (0);
 526 }
 527
 528 usb_error_t
 529 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
 530 {
 531         uint32_t temp;
 532
 533         DPRINTF("\n");
 534
 535         /* initialize some bus fields */
 536         sc->sc_bus.parent = self;
 537
 538         /* set the bus revision */
 539         sc->sc_bus.usbrev = USB_REV_3_0;
 540
 541         /* set up the bus struct */
 542         sc->sc_bus.methods = &xhci_bus_methods;
 543
 544         /* set up devices array */
 545         sc->sc_bus.devices = sc->sc_devices;
 546         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 547
 548         /* set default cycle state in case of early interrupts */
 549         sc->sc_event_ccs = 1;
 550         sc->sc_command_ccs = 1;
 551
 552         /* set up bus space offsets */
 553         sc->sc_capa_off = 0;
 554         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 555         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 556         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 557
 558         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 559         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 560         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 561
 562         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 563
 564         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 565                 device_printf(sc->sc_bus.parent, "Controller does "
 566                     "not support 4K page size.\n");
 567                 return (ENXIO);
 568         }
 569
 570         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 571
 572         DPRINTF("HCS0 = 0x%08x\n", temp);
 573
 574         /* set up context size */
 575         if (XHCI_HCS0_CSZ(temp)) {
 576                 sc->sc_ctx_is_64_byte = 1;
 577         } else {
 578                 sc->sc_ctx_is_64_byte = 0;
 579         }
 580
 581         /* get DMA bits */
 582         sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
 583             xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
 584
 585         device_printf(self, "%d bytes context size, %d-bit DMA\n",
 586             sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
 587
 588         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 589
 590         /* get number of device slots */
 591         sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
 592
 593         if (sc->sc_noport == 0) {
 594                 device_printf(sc->sc_bus.parent, "Invalid number "
 595                     "of ports: %u\n", sc->sc_noport);
 596                 return (ENXIO);
 597         }
 598
 599         sc->sc_noport = sc->sc_noport;
 600         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 601
 602         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 603
 604         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 605                 sc->sc_noslot = XHCI_MAX_DEVICES;
 606
 607         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 608
 609         DPRINTF("HCS2=0x%08x\n", temp);
 610
 611         /* get number of scratchpads */
 612         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 613
 614         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 615                 device_printf(sc->sc_bus.parent, "XHCI request "
 616                     "too many scratchpads\n");
 617                 return (ENOMEM);
 618         }
 619
 620         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 621
 622         /* get event table size */
 623         sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
 624         if (sc->sc_erst_max > XHCI_MAX_RSEG)
 625                 sc->sc_erst_max = XHCI_MAX_RSEG;
 626
 627         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 628
 629         /* get maximum exit latency */
 630         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 631             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 632
 633         /* Check if we should use the default IMOD value. */
 634         if (sc->sc_imod_default == 0)
 635                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 636
 637         /* get all DMA memory */
 638         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 639             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 640                 return (ENOMEM);
 641         }
 642
 643         /* set up command queue mutex and condition varible */
 644         cv_init(&sc->sc_cmd_cv, "CMDQ");
 645         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 646
 647         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 648         sc->sc_config_msg[0].bus = &sc->sc_bus;
 649         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 650         sc->sc_config_msg[1].bus = &sc->sc_bus;
 651
 652         return (0);
 653 }
 654
 655 void
 656 xhci_uninit(struct xhci_softc *sc)
 657 {
 658         /*
 659          * NOTE: At this point the control transfer process is gone
 660          * and "xhci_configure_msg" is no longer called. Consequently
 661          * waiting for the configuration messages to complete is not
 662          * needed.
 663          */
 664         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 665
 666         cv_destroy(&sc->sc_cmd_cv);
 667         sx_destroy(&sc->sc_cmd_sx);
 668 }
 669
 670 static void
 671 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 672 {
 673         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 674
 675         switch (state) {
 676         case USB_HW_POWER_SUSPEND:
 677                 DPRINTF("Stopping the XHCI\n");
 678                 xhci_halt_controller(sc);
 679                 break;
 680         case USB_HW_POWER_SHUTDOWN:
 681                 DPRINTF("Stopping the XHCI\n");
 682                 xhci_halt_controller(sc);
 683                 break;
 684         case USB_HW_POWER_RESUME:
 685                 DPRINTF("Starting the XHCI\n");
 686                 xhci_start_controller(sc);
 687                 break;
 688         default:
 689                 break;
 690         }
 691 }
 692
 693 static usb_error_t
 694 xhci_generic_done_sub(struct usb_xfer *xfer)
 695 {
 696         struct xhci_td *td;
 697         struct xhci_td *td_alt_next;
 698         uint32_t len;
 699         uint8_t status;
 700
 701         td = xfer->td_transfer_cache;
 702         td_alt_next = td->alt_next;
 703
 704         if (xfer->aframes != xfer->nframes)
 705                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 706
 707         while (1) {
 708
 709                 usb_pc_cpu_invalidate(td->page_cache);
 710
 711                 status = td->status;
 712                 len = td->remainder;
 713
 714                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 715                     xfer, (unsigned int)xfer->aframes,
 716                     (unsigned int)xfer->nframes,
 717                     (unsigned int)len, (unsigned int)td->len,
 718                     (unsigned int)status);
 719
 720                 /*
 721                  * Verify the status length and
 722                  * add the length to "frlengths[]":
 723                  */
 724                 if (len > td->len) {
 725                         /* should not happen */
 726                         DPRINTF("Invalid status length, "
 727                             "0x%04x/0x%04x bytes\n", len, td->len);
 728                         status = XHCI_TRB_ERROR_LENGTH;
 729                 } else if (xfer->aframes != xfer->nframes) {
 730                         xfer->frlengths[xfer->aframes] += td->len - len;
 731                 }
 732                 /* Check for last transfer */
 733                 if (((void *)td) == xfer->td_transfer_last) {
 734                         td = NULL;
 735                         break;
 736                 }
 737                 /* Check for transfer error */
 738                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 739                     status != XHCI_TRB_ERROR_SUCCESS) {
 740                         /* the transfer is finished */
 741                         td = NULL;
 742                         break;
 743                 }
 744                 /* Check for short transfer */
 745                 if (len > 0) {
 746                         if (xfer->flags_int.short_frames_ok ||
 747                             xfer->flags_int.isochronous_xfr ||
 748                             xfer->flags_int.control_xfr) {
 749                                 /* follow alt next */
 750                                 td = td->alt_next;
 751                         } else {
 752                                 /* the transfer is finished */
 753                                 td = NULL;
 754                         }
 755                         break;
 756                 }
 757                 td = td->obj_next;
 758
 759                 if (td->alt_next != td_alt_next) {
 760                         /* this USB frame is complete */
 761                         break;
 762                 }
 763         }
 764
 765         /* update transfer cache */
 766
 767         xfer->td_transfer_cache = td;
 768
 769         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 770             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 771             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 772             USB_ERR_NORMAL_COMPLETION);
 773 }
 774
 775 static void
 776 xhci_generic_done(struct usb_xfer *xfer)
 777 {
 778         usb_error_t err = 0;
 779
 780         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 781             xfer, xfer->endpoint);
 782
 783         /* reset scanner */
 784
 785         xfer->td_transfer_cache = xfer->td_transfer_first;
 786
 787         if (xfer->flags_int.control_xfr) {
 788
 789                 if (xfer->flags_int.control_hdr)
 790                         err = xhci_generic_done_sub(xfer);
 791
 792                 xfer->aframes = 1;
 793
 794                 if (xfer->td_transfer_cache == NULL)
 795                         goto done;
 796         }
 797
 798         while (xfer->aframes != xfer->nframes) {
 799
 800                 err = xhci_generic_done_sub(xfer);
 801                 xfer->aframes++;
 802
 803                 if (xfer->td_transfer_cache == NULL)
 804                         goto done;
 805         }
 806
 807         if (xfer->flags_int.control_xfr &&
 808             !xfer->flags_int.control_act)
 809                 err = xhci_generic_done_sub(xfer);
 810 done:
 811         /* transfer is complete */
 812         xhci_device_done(xfer, err);
 813 }
 814
 815 static void
 816 xhci_activate_transfer(struct usb_xfer *xfer)
 817 {
 818         struct xhci_td *td;
 819
 820         td = xfer->td_transfer_cache;
 821
 822         usb_pc_cpu_invalidate(td->page_cache);
 823
 824         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 825
 826                 /* activate the transfer */
 827
 828                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 829                 usb_pc_cpu_flush(td->page_cache);
 830
 831                 xhci_endpoint_doorbell(xfer);
 832         }
 833 }
 834
 835 static void
 836 xhci_skip_transfer(struct usb_xfer *xfer)
 837 {
 838         struct xhci_td *td;
 839         struct xhci_td *td_last;
 840
 841         td = xfer->td_transfer_cache;
 842         td_last = xfer->td_transfer_last;
 843
 844         td = td->alt_next;
 845
 846         usb_pc_cpu_invalidate(td->page_cache);
 847
 848         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 849
 850                 usb_pc_cpu_invalidate(td_last->page_cache);
 851
 852                 /* copy LINK TRB to current waiting location */
 853
 854                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 855                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 856                 usb_pc_cpu_flush(td->page_cache);
 857
 858                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 859                 usb_pc_cpu_flush(td->page_cache);
 860
 861                 xhci_endpoint_doorbell(xfer);
 862         }
 863 }
 864
 865 /*------------------------------------------------------------------------*
 866  *      xhci_check_transfer
 867  *------------------------------------------------------------------------*/
 868 static void
 869 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 870 {
 871         struct xhci_endpoint_ext *pepext;
 872         int64_t offset;
 873         uint64_t td_event;
 874         uint32_t temp;
 875         uint32_t remainder;
 876         uint16_t stream_id;
 877         uint16_t i;
 878         uint8_t status;
 879         uint8_t halted;
 880         uint8_t epno;
 881         uint8_t index;
 882
 883         /* decode TRB */
 884         td_event = le64toh(trb->qwTrb0);
 885         temp = le32toh(trb->dwTrb2);
 886
 887         remainder = XHCI_TRB_2_REM_GET(temp);
 888         status = XHCI_TRB_2_ERROR_GET(temp);
 889         stream_id = XHCI_TRB_2_STREAM_GET(temp);
 890
 891         temp = le32toh(trb->dwTrb3);
 892         epno = XHCI_TRB_3_EP_GET(temp);
 893         index = XHCI_TRB_3_SLOT_GET(temp);
 894
 895         /* check if error means halted */
 896         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 897             status != XHCI_TRB_ERROR_SUCCESS);
 898
 899         DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
 900             index, epno, stream_id, remainder, status);
 901
 902         if (index > sc->sc_noslot) {
 903                 DPRINTF("Invalid slot.\n");
 904                 return;
 905         }
 906
 907         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 908                 DPRINTF("Invalid endpoint.\n");
 909                 return;
 910         }
 911
 912         pepext = &sc->sc_hw.devs[index].endp[epno];
 913
 914         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
 915                 stream_id = 0;
 916                 DPRINTF("stream_id=0\n");
 917         } else if (stream_id >= XHCI_MAX_STREAMS) {
 918                 DPRINTF("Invalid stream ID.\n");
 919                 return;
 920         }
 921
 922         /* try to find the USB transfer that generated the event */
 923         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 924                 struct usb_xfer *xfer;
 925                 struct xhci_td *td;
 926
 927                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 928                 if (xfer == NULL)
 929                         continue;
 930
 931                 td = xfer->td_transfer_cache;
 932
 933                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 934                         (long long)td_event,
 935                         (long long)td->td_self,
 936                         (long long)td->td_self + sizeof(td->td_trb));
 937
 938                 /*
 939                  * NOTE: Some XHCI implementations might not trigger
 940                  * an event on the last LINK TRB so we need to
 941                  * consider both the last and second last event
 942                  * address as conditions for a successful transfer.
 943                  *
 944                  * NOTE: We assume that the XHCI will only trigger one
 945                  * event per chain of TRBs.
 946                  */
 947
 948                 offset = td_event - td->td_self;
 949
 950                 if (offset >= 0 &&
 951                     offset < (int64_t)sizeof(td->td_trb)) {
 952
 953                         usb_pc_cpu_invalidate(td->page_cache);
 954
 955                         /* compute rest of remainder, if any */
 956                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 957                                 temp = le32toh(td->td_trb[i].dwTrb2);
 958                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 959                         }
 960
 961                         DPRINTFN(5, "New remainder: %u\n", remainder);
 962
 963                         /* clear isochronous transfer errors */
 964                         if (xfer->flags_int.isochronous_xfr) {
 965                                 if (halted) {
 966                                         halted = 0;
 967                                         status = XHCI_TRB_ERROR_SUCCESS;
 968                                         remainder = td->len;
 969                                 }
 970                         }
 971
 972                         /* "td->remainder" is verified later */
 973                         td->remainder = remainder;
 974                         td->status = status;
 975
 976                         usb_pc_cpu_flush(td->page_cache);
 977
 978                         /*
 979                          * 1) Last transfer descriptor makes the
 980                          * transfer done
 981                          */
 982                         if (((void *)td) == xfer->td_transfer_last) {
 983                                 DPRINTF("TD is last\n");
 984                                 xhci_generic_done(xfer);
 985                                 break;
 986                         }
 987
 988                         /*
 989                          * 2) Any kind of error makes the transfer
 990                          * done
 991                          */
 992                         if (halted) {
 993                                 DPRINTF("TD has I/O error\n");
 994                                 xhci_generic_done(xfer);
 995                                 break;
 996                         }
 997
 998                         /*
 999                          * 3) If there is no alternate next transfer,
1000                          * a short packet also makes the transfer done
1001                          */
1002                         if (td->remainder > 0) {
1003                                 if (td->alt_next == NULL) {
1004                                         DPRINTF(
1005                                             "short TD has no alternate next\n");
1006                                         xhci_generic_done(xfer);
1007                                         break;
1008                                 }
1009                                 DPRINTF("TD has short pkt\n");
1010                                 if (xfer->flags_int.short_frames_ok ||
1011                                     xfer->flags_int.isochronous_xfr ||
1012                                     xfer->flags_int.control_xfr) {
1013                                         /* follow the alt next */
1014                                         xfer->td_transfer_cache = td->alt_next;
1015                                         xhci_activate_transfer(xfer);
1016                                         break;
1017                                 }
1018                                 xhci_skip_transfer(xfer);
1019                                 xhci_generic_done(xfer);
1020                                 break;
1021                         }
1022
1023                         /*
1024                          * 4) Transfer complete - go to next TD
1025                          */
1026                         DPRINTF("Following next TD\n");
1027                         xfer->td_transfer_cache = td->obj_next;
1028                         xhci_activate_transfer(xfer);
1029                         break;          /* there should only be one match */
1030                 }
1031         }
1032 }
1033
1034 static int
1035 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1036 {
1037         if (sc->sc_cmd_addr == trb->qwTrb0) {
1038                 DPRINTF("Received command event\n");
1039                 sc->sc_cmd_result[0] = trb->dwTrb2;
1040                 sc->sc_cmd_result[1] = trb->dwTrb3;
1041                 cv_signal(&sc->sc_cmd_cv);
1042                 return (1);     /* command match */
1043         }
1044         return (0);
1045 }
1046
1047 static int
1048 xhci_interrupt_poll(struct xhci_softc *sc)
1049 {
1050         struct usb_page_search buf_res;
1051         struct xhci_hw_root *phwr;
1052         uint64_t addr;
1053         uint32_t temp;
1054         int retval = 0;
1055         uint16_t i;
1056         uint8_t event;
1057         uint8_t j;
1058         uint8_t k;
1059         uint8_t t;
1060
1061         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1062
1063         phwr = buf_res.buffer;
1064
1065         /* Receive any events */
1066
1067         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1068
1069         i = sc->sc_event_idx;
1070         j = sc->sc_event_ccs;
1071         t = 2;
1072
1073         while (1) {
1074
1075                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1076
1077                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1078
1079                 if (j != k)
1080                         break;
1081
1082                 event = XHCI_TRB_3_TYPE_GET(temp);
1083
1084                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1085                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1086                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1087                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1088
1089                 switch (event) {
1090                 case XHCI_TRB_EVENT_TRANSFER:
1091                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1092                         break;
1093                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1094                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1095                         break;
1096                 default:
1097                         DPRINTF("Unhandled event = %u\n", event);
1098                         break;
1099                 }
1100
1101                 i++;
1102
1103                 if (i == XHCI_MAX_EVENTS) {
1104                         i = 0;
1105                         j ^= 1;
1106
1107                         /* check for timeout */
1108                         if (!--t)
1109                                 break;
1110                 }
1111         }
1112
1113         sc->sc_event_idx = i;
1114         sc->sc_event_ccs = j;
1115
1116         /*
1117          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1118          * latched. That means to activate the register we need to
1119          * write both the low and high double word of the 64-bit
1120          * register.
1121          */
1122
1123         addr = buf_res.physaddr;
1124         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1125
1126         /* try to clear busy bit */
1127         addr |= XHCI_ERDP_LO_BUSY;
1128
1129         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1130         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1131
1132         return (retval);
1133 }
1134
1135 static usb_error_t
1136 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1137     uint16_t timeout_ms)
1138 {
1139         struct usb_page_search buf_res;
1140         struct xhci_hw_root *phwr;
1141         uint64_t addr;
1142         uint32_t temp;
1143         uint8_t i;
1144         uint8_t j;
1145         uint8_t timeout = 0;
1146         int err;
1147
1148         XHCI_CMD_ASSERT_LOCKED(sc);
1149
1150         /* get hardware root structure */
1151
1152         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1153
1154         phwr = buf_res.buffer;
1155
1156         /* Queue command */
1157
1158         USB_BUS_LOCK(&sc->sc_bus);
1159 retry:
1160         i = sc->sc_command_idx;
1161         j = sc->sc_command_ccs;
1162
1163         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1164             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1165             (long long)le64toh(trb->qwTrb0),
1166             (long)le32toh(trb->dwTrb2),
1167             (long)le32toh(trb->dwTrb3));
1168
1169         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1170         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1171
1172         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1173
1174         temp = trb->dwTrb3;
1175
1176         if (j)
1177                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1178         else
1179                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1180
1181         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1182
1183         phwr->hwr_commands[i].dwTrb3 = temp;
1184
1185         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1186
1187         addr = buf_res.physaddr;
1188         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1189
1190         sc->sc_cmd_addr = htole64(addr);
1191
1192         i++;
1193
1194         if (i == (XHCI_MAX_COMMANDS - 1)) {
1195
1196                 if (j) {
1197                         temp = htole32(XHCI_TRB_3_TC_BIT |
1198                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1199                             XHCI_TRB_3_CYCLE_BIT);
1200                 } else {
1201                         temp = htole32(XHCI_TRB_3_TC_BIT |
1202                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1203                 }
1204
1205                 phwr->hwr_commands[i].dwTrb3 = temp;
1206
1207                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1208
1209                 i = 0;
1210                 j ^= 1;
1211         }
1212
1213         sc->sc_command_idx = i;
1214         sc->sc_command_ccs = j;
1215
1216         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1217
1218         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1219             USB_MS_TO_TICKS(timeout_ms));
1220
1221         /*
1222          * In some error cases event interrupts are not generated.
1223          * Poll one time to see if the command has completed.
1224          */
1225         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1226                 DPRINTF("Command was completed when polling\n");
1227                 err = 0;
1228         }
1229         if (err != 0) {
1230                 DPRINTF("Command timeout!\n");
1231                 /*
1232                  * After some weeks of continuous operation, it has
1233                  * been observed that the ASMedia Technology, ASM1042
1234                  * SuperSpeed USB Host Controller can suddenly stop
1235                  * accepting commands via the command queue. Try to
1236                  * first reset the command queue. If that fails do a
1237                  * host controller reset.
1238                  */
1239                 if (timeout == 0 &&
1240                     xhci_reset_command_queue_locked(sc) == 0) {
1241                         temp = le32toh(trb->dwTrb3);
1242
1243                         /*
1244                          * Avoid infinite XHCI reset loops if the set
1245                          * address command fails to respond due to a
1246                          * non-enumerating device:
1247                          */
1248                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1249                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1250                                 DPRINTF("Set address timeout\n");
1251                         } else {
1252                                 timeout = 1;
1253                                 goto retry;
1254                         }
1255                 } else {
1256                         DPRINTF("Controller reset!\n");
1257                         usb_bus_reset_async_locked(&sc->sc_bus);
1258                 }
1259                 err = USB_ERR_TIMEOUT;
1260                 trb->dwTrb2 = 0;
1261                 trb->dwTrb3 = 0;
1262         } else {
1263                 temp = le32toh(sc->sc_cmd_result[0]);
1264                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1265                         err = USB_ERR_IOERROR;
1266
1267                 trb->dwTrb2 = sc->sc_cmd_result[0];
1268                 trb->dwTrb3 = sc->sc_cmd_result[1];
1269         }
1270
1271         USB_BUS_UNLOCK(&sc->sc_bus);
1272
1273         return (err);
1274 }
1275
1276 #if 0
1277 static usb_error_t
1278 xhci_cmd_nop(struct xhci_softc *sc)
1279 {
1280         struct xhci_trb trb;
1281         uint32_t temp;
1282
1283         DPRINTF("\n");
1284
1285         trb.qwTrb0 = 0;
1286         trb.dwTrb2 = 0;
1287         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1288
1289         trb.dwTrb3 = htole32(temp);
1290
1291         return (xhci_do_command(sc, &trb, 100 /* ms */));
1292 }
1293 #endif
1294
1295 static usb_error_t
1296 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1297 {
1298         struct xhci_trb trb;
1299         uint32_t temp;
1300         usb_error_t err;
1301
1302         DPRINTF("\n");
1303
1304         trb.qwTrb0 = 0;
1305         trb.dwTrb2 = 0;
1306         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1307
1308         err = xhci_do_command(sc, &trb, 100 /* ms */);
1309         if (err)
1310                 goto done;
1311
1312         temp = le32toh(trb.dwTrb3);
1313
1314         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1315
1316 done:
1317         return (err);
1318 }
1319
1320 static usb_error_t
1321 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1322 {
1323         struct xhci_trb trb;
1324         uint32_t temp;
1325
1326         DPRINTF("\n");
1327
1328         trb.qwTrb0 = 0;
1329         trb.dwTrb2 = 0;
1330         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1331             XHCI_TRB_3_SLOT_SET(slot_id);
1332
1333         trb.dwTrb3 = htole32(temp);
1334
1335         return (xhci_do_command(sc, &trb, 100 /* ms */));
1336 }
1337
1338 static usb_error_t
1339 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1340     uint8_t bsr, uint8_t slot_id)
1341 {
1342         struct xhci_trb trb;
1343         uint32_t temp;
1344
1345         DPRINTF("\n");
1346
1347         trb.qwTrb0 = htole64(input_ctx);
1348         trb.dwTrb2 = 0;
1349         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1350             XHCI_TRB_3_SLOT_SET(slot_id);
1351
1352         if (bsr)
1353                 temp |= XHCI_TRB_3_BSR_BIT;
1354
1355         trb.dwTrb3 = htole32(temp);
1356
1357         return (xhci_do_command(sc, &trb, 500 /* ms */));
1358 }
1359
1360 static usb_error_t
1361 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1362 {
1363         struct usb_page_search buf_inp;
1364         struct usb_page_search buf_dev;
1365         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1366         struct xhci_hw_dev *hdev;
1367         struct xhci_dev_ctx *pdev;
1368         struct xhci_endpoint_ext *pepext;
1369         uint32_t temp;
1370         uint16_t mps;
1371         usb_error_t err;
1372         uint8_t index;
1373
1374         /* the root HUB case is not handled here */
1375         if (udev->parent_hub == NULL)
1376                 return (USB_ERR_INVAL);
1377
1378         index = udev->controller_slot_id;
1379
1380         hdev =  &sc->sc_hw.devs[index];
1381
1382         if (mtx != NULL)
1383                 mtx_unlock(mtx);
1384
1385         XHCI_CMD_LOCK(sc);
1386
1387         switch (hdev->state) {
1388         case XHCI_ST_DEFAULT:
1389         case XHCI_ST_ENABLED:
1390
1391                 hdev->state = XHCI_ST_ENABLED;
1392
1393                 /* set configure mask to slot and EP0 */
1394                 xhci_configure_mask(udev, 3, 0);
1395
1396                 /* configure input slot context structure */
1397                 err = xhci_configure_device(udev);
1398
1399                 if (err != 0) {
1400                         DPRINTF("Could not configure device\n");
1401                         break;
1402                 }
1403
1404                 /* configure input endpoint context structure */
1405                 switch (udev->speed) {
1406                 case USB_SPEED_LOW:
1407                 case USB_SPEED_FULL:
1408                         mps = 8;
1409                         break;
1410                 case USB_SPEED_HIGH:
1411                         mps = 64;
1412                         break;
1413                 default:
1414                         mps = 512;
1415                         break;
1416                 }
1417
1418                 pepext = xhci_get_endpoint_ext(udev,
1419                     &udev->ctrl_ep_desc);
1420
1421                 /* ensure the control endpoint is setup again */
1422                 USB_BUS_LOCK(udev->bus);
1423                 pepext->trb_halted = 1;
1424                 pepext->trb_running = 0;
1425                 USB_BUS_UNLOCK(udev->bus);
1426
1427                 err = xhci_configure_endpoint(udev,
1428                     &udev->ctrl_ep_desc, pepext,
1429                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1430
1431                 if (err != 0) {
1432                         DPRINTF("Could not configure default endpoint\n");
1433                         break;
1434                 }
1435
1436                 /* execute set address command */
1437                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1438
1439                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1440                     (address == 0), index);
1441
1442                 if (err != 0) {
1443                         temp = le32toh(sc->sc_cmd_result[0]);
1444                         if (address == 0 && sc->sc_port_route != NULL &&
1445                             XHCI_TRB_2_ERROR_GET(temp) ==
1446                             XHCI_TRB_ERROR_PARAMETER) {
1447                                 /* LynxPoint XHCI - ports are not switchable */
1448                                 /* Un-route all ports from the XHCI */
1449                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1450                         }
1451                         DPRINTF("Could not set address "
1452                             "for slot %u.\n", index);
1453                         if (address != 0)
1454                                 break;
1455                 }
1456
1457                 /* update device address to new value */
1458
1459                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1460                 pdev = buf_dev.buffer;
1461                 usb_pc_cpu_invalidate(&hdev->device_pc);
1462
1463                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1464                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1465
1466                 /* update device state to new value */
1467
1468                 if (address != 0)
1469                         hdev->state = XHCI_ST_ADDRESSED;
1470                 else
1471                         hdev->state = XHCI_ST_DEFAULT;
1472                 break;
1473
1474         default:
1475                 DPRINTF("Wrong state for set address.\n");
1476                 err = USB_ERR_IOERROR;
1477                 break;
1478         }
1479         XHCI_CMD_UNLOCK(sc);
1480
1481         if (mtx != NULL)
1482                 mtx_lock(mtx);
1483
1484         return (err);
1485 }
1486
1487 static usb_error_t
1488 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1489     uint8_t deconfigure, uint8_t slot_id)
1490 {
1491         struct xhci_trb trb;
1492         uint32_t temp;
1493
1494         DPRINTF("\n");
1495
1496         trb.qwTrb0 = htole64(input_ctx);
1497         trb.dwTrb2 = 0;
1498         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1499             XHCI_TRB_3_SLOT_SET(slot_id);
1500
1501         if (deconfigure)
1502                 temp |= XHCI_TRB_3_DCEP_BIT;
1503
1504         trb.dwTrb3 = htole32(temp);
1505
1506         return (xhci_do_command(sc, &trb, 100 /* ms */));
1507 }
1508
1509 static usb_error_t
1510 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1511     uint8_t slot_id)
1512 {
1513         struct xhci_trb trb;
1514         uint32_t temp;
1515
1516         DPRINTF("\n");
1517
1518         trb.qwTrb0 = htole64(input_ctx);
1519         trb.dwTrb2 = 0;
1520         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1521             XHCI_TRB_3_SLOT_SET(slot_id);
1522         trb.dwTrb3 = htole32(temp);
1523
1524         return (xhci_do_command(sc, &trb, 100 /* ms */));
1525 }
1526
1527 static usb_error_t
1528 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1529     uint8_t ep_id, uint8_t slot_id)
1530 {
1531         struct xhci_trb trb;
1532         uint32_t temp;
1533
1534         DPRINTF("\n");
1535
1536         trb.qwTrb0 = 0;
1537         trb.dwTrb2 = 0;
1538         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1539             XHCI_TRB_3_SLOT_SET(slot_id) |
1540             XHCI_TRB_3_EP_SET(ep_id);
1541
1542         if (preserve)
1543                 temp |= XHCI_TRB_3_PRSV_BIT;
1544
1545         trb.dwTrb3 = htole32(temp);
1546
1547         return (xhci_do_command(sc, &trb, 100 /* ms */));
1548 }
1549
1550 static usb_error_t
1551 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1552     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1553 {
1554         struct xhci_trb trb;
1555         uint32_t temp;
1556
1557         DPRINTF("\n");
1558
1559         trb.qwTrb0 = htole64(dequeue_ptr);
1560
1561         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1562         trb.dwTrb2 = htole32(temp);
1563
1564         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1565             XHCI_TRB_3_SLOT_SET(slot_id) |
1566             XHCI_TRB_3_EP_SET(ep_id);
1567         trb.dwTrb3 = htole32(temp);
1568
1569         return (xhci_do_command(sc, &trb, 100 /* ms */));
1570 }
1571
1572 static usb_error_t
1573 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1574     uint8_t ep_id, uint8_t slot_id)
1575 {
1576         struct xhci_trb trb;
1577         uint32_t temp;
1578
1579         DPRINTF("\n");
1580
1581         trb.qwTrb0 = 0;
1582         trb.dwTrb2 = 0;
1583         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1584             XHCI_TRB_3_SLOT_SET(slot_id) |
1585             XHCI_TRB_3_EP_SET(ep_id);
1586
1587         if (suspend)
1588                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1589
1590         trb.dwTrb3 = htole32(temp);
1591
1592         return (xhci_do_command(sc, &trb, 100 /* ms */));
1593 }
1594
1595 static usb_error_t
1596 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1597 {
1598         struct xhci_trb trb;
1599         uint32_t temp;
1600
1601         DPRINTF("\n");
1602
1603         trb.qwTrb0 = 0;
1604         trb.dwTrb2 = 0;
1605         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1606             XHCI_TRB_3_SLOT_SET(slot_id);
1607
1608         trb.dwTrb3 = htole32(temp);
1609
1610         return (xhci_do_command(sc, &trb, 100 /* ms */));
1611 }
1612
1613 /*------------------------------------------------------------------------*
1614  *      xhci_interrupt - XHCI interrupt handler
1615  *------------------------------------------------------------------------*/
1616 void
1617 xhci_interrupt(struct xhci_softc *sc)
1618 {
1619         uint32_t status;
1620         uint32_t temp;
1621
1622         USB_BUS_LOCK(&sc->sc_bus);
1623
1624         status = XREAD4(sc, oper, XHCI_USBSTS);
1625
1626         /* acknowledge interrupts, if any */
1627         if (status != 0) {
1628                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1629                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1630         }
1631
1632         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1633
1634         /* force clearing of pending interrupts */
1635         if (temp & XHCI_IMAN_INTR_PEND)
1636                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1637
1638         /* check for event(s) */
1639         xhci_interrupt_poll(sc);
1640
1641         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1642             XHCI_STS_HSE | XHCI_STS_HCE)) {
1643
1644                 if (status & XHCI_STS_PCD) {
1645                         xhci_root_intr(sc);
1646                 }
1647
1648                 if (status & XHCI_STS_HCH) {
1649                         printf("%s: host controller halted\n",
1650                             __FUNCTION__);
1651                 }
1652
1653                 if (status & XHCI_STS_HSE) {
1654                         printf("%s: host system error\n",
1655                             __FUNCTION__);
1656                 }
1657
1658                 if (status & XHCI_STS_HCE) {
1659                         printf("%s: host controller error\n",
1660                            __FUNCTION__);
1661                 }
1662         }
1663         USB_BUS_UNLOCK(&sc->sc_bus);
1664 }
1665
1666 /*------------------------------------------------------------------------*
1667  *      xhci_timeout - XHCI timeout handler
1668  *------------------------------------------------------------------------*/
1669 static void
1670 xhci_timeout(void *arg)
1671 {
1672         struct usb_xfer *xfer = arg;
1673
1674         DPRINTF("xfer=%p\n", xfer);
1675
1676         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1677
1678         /* transfer is transferred */
1679         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1680 }
1681
1682 static void
1683 xhci_do_poll(struct usb_bus *bus)
1684 {
1685         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1686
1687         USB_BUS_LOCK(&sc->sc_bus);
1688         xhci_interrupt_poll(sc);
1689         USB_BUS_UNLOCK(&sc->sc_bus);
1690 }
1691
1692 static void
1693 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1694 {
1695         struct usb_page_search buf_res;
1696         struct xhci_td *td;
1697         struct xhci_td *td_next;
1698         struct xhci_td *td_alt_next;
1699         struct xhci_td *td_first;
1700         uint32_t buf_offset;
1701         uint32_t average;
1702         uint32_t len_old;
1703         uint32_t npkt_off;
1704         uint32_t dword;
1705         uint8_t shortpkt_old;
1706         uint8_t precompute;
1707         uint8_t x;
1708
1709         td_alt_next = NULL;
1710         buf_offset = 0;
1711         shortpkt_old = temp->shortpkt;
1712         len_old = temp->len;
1713         npkt_off = 0;
1714         precompute = 1;
1715
1716 restart:
1717
1718         td = temp->td;
1719         td_next = td_first = temp->td_next;
1720
1721         while (1) {
1722
1723                 if (temp->len == 0) {
1724
1725                         if (temp->shortpkt)
1726                                 break;
1727
1728                         /* send a Zero Length Packet, ZLP, last */
1729
1730                         temp->shortpkt = 1;
1731                         average = 0;
1732
1733                 } else {
1734
1735                         average = temp->average;
1736
1737                         if (temp->len < average) {
1738                                 if (temp->len % temp->max_packet_size) {
1739                                         temp->shortpkt = 1;
1740                                 }
1741                                 average = temp->len;
1742                         }
1743                 }
1744
1745                 if (td_next == NULL)
1746                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1747
1748                 /* get next TD */
1749
1750                 td = td_next;
1751                 td_next = td->obj_next;
1752
1753                 /* check if we are pre-computing */
1754
1755                 if (precompute) {
1756
1757                         /* update remaining length */
1758
1759                         temp->len -= average;
1760
1761                         continue;
1762                 }
1763                 /* fill out current TD */
1764
1765                 td->len = average;
1766                 td->remainder = 0;
1767                 td->status = 0;
1768
1769                 /* update remaining length */
1770
1771                 temp->len -= average;
1772
1773                 /* reset TRB index */
1774
1775                 x = 0;
1776
1777                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1778                         /* immediate data */
1779
1780                         if (average > 8)
1781                                 average = 8;
1782
1783                         td->td_trb[0].qwTrb0 = 0;
1784
1785                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1786                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1787                            average);
1788
1789                         dword = XHCI_TRB_2_BYTES_SET(8) |
1790                             XHCI_TRB_2_TDSZ_SET(0) |
1791                             XHCI_TRB_2_IRQ_SET(0);
1792
1793                         td->td_trb[0].dwTrb2 = htole32(dword);
1794
1795                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1796                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1797
1798                         /* check wLength */
1799                         if (td->td_trb[0].qwTrb0 &
1800                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1801                                 if (td->td_trb[0].qwTrb0 &
1802                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1803                                         dword |= XHCI_TRB_3_TRT_IN;
1804                                 else
1805                                         dword |= XHCI_TRB_3_TRT_OUT;
1806                         }
1807
1808                         td->td_trb[0].dwTrb3 = htole32(dword);
1809 #ifdef USB_DEBUG
1810                         xhci_dump_trb(&td->td_trb[x]);
1811 #endif
1812                         x++;
1813
1814                 } else do {
1815
1816                         uint32_t npkt;
1817
1818                         /* fill out buffer pointers */
1819
1820                         if (average == 0) {
1821                                 memset(&buf_res, 0, sizeof(buf_res));
1822                         } else {
1823                                 usbd_get_page(temp->pc, temp->offset +
1824                                     buf_offset, &buf_res);
1825
1826                                 /* get length to end of page */
1827                                 if (buf_res.length > average)
1828                                         buf_res.length = average;
1829
1830                                 /* check for maximum length */
1831                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1832                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1833
1834                                 npkt_off += buf_res.length;
1835                         }
1836
1837                         /* set up npkt */
1838                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1839                             temp->max_packet_size;
1840
1841                         if (npkt == 0)
1842                                 npkt = 1;
1843                         else if (npkt > 31)
1844                                 npkt = 31;
1845
1846                         /* fill out TRB's */
1847                         td->td_trb[x].qwTrb0 =
1848                             htole64((uint64_t)buf_res.physaddr);
1849
1850                         dword =
1851                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1852                           XHCI_TRB_2_TDSZ_SET(npkt) |
1853                           XHCI_TRB_2_IRQ_SET(0);
1854
1855                         td->td_trb[x].dwTrb2 = htole32(dword);
1856
1857                         switch (temp->trb_type) {
1858                         case XHCI_TRB_TYPE_ISOCH:
1859                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1860                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1861                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1862                                 if (td != td_first) {
1863                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1864                                 } else if (temp->do_isoc_sync != 0) {
1865                                         temp->do_isoc_sync = 0;
1866                                         /* wait until "isoc_frame" */
1867                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1868                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1869                                 } else {
1870                                         /* start data transfer at next interval */
1871                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1872                                             XHCI_TRB_3_ISO_SIA_BIT;
1873                                 }
1874                                 if (temp->direction == UE_DIR_IN)
1875                                         dword |= XHCI_TRB_3_ISP_BIT;
1876                                 break;
1877                         case XHCI_TRB_TYPE_DATA_STAGE:
1878                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1879                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1880                                 if (temp->direction == UE_DIR_IN)
1881                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1882                                 /*
1883                                  * Section 3.2.9 in the XHCI
1884                                  * specification about control
1885                                  * transfers says that we should use a
1886                                  * normal-TRB if there are more TRBs
1887                                  * extending the data-stage
1888                                  * TRB. Update the "trb_type".
1889                                  */
1890                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1891                                 break;
1892                         case XHCI_TRB_TYPE_STATUS_STAGE:
1893                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1894                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1895                                 if (temp->direction == UE_DIR_IN)
1896                                         dword |= XHCI_TRB_3_DIR_IN;
1897                                 break;
1898                         default:        /* XHCI_TRB_TYPE_NORMAL */
1899                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1900                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1901                                 if (temp->direction == UE_DIR_IN)
1902                                         dword |= XHCI_TRB_3_ISP_BIT;
1903                                 break;
1904                         }
1905                         td->td_trb[x].dwTrb3 = htole32(dword);
1906
1907                         average -= buf_res.length;
1908                         buf_offset += buf_res.length;
1909 #ifdef USB_DEBUG
1910                         xhci_dump_trb(&td->td_trb[x]);
1911 #endif
1912                         x++;
1913
1914                 } while (average != 0);
1915
1916                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1917
1918                 /* store number of data TRB's */
1919
1920                 td->ntrb = x;
1921
1922                 DPRINTF("NTRB=%u\n", x);
1923
1924                 /* fill out link TRB */
1925
1926                 if (td_next != NULL) {
1927                         /* link the current TD with the next one */
1928                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1929                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1930                 } else {
1931                         /* this field will get updated later */
1932                         DPRINTF("NOLINK\n");
1933                 }
1934
1935                 dword = XHCI_TRB_2_IRQ_SET(0);
1936
1937                 td->td_trb[x].dwTrb2 = htole32(dword);
1938
1939                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1940                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1941                     /*
1942                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1943                      * frame only receives a single short packet event
1944                      * by setting the CHAIN bit in the LINK field. In
1945                      * addition some XHCI controllers have problems
1946                      * sending a ZLP unless the CHAIN-BIT is set in
1947                      * the LINK TRB.
1948                      */
1949                     XHCI_TRB_3_CHAIN_BIT;
1950
1951                 td->td_trb[x].dwTrb3 = htole32(dword);
1952
1953                 td->alt_next = td_alt_next;
1954 #ifdef USB_DEBUG
1955                 xhci_dump_trb(&td->td_trb[x]);
1956 #endif
1957                 usb_pc_cpu_flush(td->page_cache);
1958         }
1959
1960         if (precompute) {
1961                 precompute = 0;
1962
1963                 /* set up alt next pointer, if any */
1964                 if (temp->last_frame) {
1965                         td_alt_next = NULL;
1966                 } else {
1967                         /* we use this field internally */
1968                         td_alt_next = td_next;
1969                 }
1970
1971                 /* restore */
1972                 temp->shortpkt = shortpkt_old;
1973                 temp->len = len_old;
1974                 goto restart;
1975         }
1976
1977         /*
1978          * Remove cycle bit from the first TRB if we are
1979          * stepping them:
1980          */
1981         if (temp->step_td != 0) {
1982                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1983                 usb_pc_cpu_flush(td_first->page_cache);
1984         }
1985
1986         /* clear TD SIZE to zero, hence this is the last TRB */
1987         /* remove chain bit because this is the last data TRB in the chain */
1988         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1989         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1990         /* remove CHAIN-BIT from last LINK TRB */
1991         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1992
1993         usb_pc_cpu_flush(td->page_cache);
1994
1995         temp->td = td;
1996         temp->td_next = td_next;
1997 }
1998
1999 static void
2000 xhci_setup_generic_chain(struct usb_xfer *xfer)
2001 {
2002         struct xhci_std_temp temp;
2003         struct xhci_td *td;
2004         uint32_t x;
2005         uint32_t y;
2006         uint8_t mult;
2007
2008         temp.do_isoc_sync = 0;
2009         temp.step_td = 0;
2010         temp.tbc = 0;
2011         temp.tlbpc = 0;
2012         temp.average = xfer->max_hc_frame_size;
2013         temp.max_packet_size = xfer->max_packet_size;
2014         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2015         temp.pc = NULL;
2016         temp.last_frame = 0;
2017         temp.offset = 0;
2018         temp.multishort = xfer->flags_int.isochronous_xfr ||
2019             xfer->flags_int.control_xfr ||
2020             xfer->flags_int.short_frames_ok;
2021
2022         /* toggle the DMA set we are using */
2023         xfer->flags_int.curr_dma_set ^= 1;
2024
2025         /* get next DMA set */
2026         td = xfer->td_start[xfer->flags_int.curr_dma_set];
2027
2028         temp.td = NULL;
2029         temp.td_next = td;
2030
2031         xfer->td_transfer_first = td;
2032         xfer->td_transfer_cache = td;
2033
2034         if (xfer->flags_int.isochronous_xfr) {
2035                 uint8_t shift;
2036
2037                 /* compute multiplier for ISOCHRONOUS transfers */
2038                 mult = xfer->endpoint->ecomp ?
2039                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2040                     : 0;
2041                 /* check for USB 2.0 multiplier */
2042                 if (mult == 0) {
2043                         mult = (xfer->endpoint->edesc->
2044                             wMaxPacketSize[1] >> 3) & 3;
2045                 }
2046                 /* range check */
2047                 if (mult > 2)
2048                         mult = 3;
2049                 else
2050                         mult++;
2051
2052                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2053
2054                 DPRINTF("MFINDEX=0x%08x\n", x);
2055
2056                 switch (usbd_get_speed(xfer->xroot->udev)) {
2057                 case USB_SPEED_FULL:
2058                         shift = 3;
2059                         temp.isoc_delta = 8;    /* 1ms */
2060                         x += temp.isoc_delta - 1;
2061                         x &= ~(temp.isoc_delta - 1);
2062                         break;
2063                 default:
2064                         shift = usbd_xfer_get_fps_shift(xfer);
2065                         temp.isoc_delta = 1U << shift;
2066                         x += temp.isoc_delta - 1;
2067                         x &= ~(temp.isoc_delta - 1);
2068                         /* simple frame load balancing */
2069                         x += xfer->endpoint->usb_uframe;
2070                         break;
2071                 }
2072
2073                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2074
2075                 if ((xfer->endpoint->is_synced == 0) ||
2076                     (y < (xfer->nframes << shift)) ||
2077                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2078                         /*
2079                          * If there is data underflow or the pipe
2080                          * queue is empty we schedule the transfer a
2081                          * few frames ahead of the current frame
2082                          * position. Else two isochronous transfers
2083                          * might overlap.
2084                          */
2085                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2086                         xfer->endpoint->is_synced = 1;
2087                         temp.do_isoc_sync = 1;
2088
2089                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2090                 }
2091
2092                 /* compute isochronous completion time */
2093
2094                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2095
2096                 xfer->isoc_time_complete =
2097                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2098                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2099
2100                 x = 0;
2101                 temp.isoc_frame = xfer->endpoint->isoc_next;
2102                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2103
2104                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2105
2106         } else if (xfer->flags_int.control_xfr) {
2107
2108                 /* check if we should prepend a setup message */
2109
2110                 if (xfer->flags_int.control_hdr) {
2111
2112                         temp.len = xfer->frlengths[0];
2113                         temp.pc = xfer->frbuffers + 0;
2114                         temp.shortpkt = temp.len ? 1 : 0;
2115                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2116                         temp.direction = 0;
2117
2118                         /* check for last frame */
2119                         if (xfer->nframes == 1) {
2120                                 /* no STATUS stage yet, SETUP is last */
2121                                 if (xfer->flags_int.control_act)
2122                                         temp.last_frame = 1;
2123                         }
2124
2125                         xhci_setup_generic_chain_sub(&temp);
2126                 }
2127                 x = 1;
2128                 mult = 1;
2129                 temp.isoc_delta = 0;
2130                 temp.isoc_frame = 0;
2131                 temp.trb_type = xfer->flags_int.control_did_data ?
2132                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2133         } else {
2134                 x = 0;
2135                 mult = 1;
2136                 temp.isoc_delta = 0;
2137                 temp.isoc_frame = 0;
2138                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2139         }
2140
2141         if (x != xfer->nframes) {
2142                 /* set up page_cache pointer */
2143                 temp.pc = xfer->frbuffers + x;
2144                 /* set endpoint direction */
2145                 temp.direction = UE_GET_DIR(xfer->endpointno);
2146         }
2147
2148         while (x != xfer->nframes) {
2149
2150                 /* DATA0 / DATA1 message */
2151
2152                 temp.len = xfer->frlengths[x];
2153                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2154                     x != 0 && temp.multishort == 0);
2155
2156                 x++;
2157
2158                 if (x == xfer->nframes) {
2159                         if (xfer->flags_int.control_xfr) {
2160                                 /* no STATUS stage yet, DATA is last */
2161                                 if (xfer->flags_int.control_act)
2162                                         temp.last_frame = 1;
2163                         } else {
2164                                 temp.last_frame = 1;
2165                         }
2166                 }
2167                 if (temp.len == 0) {
2168
2169                         /* make sure that we send an USB packet */
2170
2171                         temp.shortpkt = 0;
2172
2173                         temp.tbc = 0;
2174                         temp.tlbpc = mult - 1;
2175
2176                 } else if (xfer->flags_int.isochronous_xfr) {
2177
2178                         uint8_t tdpc;
2179
2180                         /*
2181                          * Isochronous transfers don't have short
2182                          * packet termination:
2183                          */
2184
2185                         temp.shortpkt = 1;
2186
2187                         /* isochronous transfers have a transfer limit */
2188
2189                         if (temp.len > xfer->max_frame_size)
2190                                 temp.len = xfer->max_frame_size;
2191
2192                         /* compute TD packet count */
2193                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2194                             xfer->max_packet_size;
2195
2196                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2197                         temp.tlbpc = (tdpc % mult);
2198
2199                         if (temp.tlbpc == 0)
2200                                 temp.tlbpc = mult - 1;
2201                         else
2202                                 temp.tlbpc--;
2203                 } else {
2204
2205                         /* regular data transfer */
2206
2207                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2208                 }
2209
2210                 xhci_setup_generic_chain_sub(&temp);
2211
2212                 if (xfer->flags_int.isochronous_xfr) {
2213                         temp.offset += xfer->frlengths[x - 1];
2214                         temp.isoc_frame += temp.isoc_delta;
2215                 } else {
2216                         /* get next Page Cache pointer */
2217                         temp.pc = xfer->frbuffers + x;
2218                 }
2219         }
2220
2221         /* check if we should append a status stage */
2222
2223         if (xfer->flags_int.control_xfr &&
2224             !xfer->flags_int.control_act) {
2225
2226                 /*
2227                  * Send a DATA1 message and invert the current
2228                  * endpoint direction.
2229                  */
2230 #ifdef XHCI_STEP_STATUS_STAGE
2231                 temp.step_td = (xfer->nframes != 0);
2232 #else
2233                 temp.step_td = 0;
2234 #endif
2235                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2236                 temp.len = 0;
2237                 temp.pc = NULL;
2238                 temp.shortpkt = 0;
2239                 temp.last_frame = 1;
2240                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2241
2242                 xhci_setup_generic_chain_sub(&temp);
2243         }
2244
2245         td = temp.td;
2246
2247         /* must have at least one frame! */
2248
2249         xfer->td_transfer_last = td;
2250
2251         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2252 }
2253
2254 static void
2255 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2256 {
2257         struct usb_page_search buf_res;
2258         struct xhci_dev_ctx_addr *pdctxa;
2259
2260         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2261
2262         pdctxa = buf_res.buffer;
2263
2264         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2265
2266         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2267
2268         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2269 }
2270
2271 static usb_error_t
2272 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2273 {
2274         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2275         struct usb_page_search buf_inp;
2276         struct xhci_input_dev_ctx *pinp;
2277         uint32_t temp;
2278         uint8_t index;
2279         uint8_t x;
2280
2281         index = udev->controller_slot_id;
2282
2283         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2284
2285         pinp = buf_inp.buffer;
2286
2287         if (drop) {
2288                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2289                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2290                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2291         } else {
2292                 /*
2293                  * Some hardware requires that we drop the endpoint
2294                  * context before adding it again:
2295                  */
2296                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2297                     mask & XHCI_INCTX_NON_CTRL_MASK);
2298
2299                 /* Add new endpoint context */
2300                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2301
2302                 /* find most significant set bit */
2303                 for (x = 31; x != 1; x--) {
2304                         if (mask & (1 << x))
2305                                 break;
2306                 }
2307
2308                 /* adjust */
2309                 x--;
2310
2311                 /* figure out the maximum number of contexts */
2312                 if (x > sc->sc_hw.devs[index].context_num)
2313                         sc->sc_hw.devs[index].context_num = x;
2314                 else
2315                         x = sc->sc_hw.devs[index].context_num;
2316
2317                 /* update number of contexts */
2318                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2319                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2320                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2321                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2322         }
2323         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2324         return (0);
2325 }
2326
2327 static usb_error_t
2328 xhci_configure_endpoint(struct usb_device *udev,
2329     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2330     uint16_t interval, uint8_t max_packet_count,
2331     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2332     uint16_t max_frame_size, uint8_t ep_mode)
2333 {
2334         struct usb_page_search buf_inp;
2335         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2336         struct xhci_input_dev_ctx *pinp;
2337         uint64_t ring_addr = pepext->physaddr;
2338         uint32_t temp;
2339         uint8_t index;
2340         uint8_t epno;
2341         uint8_t type;
2342
2343         index = udev->controller_slot_id;
2344
2345         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2346
2347         pinp = buf_inp.buffer;
2348
2349         epno = edesc->bEndpointAddress;
2350         type = edesc->bmAttributes & UE_XFERTYPE;
2351
2352         if (type == UE_CONTROL)
2353                 epno |= UE_DIR_IN;
2354
2355         epno = XHCI_EPNO2EPID(epno);
2356
2357         if (epno == 0)
2358                 return (USB_ERR_NO_PIPE);               /* invalid */
2359
2360         if (max_packet_count == 0)
2361                 return (USB_ERR_BAD_BUFSIZE);
2362
2363         max_packet_count--;
2364
2365         if (mult == 0)
2366                 return (USB_ERR_BAD_BUFSIZE);
2367
2368         /* store endpoint mode */
2369         pepext->trb_ep_mode = ep_mode;
2370         /* store bMaxPacketSize for control endpoints */
2371         pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2372         usb_pc_cpu_flush(pepext->page_cache);
2373
2374         if (ep_mode == USB_EP_MODE_STREAMS) {
2375                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2376                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2377                     XHCI_EPCTX_0_LSA_SET(1);
2378
2379                 ring_addr += sizeof(struct xhci_trb) *
2380                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2381         } else {
2382                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2383                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2384                     XHCI_EPCTX_0_LSA_SET(0);
2385
2386                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2387         }
2388
2389         switch (udev->speed) {
2390         case USB_SPEED_FULL:
2391         case USB_SPEED_LOW:
2392                 /* 1ms -> 125us */
2393                 fps_shift += 3;
2394                 break;
2395         default:
2396                 break;
2397         }
2398
2399         switch (type) {
2400         case UE_INTERRUPT:
2401                 if (fps_shift > 3)
2402                         fps_shift--;
2403                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2404                 break;
2405         case UE_ISOCHRONOUS:
2406                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2407
2408                 switch (udev->speed) {
2409                 case USB_SPEED_SUPER:
2410                         if (mult > 3)
2411                                 mult = 3;
2412                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2413                         max_packet_count /= mult;
2414                         break;
2415                 default:
2416                         break;
2417                 }
2418                 break;
2419         default:
2420                 break;
2421         }
2422
2423         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2424
2425         temp =
2426             XHCI_EPCTX_1_HID_SET(0) |
2427             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2428             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2429
2430         /*
2431          * Always enable the "three strikes and you are gone" feature
2432          * except for ISOCHRONOUS endpoints. This is suggested by
2433          * section 4.3.3 in the XHCI specification about device slot
2434          * initialisation.
2435          */
2436         if (type != UE_ISOCHRONOUS)
2437                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2438
2439         switch (type) {
2440         case UE_CONTROL:
2441                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2442                 break;
2443         case UE_ISOCHRONOUS:
2444                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2445                 break;
2446         case UE_BULK:
2447                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2448                 break;
2449         default:
2450                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2451                 break;
2452         }
2453
2454         /* check for IN direction */
2455         if (epno & 1)
2456                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2457
2458         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2459         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2460
2461         switch (edesc->bmAttributes & UE_XFERTYPE) {
2462         case UE_INTERRUPT:
2463         case UE_ISOCHRONOUS:
2464                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2465                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2466                     max_frame_size));
2467                 break;
2468         case UE_CONTROL:
2469                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2470                 break;
2471         default:
2472                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2473                 break;
2474         }
2475
2476         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2477
2478 #ifdef USB_DEBUG
2479         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2480 #endif
2481         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2482
2483         return (0);             /* success */
2484 }
2485
2486 static usb_error_t
2487 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2488 {
2489         struct xhci_endpoint_ext *pepext;
2490         struct usb_endpoint_ss_comp_descriptor *ecomp;
2491         usb_stream_t x;
2492
2493         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2494             xfer->endpoint->edesc);
2495
2496         ecomp = xfer->endpoint->ecomp;
2497
2498         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2499                 uint64_t temp;
2500
2501                 /* halt any transfers */
2502                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2503
2504                 /* compute start of TRB ring for stream "x" */
2505                 temp = pepext->physaddr +
2506                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2507                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2508
2509                 /* make tree structure */
2510                 pepext->trb[(XHCI_MAX_TRANSFERS *
2511                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2512
2513                 /* reserved fields */
2514                 pepext->trb[(XHCI_MAX_TRANSFERS *
2515                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2516                 pepext->trb[(XHCI_MAX_TRANSFERS *
2517                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2518         }
2519         usb_pc_cpu_flush(pepext->page_cache);
2520
2521         return (xhci_configure_endpoint(xfer->xroot->udev,
2522             xfer->endpoint->edesc, pepext,
2523             xfer->interval, xfer->max_packet_count,
2524             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2525             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2526             xfer->max_frame_size, xfer->endpoint->ep_mode));
2527 }
2528
2529 static usb_error_t
2530 xhci_configure_device(struct usb_device *udev)
2531 {
2532         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2533         struct usb_page_search buf_inp;
2534         struct usb_page_cache *pcinp;
2535         struct xhci_input_dev_ctx *pinp;
2536         struct usb_device *hubdev;
2537         uint32_t temp;
2538         uint32_t route;
2539         uint32_t rh_port;
2540         uint8_t is_hub;
2541         uint8_t index;
2542         uint8_t depth;
2543
2544         index = udev->controller_slot_id;
2545
2546         DPRINTF("index=%u\n", index);
2547
2548         pcinp = &sc->sc_hw.devs[index].input_pc;
2549
2550         usbd_get_page(pcinp, 0, &buf_inp);
2551
2552         pinp = buf_inp.buffer;
2553
2554         rh_port = 0;
2555         route = 0;
2556
2557         /* figure out route string and root HUB port number */
2558
2559         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2560
2561                 if (hubdev->parent_hub == NULL)
2562                         break;
2563
2564                 depth = hubdev->parent_hub->depth;
2565
2566                 /*
2567                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2568                  * more than 15 ports
2569                  */
2570
2571                 rh_port = hubdev->port_no;
2572
2573                 if (depth == 0)
2574                         break;
2575
2576                 if (rh_port > 15)
2577                         rh_port = 15;
2578
2579                 if (depth < 6)
2580                         route |= rh_port << (4 * (depth - 1));
2581         }
2582
2583         DPRINTF("Route=0x%08x\n", route);
2584
2585         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2586             XHCI_SCTX_0_CTX_NUM_SET(
2587             sc->sc_hw.devs[index].context_num + 1);
2588
2589         switch (udev->speed) {
2590         case USB_SPEED_LOW:
2591                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2592                 if (udev->parent_hs_hub != NULL &&
2593                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2594                     UDPROTO_HSHUBMTT) {
2595                         DPRINTF("Device inherits MTT\n");
2596                         temp |= XHCI_SCTX_0_MTT_SET(1);
2597                 }
2598                 break;
2599         case USB_SPEED_HIGH:
2600                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2601                 if (sc->sc_hw.devs[index].nports != 0 &&
2602                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2603                         DPRINTF("HUB supports MTT\n");
2604                         temp |= XHCI_SCTX_0_MTT_SET(1);
2605                 }
2606                 break;
2607         case USB_SPEED_FULL:
2608                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2609                 if (udev->parent_hs_hub != NULL &&
2610                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2611                     UDPROTO_HSHUBMTT) {
2612                         DPRINTF("Device inherits MTT\n");
2613                         temp |= XHCI_SCTX_0_MTT_SET(1);
2614                 }
2615                 break;
2616         default:
2617                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2618                 break;
2619         }
2620
2621         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2622             (udev->speed == USB_SPEED_SUPER ||
2623             udev->speed == USB_SPEED_HIGH);
2624
2625         if (is_hub)
2626                 temp |= XHCI_SCTX_0_HUB_SET(1);
2627
2628         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2629
2630         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2631
2632         if (is_hub) {
2633                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2634                     sc->sc_hw.devs[index].nports);
2635         }
2636
2637         switch (udev->speed) {
2638         case USB_SPEED_SUPER:
2639                 switch (sc->sc_hw.devs[index].state) {
2640                 case XHCI_ST_ADDRESSED:
2641                 case XHCI_ST_CONFIGURED:
2642                         /* enable power save */
2643                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2644                         break;
2645                 default:
2646                         /* disable power save */
2647                         break;
2648                 }
2649                 break;
2650         default:
2651                 break;
2652         }
2653
2654         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2655
2656         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2657
2658         if (is_hub) {
2659                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2660                     sc->sc_hw.devs[index].tt);
2661         }
2662
2663         hubdev = udev->parent_hs_hub;
2664
2665         /* check if we should activate the transaction translator */
2666         switch (udev->speed) {
2667         case USB_SPEED_FULL:
2668         case USB_SPEED_LOW:
2669                 if (hubdev != NULL) {
2670                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2671                             hubdev->controller_slot_id);
2672                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2673                             udev->hs_port_no);
2674                 }
2675                 break;
2676         default:
2677                 break;
2678         }
2679
2680         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2681
2682         /*
2683          * These fields should be initialized to zero, according to
2684          * XHCI section 6.2.2 - slot context:
2685          */
2686         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2687             XHCI_SCTX_3_SLOT_STATE_SET(0);
2688
2689         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2690
2691 #ifdef USB_DEBUG
2692         xhci_dump_device(sc, &pinp->ctx_slot);
2693 #endif
2694         usb_pc_cpu_flush(pcinp);
2695
2696         return (0);             /* success */
2697 }
2698
2699 static usb_error_t
2700 xhci_alloc_device_ext(struct usb_device *udev)
2701 {
2702         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2703         struct usb_page_search buf_dev;
2704         struct usb_page_search buf_ep;
2705         struct xhci_trb *trb;
2706         struct usb_page_cache *pc;
2707         struct usb_page *pg;
2708         uint64_t addr;
2709         uint8_t index;
2710         uint8_t i;
2711
2712         index = udev->controller_slot_id;
2713
2714         pc = &sc->sc_hw.devs[index].device_pc;
2715         pg = &sc->sc_hw.devs[index].device_pg;
2716
2717         /* need to initialize the page cache */
2718         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2719
2720         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2721             (2 * sizeof(struct xhci_dev_ctx)) :
2722             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2723                 goto error;
2724
2725         usbd_get_page(pc, 0, &buf_dev);
2726
2727         pc = &sc->sc_hw.devs[index].input_pc;
2728         pg = &sc->sc_hw.devs[index].input_pg;
2729
2730         /* need to initialize the page cache */
2731         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2732
2733         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2734             (2 * sizeof(struct xhci_input_dev_ctx)) :
2735             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2736                 goto error;
2737         }
2738
2739         /* initialize all endpoint LINK TRBs */
2740
2741         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2742
2743                 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2744                 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2745
2746                 /* need to initialize the page cache */
2747                 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2748
2749                 if (usb_pc_alloc_mem(pc, pg,
2750                     sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2751                         goto error;
2752                 }
2753
2754                 /* lookup endpoint TRB ring */
2755                 usbd_get_page(pc, 0, &buf_ep);
2756
2757                 /* get TRB pointer */
2758                 trb = buf_ep.buffer;
2759                 trb += XHCI_MAX_TRANSFERS - 1;
2760
2761                 /* get TRB start address */
2762                 addr = buf_ep.physaddr;
2763
2764                 /* create LINK TRB */
2765                 trb->qwTrb0 = htole64(addr);
2766                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2767                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2768                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2769
2770                 usb_pc_cpu_flush(pc);
2771         }
2772
2773         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2774
2775         return (0);
2776
2777 error:
2778         xhci_free_device_ext(udev);
2779
2780         return (USB_ERR_NOMEM);
2781 }
2782
2783 static void
2784 xhci_free_device_ext(struct usb_device *udev)
2785 {
2786         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2787         uint8_t index;
2788         uint8_t i;
2789
2790         index = udev->controller_slot_id;
2791         xhci_set_slot_pointer(sc, index, 0);
2792
2793         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2794         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2795         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2796                 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2797 }
2798
2799 static struct xhci_endpoint_ext *
2800 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2801 {
2802         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2803         struct xhci_endpoint_ext *pepext;
2804         struct usb_page_cache *pc;
2805         struct usb_page_search buf_ep;
2806         uint8_t epno;
2807         uint8_t index;
2808
2809         epno = edesc->bEndpointAddress;
2810         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2811                 epno |= UE_DIR_IN;
2812
2813         epno = XHCI_EPNO2EPID(epno);
2814
2815         index = udev->controller_slot_id;
2816
2817         pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2818
2819         usbd_get_page(pc, 0, &buf_ep);
2820
2821         pepext = &sc->sc_hw.devs[index].endp[epno];
2822         pepext->page_cache = pc;
2823         pepext->trb = buf_ep.buffer;
2824         pepext->physaddr = buf_ep.physaddr;
2825
2826         return (pepext);
2827 }
2828
2829 static void
2830 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2831 {
2832         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2833         uint8_t epno;
2834         uint8_t index;
2835
2836         epno = xfer->endpointno;
2837         if (xfer->flags_int.control_xfr)
2838                 epno |= UE_DIR_IN;
2839
2840         epno = XHCI_EPNO2EPID(epno);
2841         index = xfer->xroot->udev->controller_slot_id;
2842
2843         if (xfer->xroot->udev->flags.self_suspended == 0) {
2844                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2845                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2846         }
2847 }
2848
2849 static void
2850 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2851 {
2852         struct xhci_endpoint_ext *pepext;
2853
2854         if (xfer->flags_int.bandwidth_reclaimed) {
2855                 xfer->flags_int.bandwidth_reclaimed = 0;
2856
2857                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2858                     xfer->endpoint->edesc);
2859
2860                 pepext->trb_used[xfer->stream_id]--;
2861
2862                 pepext->xfer[xfer->qh_pos] = NULL;
2863
2864                 if (error && pepext->trb_running != 0) {
2865                         pepext->trb_halted = 1;
2866                         pepext->trb_running = 0;
2867                 }
2868         }
2869 }
2870
2871 static usb_error_t
2872 xhci_transfer_insert(struct usb_xfer *xfer)
2873 {
2874         struct xhci_td *td_first;
2875         struct xhci_td *td_last;
2876         struct xhci_trb *trb_link;
2877         struct xhci_endpoint_ext *pepext;
2878         uint64_t addr;
2879         usb_stream_t id;
2880         uint8_t i;
2881         uint8_t inext;
2882         uint8_t trb_limit;
2883
2884         DPRINTFN(8, "\n");
2885
2886         id = xfer->stream_id;
2887
2888         /* check if already inserted */
2889         if (xfer->flags_int.bandwidth_reclaimed) {
2890                 DPRINTFN(8, "Already in schedule\n");
2891                 return (0);
2892         }
2893
2894         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2895             xfer->endpoint->edesc);
2896
2897         td_first = xfer->td_transfer_first;
2898         td_last = xfer->td_transfer_last;
2899         addr = pepext->physaddr;
2900
2901         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2902         case UE_CONTROL:
2903         case UE_INTERRUPT:
2904                 /* single buffered */
2905                 trb_limit = 1;
2906                 break;
2907         default:
2908                 /* multi buffered */
2909                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2910                 break;
2911         }
2912
2913         if (pepext->trb_used[id] >= trb_limit) {
2914                 DPRINTFN(8, "Too many TDs queued.\n");
2915                 return (USB_ERR_NOMEM);
2916         }
2917
2918         /* check if bMaxPacketSize changed */
2919         if (xfer->flags_int.control_xfr != 0 &&
2920             pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2921
2922                 DPRINTFN(8, "Reconfigure control endpoint\n");
2923
2924                 /* force driver to reconfigure endpoint */
2925                 pepext->trb_halted = 1;
2926                 pepext->trb_running = 0;
2927         }
2928
2929         /* check for stopped condition, after putting transfer on interrupt queue */
2930         if (pepext->trb_running == 0) {
2931                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2932
2933                 DPRINTFN(8, "Not running\n");
2934
2935                 /* start configuration */
2936                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2937                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2938                 return (0);
2939         }
2940
2941         pepext->trb_used[id]++;
2942
2943         /* get current TRB index */
2944         i = pepext->trb_index[id];
2945
2946         /* get next TRB index */
2947         inext = (i + 1);
2948
2949         /* the last entry of the ring is a hardcoded link TRB */
2950         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2951                 inext = 0;
2952
2953         /* store next TRB index, before stream ID offset is added */
2954         pepext->trb_index[id] = inext;
2955
2956         /* offset for stream */
2957         i += id * XHCI_MAX_TRANSFERS;
2958         inext += id * XHCI_MAX_TRANSFERS;
2959
2960         /* compute terminating return address */
2961         addr += (inext * sizeof(struct xhci_trb));
2962
2963         /* compute link TRB pointer */
2964         trb_link = td_last->td_trb + td_last->ntrb;
2965
2966         /* update next pointer of last link TRB */
2967         trb_link->qwTrb0 = htole64(addr);
2968         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2969         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2970             XHCI_TRB_3_CYCLE_BIT |
2971             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2972
2973 #ifdef USB_DEBUG
2974         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2975 #endif
2976         usb_pc_cpu_flush(td_last->page_cache);
2977
2978         /* write ahead chain end marker */
2979
2980         pepext->trb[inext].qwTrb0 = 0;
2981         pepext->trb[inext].dwTrb2 = 0;
2982         pepext->trb[inext].dwTrb3 = 0;
2983
2984         /* update next pointer of link TRB */
2985
2986         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2987         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2988
2989 #ifdef USB_DEBUG
2990         xhci_dump_trb(&pepext->trb[i]);
2991 #endif
2992         usb_pc_cpu_flush(pepext->page_cache);
2993
2994         /* toggle cycle bit which activates the transfer chain */
2995
2996         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2997             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2998
2999         usb_pc_cpu_flush(pepext->page_cache);
3000
3001         DPRINTF("qh_pos = %u\n", i);
3002
3003         pepext->xfer[i] = xfer;
3004
3005         xfer->qh_pos = i;
3006
3007         xfer->flags_int.bandwidth_reclaimed = 1;
3008
3009         xhci_endpoint_doorbell(xfer);
3010
3011         return (0);
3012 }
3013
3014 static void
3015 xhci_root_intr(struct xhci_softc *sc)
3016 {
3017         uint16_t i;
3018
3019         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3020
3021         /* clear any old interrupt data */
3022         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3023
3024         for (i = 1; i <= sc->sc_noport; i++) {
3025                 /* pick out CHANGE bits from the status register */
3026                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3027                     XHCI_PS_CSC | XHCI_PS_PEC |
3028                     XHCI_PS_OCC | XHCI_PS_WRC |
3029                     XHCI_PS_PRC | XHCI_PS_PLC |
3030                     XHCI_PS_CEC)) {
3031                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3032                         DPRINTF("port %d changed\n", i);
3033                 }
3034         }
3035         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3036             sizeof(sc->sc_hub_idata));
3037 }
3038
3039 /*------------------------------------------------------------------------*
3040  *      xhci_device_done - XHCI done handler
3041  *
3042  * NOTE: This function can be called two times in a row on
3043  * the same USB transfer. From close and from interrupt.
3044  *------------------------------------------------------------------------*/
3045 static void
3046 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3047 {
3048         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3049             xfer, xfer->endpoint, error);
3050
3051         /* remove transfer from HW queue */
3052         xhci_transfer_remove(xfer, error);
3053
3054         /* dequeue transfer and start next transfer */
3055         usbd_transfer_done(xfer, error);
3056 }
3057
3058 /*------------------------------------------------------------------------*
3059  * XHCI data transfer support (generic type)
3060  *------------------------------------------------------------------------*/
3061 static void
3062 xhci_device_generic_open(struct usb_xfer *xfer)
3063 {
3064         if (xfer->flags_int.isochronous_xfr) {
3065                 switch (xfer->xroot->udev->speed) {
3066                 case USB_SPEED_FULL:
3067                         break;
3068                 default:
3069                         usb_hs_bandwidth_alloc(xfer);
3070                         break;
3071                 }
3072         }
3073 }
3074
3075 static void
3076 xhci_device_generic_close(struct usb_xfer *xfer)
3077 {
3078         DPRINTF("\n");
3079
3080         xhci_device_done(xfer, USB_ERR_CANCELLED);
3081
3082         if (xfer->flags_int.isochronous_xfr) {
3083                 switch (xfer->xroot->udev->speed) {
3084                 case USB_SPEED_FULL:
3085                         break;
3086                 default:
3087                         usb_hs_bandwidth_free(xfer);
3088                         break;
3089                 }
3090         }
3091 }
3092
3093 static void
3094 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3095     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3096 {
3097         struct usb_xfer *xfer;
3098
3099         /* check if there is a current transfer */
3100         xfer = ep->endpoint_q[stream_id].curr;
3101         if (xfer == NULL)
3102                 return;
3103
3104         /*
3105          * Check if the current transfer is started and then pickup
3106          * the next one, if any. Else wait for next start event due to
3107          * block on failure feature.
3108          */
3109         if (!xfer->flags_int.bandwidth_reclaimed)
3110                 return;
3111
3112         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3113         if (xfer == NULL) {
3114                 /*
3115                  * In case of enter we have to consider that the
3116                  * transfer is queued by the USB core after the enter
3117                  * method is called.
3118                  */
3119                 xfer = enter_xfer;
3120
3121                 if (xfer == NULL)
3122                         return;
3123         }
3124
3125         /* try to multi buffer */
3126         xhci_transfer_insert(xfer);
3127 }
3128
3129 static void
3130 xhci_device_generic_enter(struct usb_xfer *xfer)
3131 {
3132         DPRINTF("\n");
3133
3134         /* set up TD's and QH */
3135         xhci_setup_generic_chain(xfer);
3136
3137         xhci_device_generic_multi_enter(xfer->endpoint,
3138             xfer->stream_id, xfer);
3139 }
3140
3141 static void
3142 xhci_device_generic_start(struct usb_xfer *xfer)
3143 {
3144         DPRINTF("\n");
3145
3146         /* try to insert xfer on HW queue */
3147         xhci_transfer_insert(xfer);
3148
3149         /* try to multi buffer */
3150         xhci_device_generic_multi_enter(xfer->endpoint,
3151             xfer->stream_id, NULL);
3152
3153         /* add transfer last on interrupt queue */
3154         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3155
3156         /* start timeout, if any */
3157         if (xfer->timeout != 0)
3158                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3159 }
3160
3161 struct usb_pipe_methods xhci_device_generic_methods =
3162 {
3163         .open = xhci_device_generic_open,
3164         .close = xhci_device_generic_close,
3165         .enter = xhci_device_generic_enter,
3166         .start = xhci_device_generic_start,
3167 };
3168
3169 /*------------------------------------------------------------------------*
3170  * xhci root HUB support
3171  *------------------------------------------------------------------------*
3172  * Simulate a hardware HUB by handling all the necessary requests.
3173  *------------------------------------------------------------------------*/
3174
3175 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3176
3177 static const
3178 struct usb_device_descriptor xhci_devd =
3179 {
3180         .bLength = sizeof(xhci_devd),
3181         .bDescriptorType = UDESC_DEVICE,        /* type */
3182         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3183         .bDeviceClass = UDCLASS_HUB,            /* class */
3184         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3185         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3186         .bMaxPacketSize = 9,                    /* max packet size */
3187         HSETW(.idVendor, 0x0000),               /* vendor */
3188         HSETW(.idProduct, 0x0000),              /* product */
3189         HSETW(.bcdDevice, 0x0100),              /* device version */
3190         .iManufacturer = 1,
3191         .iProduct = 2,
3192         .iSerialNumber = 0,
3193         .bNumConfigurations = 1,                /* # of configurations */
3194 };
3195
3196 static const
3197 struct xhci_bos_desc xhci_bosd = {
3198         .bosd = {
3199                 .bLength = sizeof(xhci_bosd.bosd),
3200                 .bDescriptorType = UDESC_BOS,
3201                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3202                 .bNumDeviceCaps = 3,
3203         },
3204         .usb2extd = {
3205                 .bLength = sizeof(xhci_bosd.usb2extd),
3206                 .bDescriptorType = 1,
3207                 .bDevCapabilityType = 2,
3208                 .bmAttributes[0] = 2,
3209         },
3210         .usbdcd = {
3211                 .bLength = sizeof(xhci_bosd.usbdcd),
3212                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3213                 .bDevCapabilityType = 3,
3214                 .bmAttributes = 0, /* XXX */
3215                 HSETW(.wSpeedsSupported, 0x000C),
3216                 .bFunctionalitySupport = 8,
3217                 .bU1DevExitLat = 255,   /* dummy - not used */
3218                 .wU2DevExitLat = { 0x00, 0x08 },
3219         },
3220         .cidd = {
3221                 .bLength = sizeof(xhci_bosd.cidd),
3222                 .bDescriptorType = 1,
3223                 .bDevCapabilityType = 4,
3224                 .bReserved = 0,
3225                 .bContainerID = 0, /* XXX */
3226         },
3227 };
3228
3229 static const
3230 struct xhci_config_desc xhci_confd = {
3231         .confd = {
3232                 .bLength = sizeof(xhci_confd.confd),
3233                 .bDescriptorType = UDESC_CONFIG,
3234                 .wTotalLength[0] = sizeof(xhci_confd),
3235                 .bNumInterface = 1,
3236                 .bConfigurationValue = 1,
3237                 .iConfiguration = 0,
3238                 .bmAttributes = UC_SELF_POWERED,
3239                 .bMaxPower = 0          /* max power */
3240         },
3241         .ifcd = {
3242                 .bLength = sizeof(xhci_confd.ifcd),
3243                 .bDescriptorType = UDESC_INTERFACE,
3244                 .bNumEndpoints = 1,
3245                 .bInterfaceClass = UICLASS_HUB,
3246                 .bInterfaceSubClass = UISUBCLASS_HUB,
3247                 .bInterfaceProtocol = 0,
3248         },
3249         .endpd = {
3250                 .bLength = sizeof(xhci_confd.endpd),
3251                 .bDescriptorType = UDESC_ENDPOINT,
3252                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3253                 .bmAttributes = UE_INTERRUPT,
3254                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3255                 .bInterval = 255,
3256         },
3257         .endpcd = {
3258                 .bLength = sizeof(xhci_confd.endpcd),
3259                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3260                 .bMaxBurst = 0,
3261                 .bmAttributes = 0,
3262         },
3263 };
3264
3265 static const
3266 struct usb_hub_ss_descriptor xhci_hubd = {
3267         .bLength = sizeof(xhci_hubd),
3268         .bDescriptorType = UDESC_SS_HUB,
3269 };
3270
3271 static usb_error_t
3272 xhci_roothub_exec(struct usb_device *udev,
3273     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3274 {
3275         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3276         const char *str_ptr;
3277         const void *ptr;
3278         uint32_t port;
3279         uint32_t v;
3280         uint16_t len;
3281         uint16_t i;
3282         uint16_t value;
3283         uint16_t index;
3284         uint8_t j;
3285         usb_error_t err;
3286
3287         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3288
3289         /* buffer reset */
3290         ptr = (const void *)&sc->sc_hub_desc;
3291         len = 0;
3292         err = 0;
3293
3294         value = UGETW(req->wValue);
3295         index = UGETW(req->wIndex);
3296
3297         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3298             "wValue=0x%04x wIndex=0x%04x\n",
3299             req->bmRequestType, req->bRequest,
3300             UGETW(req->wLength), value, index);
3301
3302 #define C(x,y) ((x) | ((y) << 8))
3303         switch (C(req->bRequest, req->bmRequestType)) {
3304         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3305         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3306         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3307                 /*
3308                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3309                  * for the integrated root hub.
3310                  */
3311                 break;
3312         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3313                 len = 1;
3314                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3315                 break;
3316         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3317                 switch (value >> 8) {
3318                 case UDESC_DEVICE:
3319                         if ((value & 0xff) != 0) {
3320                                 err = USB_ERR_IOERROR;
3321                                 goto done;
3322                         }
3323                         len = sizeof(xhci_devd);
3324                         ptr = (const void *)&xhci_devd;
3325                         break;
3326
3327                 case UDESC_BOS:
3328                         if ((value & 0xff) != 0) {
3329                                 err = USB_ERR_IOERROR;
3330                                 goto done;
3331                         }
3332                         len = sizeof(xhci_bosd);
3333                         ptr = (const void *)&xhci_bosd;
3334                         break;
3335
3336                 case UDESC_CONFIG:
3337                         if ((value & 0xff) != 0) {
3338                                 err = USB_ERR_IOERROR;
3339                                 goto done;
3340                         }
3341                         len = sizeof(xhci_confd);
3342                         ptr = (const void *)&xhci_confd;
3343                         break;
3344
3345                 case UDESC_STRING:
3346                         switch (value & 0xff) {
3347                         case 0: /* Language table */
3348                                 str_ptr = "\001";
3349                                 break;
3350
3351                         case 1: /* Vendor */
3352                                 str_ptr = sc->sc_vendor;
3353                                 break;
3354
3355                         case 2: /* Product */
3356                                 str_ptr = "XHCI root HUB";
3357                                 break;
3358
3359                         default:
3360                                 str_ptr = "";
3361                                 break;
3362                         }
3363
3364                         len = usb_make_str_desc(
3365                             sc->sc_hub_desc.temp,
3366                             sizeof(sc->sc_hub_desc.temp),
3367                             str_ptr);
3368                         break;
3369
3370                 default:
3371                         err = USB_ERR_IOERROR;
3372                         goto done;
3373                 }
3374                 break;
3375         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3376                 len = 1;
3377                 sc->sc_hub_desc.temp[0] = 0;
3378                 break;
3379         case C(UR_GET_STATUS, UT_READ_DEVICE):
3380                 len = 2;
3381                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3382                 break;
3383         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3384         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3385                 len = 2;
3386                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3387                 break;
3388         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3389                 if (value >= XHCI_MAX_DEVICES) {
3390                         err = USB_ERR_IOERROR;
3391                         goto done;
3392                 }
3393                 break;
3394         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3395                 if (value != 0 && value != 1) {
3396                         err = USB_ERR_IOERROR;
3397                         goto done;
3398                 }
3399                 sc->sc_conf = value;
3400                 break;
3401         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3402                 break;
3403         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3404         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3405         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3406                 err = USB_ERR_IOERROR;
3407                 goto done;
3408         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3409                 break;
3410         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3411                 break;
3412                 /* Hub requests */
3413         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3414                 break;
3415         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3416                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3417
3418                 if ((index < 1) ||
3419                     (index > sc->sc_noport)) {
3420                         err = USB_ERR_IOERROR;
3421                         goto done;
3422                 }
3423                 port = XHCI_PORTSC(index);
3424
3425                 v = XREAD4(sc, oper, port);
3426                 i = XHCI_PS_PLS_GET(v);
3427                 v &= ~XHCI_PS_CLEAR;
3428
3429                 switch (value) {
3430                 case UHF_C_BH_PORT_RESET:
3431                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3432                         break;
3433                 case UHF_C_PORT_CONFIG_ERROR:
3434                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3435                         break;
3436                 case UHF_C_PORT_SUSPEND:
3437                 case UHF_C_PORT_LINK_STATE:
3438                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3439                         break;
3440                 case UHF_C_PORT_CONNECTION:
3441                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3442                         break;
3443                 case UHF_C_PORT_ENABLE:
3444                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3445                         break;
3446                 case UHF_C_PORT_OVER_CURRENT:
3447                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3448                         break;
3449                 case UHF_C_PORT_RESET:
3450                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3451                         break;
3452                 case UHF_PORT_ENABLE:
3453                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3454                         break;
3455                 case UHF_PORT_POWER:
3456                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3457                         break;
3458                 case UHF_PORT_INDICATOR:
3459                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3460                         break;
3461                 case UHF_PORT_SUSPEND:
3462
3463                         /* U3 -> U15 */
3464                         if (i == 3) {
3465                                 XWRITE4(sc, oper, port, v |
3466                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3467                         }
3468
3469                         /* wait 20ms for resume sequence to complete */
3470                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3471
3472                         /* U0 */
3473                         XWRITE4(sc, oper, port, v |
3474                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3475                         break;
3476                 default:
3477                         err = USB_ERR_IOERROR;
3478                         goto done;
3479                 }
3480                 break;
3481
3482         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3483                 if ((value & 0xff) != 0) {
3484                         err = USB_ERR_IOERROR;
3485                         goto done;
3486                 }
3487
3488                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3489
3490                 sc->sc_hub_desc.hubd = xhci_hubd;
3491
3492                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3493
3494                 if (XHCI_HCS0_PPC(v))
3495                         i = UHD_PWR_INDIVIDUAL;
3496                 else
3497                         i = UHD_PWR_GANGED;
3498
3499                 if (XHCI_HCS0_PIND(v))
3500                         i |= UHD_PORT_IND;
3501
3502                 i |= UHD_OC_INDIVIDUAL;
3503
3504                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3505
3506                 /* see XHCI section 5.4.9: */
3507                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3508
3509                 for (j = 1; j <= sc->sc_noport; j++) {
3510
3511                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3512                         if (v & XHCI_PS_DR) {
3513                                 sc->sc_hub_desc.hubd.
3514                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3515                         }
3516                 }
3517                 len = sc->sc_hub_desc.hubd.bLength;
3518                 break;
3519
3520         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3521                 len = 16;
3522                 memset(sc->sc_hub_desc.temp, 0, 16);
3523                 break;
3524
3525         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3526                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3527
3528                 if ((index < 1) ||
3529                     (index > sc->sc_noport)) {
3530                         err = USB_ERR_IOERROR;
3531                         goto done;
3532                 }
3533
3534                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3535
3536                 DPRINTFN(9, "port status=0x%08x\n", v);
3537
3538                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3539
3540                 switch (XHCI_PS_SPEED_GET(v)) {
3541                 case 3:
3542                         i |= UPS_HIGH_SPEED;
3543                         break;
3544                 case 2:
3545                         i |= UPS_LOW_SPEED;
3546                         break;
3547                 case 1:
3548                         /* FULL speed */
3549                         break;
3550                 default:
3551                         i |= UPS_OTHER_SPEED;
3552                         break;
3553                 }
3554
3555                 if (v & XHCI_PS_CCS)
3556                         i |= UPS_CURRENT_CONNECT_STATUS;
3557                 if (v & XHCI_PS_PED)
3558                         i |= UPS_PORT_ENABLED;
3559                 if (v & XHCI_PS_OCA)
3560                         i |= UPS_OVERCURRENT_INDICATOR;
3561                 if (v & XHCI_PS_PR)
3562                         i |= UPS_RESET;
3563                 if (v & XHCI_PS_PP) {
3564                         /*
3565                          * The USB 3.0 RH is using the
3566                          * USB 2.0's power bit
3567                          */
3568                         i |= UPS_PORT_POWER;
3569                 }
3570                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3571
3572                 i = 0;
3573                 if (v & XHCI_PS_CSC)
3574                         i |= UPS_C_CONNECT_STATUS;
3575                 if (v & XHCI_PS_PEC)
3576                         i |= UPS_C_PORT_ENABLED;
3577                 if (v & XHCI_PS_OCC)
3578                         i |= UPS_C_OVERCURRENT_INDICATOR;
3579                 if (v & XHCI_PS_WRC)
3580                         i |= UPS_C_BH_PORT_RESET;
3581                 if (v & XHCI_PS_PRC)
3582                         i |= UPS_C_PORT_RESET;
3583                 if (v & XHCI_PS_PLC)
3584                         i |= UPS_C_PORT_LINK_STATE;
3585                 if (v & XHCI_PS_CEC)
3586                         i |= UPS_C_PORT_CONFIG_ERROR;
3587
3588                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3589                 len = sizeof(sc->sc_hub_desc.ps);
3590                 break;
3591
3592         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3593                 err = USB_ERR_IOERROR;
3594                 goto done;
3595
3596         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3597                 break;
3598
3599         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3600
3601                 i = index >> 8;
3602                 index &= 0x00FF;
3603
3604                 if ((index < 1) ||
3605                     (index > sc->sc_noport)) {
3606                         err = USB_ERR_IOERROR;
3607                         goto done;
3608                 }
3609
3610                 port = XHCI_PORTSC(index);
3611                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3612
3613                 switch (value) {
3614                 case UHF_PORT_U1_TIMEOUT:
3615                         if (XHCI_PS_SPEED_GET(v) != 4) {
3616                                 err = USB_ERR_IOERROR;
3617                                 goto done;
3618                         }
3619                         port = XHCI_PORTPMSC(index);
3620                         v = XREAD4(sc, oper, port);
3621                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3622                         v |= XHCI_PM3_U1TO_SET(i);
3623                         XWRITE4(sc, oper, port, v);
3624                         break;
3625                 case UHF_PORT_U2_TIMEOUT:
3626                         if (XHCI_PS_SPEED_GET(v) != 4) {
3627                                 err = USB_ERR_IOERROR;
3628                                 goto done;
3629                         }
3630                         port = XHCI_PORTPMSC(index);
3631                         v = XREAD4(sc, oper, port);
3632                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3633                         v |= XHCI_PM3_U2TO_SET(i);
3634                         XWRITE4(sc, oper, port, v);
3635                         break;
3636                 case UHF_BH_PORT_RESET:
3637                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3638                         break;
3639                 case UHF_PORT_LINK_STATE:
3640                         XWRITE4(sc, oper, port, v |
3641                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3642                         /* 4ms settle time */
3643                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3644                         break;
3645                 case UHF_PORT_ENABLE:
3646                         DPRINTFN(3, "set port enable %d\n", index);
3647                         break;
3648                 case UHF_PORT_SUSPEND:
3649                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3650                         j = XHCI_PS_SPEED_GET(v);
3651                         if ((j < 1) || (j > 3)) {
3652                                 /* non-supported speed */
3653                                 err = USB_ERR_IOERROR;
3654                                 goto done;
3655                         }
3656                         XWRITE4(sc, oper, port, v |
3657                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3658                         break;
3659                 case UHF_PORT_RESET:
3660                         DPRINTFN(6, "reset port %d\n", index);
3661                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3662                         break;
3663                 case UHF_PORT_POWER:
3664                         DPRINTFN(3, "set port power %d\n", index);
3665                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3666                         break;
3667                 case UHF_PORT_TEST:
3668                         DPRINTFN(3, "set port test %d\n", index);
3669                         break;
3670                 case UHF_PORT_INDICATOR:
3671                         DPRINTFN(3, "set port indicator %d\n", index);
3672
3673                         v &= ~XHCI_PS_PIC_SET(3);
3674                         v |= XHCI_PS_PIC_SET(1);
3675
3676                         XWRITE4(sc, oper, port, v);
3677                         break;
3678                 default:
3679                         err = USB_ERR_IOERROR;
3680                         goto done;
3681                 }
3682                 break;
3683
3684         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3685         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3686         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3687         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3688                 break;
3689         default:
3690                 err = USB_ERR_IOERROR;
3691                 goto done;
3692         }
3693 done:
3694         *plength = len;
3695         *pptr = ptr;
3696         return (err);
3697 }
3698
3699 static void
3700 xhci_xfer_setup(struct usb_setup_params *parm)
3701 {
3702         struct usb_page_search page_info;
3703         struct usb_page_cache *pc;
3704         struct xhci_softc *sc;
3705         struct usb_xfer *xfer;
3706         void *last_obj;
3707         uint32_t ntd;
3708         uint32_t n;
3709
3710         sc = XHCI_BUS2SC(parm->udev->bus);
3711         xfer = parm->curr_xfer;
3712
3713         /*
3714          * The proof for the "ntd" formula is illustrated like this:
3715          *
3716          * +------------------------------------+
3717          * |                                    |
3718          * |         |remainder ->              |
3719          * |   +-----+---+                      |
3720          * |   | xxx | x | frm 0                |
3721          * |   +-----+---++                     |
3722          * |   | xxx | xx | frm 1               |
3723          * |   +-----+----+                     |
3724          * |            ...                     |
3725          * +------------------------------------+
3726          *
3727          * "xxx" means a completely full USB transfer descriptor
3728          *
3729          * "x" and "xx" means a short USB packet
3730          *
3731          * For the remainder of an USB transfer modulo
3732          * "max_data_length" we need two USB transfer descriptors.
3733          * One to transfer the remaining data and one to finalise with
3734          * a zero length packet in case the "force_short_xfer" flag is
3735          * set. We only need two USB transfer descriptors in the case
3736          * where the transfer length of the first one is a factor of
3737          * "max_frame_size". The rest of the needed USB transfer
3738          * descriptors is given by the buffer size divided by the
3739          * maximum data payload.
3740          */
3741         parm->hc_max_packet_size = 0x400;
3742         parm->hc_max_packet_count = 16 * 3;
3743         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3744
3745         xfer->flags_int.bdma_enable = 1;
3746
3747         usbd_transfer_setup_sub(parm);
3748
3749         if (xfer->flags_int.isochronous_xfr) {
3750                 ntd = ((1 * xfer->nframes)
3751                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3752         } else if (xfer->flags_int.control_xfr) {
3753                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3754                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3755         } else {
3756                 ntd = ((2 * xfer->nframes)
3757                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3758         }
3759
3760 alloc_dma_set:
3761
3762         if (parm->err)
3763                 return;
3764
3765         /*
3766          * Allocate queue heads and transfer descriptors
3767          */
3768         last_obj = NULL;
3769
3770         if (usbd_transfer_setup_sub_malloc(
3771             parm, &pc, sizeof(struct xhci_td),
3772             XHCI_TD_ALIGN, ntd)) {
3773                 parm->err = USB_ERR_NOMEM;
3774                 return;
3775         }
3776         if (parm->buf) {
3777                 for (n = 0; n != ntd; n++) {
3778                         struct xhci_td *td;
3779
3780                         usbd_get_page(pc + n, 0, &page_info);
3781
3782                         td = page_info.buffer;
3783
3784                         /* init TD */
3785                         td->td_self = page_info.physaddr;
3786                         td->obj_next = last_obj;
3787                         td->page_cache = pc + n;
3788
3789                         last_obj = td;
3790
3791                         usb_pc_cpu_flush(pc + n);
3792                 }
3793         }
3794         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3795
3796         if (!xfer->flags_int.curr_dma_set) {
3797                 xfer->flags_int.curr_dma_set = 1;
3798                 goto alloc_dma_set;
3799         }
3800 }
3801
3802 static usb_error_t
3803 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3804 {
3805         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3806         struct usb_page_search buf_inp;
3807         struct usb_device *udev;
3808         struct xhci_endpoint_ext *pepext;
3809         struct usb_endpoint_descriptor *edesc;
3810         struct usb_page_cache *pcinp;
3811         usb_error_t err;
3812         usb_stream_t stream_id;
3813         uint8_t index;
3814         uint8_t epno;
3815
3816         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3817             xfer->endpoint->edesc);
3818
3819         udev = xfer->xroot->udev;
3820         index = udev->controller_slot_id;
3821
3822         pcinp = &sc->sc_hw.devs[index].input_pc;
3823
3824         usbd_get_page(pcinp, 0, &buf_inp);
3825
3826         edesc = xfer->endpoint->edesc;
3827
3828         epno = edesc->bEndpointAddress;
3829         stream_id = xfer->stream_id;
3830
3831         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3832                 epno |= UE_DIR_IN;
3833
3834         epno = XHCI_EPNO2EPID(epno);
3835
3836         if (epno == 0)
3837                 return (USB_ERR_NO_PIPE);               /* invalid */
3838
3839         XHCI_CMD_LOCK(sc);
3840
3841         /* configure endpoint */
3842
3843         err = xhci_configure_endpoint_by_xfer(xfer);
3844
3845         if (err != 0) {
3846                 XHCI_CMD_UNLOCK(sc);
3847                 return (err);
3848         }
3849
3850         /*
3851          * Get the endpoint into the stopped state according to the
3852          * endpoint context state diagram in the XHCI specification:
3853          */
3854
3855         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3856
3857         if (err != 0)
3858                 DPRINTF("Could not stop endpoint %u\n", epno);
3859
3860         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3861
3862         if (err != 0)
3863                 DPRINTF("Could not reset endpoint %u\n", epno);
3864
3865         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3866             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3867             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3868             stream_id, epno, index);
3869
3870         if (err != 0)
3871                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3872
3873         /*
3874          * Get the endpoint into the running state according to the
3875          * endpoint context state diagram in the XHCI specification:
3876          */
3877
3878         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3879
3880         if (epno > 1)
3881                 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3882         else
3883                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3884
3885         if (err != 0)
3886                 DPRINTF("Could not configure endpoint %u\n", epno);
3887
3888         XHCI_CMD_UNLOCK(sc);
3889
3890         return (0);
3891 }
3892
3893 static void
3894 xhci_xfer_unsetup(struct usb_xfer *xfer)
3895 {
3896         return;
3897 }
3898
3899 static void
3900 xhci_start_dma_delay(struct usb_xfer *xfer)
3901 {
3902         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3903
3904         /* put transfer on interrupt queue (again) */
3905         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3906
3907         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3908             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3909 }
3910
3911 static void
3912 xhci_configure_msg(struct usb_proc_msg *pm)
3913 {
3914         struct xhci_softc *sc;
3915         struct xhci_endpoint_ext *pepext;
3916         struct usb_xfer *xfer;
3917
3918         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3919
3920 restart:
3921         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3922
3923                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3924                     xfer->endpoint->edesc);
3925
3926                 if ((pepext->trb_halted != 0) ||
3927                     (pepext->trb_running == 0)) {
3928
3929                         uint16_t i;
3930
3931                         /* clear halted and running */
3932                         pepext->trb_halted = 0;
3933                         pepext->trb_running = 0;
3934
3935                         /* nuke remaining buffered transfers */
3936
3937                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3938                             XHCI_MAX_STREAMS); i++) {
3939                                 /*
3940                                  * NOTE: We need to use the timeout
3941                                  * error code here else existing
3942                                  * isochronous clients can get
3943                                  * confused:
3944                                  */
3945                                 if (pepext->xfer[i] != NULL) {
3946                                         xhci_device_done(pepext->xfer[i],
3947                                             USB_ERR_TIMEOUT);
3948                                 }
3949                         }
3950
3951                         /*
3952                          * NOTE: The USB transfer cannot vanish in
3953                          * this state!
3954                          */
3955
3956                         USB_BUS_UNLOCK(&sc->sc_bus);
3957
3958                         xhci_configure_reset_endpoint(xfer);
3959
3960                         USB_BUS_LOCK(&sc->sc_bus);
3961
3962                         /* check if halted is still cleared */
3963                         if (pepext->trb_halted == 0) {
3964                                 pepext->trb_running = 1;
3965                                 memset(pepext->trb_index, 0,
3966                                     sizeof(pepext->trb_index));
3967                         }
3968                         goto restart;
3969                 }
3970
3971                 if (xfer->flags_int.did_dma_delay) {
3972
3973                         /* remove transfer from interrupt queue (again) */
3974                         usbd_transfer_dequeue(xfer);
3975
3976                         /* we are finally done */
3977                         usb_dma_delay_done_cb(xfer);
3978
3979                         /* queue changed - restart */
3980                         goto restart;
3981                 }
3982         }
3983
3984         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3985
3986                 /* try to insert xfer on HW queue */
3987                 xhci_transfer_insert(xfer);
3988
3989                 /* try to multi buffer */
3990                 xhci_device_generic_multi_enter(xfer->endpoint,
3991                     xfer->stream_id, NULL);
3992         }
3993 }
3994
3995 static void
3996 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3997     struct usb_endpoint *ep)
3998 {
3999         struct xhci_endpoint_ext *pepext;
4000
4001         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4002             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4003
4004         if (udev->parent_hub == NULL) {
4005                 /* root HUB has special endpoint handling */
4006                 return;
4007         }
4008
4009         ep->methods = &xhci_device_generic_methods;
4010
4011         pepext = xhci_get_endpoint_ext(udev, edesc);
4012
4013         USB_BUS_LOCK(udev->bus);
4014         pepext->trb_halted = 1;
4015         pepext->trb_running = 0;
4016         USB_BUS_UNLOCK(udev->bus);
4017 }
4018
4019 static void
4020 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4021 {
4022
4023 }
4024
4025 static void
4026 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4027 {
4028         struct xhci_endpoint_ext *pepext;
4029
4030         DPRINTF("\n");
4031
4032         if (udev->flags.usb_mode != USB_MODE_HOST) {
4033                 /* not supported */
4034                 return;
4035         }
4036         if (udev->parent_hub == NULL) {
4037                 /* root HUB has special endpoint handling */
4038                 return;
4039         }
4040
4041         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4042
4043         USB_BUS_LOCK(udev->bus);
4044         pepext->trb_halted = 1;
4045         pepext->trb_running = 0;
4046         USB_BUS_UNLOCK(udev->bus);
4047 }
4048
4049 static usb_error_t
4050 xhci_device_init(struct usb_device *udev)
4051 {
4052         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4053         usb_error_t err;
4054         uint8_t temp;
4055
4056         /* no init for root HUB */
4057         if (udev->parent_hub == NULL)
4058                 return (0);
4059
4060         XHCI_CMD_LOCK(sc);
4061
4062         /* set invalid default */
4063
4064         udev->controller_slot_id = sc->sc_noslot + 1;
4065
4066         /* try to get a new slot ID from the XHCI */
4067
4068         err = xhci_cmd_enable_slot(sc, &temp);
4069
4070         if (err) {
4071                 XHCI_CMD_UNLOCK(sc);
4072                 return (err);
4073         }
4074
4075         if (temp > sc->sc_noslot) {
4076                 XHCI_CMD_UNLOCK(sc);
4077                 return (USB_ERR_BAD_ADDRESS);
4078         }
4079
4080         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4081                 DPRINTF("slot %u already allocated.\n", temp);
4082                 XHCI_CMD_UNLOCK(sc);
4083                 return (USB_ERR_BAD_ADDRESS);
4084         }
4085
4086         /* store slot ID for later reference */
4087
4088         udev->controller_slot_id = temp;
4089
4090         /* reset data structure */
4091
4092         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4093
4094         /* set mark slot allocated */
4095
4096         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4097
4098         err = xhci_alloc_device_ext(udev);
4099
4100         XHCI_CMD_UNLOCK(sc);
4101
4102         /* get device into default state */
4103
4104         if (err == 0)
4105                 err = xhci_set_address(udev, NULL, 0);
4106
4107         return (err);
4108 }
4109
4110 static void
4111 xhci_device_uninit(struct usb_device *udev)
4112 {
4113         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4114         uint8_t index;
4115
4116         /* no init for root HUB */
4117         if (udev->parent_hub == NULL)
4118                 return;
4119
4120         XHCI_CMD_LOCK(sc);
4121
4122         index = udev->controller_slot_id;
4123
4124         if (index <= sc->sc_noslot) {
4125                 xhci_cmd_disable_slot(sc, index);
4126                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4127
4128                 /* free device extension */
4129                 xhci_free_device_ext(udev);
4130         }
4131
4132         XHCI_CMD_UNLOCK(sc);
4133 }
4134
4135 static void
4136 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4137 {
4138         /*
4139          * Wait until the hardware has finished any possible use of
4140          * the transfer descriptor(s)
4141          */
4142         *pus = 2048;                    /* microseconds */
4143 }
4144
4145 static void
4146 xhci_device_resume(struct usb_device *udev)
4147 {
4148         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4149         uint8_t index;
4150         uint8_t n;
4151         uint8_t p;
4152
4153         DPRINTF("\n");
4154
4155         /* check for root HUB */
4156         if (udev->parent_hub == NULL)
4157                 return;
4158
4159         index = udev->controller_slot_id;
4160
4161         XHCI_CMD_LOCK(sc);
4162
4163         /* blindly resume all endpoints */
4164
4165         USB_BUS_LOCK(udev->bus);
4166
4167         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4168                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4169                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4170                             n | XHCI_DB_SID_SET(p));
4171                 }
4172         }
4173
4174         USB_BUS_UNLOCK(udev->bus);
4175
4176         XHCI_CMD_UNLOCK(sc);
4177 }
4178
4179 static void
4180 xhci_device_suspend(struct usb_device *udev)
4181 {
4182         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4183         uint8_t index;
4184         uint8_t n;
4185         usb_error_t err;
4186
4187         DPRINTF("\n");
4188
4189         /* check for root HUB */
4190         if (udev->parent_hub == NULL)
4191                 return;
4192
4193         index = udev->controller_slot_id;
4194
4195         XHCI_CMD_LOCK(sc);
4196
4197         /* blindly suspend all endpoints */
4198
4199         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4200                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4201                 if (err != 0) {
4202                         DPRINTF("Failed to suspend endpoint "
4203                             "%u on slot %u (ignored).\n", n, index);
4204                 }
4205         }
4206
4207         XHCI_CMD_UNLOCK(sc);
4208 }
4209
4210 static void
4211 xhci_set_hw_power(struct usb_bus *bus)
4212 {
4213         DPRINTF("\n");
4214 }
4215
4216 static void
4217 xhci_device_state_change(struct usb_device *udev)
4218 {
4219         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4220         struct usb_page_search buf_inp;
4221         usb_error_t err;
4222         uint8_t index;
4223
4224         /* check for root HUB */
4225         if (udev->parent_hub == NULL)
4226                 return;
4227
4228         index = udev->controller_slot_id;
4229
4230         DPRINTF("\n");
4231
4232         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4233                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4234                     &sc->sc_hw.devs[index].tt);
4235                 if (err != 0)
4236                         sc->sc_hw.devs[index].nports = 0;
4237         }
4238
4239         XHCI_CMD_LOCK(sc);
4240
4241         switch (usb_get_device_state(udev)) {
4242         case USB_STATE_POWERED:
4243                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4244                         break;
4245
4246                 /* set default state */
4247                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4248
4249                 /* reset number of contexts */
4250                 sc->sc_hw.devs[index].context_num = 0;
4251
4252                 err = xhci_cmd_reset_dev(sc, index);
4253
4254                 if (err != 0) {
4255                         DPRINTF("Device reset failed "
4256                             "for slot %u.\n", index);
4257                 }
4258                 break;
4259
4260         case USB_STATE_ADDRESSED:
4261                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4262                         break;
4263
4264                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4265
4266                 /* set configure mask to slot only */
4267                 xhci_configure_mask(udev, 1, 0);
4268
4269                 /* deconfigure all endpoints, except EP0 */
4270                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4271
4272                 if (err) {
4273                         DPRINTF("Failed to deconfigure "
4274                             "slot %u.\n", index);
4275                 }
4276                 break;
4277
4278         case USB_STATE_CONFIGURED:
4279                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4280                         break;
4281
4282                 /* set configured state */
4283                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4284
4285                 /* reset number of contexts */
4286                 sc->sc_hw.devs[index].context_num = 0;
4287
4288                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4289
4290                 xhci_configure_mask(udev, 3, 0);
4291
4292                 err = xhci_configure_device(udev);
4293                 if (err != 0) {
4294                         DPRINTF("Could not configure device "
4295                             "at slot %u.\n", index);
4296                 }
4297
4298                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4299                 if (err != 0) {
4300                         DPRINTF("Could not evaluate device "
4301                             "context at slot %u.\n", index);
4302                 }
4303                 break;
4304
4305         default:
4306                 break;
4307         }
4308         XHCI_CMD_UNLOCK(sc);
4309 }
4310
4311 static usb_error_t
4312 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4313     uint8_t ep_mode)
4314 {
4315         switch (ep_mode) {
4316         case USB_EP_MODE_DEFAULT:
4317                 return (0);
4318         case USB_EP_MODE_STREAMS:
4319                 if (xhcistreams == 0 ||
4320                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4321                     udev->speed != USB_SPEED_SUPER)
4322                         return (USB_ERR_INVAL);
4323                 return (0);
4324         default:
4325                 return (USB_ERR_INVAL);
4326         }
4327 }
4328
4329 struct usb_bus_methods xhci_bus_methods = {
4330         .endpoint_init = xhci_ep_init,
4331         .endpoint_uninit = xhci_ep_uninit,
4332         .xfer_setup = xhci_xfer_setup,
4333         .xfer_unsetup = xhci_xfer_unsetup,
4334         .get_dma_delay = xhci_get_dma_delay,
4335         .device_init = xhci_device_init,
4336         .device_uninit = xhci_device_uninit,
4337         .device_resume = xhci_device_resume,
4338         .device_suspend = xhci_device_suspend,
4339         .set_hw_power = xhci_set_hw_power,
4340         .roothub_exec = xhci_roothub_exec,
4341         .xfer_poll = xhci_do_poll,
4342         .start_dma_delay = xhci_start_dma_delay,
4343         .set_address = xhci_set_address,
4344         .clear_stall = xhci_ep_clear_stall,
4345         .device_state_change = xhci_device_state_change,
4346         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4347         .set_endpoint_mode = xhci_set_endpoint_mode,
4348 };