2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29 * The XHCI 1.0 spec can be found at
30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
31 * and the USB 3.0 spec at
32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
36 * A few words about the design implementation: This driver emulates
37 * the concept about TDs which is found in EHCI specification. This
38 * way we avoid too much diveration among USB drivers.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR xhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #include <dev/usb/controller/xhci.h>
80 #include <dev/usb/controller/xhcireg.h>
82 #define XHCI_BUS2SC(bus) \
83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
92 &xhcidebug, 0, "Debug level");
93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
95 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
101 #define XHCI_INTR_ENDPT 1
103 struct xhci_std_temp {
104 struct xhci_softc *sc;
105 struct usb_page_cache *pc;
107 struct xhci_td *td_next;
110 uint32_t max_packet_size;
122 uint8_t do_isoc_sync;
125 static void xhci_do_poll(struct usb_bus *);
126 static void xhci_device_done(struct usb_xfer *, usb_error_t);
127 static void xhci_root_intr(struct xhci_softc *);
128 static void xhci_free_device_ext(struct usb_device *);
129 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
130 struct usb_endpoint_descriptor *);
131 static usb_proc_callback_t xhci_configure_msg;
132 static usb_error_t xhci_configure_device(struct usb_device *);
133 static usb_error_t xhci_configure_endpoint(struct usb_device *,
134 struct usb_endpoint_descriptor *, uint64_t, uint16_t,
135 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
136 static usb_error_t xhci_configure_mask(struct usb_device *,
138 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
140 static void xhci_endpoint_doorbell(struct usb_xfer *);
141 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
142 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
143 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
145 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
148 extern struct usb_bus_methods xhci_bus_methods;
152 xhci_dump_trb(struct xhci_trb *trb)
154 DPRINTFN(5, "trb = %p\n", trb);
155 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
156 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
157 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
161 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
163 DPRINTFN(5, "pep = %p\n", pep);
164 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
165 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
166 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
167 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
168 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
169 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
170 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
174 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
176 DPRINTFN(5, "psl = %p\n", psl);
177 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
178 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
179 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
180 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
185 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
187 struct xhci_softc *sc = XHCI_BUS2SC(bus);
190 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
191 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
193 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
194 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
196 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
197 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
198 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
203 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
205 if (sc->sc_ctx_is_64_byte) {
207 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
208 /* all contexts are initially 32-bytes */
209 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
210 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
216 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
218 if (sc->sc_ctx_is_64_byte) {
220 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
221 /* all contexts are initially 32-bytes */
222 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
223 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
225 return (le32toh(*ptr));
229 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
231 if (sc->sc_ctx_is_64_byte) {
233 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
234 /* all contexts are initially 32-bytes */
235 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
236 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
243 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
245 if (sc->sc_ctx_is_64_byte) {
247 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
248 /* all contexts are initially 32-bytes */
249 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
250 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
252 return (le64toh(*ptr));
257 xhci_reset_command_queue_locked(struct xhci_softc *sc)
259 struct usb_page_search buf_res;
260 struct xhci_hw_root *phwr;
266 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
267 if (temp & XHCI_CRCR_LO_CRR) {
268 DPRINTF("Command ring running\n");
269 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
272 * Try to abort the last command as per section
273 * 4.6.1.2 "Aborting a Command" of the XHCI
277 /* stop and cancel */
278 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
279 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
281 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
282 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
285 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
287 /* check if command ring is still running */
288 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
289 if (temp & XHCI_CRCR_LO_CRR) {
290 DPRINTF("Comand ring still running\n");
291 return (USB_ERR_IOERROR);
295 /* reset command ring */
296 sc->sc_command_ccs = 1;
297 sc->sc_command_idx = 0;
299 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
301 /* setup command ring control base address */
302 addr = buf_res.physaddr;
303 phwr = buf_res.buffer;
304 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
306 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
308 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
309 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
311 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
313 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
314 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
320 xhci_start_controller(struct xhci_softc *sc)
322 struct usb_page_search buf_res;
323 struct xhci_hw_root *phwr;
324 struct xhci_dev_ctx_addr *pdctxa;
332 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
333 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
334 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
336 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
337 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
338 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
340 sc->sc_event_ccs = 1;
341 sc->sc_event_idx = 0;
342 sc->sc_command_ccs = 1;
343 sc->sc_command_idx = 0;
345 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
347 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
349 DPRINTF("HCS0 = 0x%08x\n", temp);
351 if (XHCI_HCS0_CSZ(temp)) {
352 sc->sc_ctx_is_64_byte = 1;
353 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
355 sc->sc_ctx_is_64_byte = 0;
356 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
359 /* Reset controller */
360 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
362 for (i = 0; i != 100; i++) {
363 usb_pause_mtx(NULL, hz / 100);
364 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
365 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
371 device_printf(sc->sc_bus.parent, "Controller "
373 return (USB_ERR_IOERROR);
376 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
377 device_printf(sc->sc_bus.parent, "Controller does "
378 "not support 4K page size.\n");
379 return (USB_ERR_IOERROR);
382 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
384 i = XHCI_HCS1_N_PORTS(temp);
387 device_printf(sc->sc_bus.parent, "Invalid number "
388 "of ports: %u\n", i);
389 return (USB_ERR_IOERROR);
393 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
395 if (sc->sc_noslot > XHCI_MAX_DEVICES)
396 sc->sc_noslot = XHCI_MAX_DEVICES;
398 /* setup number of device slots */
400 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
401 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
403 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
405 DPRINTF("Max slots: %u\n", sc->sc_noslot);
407 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
409 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
411 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
412 device_printf(sc->sc_bus.parent, "XHCI request "
413 "too many scratchpads\n");
414 return (USB_ERR_NOMEM);
417 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
419 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
421 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
422 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
424 temp = XREAD4(sc, oper, XHCI_USBSTS);
426 /* clear interrupts */
427 XWRITE4(sc, oper, XHCI_USBSTS, temp);
428 /* disable all device notifications */
429 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
431 /* setup device context base address */
432 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
433 pdctxa = buf_res.buffer;
434 memset(pdctxa, 0, sizeof(*pdctxa));
436 addr = buf_res.physaddr;
437 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
439 /* slot 0 points to the table of scratchpad pointers */
440 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
442 for (i = 0; i != sc->sc_noscratch; i++) {
443 struct usb_page_search buf_scp;
444 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
445 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
448 addr = buf_res.physaddr;
450 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
451 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
452 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
453 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
455 /* Setup event table size */
457 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
459 DPRINTF("HCS2=0x%08x\n", temp);
461 temp = XHCI_HCS2_ERST_MAX(temp);
463 if (temp > XHCI_MAX_RSEG)
464 temp = XHCI_MAX_RSEG;
466 sc->sc_erst_max = temp;
468 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
469 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
471 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
473 /* Setup interrupt rate */
474 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
476 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
478 phwr = buf_res.buffer;
479 addr = buf_res.physaddr;
480 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
482 /* reset hardware root structure */
483 memset(phwr, 0, sizeof(*phwr));
485 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
486 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
488 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
490 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
491 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
493 addr = (uint64_t)buf_res.physaddr;
495 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
497 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
498 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
500 /* Setup interrupter registers */
502 temp = XREAD4(sc, runt, XHCI_IMAN(0));
503 temp |= XHCI_IMAN_INTR_ENA;
504 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
506 /* setup command ring control base address */
507 addr = buf_res.physaddr;
508 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
510 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
512 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
513 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
515 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
517 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
520 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
521 XHCI_CMD_INTE | XHCI_CMD_HSEE);
523 for (i = 0; i != 100; i++) {
524 usb_pause_mtx(NULL, hz / 100);
525 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
530 XWRITE4(sc, oper, XHCI_USBCMD, 0);
531 device_printf(sc->sc_bus.parent, "Run timeout.\n");
532 return (USB_ERR_IOERROR);
535 /* catch any lost interrupts */
536 xhci_do_poll(&sc->sc_bus);
538 if (sc->sc_port_route != NULL) {
539 /* Route all ports to the XHCI by default */
540 sc->sc_port_route(sc->sc_bus.parent,
541 ~xhciroute, xhciroute);
547 xhci_halt_controller(struct xhci_softc *sc)
555 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
556 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
557 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
559 /* Halt controller */
560 XWRITE4(sc, oper, XHCI_USBCMD, 0);
562 for (i = 0; i != 100; i++) {
563 usb_pause_mtx(NULL, hz / 100);
564 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
570 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
571 return (USB_ERR_IOERROR);
577 xhci_init(struct xhci_softc *sc, device_t self)
579 /* initialise some bus fields */
580 sc->sc_bus.parent = self;
582 /* set the bus revision */
583 sc->sc_bus.usbrev = USB_REV_3_0;
585 /* set up the bus struct */
586 sc->sc_bus.methods = &xhci_bus_methods;
588 /* setup devices array */
589 sc->sc_bus.devices = sc->sc_devices;
590 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
592 /* setup command queue mutex and condition varible */
593 cv_init(&sc->sc_cmd_cv, "CMDQ");
594 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
596 /* get all DMA memory */
597 if (usb_bus_mem_alloc_all(&sc->sc_bus,
598 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
602 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
603 sc->sc_config_msg[0].bus = &sc->sc_bus;
604 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
605 sc->sc_config_msg[1].bus = &sc->sc_bus;
607 if (usb_proc_create(&sc->sc_config_proc,
608 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
609 printf("WARNING: Creation of XHCI configure "
610 "callback process failed.\n");
616 xhci_uninit(struct xhci_softc *sc)
618 usb_proc_free(&sc->sc_config_proc);
620 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
622 cv_destroy(&sc->sc_cmd_cv);
623 sx_destroy(&sc->sc_cmd_sx);
627 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
629 struct xhci_softc *sc = XHCI_BUS2SC(bus);
632 case USB_HW_POWER_SUSPEND:
633 DPRINTF("Stopping the XHCI\n");
634 xhci_halt_controller(sc);
636 case USB_HW_POWER_SHUTDOWN:
637 DPRINTF("Stopping the XHCI\n");
638 xhci_halt_controller(sc);
640 case USB_HW_POWER_RESUME:
641 DPRINTF("Starting the XHCI\n");
642 xhci_start_controller(sc);
650 xhci_generic_done_sub(struct usb_xfer *xfer)
653 struct xhci_td *td_alt_next;
657 td = xfer->td_transfer_cache;
658 td_alt_next = td->alt_next;
660 if (xfer->aframes != xfer->nframes)
661 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
665 usb_pc_cpu_invalidate(td->page_cache);
670 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
671 xfer, (unsigned int)xfer->aframes,
672 (unsigned int)xfer->nframes,
673 (unsigned int)len, (unsigned int)td->len,
674 (unsigned int)status);
677 * Verify the status length and
678 * add the length to "frlengths[]":
681 /* should not happen */
682 DPRINTF("Invalid status length, "
683 "0x%04x/0x%04x bytes\n", len, td->len);
684 status = XHCI_TRB_ERROR_LENGTH;
685 } else if (xfer->aframes != xfer->nframes) {
686 xfer->frlengths[xfer->aframes] += td->len - len;
688 /* Check for last transfer */
689 if (((void *)td) == xfer->td_transfer_last) {
693 /* Check for transfer error */
694 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
695 status != XHCI_TRB_ERROR_SUCCESS) {
696 /* the transfer is finished */
700 /* Check for short transfer */
702 if (xfer->flags_int.short_frames_ok ||
703 xfer->flags_int.isochronous_xfr ||
704 xfer->flags_int.control_xfr) {
705 /* follow alt next */
708 /* the transfer is finished */
715 if (td->alt_next != td_alt_next) {
716 /* this USB frame is complete */
721 /* update transfer cache */
723 xfer->td_transfer_cache = td;
725 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
726 (status != XHCI_TRB_ERROR_SHORT_PKT &&
727 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
728 USB_ERR_NORMAL_COMPLETION);
732 xhci_generic_done(struct usb_xfer *xfer)
736 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
737 xfer, xfer->endpoint);
741 xfer->td_transfer_cache = xfer->td_transfer_first;
743 if (xfer->flags_int.control_xfr) {
745 if (xfer->flags_int.control_hdr)
746 err = xhci_generic_done_sub(xfer);
750 if (xfer->td_transfer_cache == NULL)
754 while (xfer->aframes != xfer->nframes) {
756 err = xhci_generic_done_sub(xfer);
759 if (xfer->td_transfer_cache == NULL)
763 if (xfer->flags_int.control_xfr &&
764 !xfer->flags_int.control_act)
765 err = xhci_generic_done_sub(xfer);
767 /* transfer is complete */
768 xhci_device_done(xfer, err);
772 xhci_activate_transfer(struct usb_xfer *xfer)
776 td = xfer->td_transfer_cache;
778 usb_pc_cpu_invalidate(td->page_cache);
780 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
782 /* activate the transfer */
784 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
785 usb_pc_cpu_flush(td->page_cache);
787 xhci_endpoint_doorbell(xfer);
792 xhci_skip_transfer(struct usb_xfer *xfer)
795 struct xhci_td *td_last;
797 td = xfer->td_transfer_cache;
798 td_last = xfer->td_transfer_last;
802 usb_pc_cpu_invalidate(td->page_cache);
804 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
806 usb_pc_cpu_invalidate(td_last->page_cache);
808 /* copy LINK TRB to current waiting location */
810 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
811 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
812 usb_pc_cpu_flush(td->page_cache);
814 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
815 usb_pc_cpu_flush(td->page_cache);
817 xhci_endpoint_doorbell(xfer);
821 /*------------------------------------------------------------------------*
822 * xhci_check_transfer
823 *------------------------------------------------------------------------*/
825 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
838 td_event = le64toh(trb->qwTrb0);
839 temp = le32toh(trb->dwTrb2);
841 remainder = XHCI_TRB_2_REM_GET(temp);
842 status = XHCI_TRB_2_ERROR_GET(temp);
844 temp = le32toh(trb->dwTrb3);
845 epno = XHCI_TRB_3_EP_GET(temp);
846 index = XHCI_TRB_3_SLOT_GET(temp);
848 /* check if error means halted */
849 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
850 status != XHCI_TRB_ERROR_SUCCESS);
852 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
853 index, epno, remainder, status);
855 if (index > sc->sc_noslot) {
856 DPRINTF("Invalid slot.\n");
860 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
861 DPRINTF("Invalid endpoint.\n");
865 /* try to find the USB transfer that generated the event */
866 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
867 struct usb_xfer *xfer;
869 struct xhci_endpoint_ext *pepext;
871 pepext = &sc->sc_hw.devs[index].endp[epno];
873 xfer = pepext->xfer[i];
877 td = xfer->td_transfer_cache;
879 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
881 (long long)td->td_self,
882 (long long)td->td_self + sizeof(td->td_trb));
885 * NOTE: Some XHCI implementations might not trigger
886 * an event on the last LINK TRB so we need to
887 * consider both the last and second last event
888 * address as conditions for a successful transfer.
890 * NOTE: We assume that the XHCI will only trigger one
891 * event per chain of TRBs.
894 offset = td_event - td->td_self;
897 offset < (int64_t)sizeof(td->td_trb)) {
899 usb_pc_cpu_invalidate(td->page_cache);
901 /* compute rest of remainder, if any */
902 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
903 temp = le32toh(td->td_trb[i].dwTrb2);
904 remainder += XHCI_TRB_2_BYTES_GET(temp);
907 DPRINTFN(5, "New remainder: %u\n", remainder);
909 /* clear isochronous transfer errors */
910 if (xfer->flags_int.isochronous_xfr) {
913 status = XHCI_TRB_ERROR_SUCCESS;
918 /* "td->remainder" is verified later */
919 td->remainder = remainder;
922 usb_pc_cpu_flush(td->page_cache);
925 * 1) Last transfer descriptor makes the
928 if (((void *)td) == xfer->td_transfer_last) {
929 DPRINTF("TD is last\n");
930 xhci_generic_done(xfer);
935 * 2) Any kind of error makes the transfer
939 DPRINTF("TD has I/O error\n");
940 xhci_generic_done(xfer);
945 * 3) If there is no alternate next transfer,
946 * a short packet also makes the transfer done
948 if (td->remainder > 0) {
949 if (td->alt_next == NULL) {
951 "short TD has no alternate next\n");
952 xhci_generic_done(xfer);
955 DPRINTF("TD has short pkt\n");
956 if (xfer->flags_int.short_frames_ok ||
957 xfer->flags_int.isochronous_xfr ||
958 xfer->flags_int.control_xfr) {
959 /* follow the alt next */
960 xfer->td_transfer_cache = td->alt_next;
961 xhci_activate_transfer(xfer);
964 xhci_skip_transfer(xfer);
965 xhci_generic_done(xfer);
970 * 4) Transfer complete - go to next TD
972 DPRINTF("Following next TD\n");
973 xfer->td_transfer_cache = td->obj_next;
974 xhci_activate_transfer(xfer);
975 break; /* there should only be one match */
981 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
983 if (sc->sc_cmd_addr == trb->qwTrb0) {
984 DPRINTF("Received command event\n");
985 sc->sc_cmd_result[0] = trb->dwTrb2;
986 sc->sc_cmd_result[1] = trb->dwTrb3;
987 cv_signal(&sc->sc_cmd_cv);
988 return (1); /* command match */
994 xhci_interrupt_poll(struct xhci_softc *sc)
996 struct usb_page_search buf_res;
997 struct xhci_hw_root *phwr;
1007 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1009 phwr = buf_res.buffer;
1011 /* Receive any events */
1013 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1015 i = sc->sc_event_idx;
1016 j = sc->sc_event_ccs;
1021 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1023 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1028 event = XHCI_TRB_3_TYPE_GET(temp);
1030 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1031 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1032 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1033 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1036 case XHCI_TRB_EVENT_TRANSFER:
1037 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1039 case XHCI_TRB_EVENT_CMD_COMPLETE:
1040 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1043 DPRINTF("Unhandled event = %u\n", event);
1049 if (i == XHCI_MAX_EVENTS) {
1053 /* check for timeout */
1059 sc->sc_event_idx = i;
1060 sc->sc_event_ccs = j;
1063 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1064 * latched. That means to activate the register we need to
1065 * write both the low and high double word of the 64-bit
1069 addr = (uint32_t)buf_res.physaddr;
1070 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1072 /* try to clear busy bit */
1073 addr |= XHCI_ERDP_LO_BUSY;
1075 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1076 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1082 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1083 uint16_t timeout_ms)
1085 struct usb_page_search buf_res;
1086 struct xhci_hw_root *phwr;
1091 uint8_t timeout = 0;
1094 XHCI_CMD_ASSERT_LOCKED(sc);
1096 /* get hardware root structure */
1098 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1100 phwr = buf_res.buffer;
1104 USB_BUS_LOCK(&sc->sc_bus);
1106 i = sc->sc_command_idx;
1107 j = sc->sc_command_ccs;
1109 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1110 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1111 (long long)le64toh(trb->qwTrb0),
1112 (long)le32toh(trb->dwTrb2),
1113 (long)le32toh(trb->dwTrb3));
1115 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1116 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1118 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1123 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1125 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1127 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1129 phwr->hwr_commands[i].dwTrb3 = temp;
1131 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1133 addr = buf_res.physaddr;
1134 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1136 sc->sc_cmd_addr = htole64(addr);
1140 if (i == (XHCI_MAX_COMMANDS - 1)) {
1143 temp = htole32(XHCI_TRB_3_TC_BIT |
1144 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1145 XHCI_TRB_3_CYCLE_BIT);
1147 temp = htole32(XHCI_TRB_3_TC_BIT |
1148 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1151 phwr->hwr_commands[i].dwTrb3 = temp;
1153 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1159 sc->sc_command_idx = i;
1160 sc->sc_command_ccs = j;
1162 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1164 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1165 USB_MS_TO_TICKS(timeout_ms));
1168 * In some error cases event interrupts are not generated.
1169 * Poll one time to see if the command has completed.
1171 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1172 DPRINTF("Command was completed when polling\n");
1176 DPRINTF("Command timeout!\n");
1178 * After some weeks of continuous operation, it has
1179 * been observed that the ASMedia Technology, ASM1042
1180 * SuperSpeed USB Host Controller can suddenly stop
1181 * accepting commands via the command queue. Try to
1182 * first reset the command queue. If that fails do a
1183 * host controller reset.
1186 xhci_reset_command_queue_locked(sc) == 0) {
1190 DPRINTF("Controller reset!\n");
1191 usb_bus_reset_async_locked(&sc->sc_bus);
1193 err = USB_ERR_TIMEOUT;
1197 temp = le32toh(sc->sc_cmd_result[0]);
1198 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1199 err = USB_ERR_IOERROR;
1201 trb->dwTrb2 = sc->sc_cmd_result[0];
1202 trb->dwTrb3 = sc->sc_cmd_result[1];
1205 USB_BUS_UNLOCK(&sc->sc_bus);
1212 xhci_cmd_nop(struct xhci_softc *sc)
1214 struct xhci_trb trb;
1221 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1223 trb.dwTrb3 = htole32(temp);
1225 return (xhci_do_command(sc, &trb, 100 /* ms */));
1230 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1232 struct xhci_trb trb;
1240 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1242 err = xhci_do_command(sc, &trb, 100 /* ms */);
1246 temp = le32toh(trb.dwTrb3);
1248 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1255 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1257 struct xhci_trb trb;
1264 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1265 XHCI_TRB_3_SLOT_SET(slot_id);
1267 trb.dwTrb3 = htole32(temp);
1269 return (xhci_do_command(sc, &trb, 100 /* ms */));
1273 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1274 uint8_t bsr, uint8_t slot_id)
1276 struct xhci_trb trb;
1281 trb.qwTrb0 = htole64(input_ctx);
1283 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1284 XHCI_TRB_3_SLOT_SET(slot_id);
1287 temp |= XHCI_TRB_3_BSR_BIT;
1289 trb.dwTrb3 = htole32(temp);
1291 return (xhci_do_command(sc, &trb, 500 /* ms */));
1295 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1297 struct usb_page_search buf_inp;
1298 struct usb_page_search buf_dev;
1299 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1300 struct xhci_hw_dev *hdev;
1301 struct xhci_dev_ctx *pdev;
1302 struct xhci_endpoint_ext *pepext;
1308 /* the root HUB case is not handled here */
1309 if (udev->parent_hub == NULL)
1310 return (USB_ERR_INVAL);
1312 index = udev->controller_slot_id;
1314 hdev = &sc->sc_hw.devs[index];
1321 switch (hdev->state) {
1322 case XHCI_ST_DEFAULT:
1323 case XHCI_ST_ENABLED:
1325 hdev->state = XHCI_ST_ENABLED;
1327 /* set configure mask to slot and EP0 */
1328 xhci_configure_mask(udev, 3, 0);
1330 /* configure input slot context structure */
1331 err = xhci_configure_device(udev);
1334 DPRINTF("Could not configure device\n");
1338 /* configure input endpoint context structure */
1339 switch (udev->speed) {
1341 case USB_SPEED_FULL:
1344 case USB_SPEED_HIGH:
1352 pepext = xhci_get_endpoint_ext(udev,
1353 &udev->ctrl_ep_desc);
1354 err = xhci_configure_endpoint(udev,
1355 &udev->ctrl_ep_desc, pepext->physaddr,
1356 0, 1, 1, 0, mps, mps);
1359 DPRINTF("Could not configure default endpoint\n");
1363 /* execute set address command */
1364 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1366 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1367 (address == 0), index);
1370 temp = le32toh(sc->sc_cmd_result[0]);
1371 if (address == 0 && sc->sc_port_route != NULL &&
1372 XHCI_TRB_2_ERROR_GET(temp) ==
1373 XHCI_TRB_ERROR_PARAMETER) {
1374 /* LynxPoint XHCI - ports are not switchable */
1375 /* Un-route all ports from the XHCI */
1376 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1378 DPRINTF("Could not set address "
1379 "for slot %u.\n", index);
1384 /* update device address to new value */
1386 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1387 pdev = buf_dev.buffer;
1388 usb_pc_cpu_invalidate(&hdev->device_pc);
1390 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1391 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1393 /* update device state to new value */
1396 hdev->state = XHCI_ST_ADDRESSED;
1398 hdev->state = XHCI_ST_DEFAULT;
1402 DPRINTF("Wrong state for set address.\n");
1403 err = USB_ERR_IOERROR;
1406 XHCI_CMD_UNLOCK(sc);
1415 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1416 uint8_t deconfigure, uint8_t slot_id)
1418 struct xhci_trb trb;
1423 trb.qwTrb0 = htole64(input_ctx);
1425 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1426 XHCI_TRB_3_SLOT_SET(slot_id);
1429 temp |= XHCI_TRB_3_DCEP_BIT;
1431 trb.dwTrb3 = htole32(temp);
1433 return (xhci_do_command(sc, &trb, 100 /* ms */));
1437 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1440 struct xhci_trb trb;
1445 trb.qwTrb0 = htole64(input_ctx);
1447 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1448 XHCI_TRB_3_SLOT_SET(slot_id);
1449 trb.dwTrb3 = htole32(temp);
1451 return (xhci_do_command(sc, &trb, 100 /* ms */));
1455 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1456 uint8_t ep_id, uint8_t slot_id)
1458 struct xhci_trb trb;
1465 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1466 XHCI_TRB_3_SLOT_SET(slot_id) |
1467 XHCI_TRB_3_EP_SET(ep_id);
1470 temp |= XHCI_TRB_3_PRSV_BIT;
1472 trb.dwTrb3 = htole32(temp);
1474 return (xhci_do_command(sc, &trb, 100 /* ms */));
1478 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1479 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1481 struct xhci_trb trb;
1486 trb.qwTrb0 = htole64(dequeue_ptr);
1488 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1489 trb.dwTrb2 = htole32(temp);
1491 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1492 XHCI_TRB_3_SLOT_SET(slot_id) |
1493 XHCI_TRB_3_EP_SET(ep_id);
1494 trb.dwTrb3 = htole32(temp);
1496 return (xhci_do_command(sc, &trb, 100 /* ms */));
1500 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1501 uint8_t ep_id, uint8_t slot_id)
1503 struct xhci_trb trb;
1510 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1511 XHCI_TRB_3_SLOT_SET(slot_id) |
1512 XHCI_TRB_3_EP_SET(ep_id);
1515 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1517 trb.dwTrb3 = htole32(temp);
1519 return (xhci_do_command(sc, &trb, 100 /* ms */));
1523 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1525 struct xhci_trb trb;
1532 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1533 XHCI_TRB_3_SLOT_SET(slot_id);
1535 trb.dwTrb3 = htole32(temp);
1537 return (xhci_do_command(sc, &trb, 100 /* ms */));
1540 /*------------------------------------------------------------------------*
1541 * xhci_interrupt - XHCI interrupt handler
1542 *------------------------------------------------------------------------*/
1544 xhci_interrupt(struct xhci_softc *sc)
1549 USB_BUS_LOCK(&sc->sc_bus);
1551 status = XREAD4(sc, oper, XHCI_USBSTS);
1553 /* acknowledge interrupts, if any */
1555 XWRITE4(sc, oper, XHCI_USBSTS, status);
1556 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1559 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1561 /* force clearing of pending interrupts */
1562 if (temp & XHCI_IMAN_INTR_PEND)
1563 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1565 /* check for event(s) */
1566 xhci_interrupt_poll(sc);
1568 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1569 XHCI_STS_HSE | XHCI_STS_HCE)) {
1571 if (status & XHCI_STS_PCD) {
1575 if (status & XHCI_STS_HCH) {
1576 printf("%s: host controller halted\n",
1580 if (status & XHCI_STS_HSE) {
1581 printf("%s: host system error\n",
1585 if (status & XHCI_STS_HCE) {
1586 printf("%s: host controller error\n",
1590 USB_BUS_UNLOCK(&sc->sc_bus);
1593 /*------------------------------------------------------------------------*
1594 * xhci_timeout - XHCI timeout handler
1595 *------------------------------------------------------------------------*/
1597 xhci_timeout(void *arg)
1599 struct usb_xfer *xfer = arg;
1601 DPRINTF("xfer=%p\n", xfer);
1603 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1605 /* transfer is transferred */
1606 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1610 xhci_do_poll(struct usb_bus *bus)
1612 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1614 USB_BUS_LOCK(&sc->sc_bus);
1615 xhci_interrupt_poll(sc);
1616 USB_BUS_UNLOCK(&sc->sc_bus);
1620 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1622 struct usb_page_search buf_res;
1624 struct xhci_td *td_next;
1625 struct xhci_td *td_alt_next;
1626 struct xhci_td *td_first;
1627 uint32_t buf_offset;
1632 uint8_t shortpkt_old;
1638 shortpkt_old = temp->shortpkt;
1639 len_old = temp->len;
1646 td_next = td_first = temp->td_next;
1650 if (temp->len == 0) {
1655 /* send a Zero Length Packet, ZLP, last */
1662 average = temp->average;
1664 if (temp->len < average) {
1665 if (temp->len % temp->max_packet_size) {
1668 average = temp->len;
1672 if (td_next == NULL)
1673 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1678 td_next = td->obj_next;
1680 /* check if we are pre-computing */
1684 /* update remaining length */
1686 temp->len -= average;
1690 /* fill out current TD */
1696 /* update remaining length */
1698 temp->len -= average;
1700 /* reset TRB index */
1704 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1705 /* immediate data */
1710 td->td_trb[0].qwTrb0 = 0;
1712 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1713 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1716 dword = XHCI_TRB_2_BYTES_SET(8) |
1717 XHCI_TRB_2_TDSZ_SET(0) |
1718 XHCI_TRB_2_IRQ_SET(0);
1720 td->td_trb[0].dwTrb2 = htole32(dword);
1722 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1723 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1726 if (td->td_trb[0].qwTrb0 &
1727 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1728 if (td->td_trb[0].qwTrb0 & htole64(1))
1729 dword |= XHCI_TRB_3_TRT_IN;
1731 dword |= XHCI_TRB_3_TRT_OUT;
1734 td->td_trb[0].dwTrb3 = htole32(dword);
1736 xhci_dump_trb(&td->td_trb[x]);
1744 /* fill out buffer pointers */
1747 memset(&buf_res, 0, sizeof(buf_res));
1749 usbd_get_page(temp->pc, temp->offset +
1750 buf_offset, &buf_res);
1752 /* get length to end of page */
1753 if (buf_res.length > average)
1754 buf_res.length = average;
1756 /* check for maximum length */
1757 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1758 buf_res.length = XHCI_TD_PAGE_SIZE;
1760 npkt_off += buf_res.length;
1764 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1765 temp->max_packet_size;
1772 /* fill out TRB's */
1773 td->td_trb[x].qwTrb0 =
1774 htole64((uint64_t)buf_res.physaddr);
1777 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1778 XHCI_TRB_2_TDSZ_SET(npkt) |
1779 XHCI_TRB_2_IRQ_SET(0);
1781 td->td_trb[x].dwTrb2 = htole32(dword);
1783 switch (temp->trb_type) {
1784 case XHCI_TRB_TYPE_ISOCH:
1785 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1786 XHCI_TRB_3_TBC_SET(temp->tbc) |
1787 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1788 if (td != td_first) {
1789 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1790 } else if (temp->do_isoc_sync != 0) {
1791 temp->do_isoc_sync = 0;
1792 /* wait until "isoc_frame" */
1793 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1794 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1796 /* start data transfer at next interval */
1797 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1798 XHCI_TRB_3_ISO_SIA_BIT;
1800 if (temp->direction == UE_DIR_IN)
1801 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1803 case XHCI_TRB_TYPE_DATA_STAGE:
1804 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1805 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1806 XHCI_TRB_3_TBC_SET(temp->tbc) |
1807 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1808 if (temp->direction == UE_DIR_IN)
1809 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1811 case XHCI_TRB_TYPE_STATUS_STAGE:
1812 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1813 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1814 XHCI_TRB_3_TBC_SET(temp->tbc) |
1815 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1816 if (temp->direction == UE_DIR_IN)
1817 dword |= XHCI_TRB_3_DIR_IN;
1819 default: /* XHCI_TRB_TYPE_NORMAL */
1820 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1821 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1822 XHCI_TRB_3_TBC_SET(temp->tbc) |
1823 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1824 if (temp->direction == UE_DIR_IN)
1825 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1828 td->td_trb[x].dwTrb3 = htole32(dword);
1830 average -= buf_res.length;
1831 buf_offset += buf_res.length;
1833 xhci_dump_trb(&td->td_trb[x]);
1837 } while (average != 0);
1839 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1841 /* store number of data TRB's */
1845 DPRINTF("NTRB=%u\n", x);
1847 /* fill out link TRB */
1849 if (td_next != NULL) {
1850 /* link the current TD with the next one */
1851 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1852 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1854 /* this field will get updated later */
1855 DPRINTF("NOLINK\n");
1858 dword = XHCI_TRB_2_IRQ_SET(0);
1860 td->td_trb[x].dwTrb2 = htole32(dword);
1862 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1863 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1865 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1866 * frame only receives a single short packet event
1867 * by setting the CHAIN bit in the LINK field. In
1868 * addition some XHCI controllers have problems
1869 * sending a ZLP unless the CHAIN-BIT is set in
1872 XHCI_TRB_3_CHAIN_BIT;
1874 td->td_trb[x].dwTrb3 = htole32(dword);
1876 td->alt_next = td_alt_next;
1878 xhci_dump_trb(&td->td_trb[x]);
1880 usb_pc_cpu_flush(td->page_cache);
1886 /* setup alt next pointer, if any */
1887 if (temp->last_frame) {
1890 /* we use this field internally */
1891 td_alt_next = td_next;
1895 temp->shortpkt = shortpkt_old;
1896 temp->len = len_old;
1901 * Remove cycle bit from the first TRB if we are
1904 if (temp->step_td != 0) {
1905 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1906 usb_pc_cpu_flush(td_first->page_cache);
1909 /* clear TD SIZE to zero, hence this is the last TRB */
1910 /* remove chain bit because this is the last data TRB in the chain */
1911 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1912 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1913 /* remove CHAIN-BIT from last LINK TRB */
1914 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1916 usb_pc_cpu_flush(td->page_cache);
1919 temp->td_next = td_next;
1923 xhci_setup_generic_chain(struct usb_xfer *xfer)
1925 struct xhci_std_temp temp;
1931 temp.do_isoc_sync = 0;
1935 temp.average = xfer->max_hc_frame_size;
1936 temp.max_packet_size = xfer->max_packet_size;
1937 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1939 temp.last_frame = 0;
1941 temp.multishort = xfer->flags_int.isochronous_xfr ||
1942 xfer->flags_int.control_xfr ||
1943 xfer->flags_int.short_frames_ok;
1945 /* toggle the DMA set we are using */
1946 xfer->flags_int.curr_dma_set ^= 1;
1948 /* get next DMA set */
1949 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1954 xfer->td_transfer_first = td;
1955 xfer->td_transfer_cache = td;
1957 if (xfer->flags_int.isochronous_xfr) {
1960 /* compute multiplier for ISOCHRONOUS transfers */
1961 mult = xfer->endpoint->ecomp ?
1962 (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1963 /* check for USB 2.0 multiplier */
1965 mult = (xfer->endpoint->edesc->
1966 wMaxPacketSize[1] >> 3) & 3;
1974 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1976 DPRINTF("MFINDEX=0x%08x\n", x);
1978 switch (usbd_get_speed(xfer->xroot->udev)) {
1979 case USB_SPEED_FULL:
1981 temp.isoc_delta = 8; /* 1ms */
1982 x += temp.isoc_delta - 1;
1983 x &= ~(temp.isoc_delta - 1);
1986 shift = usbd_xfer_get_fps_shift(xfer);
1987 temp.isoc_delta = 1U << shift;
1988 x += temp.isoc_delta - 1;
1989 x &= ~(temp.isoc_delta - 1);
1990 /* simple frame load balancing */
1991 x += xfer->endpoint->usb_uframe;
1995 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1997 if ((xfer->endpoint->is_synced == 0) ||
1998 (y < (xfer->nframes << shift)) ||
1999 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2001 * If there is data underflow or the pipe
2002 * queue is empty we schedule the transfer a
2003 * few frames ahead of the current frame
2004 * position. Else two isochronous transfers
2007 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2008 xfer->endpoint->is_synced = 1;
2009 temp.do_isoc_sync = 1;
2011 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2014 /* compute isochronous completion time */
2016 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2018 xfer->isoc_time_complete =
2019 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2020 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2023 temp.isoc_frame = xfer->endpoint->isoc_next;
2024 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2026 xfer->endpoint->isoc_next += xfer->nframes << shift;
2028 } else if (xfer->flags_int.control_xfr) {
2030 /* check if we should prepend a setup message */
2032 if (xfer->flags_int.control_hdr) {
2034 temp.len = xfer->frlengths[0];
2035 temp.pc = xfer->frbuffers + 0;
2036 temp.shortpkt = temp.len ? 1 : 0;
2037 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2040 /* check for last frame */
2041 if (xfer->nframes == 1) {
2042 /* no STATUS stage yet, SETUP is last */
2043 if (xfer->flags_int.control_act)
2044 temp.last_frame = 1;
2047 xhci_setup_generic_chain_sub(&temp);
2051 temp.isoc_delta = 0;
2052 temp.isoc_frame = 0;
2053 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2057 temp.isoc_delta = 0;
2058 temp.isoc_frame = 0;
2059 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2062 if (x != xfer->nframes) {
2063 /* setup page_cache pointer */
2064 temp.pc = xfer->frbuffers + x;
2065 /* set endpoint direction */
2066 temp.direction = UE_GET_DIR(xfer->endpointno);
2069 while (x != xfer->nframes) {
2071 /* DATA0 / DATA1 message */
2073 temp.len = xfer->frlengths[x];
2074 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2075 x != 0 && temp.multishort == 0);
2079 if (x == xfer->nframes) {
2080 if (xfer->flags_int.control_xfr) {
2081 /* no STATUS stage yet, DATA is last */
2082 if (xfer->flags_int.control_act)
2083 temp.last_frame = 1;
2085 temp.last_frame = 1;
2088 if (temp.len == 0) {
2090 /* make sure that we send an USB packet */
2095 temp.tlbpc = mult - 1;
2097 } else if (xfer->flags_int.isochronous_xfr) {
2102 * Isochronous transfers don't have short
2103 * packet termination:
2108 /* isochronous transfers have a transfer limit */
2110 if (temp.len > xfer->max_frame_size)
2111 temp.len = xfer->max_frame_size;
2113 /* compute TD packet count */
2114 tdpc = (temp.len + xfer->max_packet_size - 1) /
2115 xfer->max_packet_size;
2117 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2118 temp.tlbpc = (tdpc % mult);
2120 if (temp.tlbpc == 0)
2121 temp.tlbpc = mult - 1;
2126 /* regular data transfer */
2128 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2131 xhci_setup_generic_chain_sub(&temp);
2133 if (xfer->flags_int.isochronous_xfr) {
2134 temp.offset += xfer->frlengths[x - 1];
2135 temp.isoc_frame += temp.isoc_delta;
2137 /* get next Page Cache pointer */
2138 temp.pc = xfer->frbuffers + x;
2142 /* check if we should append a status stage */
2144 if (xfer->flags_int.control_xfr &&
2145 !xfer->flags_int.control_act) {
2148 * Send a DATA1 message and invert the current
2149 * endpoint direction.
2151 temp.step_td = (xfer->nframes != 0);
2152 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2156 temp.last_frame = 1;
2157 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2159 xhci_setup_generic_chain_sub(&temp);
2164 /* must have at least one frame! */
2166 xfer->td_transfer_last = td;
2168 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2172 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2174 struct usb_page_search buf_res;
2175 struct xhci_dev_ctx_addr *pdctxa;
2177 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2179 pdctxa = buf_res.buffer;
2181 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2183 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2185 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2189 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2191 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2192 struct usb_page_search buf_inp;
2193 struct xhci_input_dev_ctx *pinp;
2198 index = udev->controller_slot_id;
2200 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2202 pinp = buf_inp.buffer;
2205 mask &= XHCI_INCTX_NON_CTRL_MASK;
2206 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2207 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2209 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2210 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2212 /* find most significant set bit */
2213 for (x = 31; x != 1; x--) {
2214 if (mask & (1 << x))
2221 /* figure out maximum */
2222 if (x > sc->sc_hw.devs[index].context_num) {
2223 sc->sc_hw.devs[index].context_num = x;
2224 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2225 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2226 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2227 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2234 xhci_configure_endpoint(struct usb_device *udev,
2235 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2236 uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2237 uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2239 struct usb_page_search buf_inp;
2240 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2241 struct xhci_input_dev_ctx *pinp;
2247 index = udev->controller_slot_id;
2249 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2251 pinp = buf_inp.buffer;
2253 epno = edesc->bEndpointAddress;
2254 type = edesc->bmAttributes & UE_XFERTYPE;
2256 if (type == UE_CONTROL)
2259 epno = XHCI_EPNO2EPID(epno);
2262 return (USB_ERR_NO_PIPE); /* invalid */
2264 if (max_packet_count == 0)
2265 return (USB_ERR_BAD_BUFSIZE);
2270 return (USB_ERR_BAD_BUFSIZE);
2272 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2273 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2274 XHCI_EPCTX_0_LSA_SET(0);
2276 switch (udev->speed) {
2277 case USB_SPEED_FULL:
2290 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2292 case UE_ISOCHRONOUS:
2293 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2295 switch (udev->speed) {
2296 case USB_SPEED_SUPER:
2299 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2300 max_packet_count /= mult;
2310 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2313 XHCI_EPCTX_1_HID_SET(0) |
2314 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2315 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2317 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2318 if (type != UE_ISOCHRONOUS)
2319 temp |= XHCI_EPCTX_1_CERR_SET(3);
2324 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2326 case UE_ISOCHRONOUS:
2327 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2330 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2333 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2337 /* check for IN direction */
2339 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2341 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2343 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2345 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2347 switch (edesc->bmAttributes & UE_XFERTYPE) {
2349 case UE_ISOCHRONOUS:
2350 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2351 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2355 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2358 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2362 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2365 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2367 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2369 return (0); /* success */
2373 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2375 struct xhci_endpoint_ext *pepext;
2376 struct usb_endpoint_ss_comp_descriptor *ecomp;
2378 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2379 xfer->endpoint->edesc);
2381 ecomp = xfer->endpoint->ecomp;
2383 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */
2384 usb_pc_cpu_flush(pepext->page_cache);
2386 return (xhci_configure_endpoint(xfer->xroot->udev,
2387 xfer->endpoint->edesc, pepext->physaddr,
2388 xfer->interval, xfer->max_packet_count,
2389 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2390 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2391 xfer->max_frame_size));
2395 xhci_configure_device(struct usb_device *udev)
2397 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2398 struct usb_page_search buf_inp;
2399 struct usb_page_cache *pcinp;
2400 struct xhci_input_dev_ctx *pinp;
2401 struct usb_device *hubdev;
2409 index = udev->controller_slot_id;
2411 DPRINTF("index=%u\n", index);
2413 pcinp = &sc->sc_hw.devs[index].input_pc;
2415 usbd_get_page(pcinp, 0, &buf_inp);
2417 pinp = buf_inp.buffer;
2422 /* figure out route string and root HUB port number */
2424 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2426 if (hubdev->parent_hub == NULL)
2429 depth = hubdev->parent_hub->depth;
2432 * NOTE: HS/FS/LS devices and the SS root HUB can have
2433 * more than 15 ports
2436 rh_port = hubdev->port_no;
2445 route |= rh_port << (4 * (depth - 1));
2448 DPRINTF("Route=0x%08x\n", route);
2450 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2451 XHCI_SCTX_0_CTX_NUM_SET(
2452 sc->sc_hw.devs[index].context_num + 1);
2454 switch (udev->speed) {
2456 temp |= XHCI_SCTX_0_SPEED_SET(2);
2457 if (udev->parent_hs_hub != NULL &&
2458 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2460 DPRINTF("Device inherits MTT\n");
2461 temp |= XHCI_SCTX_0_MTT_SET(1);
2464 case USB_SPEED_HIGH:
2465 temp |= XHCI_SCTX_0_SPEED_SET(3);
2466 if (sc->sc_hw.devs[index].nports != 0 &&
2467 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2468 DPRINTF("HUB supports MTT\n");
2469 temp |= XHCI_SCTX_0_MTT_SET(1);
2472 case USB_SPEED_FULL:
2473 temp |= XHCI_SCTX_0_SPEED_SET(1);
2474 if (udev->parent_hs_hub != NULL &&
2475 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2477 DPRINTF("Device inherits MTT\n");
2478 temp |= XHCI_SCTX_0_MTT_SET(1);
2482 temp |= XHCI_SCTX_0_SPEED_SET(4);
2486 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2487 (udev->speed == USB_SPEED_SUPER ||
2488 udev->speed == USB_SPEED_HIGH);
2491 temp |= XHCI_SCTX_0_HUB_SET(1);
2493 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2495 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2498 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2499 sc->sc_hw.devs[index].nports);
2502 switch (udev->speed) {
2503 case USB_SPEED_SUPER:
2504 switch (sc->sc_hw.devs[index].state) {
2505 case XHCI_ST_ADDRESSED:
2506 case XHCI_ST_CONFIGURED:
2507 /* enable power save */
2508 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2511 /* disable power save */
2519 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2521 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2524 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2525 sc->sc_hw.devs[index].tt);
2528 hubdev = udev->parent_hs_hub;
2530 /* check if we should activate the transaction translator */
2531 switch (udev->speed) {
2532 case USB_SPEED_FULL:
2534 if (hubdev != NULL) {
2535 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2536 hubdev->controller_slot_id);
2537 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2545 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2548 * These fields should be initialized to zero, according to
2549 * XHCI section 6.2.2 - slot context:
2551 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2552 XHCI_SCTX_3_SLOT_STATE_SET(0);
2554 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2557 xhci_dump_device(sc, &pinp->ctx_slot);
2559 usb_pc_cpu_flush(pcinp);
2561 return (0); /* success */
2565 xhci_alloc_device_ext(struct usb_device *udev)
2567 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2568 struct usb_page_search buf_dev;
2569 struct usb_page_search buf_ep;
2570 struct xhci_trb *trb;
2571 struct usb_page_cache *pc;
2572 struct usb_page *pg;
2577 index = udev->controller_slot_id;
2579 pc = &sc->sc_hw.devs[index].device_pc;
2580 pg = &sc->sc_hw.devs[index].device_pg;
2582 /* need to initialize the page cache */
2583 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2585 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2586 (2 * sizeof(struct xhci_dev_ctx)) :
2587 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2590 usbd_get_page(pc, 0, &buf_dev);
2592 pc = &sc->sc_hw.devs[index].input_pc;
2593 pg = &sc->sc_hw.devs[index].input_pg;
2595 /* need to initialize the page cache */
2596 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2598 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2599 (2 * sizeof(struct xhci_input_dev_ctx)) :
2600 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2604 pc = &sc->sc_hw.devs[index].endpoint_pc;
2605 pg = &sc->sc_hw.devs[index].endpoint_pg;
2607 /* need to initialize the page cache */
2608 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2610 if (usb_pc_alloc_mem(pc, pg,
2611 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2615 /* initialise all endpoint LINK TRBs */
2617 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2619 /* lookup endpoint TRB ring */
2620 usbd_get_page(pc, (uintptr_t)&
2621 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2623 /* get TRB pointer */
2624 trb = buf_ep.buffer;
2625 trb += XHCI_MAX_TRANSFERS - 1;
2627 /* get TRB start address */
2628 addr = buf_ep.physaddr;
2630 /* create LINK TRB */
2631 trb->qwTrb0 = htole64(addr);
2632 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2633 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2634 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2637 usb_pc_cpu_flush(pc);
2639 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2644 xhci_free_device_ext(udev);
2646 return (USB_ERR_NOMEM);
2650 xhci_free_device_ext(struct usb_device *udev)
2652 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2655 index = udev->controller_slot_id;
2656 xhci_set_slot_pointer(sc, index, 0);
2658 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2659 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2660 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2663 static struct xhci_endpoint_ext *
2664 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2666 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2667 struct xhci_endpoint_ext *pepext;
2668 struct usb_page_cache *pc;
2669 struct usb_page_search buf_ep;
2673 epno = edesc->bEndpointAddress;
2674 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2677 epno = XHCI_EPNO2EPID(epno);
2679 index = udev->controller_slot_id;
2681 pc = &sc->sc_hw.devs[index].endpoint_pc;
2683 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2685 pepext = &sc->sc_hw.devs[index].endp[epno];
2686 pepext->page_cache = pc;
2687 pepext->trb = buf_ep.buffer;
2688 pepext->physaddr = buf_ep.physaddr;
2694 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2696 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2700 epno = xfer->endpointno;
2701 if (xfer->flags_int.control_xfr)
2704 epno = XHCI_EPNO2EPID(epno);
2705 index = xfer->xroot->udev->controller_slot_id;
2707 if (xfer->xroot->udev->flags.self_suspended == 0) {
2708 XWRITE4(sc, door, XHCI_DOORBELL(index),
2709 epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2714 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2716 struct xhci_endpoint_ext *pepext;
2718 if (xfer->flags_int.bandwidth_reclaimed) {
2719 xfer->flags_int.bandwidth_reclaimed = 0;
2721 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2722 xfer->endpoint->edesc);
2726 pepext->xfer[xfer->qh_pos] = NULL;
2728 if (error && pepext->trb_running != 0) {
2729 pepext->trb_halted = 1;
2730 pepext->trb_running = 0;
2736 xhci_transfer_insert(struct usb_xfer *xfer)
2738 struct xhci_td *td_first;
2739 struct xhci_td *td_last;
2740 struct xhci_trb *trb_link;
2741 struct xhci_endpoint_ext *pepext;
2749 /* check if already inserted */
2750 if (xfer->flags_int.bandwidth_reclaimed) {
2751 DPRINTFN(8, "Already in schedule\n");
2755 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2756 xfer->endpoint->edesc);
2758 td_first = xfer->td_transfer_first;
2759 td_last = xfer->td_transfer_last;
2760 addr = pepext->physaddr;
2762 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2765 /* single buffered */
2769 /* multi buffered */
2770 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2774 if (pepext->trb_used >= trb_limit) {
2775 DPRINTFN(8, "Too many TDs queued.\n");
2776 return (USB_ERR_NOMEM);
2779 /* check for stopped condition, after putting transfer on interrupt queue */
2780 if (pepext->trb_running == 0) {
2781 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2783 DPRINTFN(8, "Not running\n");
2785 /* start configuration */
2786 (void)usb_proc_msignal(&sc->sc_config_proc,
2787 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2793 /* get current TRB index */
2794 i = pepext->trb_index;
2796 /* get next TRB index */
2799 /* the last entry of the ring is a hardcoded link TRB */
2800 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2803 /* compute terminating return address */
2804 addr += inext * sizeof(struct xhci_trb);
2806 /* compute link TRB pointer */
2807 trb_link = td_last->td_trb + td_last->ntrb;
2809 /* update next pointer of last link TRB */
2810 trb_link->qwTrb0 = htole64(addr);
2811 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2812 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2813 XHCI_TRB_3_CYCLE_BIT |
2814 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2817 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2819 usb_pc_cpu_flush(td_last->page_cache);
2821 /* write ahead chain end marker */
2823 pepext->trb[inext].qwTrb0 = 0;
2824 pepext->trb[inext].dwTrb2 = 0;
2825 pepext->trb[inext].dwTrb3 = 0;
2827 /* update next pointer of link TRB */
2829 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2830 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2833 xhci_dump_trb(&pepext->trb[i]);
2835 usb_pc_cpu_flush(pepext->page_cache);
2837 /* toggle cycle bit which activates the transfer chain */
2839 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2840 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2842 usb_pc_cpu_flush(pepext->page_cache);
2844 DPRINTF("qh_pos = %u\n", i);
2846 pepext->xfer[i] = xfer;
2850 xfer->flags_int.bandwidth_reclaimed = 1;
2852 pepext->trb_index = inext;
2854 xhci_endpoint_doorbell(xfer);
2860 xhci_root_intr(struct xhci_softc *sc)
2864 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2866 /* clear any old interrupt data */
2867 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2869 for (i = 1; i <= sc->sc_noport; i++) {
2870 /* pick out CHANGE bits from the status register */
2871 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2872 XHCI_PS_CSC | XHCI_PS_PEC |
2873 XHCI_PS_OCC | XHCI_PS_WRC |
2874 XHCI_PS_PRC | XHCI_PS_PLC |
2876 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2877 DPRINTF("port %d changed\n", i);
2880 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2881 sizeof(sc->sc_hub_idata));
2884 /*------------------------------------------------------------------------*
2885 * xhci_device_done - XHCI done handler
2887 * NOTE: This function can be called two times in a row on
2888 * the same USB transfer. From close and from interrupt.
2889 *------------------------------------------------------------------------*/
2891 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2893 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2894 xfer, xfer->endpoint, error);
2896 /* remove transfer from HW queue */
2897 xhci_transfer_remove(xfer, error);
2899 /* dequeue transfer and start next transfer */
2900 usbd_transfer_done(xfer, error);
2903 /*------------------------------------------------------------------------*
2904 * XHCI data transfer support (generic type)
2905 *------------------------------------------------------------------------*/
2907 xhci_device_generic_open(struct usb_xfer *xfer)
2909 if (xfer->flags_int.isochronous_xfr) {
2910 switch (xfer->xroot->udev->speed) {
2911 case USB_SPEED_FULL:
2914 usb_hs_bandwidth_alloc(xfer);
2921 xhci_device_generic_close(struct usb_xfer *xfer)
2925 xhci_device_done(xfer, USB_ERR_CANCELLED);
2927 if (xfer->flags_int.isochronous_xfr) {
2928 switch (xfer->xroot->udev->speed) {
2929 case USB_SPEED_FULL:
2932 usb_hs_bandwidth_free(xfer);
2939 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2940 struct usb_xfer *enter_xfer)
2942 struct usb_xfer *xfer;
2944 /* check if there is a current transfer */
2945 xfer = ep->endpoint_q.curr;
2950 * Check if the current transfer is started and then pickup
2951 * the next one, if any. Else wait for next start event due to
2952 * block on failure feature.
2954 if (!xfer->flags_int.bandwidth_reclaimed)
2957 xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2960 * In case of enter we have to consider that the
2961 * transfer is queued by the USB core after the enter
2970 /* try to multi buffer */
2971 xhci_transfer_insert(xfer);
2975 xhci_device_generic_enter(struct usb_xfer *xfer)
2979 /* setup TD's and QH */
2980 xhci_setup_generic_chain(xfer);
2982 xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2986 xhci_device_generic_start(struct usb_xfer *xfer)
2990 /* try to insert xfer on HW queue */
2991 xhci_transfer_insert(xfer);
2993 /* try to multi buffer */
2994 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2996 /* add transfer last on interrupt queue */
2997 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2999 /* start timeout, if any */
3000 if (xfer->timeout != 0)
3001 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3004 struct usb_pipe_methods xhci_device_generic_methods =
3006 .open = xhci_device_generic_open,
3007 .close = xhci_device_generic_close,
3008 .enter = xhci_device_generic_enter,
3009 .start = xhci_device_generic_start,
3012 /*------------------------------------------------------------------------*
3013 * xhci root HUB support
3014 *------------------------------------------------------------------------*
3015 * Simulate a hardware HUB by handling all the necessary requests.
3016 *------------------------------------------------------------------------*/
3018 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3021 struct usb_device_descriptor xhci_devd =
3023 .bLength = sizeof(xhci_devd),
3024 .bDescriptorType = UDESC_DEVICE, /* type */
3025 HSETW(.bcdUSB, 0x0300), /* USB version */
3026 .bDeviceClass = UDCLASS_HUB, /* class */
3027 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3028 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3029 .bMaxPacketSize = 9, /* max packet size */
3030 HSETW(.idVendor, 0x0000), /* vendor */
3031 HSETW(.idProduct, 0x0000), /* product */
3032 HSETW(.bcdDevice, 0x0100), /* device version */
3036 .bNumConfigurations = 1, /* # of configurations */
3040 struct xhci_bos_desc xhci_bosd = {
3042 .bLength = sizeof(xhci_bosd.bosd),
3043 .bDescriptorType = UDESC_BOS,
3044 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3045 .bNumDeviceCaps = 3,
3048 .bLength = sizeof(xhci_bosd.usb2extd),
3049 .bDescriptorType = 1,
3050 .bDevCapabilityType = 2,
3051 .bmAttributes[0] = 2,
3054 .bLength = sizeof(xhci_bosd.usbdcd),
3055 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3056 .bDevCapabilityType = 3,
3057 .bmAttributes = 0, /* XXX */
3058 HSETW(.wSpeedsSupported, 0x000C),
3059 .bFunctionalitySupport = 8,
3060 .bU1DevExitLat = 255, /* dummy - not used */
3061 .wU2DevExitLat = { 0x00, 0x08 },
3064 .bLength = sizeof(xhci_bosd.cidd),
3065 .bDescriptorType = 1,
3066 .bDevCapabilityType = 4,
3068 .bContainerID = 0, /* XXX */
3073 struct xhci_config_desc xhci_confd = {
3075 .bLength = sizeof(xhci_confd.confd),
3076 .bDescriptorType = UDESC_CONFIG,
3077 .wTotalLength[0] = sizeof(xhci_confd),
3079 .bConfigurationValue = 1,
3080 .iConfiguration = 0,
3081 .bmAttributes = UC_SELF_POWERED,
3082 .bMaxPower = 0 /* max power */
3085 .bLength = sizeof(xhci_confd.ifcd),
3086 .bDescriptorType = UDESC_INTERFACE,
3088 .bInterfaceClass = UICLASS_HUB,
3089 .bInterfaceSubClass = UISUBCLASS_HUB,
3090 .bInterfaceProtocol = 0,
3093 .bLength = sizeof(xhci_confd.endpd),
3094 .bDescriptorType = UDESC_ENDPOINT,
3095 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3096 .bmAttributes = UE_INTERRUPT,
3097 .wMaxPacketSize[0] = 2, /* max 15 ports */
3101 .bLength = sizeof(xhci_confd.endpcd),
3102 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3109 struct usb_hub_ss_descriptor xhci_hubd = {
3110 .bLength = sizeof(xhci_hubd),
3111 .bDescriptorType = UDESC_SS_HUB,
3115 xhci_roothub_exec(struct usb_device *udev,
3116 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3118 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3119 const char *str_ptr;
3130 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3133 ptr = (const void *)&sc->sc_hub_desc;
3137 value = UGETW(req->wValue);
3138 index = UGETW(req->wIndex);
3140 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3141 "wValue=0x%04x wIndex=0x%04x\n",
3142 req->bmRequestType, req->bRequest,
3143 UGETW(req->wLength), value, index);
3145 #define C(x,y) ((x) | ((y) << 8))
3146 switch (C(req->bRequest, req->bmRequestType)) {
3147 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3148 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3149 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3151 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3152 * for the integrated root hub.
3155 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3157 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3159 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3160 switch (value >> 8) {
3162 if ((value & 0xff) != 0) {
3163 err = USB_ERR_IOERROR;
3166 len = sizeof(xhci_devd);
3167 ptr = (const void *)&xhci_devd;
3171 if ((value & 0xff) != 0) {
3172 err = USB_ERR_IOERROR;
3175 len = sizeof(xhci_bosd);
3176 ptr = (const void *)&xhci_bosd;
3180 if ((value & 0xff) != 0) {
3181 err = USB_ERR_IOERROR;
3184 len = sizeof(xhci_confd);
3185 ptr = (const void *)&xhci_confd;
3189 switch (value & 0xff) {
3190 case 0: /* Language table */
3194 case 1: /* Vendor */
3195 str_ptr = sc->sc_vendor;
3198 case 2: /* Product */
3199 str_ptr = "XHCI root HUB";
3207 len = usb_make_str_desc(
3208 sc->sc_hub_desc.temp,
3209 sizeof(sc->sc_hub_desc.temp),
3214 err = USB_ERR_IOERROR;
3218 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3220 sc->sc_hub_desc.temp[0] = 0;
3222 case C(UR_GET_STATUS, UT_READ_DEVICE):
3224 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3226 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3227 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3229 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3231 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3232 if (value >= XHCI_MAX_DEVICES) {
3233 err = USB_ERR_IOERROR;
3237 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3238 if (value != 0 && value != 1) {
3239 err = USB_ERR_IOERROR;
3242 sc->sc_conf = value;
3244 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3246 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3247 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3248 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3249 err = USB_ERR_IOERROR;
3251 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3253 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3256 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3258 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3259 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3262 (index > sc->sc_noport)) {
3263 err = USB_ERR_IOERROR;
3266 port = XHCI_PORTSC(index);
3268 v = XREAD4(sc, oper, port);
3269 i = XHCI_PS_PLS_GET(v);
3270 v &= ~XHCI_PS_CLEAR;
3273 case UHF_C_BH_PORT_RESET:
3274 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3276 case UHF_C_PORT_CONFIG_ERROR:
3277 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3279 case UHF_C_PORT_SUSPEND:
3280 case UHF_C_PORT_LINK_STATE:
3281 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3283 case UHF_C_PORT_CONNECTION:
3284 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3286 case UHF_C_PORT_ENABLE:
3287 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3289 case UHF_C_PORT_OVER_CURRENT:
3290 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3292 case UHF_C_PORT_RESET:
3293 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3295 case UHF_PORT_ENABLE:
3296 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3298 case UHF_PORT_POWER:
3299 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3301 case UHF_PORT_INDICATOR:
3302 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3304 case UHF_PORT_SUSPEND:
3308 XWRITE4(sc, oper, port, v |
3309 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3312 /* wait 20ms for resume sequence to complete */
3313 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3316 XWRITE4(sc, oper, port, v |
3317 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3320 err = USB_ERR_IOERROR;
3325 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3326 if ((value & 0xff) != 0) {
3327 err = USB_ERR_IOERROR;
3331 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3333 sc->sc_hub_desc.hubd = xhci_hubd;
3335 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3337 if (XHCI_HCS0_PPC(v))
3338 i = UHD_PWR_INDIVIDUAL;
3342 if (XHCI_HCS0_PIND(v))
3345 i |= UHD_OC_INDIVIDUAL;
3347 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3349 /* see XHCI section 5.4.9: */
3350 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3352 for (j = 1; j <= sc->sc_noport; j++) {
3354 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3355 if (v & XHCI_PS_DR) {
3356 sc->sc_hub_desc.hubd.
3357 DeviceRemovable[j / 8] |= 1U << (j % 8);
3360 len = sc->sc_hub_desc.hubd.bLength;
3363 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3365 memset(sc->sc_hub_desc.temp, 0, 16);
3368 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3369 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3372 (index > sc->sc_noport)) {
3373 err = USB_ERR_IOERROR;
3377 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3379 DPRINTFN(9, "port status=0x%08x\n", v);
3381 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3383 switch (XHCI_PS_SPEED_GET(v)) {
3385 i |= UPS_HIGH_SPEED;
3394 i |= UPS_OTHER_SPEED;
3398 if (v & XHCI_PS_CCS)
3399 i |= UPS_CURRENT_CONNECT_STATUS;
3400 if (v & XHCI_PS_PED)
3401 i |= UPS_PORT_ENABLED;
3402 if (v & XHCI_PS_OCA)
3403 i |= UPS_OVERCURRENT_INDICATOR;
3406 if (v & XHCI_PS_PP) {
3408 * The USB 3.0 RH is using the
3409 * USB 2.0's power bit
3411 i |= UPS_PORT_POWER;
3413 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3416 if (v & XHCI_PS_CSC)
3417 i |= UPS_C_CONNECT_STATUS;
3418 if (v & XHCI_PS_PEC)
3419 i |= UPS_C_PORT_ENABLED;
3420 if (v & XHCI_PS_OCC)
3421 i |= UPS_C_OVERCURRENT_INDICATOR;
3422 if (v & XHCI_PS_WRC)
3423 i |= UPS_C_BH_PORT_RESET;
3424 if (v & XHCI_PS_PRC)
3425 i |= UPS_C_PORT_RESET;
3426 if (v & XHCI_PS_PLC)
3427 i |= UPS_C_PORT_LINK_STATE;
3428 if (v & XHCI_PS_CEC)
3429 i |= UPS_C_PORT_CONFIG_ERROR;
3431 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3432 len = sizeof(sc->sc_hub_desc.ps);
3435 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3436 err = USB_ERR_IOERROR;
3439 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3442 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3448 (index > sc->sc_noport)) {
3449 err = USB_ERR_IOERROR;
3453 port = XHCI_PORTSC(index);
3454 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3457 case UHF_PORT_U1_TIMEOUT:
3458 if (XHCI_PS_SPEED_GET(v) != 4) {
3459 err = USB_ERR_IOERROR;
3462 port = XHCI_PORTPMSC(index);
3463 v = XREAD4(sc, oper, port);
3464 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3465 v |= XHCI_PM3_U1TO_SET(i);
3466 XWRITE4(sc, oper, port, v);
3468 case UHF_PORT_U2_TIMEOUT:
3469 if (XHCI_PS_SPEED_GET(v) != 4) {
3470 err = USB_ERR_IOERROR;
3473 port = XHCI_PORTPMSC(index);
3474 v = XREAD4(sc, oper, port);
3475 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3476 v |= XHCI_PM3_U2TO_SET(i);
3477 XWRITE4(sc, oper, port, v);
3479 case UHF_BH_PORT_RESET:
3480 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3482 case UHF_PORT_LINK_STATE:
3483 XWRITE4(sc, oper, port, v |
3484 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3485 /* 4ms settle time */
3486 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3488 case UHF_PORT_ENABLE:
3489 DPRINTFN(3, "set port enable %d\n", index);
3491 case UHF_PORT_SUSPEND:
3492 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3493 j = XHCI_PS_SPEED_GET(v);
3494 if ((j < 1) || (j > 3)) {
3495 /* non-supported speed */
3496 err = USB_ERR_IOERROR;
3499 XWRITE4(sc, oper, port, v |
3500 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3502 case UHF_PORT_RESET:
3503 DPRINTFN(6, "reset port %d\n", index);
3504 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3506 case UHF_PORT_POWER:
3507 DPRINTFN(3, "set port power %d\n", index);
3508 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3511 DPRINTFN(3, "set port test %d\n", index);
3513 case UHF_PORT_INDICATOR:
3514 DPRINTFN(3, "set port indicator %d\n", index);
3516 v &= ~XHCI_PS_PIC_SET(3);
3517 v |= XHCI_PS_PIC_SET(1);
3519 XWRITE4(sc, oper, port, v);
3522 err = USB_ERR_IOERROR;
3527 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3528 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3529 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3530 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3533 err = USB_ERR_IOERROR;
3543 xhci_xfer_setup(struct usb_setup_params *parm)
3545 struct usb_page_search page_info;
3546 struct usb_page_cache *pc;
3547 struct xhci_softc *sc;
3548 struct usb_xfer *xfer;
3553 sc = XHCI_BUS2SC(parm->udev->bus);
3554 xfer = parm->curr_xfer;
3557 * The proof for the "ntd" formula is illustrated like this:
3559 * +------------------------------------+
3563 * | | xxx | x | frm 0 |
3565 * | | xxx | xx | frm 1 |
3568 * +------------------------------------+
3570 * "xxx" means a completely full USB transfer descriptor
3572 * "x" and "xx" means a short USB packet
3574 * For the remainder of an USB transfer modulo
3575 * "max_data_length" we need two USB transfer descriptors.
3576 * One to transfer the remaining data and one to finalise with
3577 * a zero length packet in case the "force_short_xfer" flag is
3578 * set. We only need two USB transfer descriptors in the case
3579 * where the transfer length of the first one is a factor of
3580 * "max_frame_size". The rest of the needed USB transfer
3581 * descriptors is given by the buffer size divided by the
3582 * maximum data payload.
3584 parm->hc_max_packet_size = 0x400;
3585 parm->hc_max_packet_count = 16 * 3;
3586 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3588 xfer->flags_int.bdma_enable = 1;
3590 usbd_transfer_setup_sub(parm);
3592 if (xfer->flags_int.isochronous_xfr) {
3593 ntd = ((1 * xfer->nframes)
3594 + (xfer->max_data_length / xfer->max_hc_frame_size));
3595 } else if (xfer->flags_int.control_xfr) {
3596 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3597 + (xfer->max_data_length / xfer->max_hc_frame_size));
3599 ntd = ((2 * xfer->nframes)
3600 + (xfer->max_data_length / xfer->max_hc_frame_size));
3609 * Allocate queue heads and transfer descriptors
3613 if (usbd_transfer_setup_sub_malloc(
3614 parm, &pc, sizeof(struct xhci_td),
3615 XHCI_TD_ALIGN, ntd)) {
3616 parm->err = USB_ERR_NOMEM;
3620 for (n = 0; n != ntd; n++) {
3623 usbd_get_page(pc + n, 0, &page_info);
3625 td = page_info.buffer;
3628 td->td_self = page_info.physaddr;
3629 td->obj_next = last_obj;
3630 td->page_cache = pc + n;
3634 usb_pc_cpu_flush(pc + n);
3637 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3639 if (!xfer->flags_int.curr_dma_set) {
3640 xfer->flags_int.curr_dma_set = 1;
3646 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3648 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3649 struct usb_page_search buf_inp;
3650 struct usb_device *udev;
3651 struct xhci_endpoint_ext *pepext;
3652 struct usb_endpoint_descriptor *edesc;
3653 struct usb_page_cache *pcinp;
3658 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3659 xfer->endpoint->edesc);
3661 udev = xfer->xroot->udev;
3662 index = udev->controller_slot_id;
3664 pcinp = &sc->sc_hw.devs[index].input_pc;
3666 usbd_get_page(pcinp, 0, &buf_inp);
3668 edesc = xfer->endpoint->edesc;
3670 epno = edesc->bEndpointAddress;
3672 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3675 epno = XHCI_EPNO2EPID(epno);
3678 return (USB_ERR_NO_PIPE); /* invalid */
3682 /* configure endpoint */
3684 err = xhci_configure_endpoint_by_xfer(xfer);
3687 XHCI_CMD_UNLOCK(sc);
3692 * Get the endpoint into the stopped state according to the
3693 * endpoint context state diagram in the XHCI specification:
3696 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3699 DPRINTF("Could not stop endpoint %u\n", epno);
3701 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3704 DPRINTF("Could not reset endpoint %u\n", epno);
3706 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3707 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3710 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3713 * Get the endpoint into the running state according to the
3714 * endpoint context state diagram in the XHCI specification:
3717 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3719 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3722 DPRINTF("Could not configure endpoint %u\n", epno);
3724 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3727 DPRINTF("Could not configure endpoint %u\n", epno);
3729 XHCI_CMD_UNLOCK(sc);
3735 xhci_xfer_unsetup(struct usb_xfer *xfer)
3741 xhci_start_dma_delay(struct usb_xfer *xfer)
3743 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3745 /* put transfer on interrupt queue (again) */
3746 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3748 (void)usb_proc_msignal(&sc->sc_config_proc,
3749 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3753 xhci_configure_msg(struct usb_proc_msg *pm)
3755 struct xhci_softc *sc;
3756 struct xhci_endpoint_ext *pepext;
3757 struct usb_xfer *xfer;
3759 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3762 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3764 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3765 xfer->endpoint->edesc);
3767 if ((pepext->trb_halted != 0) ||
3768 (pepext->trb_running == 0)) {
3772 /* clear halted and running */
3773 pepext->trb_halted = 0;
3774 pepext->trb_running = 0;
3776 /* nuke remaining buffered transfers */
3778 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3780 * NOTE: We need to use the timeout
3781 * error code here else existing
3782 * isochronous clients can get
3785 if (pepext->xfer[i] != NULL) {
3786 xhci_device_done(pepext->xfer[i],
3792 * NOTE: The USB transfer cannot vanish in
3796 USB_BUS_UNLOCK(&sc->sc_bus);
3798 xhci_configure_reset_endpoint(xfer);
3800 USB_BUS_LOCK(&sc->sc_bus);
3802 /* check if halted is still cleared */
3803 if (pepext->trb_halted == 0) {
3804 pepext->trb_running = 1;
3805 pepext->trb_index = 0;
3810 if (xfer->flags_int.did_dma_delay) {
3812 /* remove transfer from interrupt queue (again) */
3813 usbd_transfer_dequeue(xfer);
3815 /* we are finally done */
3816 usb_dma_delay_done_cb(xfer);
3818 /* queue changed - restart */
3823 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3825 /* try to insert xfer on HW queue */
3826 xhci_transfer_insert(xfer);
3828 /* try to multi buffer */
3829 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3834 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3835 struct usb_endpoint *ep)
3837 struct xhci_endpoint_ext *pepext;
3839 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3840 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3842 if (udev->parent_hub == NULL) {
3843 /* root HUB has special endpoint handling */
3847 ep->methods = &xhci_device_generic_methods;
3849 pepext = xhci_get_endpoint_ext(udev, edesc);
3851 USB_BUS_LOCK(udev->bus);
3852 pepext->trb_halted = 1;
3853 pepext->trb_running = 0;
3854 USB_BUS_UNLOCK(udev->bus);
3858 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3864 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3866 struct xhci_endpoint_ext *pepext;
3870 if (udev->flags.usb_mode != USB_MODE_HOST) {
3874 if (udev->parent_hub == NULL) {
3875 /* root HUB has special endpoint handling */
3879 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3881 USB_BUS_LOCK(udev->bus);
3882 pepext->trb_halted = 1;
3883 pepext->trb_running = 0;
3884 USB_BUS_UNLOCK(udev->bus);
3888 xhci_device_init(struct usb_device *udev)
3890 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3894 /* no init for root HUB */
3895 if (udev->parent_hub == NULL)
3900 /* set invalid default */
3902 udev->controller_slot_id = sc->sc_noslot + 1;
3904 /* try to get a new slot ID from the XHCI */
3906 err = xhci_cmd_enable_slot(sc, &temp);
3909 XHCI_CMD_UNLOCK(sc);
3913 if (temp > sc->sc_noslot) {
3914 XHCI_CMD_UNLOCK(sc);
3915 return (USB_ERR_BAD_ADDRESS);
3918 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3919 DPRINTF("slot %u already allocated.\n", temp);
3920 XHCI_CMD_UNLOCK(sc);
3921 return (USB_ERR_BAD_ADDRESS);
3924 /* store slot ID for later reference */
3926 udev->controller_slot_id = temp;
3928 /* reset data structure */
3930 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3932 /* set mark slot allocated */
3934 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3936 err = xhci_alloc_device_ext(udev);
3938 XHCI_CMD_UNLOCK(sc);
3940 /* get device into default state */
3943 err = xhci_set_address(udev, NULL, 0);
3949 xhci_device_uninit(struct usb_device *udev)
3951 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3954 /* no init for root HUB */
3955 if (udev->parent_hub == NULL)
3960 index = udev->controller_slot_id;
3962 if (index <= sc->sc_noslot) {
3963 xhci_cmd_disable_slot(sc, index);
3964 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3966 /* free device extension */
3967 xhci_free_device_ext(udev);
3970 XHCI_CMD_UNLOCK(sc);
3974 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3977 * Wait until the hardware has finished any possible use of
3978 * the transfer descriptor(s)
3980 *pus = 2048; /* microseconds */
3984 xhci_device_resume(struct usb_device *udev)
3986 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3993 /* check for root HUB */
3994 if (udev->parent_hub == NULL)
3997 index = udev->controller_slot_id;
4001 /* blindly resume all endpoints */
4003 USB_BUS_LOCK(udev->bus);
4005 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4006 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4007 XWRITE4(sc, door, XHCI_DOORBELL(index),
4008 n | XHCI_DB_SID_SET(p));
4012 USB_BUS_UNLOCK(udev->bus);
4014 XHCI_CMD_UNLOCK(sc);
4018 xhci_device_suspend(struct usb_device *udev)
4020 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4027 /* check for root HUB */
4028 if (udev->parent_hub == NULL)
4031 index = udev->controller_slot_id;
4035 /* blindly suspend all endpoints */
4037 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4038 err = xhci_cmd_stop_ep(sc, 1, n, index);
4040 DPRINTF("Failed to suspend endpoint "
4041 "%u on slot %u (ignored).\n", n, index);
4045 XHCI_CMD_UNLOCK(sc);
4049 xhci_set_hw_power(struct usb_bus *bus)
4055 xhci_device_state_change(struct usb_device *udev)
4057 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4058 struct usb_page_search buf_inp;
4062 /* check for root HUB */
4063 if (udev->parent_hub == NULL)
4066 index = udev->controller_slot_id;
4070 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4071 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4072 &sc->sc_hw.devs[index].tt);
4074 sc->sc_hw.devs[index].nports = 0;
4079 switch (usb_get_device_state(udev)) {
4080 case USB_STATE_POWERED:
4081 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4084 /* set default state */
4085 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4087 /* reset number of contexts */
4088 sc->sc_hw.devs[index].context_num = 0;
4090 err = xhci_cmd_reset_dev(sc, index);
4093 DPRINTF("Device reset failed "
4094 "for slot %u.\n", index);
4098 case USB_STATE_ADDRESSED:
4099 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4102 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4104 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4107 DPRINTF("Failed to deconfigure "
4108 "slot %u.\n", index);
4112 case USB_STATE_CONFIGURED:
4113 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4116 /* set configured state */
4117 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4119 /* reset number of contexts */
4120 sc->sc_hw.devs[index].context_num = 0;
4122 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4124 xhci_configure_mask(udev, 3, 0);
4126 err = xhci_configure_device(udev);
4128 DPRINTF("Could not configure device "
4129 "at slot %u.\n", index);
4132 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4134 DPRINTF("Could not evaluate device "
4135 "context at slot %u.\n", index);
4142 XHCI_CMD_UNLOCK(sc);
4145 struct usb_bus_methods xhci_bus_methods = {
4146 .endpoint_init = xhci_ep_init,
4147 .endpoint_uninit = xhci_ep_uninit,
4148 .xfer_setup = xhci_xfer_setup,
4149 .xfer_unsetup = xhci_xfer_unsetup,
4150 .get_dma_delay = xhci_get_dma_delay,
4151 .device_init = xhci_device_init,
4152 .device_uninit = xhci_device_uninit,
4153 .device_resume = xhci_device_resume,
4154 .device_suspend = xhci_device_suspend,
4155 .set_hw_power = xhci_set_hw_power,
4156 .roothub_exec = xhci_roothub_exec,
4157 .xfer_poll = xhci_do_poll,
4158 .start_dma_delay = xhci_start_dma_delay,
4159 .set_address = xhci_set_address,
4160 .clear_stall = xhci_ep_clear_stall,
4161 .device_state_change = xhci_device_state_change,
4162 .set_hw_power_sleep = xhci_set_hw_power_sleep,