3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
30 * The XHCI 1.0 spec can be found at
31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
32 * and the USB 3.0 spec at
33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
37 * A few words about the design implementation: This driver emulates
38 * the concept about TDs which is found in EHCI specification. This
39 * way we achieve that the USB controller drivers look similar to
40 * eachother which makes it easier to understand the code.
43 #ifdef USB_GLOBAL_INCLUDE_FILE
44 #include USB_GLOBAL_INCLUDE_FILE
46 #include <sys/stdint.h>
47 #include <sys/stddef.h>
48 #include <sys/param.h>
49 #include <sys/queue.h>
50 #include <sys/types.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
54 #include <sys/module.h>
56 #include <sys/mutex.h>
57 #include <sys/condvar.h>
58 #include <sys/sysctl.h>
60 #include <sys/unistd.h>
61 #include <sys/callout.h>
62 #include <sys/malloc.h>
65 #include <dev/usb/usb.h>
66 #include <dev/usb/usbdi.h>
68 #define USB_DEBUG_VAR xhcidebug
70 #include <dev/usb/usb_core.h>
71 #include <dev/usb/usb_debug.h>
72 #include <dev/usb/usb_busdma.h>
73 #include <dev/usb/usb_process.h>
74 #include <dev/usb/usb_transfer.h>
75 #include <dev/usb/usb_device.h>
76 #include <dev/usb/usb_hub.h>
77 #include <dev/usb/usb_util.h>
79 #include <dev/usb/usb_controller.h>
80 #include <dev/usb/usb_bus.h>
81 #endif /* USB_GLOBAL_INCLUDE_FILE */
83 #include <dev/usb/controller/xhci.h>
84 #include <dev/usb/controller/xhcireg.h>
86 #define XHCI_BUS2SC(bus) \
87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
92 static int xhcistreams;
93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
94 &xhcistreams, 0, "Set to enable streams mode support");
95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
100 static int xhcipolling;
101 static int xhcidma32;
103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
104 &xhcidebug, 0, "Debug level");
105 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
106 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
107 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
108 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
109 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
110 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
111 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
112 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
113 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
114 TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32);
120 #define XHCI_INTR_ENDPT 1
122 struct xhci_std_temp {
123 struct xhci_softc *sc;
124 struct usb_page_cache *pc;
126 struct xhci_td *td_next;
129 uint32_t max_packet_size;
141 uint8_t do_isoc_sync;
144 static void xhci_do_poll(struct usb_bus *);
145 static void xhci_device_done(struct usb_xfer *, usb_error_t);
146 static void xhci_root_intr(struct xhci_softc *);
147 static void xhci_free_device_ext(struct usb_device *);
148 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
149 struct usb_endpoint_descriptor *);
150 static usb_proc_callback_t xhci_configure_msg;
151 static usb_error_t xhci_configure_device(struct usb_device *);
152 static usb_error_t xhci_configure_endpoint(struct usb_device *,
153 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
154 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
156 static usb_error_t xhci_configure_mask(struct usb_device *,
158 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
160 static void xhci_endpoint_doorbell(struct usb_xfer *);
161 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
162 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
163 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
165 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
168 extern struct usb_bus_methods xhci_bus_methods;
172 xhci_dump_trb(struct xhci_trb *trb)
174 DPRINTFN(5, "trb = %p\n", trb);
175 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
176 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
177 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
181 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
183 DPRINTFN(5, "pep = %p\n", pep);
184 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
185 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
186 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
187 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
188 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
189 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
190 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
194 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
196 DPRINTFN(5, "psl = %p\n", psl);
197 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
198 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
199 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
200 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
205 xhci_use_polling(void)
208 return (xhcipolling != 0);
215 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
217 struct xhci_softc *sc = XHCI_BUS2SC(bus);
220 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
221 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
223 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
224 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
226 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
227 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
228 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
233 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
235 if (sc->sc_ctx_is_64_byte) {
237 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
238 /* all contexts are initially 32-bytes */
239 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
240 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
246 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
248 if (sc->sc_ctx_is_64_byte) {
250 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
251 /* all contexts are initially 32-bytes */
252 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
253 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
255 return (le32toh(*ptr));
259 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
261 if (sc->sc_ctx_is_64_byte) {
263 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
264 /* all contexts are initially 32-bytes */
265 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
266 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
273 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
275 if (sc->sc_ctx_is_64_byte) {
277 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
278 /* all contexts are initially 32-bytes */
279 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
280 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
282 return (le64toh(*ptr));
287 xhci_reset_command_queue_locked(struct xhci_softc *sc)
289 struct usb_page_search buf_res;
290 struct xhci_hw_root *phwr;
296 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
297 if (temp & XHCI_CRCR_LO_CRR) {
298 DPRINTF("Command ring running\n");
299 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
302 * Try to abort the last command as per section
303 * 4.6.1.2 "Aborting a Command" of the XHCI
307 /* stop and cancel */
308 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
309 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
311 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
312 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
315 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
317 /* check if command ring is still running */
318 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
319 if (temp & XHCI_CRCR_LO_CRR) {
320 DPRINTF("Comand ring still running\n");
321 return (USB_ERR_IOERROR);
325 /* reset command ring */
326 sc->sc_command_ccs = 1;
327 sc->sc_command_idx = 0;
329 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
331 /* set up command ring control base address */
332 addr = buf_res.physaddr;
333 phwr = buf_res.buffer;
334 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
336 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
338 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
339 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
341 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
343 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
344 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
350 xhci_start_controller(struct xhci_softc *sc)
352 struct usb_page_search buf_res;
353 struct xhci_hw_root *phwr;
354 struct xhci_dev_ctx_addr *pdctxa;
361 sc->sc_event_ccs = 1;
362 sc->sc_event_idx = 0;
363 sc->sc_command_ccs = 1;
364 sc->sc_command_idx = 0;
366 /* Reset controller */
367 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
369 for (i = 0; i != 100; i++) {
370 usb_pause_mtx(NULL, hz / 100);
371 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
372 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
378 device_printf(sc->sc_bus.parent, "Controller "
380 return (USB_ERR_IOERROR);
383 /* set up number of device slots */
384 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
385 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
387 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
389 temp = XREAD4(sc, oper, XHCI_USBSTS);
391 /* clear interrupts */
392 XWRITE4(sc, oper, XHCI_USBSTS, temp);
393 /* disable all device notifications */
394 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
396 /* set up device context base address */
397 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
398 pdctxa = buf_res.buffer;
399 memset(pdctxa, 0, sizeof(*pdctxa));
401 addr = buf_res.physaddr;
402 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
404 /* slot 0 points to the table of scratchpad pointers */
405 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
407 for (i = 0; i != sc->sc_noscratch; i++) {
408 struct usb_page_search buf_scp;
409 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
410 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
413 addr = buf_res.physaddr;
415 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
416 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
417 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
418 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
420 /* set up event table size */
421 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
422 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
424 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
426 /* set up interrupt rate */
427 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
429 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
431 phwr = buf_res.buffer;
432 addr = buf_res.physaddr;
433 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
435 /* reset hardware root structure */
436 memset(phwr, 0, sizeof(*phwr));
438 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
439 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
441 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
443 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
444 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
446 addr = buf_res.physaddr;
448 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
450 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
451 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
453 /* set up interrupter registers */
454 temp = XREAD4(sc, runt, XHCI_IMAN(0));
455 temp |= XHCI_IMAN_INTR_ENA;
456 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
458 /* set up command ring control base address */
459 addr = buf_res.physaddr;
460 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
462 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
464 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
465 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
467 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
469 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
472 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
473 XHCI_CMD_INTE | XHCI_CMD_HSEE);
475 for (i = 0; i != 100; i++) {
476 usb_pause_mtx(NULL, hz / 100);
477 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
482 XWRITE4(sc, oper, XHCI_USBCMD, 0);
483 device_printf(sc->sc_bus.parent, "Run timeout.\n");
484 return (USB_ERR_IOERROR);
487 /* catch any lost interrupts */
488 xhci_do_poll(&sc->sc_bus);
490 if (sc->sc_port_route != NULL) {
491 /* Route all ports to the XHCI by default */
492 sc->sc_port_route(sc->sc_bus.parent,
493 ~xhciroute, xhciroute);
499 xhci_halt_controller(struct xhci_softc *sc)
507 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
508 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
509 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
511 /* Halt controller */
512 XWRITE4(sc, oper, XHCI_USBCMD, 0);
514 for (i = 0; i != 100; i++) {
515 usb_pause_mtx(NULL, hz / 100);
516 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
522 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
523 return (USB_ERR_IOERROR);
529 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
535 /* initialize some bus fields */
536 sc->sc_bus.parent = self;
538 /* set the bus revision */
539 sc->sc_bus.usbrev = USB_REV_3_0;
541 /* set up the bus struct */
542 sc->sc_bus.methods = &xhci_bus_methods;
544 /* set up devices array */
545 sc->sc_bus.devices = sc->sc_devices;
546 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
548 /* set default cycle state in case of early interrupts */
549 sc->sc_event_ccs = 1;
550 sc->sc_command_ccs = 1;
552 /* set up bus space offsets */
554 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
555 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
556 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
558 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
559 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
560 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
562 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
564 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
565 device_printf(sc->sc_bus.parent, "Controller does "
566 "not support 4K page size.\n");
570 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
572 DPRINTF("HCS0 = 0x%08x\n", temp);
574 /* set up context size */
575 if (XHCI_HCS0_CSZ(temp)) {
576 sc->sc_ctx_is_64_byte = 1;
578 sc->sc_ctx_is_64_byte = 0;
582 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
583 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
585 device_printf(self, "%d bytes context size, %d-bit DMA\n",
586 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
588 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
590 /* get number of device slots */
591 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
593 if (sc->sc_noport == 0) {
594 device_printf(sc->sc_bus.parent, "Invalid number "
595 "of ports: %u\n", sc->sc_noport);
599 sc->sc_noport = sc->sc_noport;
600 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
602 DPRINTF("Max slots: %u\n", sc->sc_noslot);
604 if (sc->sc_noslot > XHCI_MAX_DEVICES)
605 sc->sc_noslot = XHCI_MAX_DEVICES;
607 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
609 DPRINTF("HCS2=0x%08x\n", temp);
611 /* get number of scratchpads */
612 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
614 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
615 device_printf(sc->sc_bus.parent, "XHCI request "
616 "too many scratchpads\n");
620 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
622 /* get event table size */
623 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
624 if (sc->sc_erst_max > XHCI_MAX_RSEG)
625 sc->sc_erst_max = XHCI_MAX_RSEG;
627 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
629 /* get maximum exit latency */
630 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
631 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
633 /* Check if we should use the default IMOD value. */
634 if (sc->sc_imod_default == 0)
635 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
637 /* get all DMA memory */
638 if (usb_bus_mem_alloc_all(&sc->sc_bus,
639 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
643 /* set up command queue mutex and condition varible */
644 cv_init(&sc->sc_cmd_cv, "CMDQ");
645 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
647 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
648 sc->sc_config_msg[0].bus = &sc->sc_bus;
649 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
650 sc->sc_config_msg[1].bus = &sc->sc_bus;
656 xhci_uninit(struct xhci_softc *sc)
659 * NOTE: At this point the control transfer process is gone
660 * and "xhci_configure_msg" is no longer called. Consequently
661 * waiting for the configuration messages to complete is not
664 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
666 cv_destroy(&sc->sc_cmd_cv);
667 sx_destroy(&sc->sc_cmd_sx);
671 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
673 struct xhci_softc *sc = XHCI_BUS2SC(bus);
676 case USB_HW_POWER_SUSPEND:
677 DPRINTF("Stopping the XHCI\n");
678 xhci_halt_controller(sc);
680 case USB_HW_POWER_SHUTDOWN:
681 DPRINTF("Stopping the XHCI\n");
682 xhci_halt_controller(sc);
684 case USB_HW_POWER_RESUME:
685 DPRINTF("Starting the XHCI\n");
686 xhci_start_controller(sc);
694 xhci_generic_done_sub(struct usb_xfer *xfer)
697 struct xhci_td *td_alt_next;
701 td = xfer->td_transfer_cache;
702 td_alt_next = td->alt_next;
704 if (xfer->aframes != xfer->nframes)
705 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
709 usb_pc_cpu_invalidate(td->page_cache);
714 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
715 xfer, (unsigned int)xfer->aframes,
716 (unsigned int)xfer->nframes,
717 (unsigned int)len, (unsigned int)td->len,
718 (unsigned int)status);
721 * Verify the status length and
722 * add the length to "frlengths[]":
725 /* should not happen */
726 DPRINTF("Invalid status length, "
727 "0x%04x/0x%04x bytes\n", len, td->len);
728 status = XHCI_TRB_ERROR_LENGTH;
729 } else if (xfer->aframes != xfer->nframes) {
730 xfer->frlengths[xfer->aframes] += td->len - len;
732 /* Check for last transfer */
733 if (((void *)td) == xfer->td_transfer_last) {
737 /* Check for transfer error */
738 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
739 status != XHCI_TRB_ERROR_SUCCESS) {
740 /* the transfer is finished */
744 /* Check for short transfer */
746 if (xfer->flags_int.short_frames_ok ||
747 xfer->flags_int.isochronous_xfr ||
748 xfer->flags_int.control_xfr) {
749 /* follow alt next */
752 /* the transfer is finished */
759 if (td->alt_next != td_alt_next) {
760 /* this USB frame is complete */
765 /* update transfer cache */
767 xfer->td_transfer_cache = td;
769 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
770 (status != XHCI_TRB_ERROR_SHORT_PKT &&
771 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
772 USB_ERR_NORMAL_COMPLETION);
776 xhci_generic_done(struct usb_xfer *xfer)
780 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
781 xfer, xfer->endpoint);
785 xfer->td_transfer_cache = xfer->td_transfer_first;
787 if (xfer->flags_int.control_xfr) {
789 if (xfer->flags_int.control_hdr)
790 err = xhci_generic_done_sub(xfer);
794 if (xfer->td_transfer_cache == NULL)
798 while (xfer->aframes != xfer->nframes) {
800 err = xhci_generic_done_sub(xfer);
803 if (xfer->td_transfer_cache == NULL)
807 if (xfer->flags_int.control_xfr &&
808 !xfer->flags_int.control_act)
809 err = xhci_generic_done_sub(xfer);
811 /* transfer is complete */
812 xhci_device_done(xfer, err);
816 xhci_activate_transfer(struct usb_xfer *xfer)
820 td = xfer->td_transfer_cache;
822 usb_pc_cpu_invalidate(td->page_cache);
824 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
826 /* activate the transfer */
828 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
829 usb_pc_cpu_flush(td->page_cache);
831 xhci_endpoint_doorbell(xfer);
836 xhci_skip_transfer(struct usb_xfer *xfer)
839 struct xhci_td *td_last;
841 td = xfer->td_transfer_cache;
842 td_last = xfer->td_transfer_last;
846 usb_pc_cpu_invalidate(td->page_cache);
848 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
850 usb_pc_cpu_invalidate(td_last->page_cache);
852 /* copy LINK TRB to current waiting location */
854 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
855 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
856 usb_pc_cpu_flush(td->page_cache);
858 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
859 usb_pc_cpu_flush(td->page_cache);
861 xhci_endpoint_doorbell(xfer);
865 /*------------------------------------------------------------------------*
866 * xhci_check_transfer
867 *------------------------------------------------------------------------*/
869 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
871 struct xhci_endpoint_ext *pepext;
884 td_event = le64toh(trb->qwTrb0);
885 temp = le32toh(trb->dwTrb2);
887 remainder = XHCI_TRB_2_REM_GET(temp);
888 status = XHCI_TRB_2_ERROR_GET(temp);
889 stream_id = XHCI_TRB_2_STREAM_GET(temp);
891 temp = le32toh(trb->dwTrb3);
892 epno = XHCI_TRB_3_EP_GET(temp);
893 index = XHCI_TRB_3_SLOT_GET(temp);
895 /* check if error means halted */
896 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
897 status != XHCI_TRB_ERROR_SUCCESS);
899 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
900 index, epno, stream_id, remainder, status);
902 if (index > sc->sc_noslot) {
903 DPRINTF("Invalid slot.\n");
907 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
908 DPRINTF("Invalid endpoint.\n");
912 pepext = &sc->sc_hw.devs[index].endp[epno];
914 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
916 DPRINTF("stream_id=0\n");
917 } else if (stream_id >= XHCI_MAX_STREAMS) {
918 DPRINTF("Invalid stream ID.\n");
922 /* try to find the USB transfer that generated the event */
923 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
924 struct usb_xfer *xfer;
927 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
931 td = xfer->td_transfer_cache;
933 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
935 (long long)td->td_self,
936 (long long)td->td_self + sizeof(td->td_trb));
939 * NOTE: Some XHCI implementations might not trigger
940 * an event on the last LINK TRB so we need to
941 * consider both the last and second last event
942 * address as conditions for a successful transfer.
944 * NOTE: We assume that the XHCI will only trigger one
945 * event per chain of TRBs.
948 offset = td_event - td->td_self;
951 offset < (int64_t)sizeof(td->td_trb)) {
953 usb_pc_cpu_invalidate(td->page_cache);
955 /* compute rest of remainder, if any */
956 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
957 temp = le32toh(td->td_trb[i].dwTrb2);
958 remainder += XHCI_TRB_2_BYTES_GET(temp);
961 DPRINTFN(5, "New remainder: %u\n", remainder);
963 /* clear isochronous transfer errors */
964 if (xfer->flags_int.isochronous_xfr) {
967 status = XHCI_TRB_ERROR_SUCCESS;
972 /* "td->remainder" is verified later */
973 td->remainder = remainder;
976 usb_pc_cpu_flush(td->page_cache);
979 * 1) Last transfer descriptor makes the
982 if (((void *)td) == xfer->td_transfer_last) {
983 DPRINTF("TD is last\n");
984 xhci_generic_done(xfer);
989 * 2) Any kind of error makes the transfer
993 DPRINTF("TD has I/O error\n");
994 xhci_generic_done(xfer);
999 * 3) If there is no alternate next transfer,
1000 * a short packet also makes the transfer done
1002 if (td->remainder > 0) {
1003 if (td->alt_next == NULL) {
1005 "short TD has no alternate next\n");
1006 xhci_generic_done(xfer);
1009 DPRINTF("TD has short pkt\n");
1010 if (xfer->flags_int.short_frames_ok ||
1011 xfer->flags_int.isochronous_xfr ||
1012 xfer->flags_int.control_xfr) {
1013 /* follow the alt next */
1014 xfer->td_transfer_cache = td->alt_next;
1015 xhci_activate_transfer(xfer);
1018 xhci_skip_transfer(xfer);
1019 xhci_generic_done(xfer);
1024 * 4) Transfer complete - go to next TD
1026 DPRINTF("Following next TD\n");
1027 xfer->td_transfer_cache = td->obj_next;
1028 xhci_activate_transfer(xfer);
1029 break; /* there should only be one match */
1035 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1037 if (sc->sc_cmd_addr == trb->qwTrb0) {
1038 DPRINTF("Received command event\n");
1039 sc->sc_cmd_result[0] = trb->dwTrb2;
1040 sc->sc_cmd_result[1] = trb->dwTrb3;
1041 cv_signal(&sc->sc_cmd_cv);
1042 return (1); /* command match */
1048 xhci_interrupt_poll(struct xhci_softc *sc)
1050 struct usb_page_search buf_res;
1051 struct xhci_hw_root *phwr;
1061 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1063 phwr = buf_res.buffer;
1065 /* Receive any events */
1067 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1069 i = sc->sc_event_idx;
1070 j = sc->sc_event_ccs;
1075 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1077 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1082 event = XHCI_TRB_3_TYPE_GET(temp);
1084 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1085 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1086 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1087 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1090 case XHCI_TRB_EVENT_TRANSFER:
1091 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1093 case XHCI_TRB_EVENT_CMD_COMPLETE:
1094 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1097 DPRINTF("Unhandled event = %u\n", event);
1103 if (i == XHCI_MAX_EVENTS) {
1107 /* check for timeout */
1113 sc->sc_event_idx = i;
1114 sc->sc_event_ccs = j;
1117 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1118 * latched. That means to activate the register we need to
1119 * write both the low and high double word of the 64-bit
1123 addr = buf_res.physaddr;
1124 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1126 /* try to clear busy bit */
1127 addr |= XHCI_ERDP_LO_BUSY;
1129 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1130 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1136 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1137 uint16_t timeout_ms)
1139 struct usb_page_search buf_res;
1140 struct xhci_hw_root *phwr;
1145 uint8_t timeout = 0;
1148 XHCI_CMD_ASSERT_LOCKED(sc);
1150 /* get hardware root structure */
1152 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1154 phwr = buf_res.buffer;
1158 USB_BUS_LOCK(&sc->sc_bus);
1160 i = sc->sc_command_idx;
1161 j = sc->sc_command_ccs;
1163 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1164 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1165 (long long)le64toh(trb->qwTrb0),
1166 (long)le32toh(trb->dwTrb2),
1167 (long)le32toh(trb->dwTrb3));
1169 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1170 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1172 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1177 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1179 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1181 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1183 phwr->hwr_commands[i].dwTrb3 = temp;
1185 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1187 addr = buf_res.physaddr;
1188 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1190 sc->sc_cmd_addr = htole64(addr);
1194 if (i == (XHCI_MAX_COMMANDS - 1)) {
1197 temp = htole32(XHCI_TRB_3_TC_BIT |
1198 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1199 XHCI_TRB_3_CYCLE_BIT);
1201 temp = htole32(XHCI_TRB_3_TC_BIT |
1202 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1205 phwr->hwr_commands[i].dwTrb3 = temp;
1207 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1213 sc->sc_command_idx = i;
1214 sc->sc_command_ccs = j;
1216 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1218 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1219 USB_MS_TO_TICKS(timeout_ms));
1222 * In some error cases event interrupts are not generated.
1223 * Poll one time to see if the command has completed.
1225 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1226 DPRINTF("Command was completed when polling\n");
1230 DPRINTF("Command timeout!\n");
1232 * After some weeks of continuous operation, it has
1233 * been observed that the ASMedia Technology, ASM1042
1234 * SuperSpeed USB Host Controller can suddenly stop
1235 * accepting commands via the command queue. Try to
1236 * first reset the command queue. If that fails do a
1237 * host controller reset.
1240 xhci_reset_command_queue_locked(sc) == 0) {
1241 temp = le32toh(trb->dwTrb3);
1244 * Avoid infinite XHCI reset loops if the set
1245 * address command fails to respond due to a
1246 * non-enumerating device:
1248 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1249 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1250 DPRINTF("Set address timeout\n");
1256 DPRINTF("Controller reset!\n");
1257 usb_bus_reset_async_locked(&sc->sc_bus);
1259 err = USB_ERR_TIMEOUT;
1263 temp = le32toh(sc->sc_cmd_result[0]);
1264 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1265 err = USB_ERR_IOERROR;
1267 trb->dwTrb2 = sc->sc_cmd_result[0];
1268 trb->dwTrb3 = sc->sc_cmd_result[1];
1271 USB_BUS_UNLOCK(&sc->sc_bus);
1278 xhci_cmd_nop(struct xhci_softc *sc)
1280 struct xhci_trb trb;
1287 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1289 trb.dwTrb3 = htole32(temp);
1291 return (xhci_do_command(sc, &trb, 100 /* ms */));
1296 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1298 struct xhci_trb trb;
1306 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1308 err = xhci_do_command(sc, &trb, 100 /* ms */);
1312 temp = le32toh(trb.dwTrb3);
1314 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1321 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1323 struct xhci_trb trb;
1330 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1331 XHCI_TRB_3_SLOT_SET(slot_id);
1333 trb.dwTrb3 = htole32(temp);
1335 return (xhci_do_command(sc, &trb, 100 /* ms */));
1339 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1340 uint8_t bsr, uint8_t slot_id)
1342 struct xhci_trb trb;
1347 trb.qwTrb0 = htole64(input_ctx);
1349 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1350 XHCI_TRB_3_SLOT_SET(slot_id);
1353 temp |= XHCI_TRB_3_BSR_BIT;
1355 trb.dwTrb3 = htole32(temp);
1357 return (xhci_do_command(sc, &trb, 500 /* ms */));
1361 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1363 struct usb_page_search buf_inp;
1364 struct usb_page_search buf_dev;
1365 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1366 struct xhci_hw_dev *hdev;
1367 struct xhci_dev_ctx *pdev;
1368 struct xhci_endpoint_ext *pepext;
1374 /* the root HUB case is not handled here */
1375 if (udev->parent_hub == NULL)
1376 return (USB_ERR_INVAL);
1378 index = udev->controller_slot_id;
1380 hdev = &sc->sc_hw.devs[index];
1387 switch (hdev->state) {
1388 case XHCI_ST_DEFAULT:
1389 case XHCI_ST_ENABLED:
1391 hdev->state = XHCI_ST_ENABLED;
1393 /* set configure mask to slot and EP0 */
1394 xhci_configure_mask(udev, 3, 0);
1396 /* configure input slot context structure */
1397 err = xhci_configure_device(udev);
1400 DPRINTF("Could not configure device\n");
1404 /* configure input endpoint context structure */
1405 switch (udev->speed) {
1407 case USB_SPEED_FULL:
1410 case USB_SPEED_HIGH:
1418 pepext = xhci_get_endpoint_ext(udev,
1419 &udev->ctrl_ep_desc);
1421 /* ensure the control endpoint is setup again */
1422 USB_BUS_LOCK(udev->bus);
1423 pepext->trb_halted = 1;
1424 pepext->trb_running = 0;
1425 USB_BUS_UNLOCK(udev->bus);
1427 err = xhci_configure_endpoint(udev,
1428 &udev->ctrl_ep_desc, pepext,
1429 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1432 DPRINTF("Could not configure default endpoint\n");
1436 /* execute set address command */
1437 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1439 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1440 (address == 0), index);
1443 temp = le32toh(sc->sc_cmd_result[0]);
1444 if (address == 0 && sc->sc_port_route != NULL &&
1445 XHCI_TRB_2_ERROR_GET(temp) ==
1446 XHCI_TRB_ERROR_PARAMETER) {
1447 /* LynxPoint XHCI - ports are not switchable */
1448 /* Un-route all ports from the XHCI */
1449 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1451 DPRINTF("Could not set address "
1452 "for slot %u.\n", index);
1457 /* update device address to new value */
1459 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1460 pdev = buf_dev.buffer;
1461 usb_pc_cpu_invalidate(&hdev->device_pc);
1463 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1464 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1466 /* update device state to new value */
1469 hdev->state = XHCI_ST_ADDRESSED;
1471 hdev->state = XHCI_ST_DEFAULT;
1475 DPRINTF("Wrong state for set address.\n");
1476 err = USB_ERR_IOERROR;
1479 XHCI_CMD_UNLOCK(sc);
1488 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1489 uint8_t deconfigure, uint8_t slot_id)
1491 struct xhci_trb trb;
1496 trb.qwTrb0 = htole64(input_ctx);
1498 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1499 XHCI_TRB_3_SLOT_SET(slot_id);
1502 temp |= XHCI_TRB_3_DCEP_BIT;
1504 trb.dwTrb3 = htole32(temp);
1506 return (xhci_do_command(sc, &trb, 100 /* ms */));
1510 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1513 struct xhci_trb trb;
1518 trb.qwTrb0 = htole64(input_ctx);
1520 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1521 XHCI_TRB_3_SLOT_SET(slot_id);
1522 trb.dwTrb3 = htole32(temp);
1524 return (xhci_do_command(sc, &trb, 100 /* ms */));
1528 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1529 uint8_t ep_id, uint8_t slot_id)
1531 struct xhci_trb trb;
1538 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1539 XHCI_TRB_3_SLOT_SET(slot_id) |
1540 XHCI_TRB_3_EP_SET(ep_id);
1543 temp |= XHCI_TRB_3_PRSV_BIT;
1545 trb.dwTrb3 = htole32(temp);
1547 return (xhci_do_command(sc, &trb, 100 /* ms */));
1551 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1552 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1554 struct xhci_trb trb;
1559 trb.qwTrb0 = htole64(dequeue_ptr);
1561 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1562 trb.dwTrb2 = htole32(temp);
1564 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1565 XHCI_TRB_3_SLOT_SET(slot_id) |
1566 XHCI_TRB_3_EP_SET(ep_id);
1567 trb.dwTrb3 = htole32(temp);
1569 return (xhci_do_command(sc, &trb, 100 /* ms */));
1573 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1574 uint8_t ep_id, uint8_t slot_id)
1576 struct xhci_trb trb;
1583 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1584 XHCI_TRB_3_SLOT_SET(slot_id) |
1585 XHCI_TRB_3_EP_SET(ep_id);
1588 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1590 trb.dwTrb3 = htole32(temp);
1592 return (xhci_do_command(sc, &trb, 100 /* ms */));
1596 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1598 struct xhci_trb trb;
1605 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1606 XHCI_TRB_3_SLOT_SET(slot_id);
1608 trb.dwTrb3 = htole32(temp);
1610 return (xhci_do_command(sc, &trb, 100 /* ms */));
1613 /*------------------------------------------------------------------------*
1614 * xhci_interrupt - XHCI interrupt handler
1615 *------------------------------------------------------------------------*/
1617 xhci_interrupt(struct xhci_softc *sc)
1622 USB_BUS_LOCK(&sc->sc_bus);
1624 status = XREAD4(sc, oper, XHCI_USBSTS);
1626 /* acknowledge interrupts, if any */
1628 XWRITE4(sc, oper, XHCI_USBSTS, status);
1629 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1632 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1634 /* force clearing of pending interrupts */
1635 if (temp & XHCI_IMAN_INTR_PEND)
1636 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1638 /* check for event(s) */
1639 xhci_interrupt_poll(sc);
1641 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1642 XHCI_STS_HSE | XHCI_STS_HCE)) {
1644 if (status & XHCI_STS_PCD) {
1648 if (status & XHCI_STS_HCH) {
1649 printf("%s: host controller halted\n",
1653 if (status & XHCI_STS_HSE) {
1654 printf("%s: host system error\n",
1658 if (status & XHCI_STS_HCE) {
1659 printf("%s: host controller error\n",
1663 USB_BUS_UNLOCK(&sc->sc_bus);
1666 /*------------------------------------------------------------------------*
1667 * xhci_timeout - XHCI timeout handler
1668 *------------------------------------------------------------------------*/
1670 xhci_timeout(void *arg)
1672 struct usb_xfer *xfer = arg;
1674 DPRINTF("xfer=%p\n", xfer);
1676 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1678 /* transfer is transferred */
1679 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1683 xhci_do_poll(struct usb_bus *bus)
1685 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1687 USB_BUS_LOCK(&sc->sc_bus);
1688 xhci_interrupt_poll(sc);
1689 USB_BUS_UNLOCK(&sc->sc_bus);
1693 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1695 struct usb_page_search buf_res;
1697 struct xhci_td *td_next;
1698 struct xhci_td *td_alt_next;
1699 struct xhci_td *td_first;
1700 uint32_t buf_offset;
1705 uint8_t shortpkt_old;
1711 shortpkt_old = temp->shortpkt;
1712 len_old = temp->len;
1719 td_next = td_first = temp->td_next;
1723 if (temp->len == 0) {
1728 /* send a Zero Length Packet, ZLP, last */
1735 average = temp->average;
1737 if (temp->len < average) {
1738 if (temp->len % temp->max_packet_size) {
1741 average = temp->len;
1745 if (td_next == NULL)
1746 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1751 td_next = td->obj_next;
1753 /* check if we are pre-computing */
1757 /* update remaining length */
1759 temp->len -= average;
1763 /* fill out current TD */
1769 /* update remaining length */
1771 temp->len -= average;
1773 /* reset TRB index */
1777 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1778 /* immediate data */
1783 td->td_trb[0].qwTrb0 = 0;
1785 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1786 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1789 dword = XHCI_TRB_2_BYTES_SET(8) |
1790 XHCI_TRB_2_TDSZ_SET(0) |
1791 XHCI_TRB_2_IRQ_SET(0);
1793 td->td_trb[0].dwTrb2 = htole32(dword);
1795 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1796 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1799 if (td->td_trb[0].qwTrb0 &
1800 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1801 if (td->td_trb[0].qwTrb0 &
1802 htole64(XHCI_TRB_0_DIR_IN_MASK))
1803 dword |= XHCI_TRB_3_TRT_IN;
1805 dword |= XHCI_TRB_3_TRT_OUT;
1808 td->td_trb[0].dwTrb3 = htole32(dword);
1810 xhci_dump_trb(&td->td_trb[x]);
1818 /* fill out buffer pointers */
1821 memset(&buf_res, 0, sizeof(buf_res));
1823 usbd_get_page(temp->pc, temp->offset +
1824 buf_offset, &buf_res);
1826 /* get length to end of page */
1827 if (buf_res.length > average)
1828 buf_res.length = average;
1830 /* check for maximum length */
1831 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1832 buf_res.length = XHCI_TD_PAGE_SIZE;
1834 npkt_off += buf_res.length;
1838 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1839 temp->max_packet_size;
1846 /* fill out TRB's */
1847 td->td_trb[x].qwTrb0 =
1848 htole64((uint64_t)buf_res.physaddr);
1851 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1852 XHCI_TRB_2_TDSZ_SET(npkt) |
1853 XHCI_TRB_2_IRQ_SET(0);
1855 td->td_trb[x].dwTrb2 = htole32(dword);
1857 switch (temp->trb_type) {
1858 case XHCI_TRB_TYPE_ISOCH:
1859 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1860 XHCI_TRB_3_TBC_SET(temp->tbc) |
1861 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1862 if (td != td_first) {
1863 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1864 } else if (temp->do_isoc_sync != 0) {
1865 temp->do_isoc_sync = 0;
1866 /* wait until "isoc_frame" */
1867 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1868 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1870 /* start data transfer at next interval */
1871 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1872 XHCI_TRB_3_ISO_SIA_BIT;
1874 if (temp->direction == UE_DIR_IN)
1875 dword |= XHCI_TRB_3_ISP_BIT;
1877 case XHCI_TRB_TYPE_DATA_STAGE:
1878 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1879 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1880 if (temp->direction == UE_DIR_IN)
1881 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1883 * Section 3.2.9 in the XHCI
1884 * specification about control
1885 * transfers says that we should use a
1886 * normal-TRB if there are more TRBs
1887 * extending the data-stage
1888 * TRB. Update the "trb_type".
1890 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1892 case XHCI_TRB_TYPE_STATUS_STAGE:
1893 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1894 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1895 if (temp->direction == UE_DIR_IN)
1896 dword |= XHCI_TRB_3_DIR_IN;
1898 default: /* XHCI_TRB_TYPE_NORMAL */
1899 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1900 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1901 if (temp->direction == UE_DIR_IN)
1902 dword |= XHCI_TRB_3_ISP_BIT;
1905 td->td_trb[x].dwTrb3 = htole32(dword);
1907 average -= buf_res.length;
1908 buf_offset += buf_res.length;
1910 xhci_dump_trb(&td->td_trb[x]);
1914 } while (average != 0);
1916 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1918 /* store number of data TRB's */
1922 DPRINTF("NTRB=%u\n", x);
1924 /* fill out link TRB */
1926 if (td_next != NULL) {
1927 /* link the current TD with the next one */
1928 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1929 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1931 /* this field will get updated later */
1932 DPRINTF("NOLINK\n");
1935 dword = XHCI_TRB_2_IRQ_SET(0);
1937 td->td_trb[x].dwTrb2 = htole32(dword);
1939 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1940 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1942 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1943 * frame only receives a single short packet event
1944 * by setting the CHAIN bit in the LINK field. In
1945 * addition some XHCI controllers have problems
1946 * sending a ZLP unless the CHAIN-BIT is set in
1949 XHCI_TRB_3_CHAIN_BIT;
1951 td->td_trb[x].dwTrb3 = htole32(dword);
1953 td->alt_next = td_alt_next;
1955 xhci_dump_trb(&td->td_trb[x]);
1957 usb_pc_cpu_flush(td->page_cache);
1963 /* set up alt next pointer, if any */
1964 if (temp->last_frame) {
1967 /* we use this field internally */
1968 td_alt_next = td_next;
1972 temp->shortpkt = shortpkt_old;
1973 temp->len = len_old;
1978 * Remove cycle bit from the first TRB if we are
1981 if (temp->step_td != 0) {
1982 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1983 usb_pc_cpu_flush(td_first->page_cache);
1986 /* clear TD SIZE to zero, hence this is the last TRB */
1987 /* remove chain bit because this is the last data TRB in the chain */
1988 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1989 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1990 /* remove CHAIN-BIT from last LINK TRB */
1991 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1993 usb_pc_cpu_flush(td->page_cache);
1996 temp->td_next = td_next;
2000 xhci_setup_generic_chain(struct usb_xfer *xfer)
2002 struct xhci_std_temp temp;
2008 temp.do_isoc_sync = 0;
2012 temp.average = xfer->max_hc_frame_size;
2013 temp.max_packet_size = xfer->max_packet_size;
2014 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2016 temp.last_frame = 0;
2018 temp.multishort = xfer->flags_int.isochronous_xfr ||
2019 xfer->flags_int.control_xfr ||
2020 xfer->flags_int.short_frames_ok;
2022 /* toggle the DMA set we are using */
2023 xfer->flags_int.curr_dma_set ^= 1;
2025 /* get next DMA set */
2026 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2031 xfer->td_transfer_first = td;
2032 xfer->td_transfer_cache = td;
2034 if (xfer->flags_int.isochronous_xfr) {
2037 /* compute multiplier for ISOCHRONOUS transfers */
2038 mult = xfer->endpoint->ecomp ?
2039 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2041 /* check for USB 2.0 multiplier */
2043 mult = (xfer->endpoint->edesc->
2044 wMaxPacketSize[1] >> 3) & 3;
2052 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2054 DPRINTF("MFINDEX=0x%08x\n", x);
2056 switch (usbd_get_speed(xfer->xroot->udev)) {
2057 case USB_SPEED_FULL:
2059 temp.isoc_delta = 8; /* 1ms */
2060 x += temp.isoc_delta - 1;
2061 x &= ~(temp.isoc_delta - 1);
2064 shift = usbd_xfer_get_fps_shift(xfer);
2065 temp.isoc_delta = 1U << shift;
2066 x += temp.isoc_delta - 1;
2067 x &= ~(temp.isoc_delta - 1);
2068 /* simple frame load balancing */
2069 x += xfer->endpoint->usb_uframe;
2073 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2075 if ((xfer->endpoint->is_synced == 0) ||
2076 (y < (xfer->nframes << shift)) ||
2077 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2079 * If there is data underflow or the pipe
2080 * queue is empty we schedule the transfer a
2081 * few frames ahead of the current frame
2082 * position. Else two isochronous transfers
2085 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2086 xfer->endpoint->is_synced = 1;
2087 temp.do_isoc_sync = 1;
2089 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2092 /* compute isochronous completion time */
2094 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2096 xfer->isoc_time_complete =
2097 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2098 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2101 temp.isoc_frame = xfer->endpoint->isoc_next;
2102 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2104 xfer->endpoint->isoc_next += xfer->nframes << shift;
2106 } else if (xfer->flags_int.control_xfr) {
2108 /* check if we should prepend a setup message */
2110 if (xfer->flags_int.control_hdr) {
2112 temp.len = xfer->frlengths[0];
2113 temp.pc = xfer->frbuffers + 0;
2114 temp.shortpkt = temp.len ? 1 : 0;
2115 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2118 /* check for last frame */
2119 if (xfer->nframes == 1) {
2120 /* no STATUS stage yet, SETUP is last */
2121 if (xfer->flags_int.control_act)
2122 temp.last_frame = 1;
2125 xhci_setup_generic_chain_sub(&temp);
2129 temp.isoc_delta = 0;
2130 temp.isoc_frame = 0;
2131 temp.trb_type = xfer->flags_int.control_did_data ?
2132 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2136 temp.isoc_delta = 0;
2137 temp.isoc_frame = 0;
2138 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2141 if (x != xfer->nframes) {
2142 /* set up page_cache pointer */
2143 temp.pc = xfer->frbuffers + x;
2144 /* set endpoint direction */
2145 temp.direction = UE_GET_DIR(xfer->endpointno);
2148 while (x != xfer->nframes) {
2150 /* DATA0 / DATA1 message */
2152 temp.len = xfer->frlengths[x];
2153 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2154 x != 0 && temp.multishort == 0);
2158 if (x == xfer->nframes) {
2159 if (xfer->flags_int.control_xfr) {
2160 /* no STATUS stage yet, DATA is last */
2161 if (xfer->flags_int.control_act)
2162 temp.last_frame = 1;
2164 temp.last_frame = 1;
2167 if (temp.len == 0) {
2169 /* make sure that we send an USB packet */
2174 temp.tlbpc = mult - 1;
2176 } else if (xfer->flags_int.isochronous_xfr) {
2181 * Isochronous transfers don't have short
2182 * packet termination:
2187 /* isochronous transfers have a transfer limit */
2189 if (temp.len > xfer->max_frame_size)
2190 temp.len = xfer->max_frame_size;
2192 /* compute TD packet count */
2193 tdpc = (temp.len + xfer->max_packet_size - 1) /
2194 xfer->max_packet_size;
2196 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2197 temp.tlbpc = (tdpc % mult);
2199 if (temp.tlbpc == 0)
2200 temp.tlbpc = mult - 1;
2205 /* regular data transfer */
2207 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2210 xhci_setup_generic_chain_sub(&temp);
2212 if (xfer->flags_int.isochronous_xfr) {
2213 temp.offset += xfer->frlengths[x - 1];
2214 temp.isoc_frame += temp.isoc_delta;
2216 /* get next Page Cache pointer */
2217 temp.pc = xfer->frbuffers + x;
2221 /* check if we should append a status stage */
2223 if (xfer->flags_int.control_xfr &&
2224 !xfer->flags_int.control_act) {
2227 * Send a DATA1 message and invert the current
2228 * endpoint direction.
2230 temp.step_td = (xfer->nframes != 0);
2231 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2235 temp.last_frame = 1;
2236 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2238 xhci_setup_generic_chain_sub(&temp);
2243 /* must have at least one frame! */
2245 xfer->td_transfer_last = td;
2247 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2251 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2253 struct usb_page_search buf_res;
2254 struct xhci_dev_ctx_addr *pdctxa;
2256 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2258 pdctxa = buf_res.buffer;
2260 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2262 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2264 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2268 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2270 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2271 struct usb_page_search buf_inp;
2272 struct xhci_input_dev_ctx *pinp;
2277 index = udev->controller_slot_id;
2279 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2281 pinp = buf_inp.buffer;
2284 mask &= XHCI_INCTX_NON_CTRL_MASK;
2285 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2286 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2289 * Some hardware requires that we drop the endpoint
2290 * context before adding it again:
2292 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2293 mask & XHCI_INCTX_NON_CTRL_MASK);
2295 /* Add new endpoint context */
2296 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2298 /* find most significant set bit */
2299 for (x = 31; x != 1; x--) {
2300 if (mask & (1 << x))
2307 /* figure out the maximum number of contexts */
2308 if (x > sc->sc_hw.devs[index].context_num)
2309 sc->sc_hw.devs[index].context_num = x;
2311 x = sc->sc_hw.devs[index].context_num;
2313 /* update number of contexts */
2314 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2315 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2316 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2317 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2319 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2324 xhci_configure_endpoint(struct usb_device *udev,
2325 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2326 uint16_t interval, uint8_t max_packet_count,
2327 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2328 uint16_t max_frame_size, uint8_t ep_mode)
2330 struct usb_page_search buf_inp;
2331 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2332 struct xhci_input_dev_ctx *pinp;
2333 uint64_t ring_addr = pepext->physaddr;
2339 index = udev->controller_slot_id;
2341 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2343 pinp = buf_inp.buffer;
2345 epno = edesc->bEndpointAddress;
2346 type = edesc->bmAttributes & UE_XFERTYPE;
2348 if (type == UE_CONTROL)
2351 epno = XHCI_EPNO2EPID(epno);
2354 return (USB_ERR_NO_PIPE); /* invalid */
2356 if (max_packet_count == 0)
2357 return (USB_ERR_BAD_BUFSIZE);
2362 return (USB_ERR_BAD_BUFSIZE);
2364 /* store endpoint mode */
2365 pepext->trb_ep_mode = ep_mode;
2366 /* store bMaxPacketSize for control endpoints */
2367 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2368 usb_pc_cpu_flush(pepext->page_cache);
2370 if (ep_mode == USB_EP_MODE_STREAMS) {
2371 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2372 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2373 XHCI_EPCTX_0_LSA_SET(1);
2375 ring_addr += sizeof(struct xhci_trb) *
2376 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2378 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2379 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2380 XHCI_EPCTX_0_LSA_SET(0);
2382 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2385 switch (udev->speed) {
2386 case USB_SPEED_FULL:
2399 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2401 case UE_ISOCHRONOUS:
2402 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2404 switch (udev->speed) {
2405 case USB_SPEED_SUPER:
2408 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2409 max_packet_count /= mult;
2419 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2422 XHCI_EPCTX_1_HID_SET(0) |
2423 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2424 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2427 * Always enable the "three strikes and you are gone" feature
2428 * except for ISOCHRONOUS endpoints. This is suggested by
2429 * section 4.3.3 in the XHCI specification about device slot
2432 if (type != UE_ISOCHRONOUS)
2433 temp |= XHCI_EPCTX_1_CERR_SET(3);
2437 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2439 case UE_ISOCHRONOUS:
2440 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2443 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2446 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2450 /* check for IN direction */
2452 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2454 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2455 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2457 switch (edesc->bmAttributes & UE_XFERTYPE) {
2459 case UE_ISOCHRONOUS:
2460 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2461 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2465 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2468 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2472 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2475 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2477 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2479 return (0); /* success */
2483 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2485 struct xhci_endpoint_ext *pepext;
2486 struct usb_endpoint_ss_comp_descriptor *ecomp;
2489 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2490 xfer->endpoint->edesc);
2492 ecomp = xfer->endpoint->ecomp;
2494 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2497 /* halt any transfers */
2498 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2500 /* compute start of TRB ring for stream "x" */
2501 temp = pepext->physaddr +
2502 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2503 XHCI_SCTX_0_SCT_SEC_TR_RING;
2505 /* make tree structure */
2506 pepext->trb[(XHCI_MAX_TRANSFERS *
2507 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2509 /* reserved fields */
2510 pepext->trb[(XHCI_MAX_TRANSFERS *
2511 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2512 pepext->trb[(XHCI_MAX_TRANSFERS *
2513 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2515 usb_pc_cpu_flush(pepext->page_cache);
2517 return (xhci_configure_endpoint(xfer->xroot->udev,
2518 xfer->endpoint->edesc, pepext,
2519 xfer->interval, xfer->max_packet_count,
2520 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2521 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2522 xfer->max_frame_size, xfer->endpoint->ep_mode));
2526 xhci_configure_device(struct usb_device *udev)
2528 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2529 struct usb_page_search buf_inp;
2530 struct usb_page_cache *pcinp;
2531 struct xhci_input_dev_ctx *pinp;
2532 struct usb_device *hubdev;
2540 index = udev->controller_slot_id;
2542 DPRINTF("index=%u\n", index);
2544 pcinp = &sc->sc_hw.devs[index].input_pc;
2546 usbd_get_page(pcinp, 0, &buf_inp);
2548 pinp = buf_inp.buffer;
2553 /* figure out route string and root HUB port number */
2555 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2557 if (hubdev->parent_hub == NULL)
2560 depth = hubdev->parent_hub->depth;
2563 * NOTE: HS/FS/LS devices and the SS root HUB can have
2564 * more than 15 ports
2567 rh_port = hubdev->port_no;
2576 route |= rh_port << (4 * (depth - 1));
2579 DPRINTF("Route=0x%08x\n", route);
2581 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2582 XHCI_SCTX_0_CTX_NUM_SET(
2583 sc->sc_hw.devs[index].context_num + 1);
2585 switch (udev->speed) {
2587 temp |= XHCI_SCTX_0_SPEED_SET(2);
2588 if (udev->parent_hs_hub != NULL &&
2589 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2591 DPRINTF("Device inherits MTT\n");
2592 temp |= XHCI_SCTX_0_MTT_SET(1);
2595 case USB_SPEED_HIGH:
2596 temp |= XHCI_SCTX_0_SPEED_SET(3);
2597 if (sc->sc_hw.devs[index].nports != 0 &&
2598 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2599 DPRINTF("HUB supports MTT\n");
2600 temp |= XHCI_SCTX_0_MTT_SET(1);
2603 case USB_SPEED_FULL:
2604 temp |= XHCI_SCTX_0_SPEED_SET(1);
2605 if (udev->parent_hs_hub != NULL &&
2606 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2608 DPRINTF("Device inherits MTT\n");
2609 temp |= XHCI_SCTX_0_MTT_SET(1);
2613 temp |= XHCI_SCTX_0_SPEED_SET(4);
2617 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2618 (udev->speed == USB_SPEED_SUPER ||
2619 udev->speed == USB_SPEED_HIGH);
2622 temp |= XHCI_SCTX_0_HUB_SET(1);
2624 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2626 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2629 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2630 sc->sc_hw.devs[index].nports);
2633 switch (udev->speed) {
2634 case USB_SPEED_SUPER:
2635 switch (sc->sc_hw.devs[index].state) {
2636 case XHCI_ST_ADDRESSED:
2637 case XHCI_ST_CONFIGURED:
2638 /* enable power save */
2639 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2642 /* disable power save */
2650 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2652 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2655 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2656 sc->sc_hw.devs[index].tt);
2659 hubdev = udev->parent_hs_hub;
2661 /* check if we should activate the transaction translator */
2662 switch (udev->speed) {
2663 case USB_SPEED_FULL:
2665 if (hubdev != NULL) {
2666 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2667 hubdev->controller_slot_id);
2668 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2676 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2679 * These fields should be initialized to zero, according to
2680 * XHCI section 6.2.2 - slot context:
2682 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2683 XHCI_SCTX_3_SLOT_STATE_SET(0);
2685 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2688 xhci_dump_device(sc, &pinp->ctx_slot);
2690 usb_pc_cpu_flush(pcinp);
2692 return (0); /* success */
2696 xhci_alloc_device_ext(struct usb_device *udev)
2698 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2699 struct usb_page_search buf_dev;
2700 struct usb_page_search buf_ep;
2701 struct xhci_trb *trb;
2702 struct usb_page_cache *pc;
2703 struct usb_page *pg;
2708 index = udev->controller_slot_id;
2710 pc = &sc->sc_hw.devs[index].device_pc;
2711 pg = &sc->sc_hw.devs[index].device_pg;
2713 /* need to initialize the page cache */
2714 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2716 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2717 (2 * sizeof(struct xhci_dev_ctx)) :
2718 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2721 usbd_get_page(pc, 0, &buf_dev);
2723 pc = &sc->sc_hw.devs[index].input_pc;
2724 pg = &sc->sc_hw.devs[index].input_pg;
2726 /* need to initialize the page cache */
2727 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2729 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2730 (2 * sizeof(struct xhci_input_dev_ctx)) :
2731 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2735 /* initialize all endpoint LINK TRBs */
2737 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2739 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2740 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2742 /* need to initialize the page cache */
2743 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2745 if (usb_pc_alloc_mem(pc, pg,
2746 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2750 /* lookup endpoint TRB ring */
2751 usbd_get_page(pc, 0, &buf_ep);
2753 /* get TRB pointer */
2754 trb = buf_ep.buffer;
2755 trb += XHCI_MAX_TRANSFERS - 1;
2757 /* get TRB start address */
2758 addr = buf_ep.physaddr;
2760 /* create LINK TRB */
2761 trb->qwTrb0 = htole64(addr);
2762 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2763 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2764 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2766 usb_pc_cpu_flush(pc);
2769 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2774 xhci_free_device_ext(udev);
2776 return (USB_ERR_NOMEM);
2780 xhci_free_device_ext(struct usb_device *udev)
2782 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2786 index = udev->controller_slot_id;
2787 xhci_set_slot_pointer(sc, index, 0);
2789 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2790 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2791 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2792 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2795 static struct xhci_endpoint_ext *
2796 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2798 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2799 struct xhci_endpoint_ext *pepext;
2800 struct usb_page_cache *pc;
2801 struct usb_page_search buf_ep;
2805 epno = edesc->bEndpointAddress;
2806 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2809 epno = XHCI_EPNO2EPID(epno);
2811 index = udev->controller_slot_id;
2813 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2815 usbd_get_page(pc, 0, &buf_ep);
2817 pepext = &sc->sc_hw.devs[index].endp[epno];
2818 pepext->page_cache = pc;
2819 pepext->trb = buf_ep.buffer;
2820 pepext->physaddr = buf_ep.physaddr;
2826 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2828 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2832 epno = xfer->endpointno;
2833 if (xfer->flags_int.control_xfr)
2836 epno = XHCI_EPNO2EPID(epno);
2837 index = xfer->xroot->udev->controller_slot_id;
2839 if (xfer->xroot->udev->flags.self_suspended == 0) {
2840 XWRITE4(sc, door, XHCI_DOORBELL(index),
2841 epno | XHCI_DB_SID_SET(xfer->stream_id));
2846 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2848 struct xhci_endpoint_ext *pepext;
2850 if (xfer->flags_int.bandwidth_reclaimed) {
2851 xfer->flags_int.bandwidth_reclaimed = 0;
2853 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2854 xfer->endpoint->edesc);
2856 pepext->trb_used[xfer->stream_id]--;
2858 pepext->xfer[xfer->qh_pos] = NULL;
2860 if (error && pepext->trb_running != 0) {
2861 pepext->trb_halted = 1;
2862 pepext->trb_running = 0;
2868 xhci_transfer_insert(struct usb_xfer *xfer)
2870 struct xhci_td *td_first;
2871 struct xhci_td *td_last;
2872 struct xhci_trb *trb_link;
2873 struct xhci_endpoint_ext *pepext;
2882 id = xfer->stream_id;
2884 /* check if already inserted */
2885 if (xfer->flags_int.bandwidth_reclaimed) {
2886 DPRINTFN(8, "Already in schedule\n");
2890 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2891 xfer->endpoint->edesc);
2893 td_first = xfer->td_transfer_first;
2894 td_last = xfer->td_transfer_last;
2895 addr = pepext->physaddr;
2897 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2900 /* single buffered */
2904 /* multi buffered */
2905 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2909 if (pepext->trb_used[id] >= trb_limit) {
2910 DPRINTFN(8, "Too many TDs queued.\n");
2911 return (USB_ERR_NOMEM);
2914 /* check if bMaxPacketSize changed */
2915 if (xfer->flags_int.control_xfr != 0 &&
2916 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2918 DPRINTFN(8, "Reconfigure control endpoint\n");
2920 /* force driver to reconfigure endpoint */
2921 pepext->trb_halted = 1;
2922 pepext->trb_running = 0;
2925 /* check for stopped condition, after putting transfer on interrupt queue */
2926 if (pepext->trb_running == 0) {
2927 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2929 DPRINTFN(8, "Not running\n");
2931 /* start configuration */
2932 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2933 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2937 pepext->trb_used[id]++;
2939 /* get current TRB index */
2940 i = pepext->trb_index[id];
2942 /* get next TRB index */
2945 /* the last entry of the ring is a hardcoded link TRB */
2946 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2949 /* store next TRB index, before stream ID offset is added */
2950 pepext->trb_index[id] = inext;
2952 /* offset for stream */
2953 i += id * XHCI_MAX_TRANSFERS;
2954 inext += id * XHCI_MAX_TRANSFERS;
2956 /* compute terminating return address */
2957 addr += (inext * sizeof(struct xhci_trb));
2959 /* compute link TRB pointer */
2960 trb_link = td_last->td_trb + td_last->ntrb;
2962 /* update next pointer of last link TRB */
2963 trb_link->qwTrb0 = htole64(addr);
2964 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2965 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2966 XHCI_TRB_3_CYCLE_BIT |
2967 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2970 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2972 usb_pc_cpu_flush(td_last->page_cache);
2974 /* write ahead chain end marker */
2976 pepext->trb[inext].qwTrb0 = 0;
2977 pepext->trb[inext].dwTrb2 = 0;
2978 pepext->trb[inext].dwTrb3 = 0;
2980 /* update next pointer of link TRB */
2982 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2983 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2986 xhci_dump_trb(&pepext->trb[i]);
2988 usb_pc_cpu_flush(pepext->page_cache);
2990 /* toggle cycle bit which activates the transfer chain */
2992 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2993 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2995 usb_pc_cpu_flush(pepext->page_cache);
2997 DPRINTF("qh_pos = %u\n", i);
2999 pepext->xfer[i] = xfer;
3003 xfer->flags_int.bandwidth_reclaimed = 1;
3005 xhci_endpoint_doorbell(xfer);
3011 xhci_root_intr(struct xhci_softc *sc)
3015 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3017 /* clear any old interrupt data */
3018 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3020 for (i = 1; i <= sc->sc_noport; i++) {
3021 /* pick out CHANGE bits from the status register */
3022 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3023 XHCI_PS_CSC | XHCI_PS_PEC |
3024 XHCI_PS_OCC | XHCI_PS_WRC |
3025 XHCI_PS_PRC | XHCI_PS_PLC |
3027 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3028 DPRINTF("port %d changed\n", i);
3031 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3032 sizeof(sc->sc_hub_idata));
3035 /*------------------------------------------------------------------------*
3036 * xhci_device_done - XHCI done handler
3038 * NOTE: This function can be called two times in a row on
3039 * the same USB transfer. From close and from interrupt.
3040 *------------------------------------------------------------------------*/
3042 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3044 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3045 xfer, xfer->endpoint, error);
3047 /* remove transfer from HW queue */
3048 xhci_transfer_remove(xfer, error);
3050 /* dequeue transfer and start next transfer */
3051 usbd_transfer_done(xfer, error);
3054 /*------------------------------------------------------------------------*
3055 * XHCI data transfer support (generic type)
3056 *------------------------------------------------------------------------*/
3058 xhci_device_generic_open(struct usb_xfer *xfer)
3060 if (xfer->flags_int.isochronous_xfr) {
3061 switch (xfer->xroot->udev->speed) {
3062 case USB_SPEED_FULL:
3065 usb_hs_bandwidth_alloc(xfer);
3072 xhci_device_generic_close(struct usb_xfer *xfer)
3076 xhci_device_done(xfer, USB_ERR_CANCELLED);
3078 if (xfer->flags_int.isochronous_xfr) {
3079 switch (xfer->xroot->udev->speed) {
3080 case USB_SPEED_FULL:
3083 usb_hs_bandwidth_free(xfer);
3090 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3091 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3093 struct usb_xfer *xfer;
3095 /* check if there is a current transfer */
3096 xfer = ep->endpoint_q[stream_id].curr;
3101 * Check if the current transfer is started and then pickup
3102 * the next one, if any. Else wait for next start event due to
3103 * block on failure feature.
3105 if (!xfer->flags_int.bandwidth_reclaimed)
3108 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3111 * In case of enter we have to consider that the
3112 * transfer is queued by the USB core after the enter
3121 /* try to multi buffer */
3122 xhci_transfer_insert(xfer);
3126 xhci_device_generic_enter(struct usb_xfer *xfer)
3130 /* set up TD's and QH */
3131 xhci_setup_generic_chain(xfer);
3133 xhci_device_generic_multi_enter(xfer->endpoint,
3134 xfer->stream_id, xfer);
3138 xhci_device_generic_start(struct usb_xfer *xfer)
3142 /* try to insert xfer on HW queue */
3143 xhci_transfer_insert(xfer);
3145 /* try to multi buffer */
3146 xhci_device_generic_multi_enter(xfer->endpoint,
3147 xfer->stream_id, NULL);
3149 /* add transfer last on interrupt queue */
3150 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3152 /* start timeout, if any */
3153 if (xfer->timeout != 0)
3154 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3157 struct usb_pipe_methods xhci_device_generic_methods =
3159 .open = xhci_device_generic_open,
3160 .close = xhci_device_generic_close,
3161 .enter = xhci_device_generic_enter,
3162 .start = xhci_device_generic_start,
3165 /*------------------------------------------------------------------------*
3166 * xhci root HUB support
3167 *------------------------------------------------------------------------*
3168 * Simulate a hardware HUB by handling all the necessary requests.
3169 *------------------------------------------------------------------------*/
3171 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3174 struct usb_device_descriptor xhci_devd =
3176 .bLength = sizeof(xhci_devd),
3177 .bDescriptorType = UDESC_DEVICE, /* type */
3178 HSETW(.bcdUSB, 0x0300), /* USB version */
3179 .bDeviceClass = UDCLASS_HUB, /* class */
3180 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3181 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3182 .bMaxPacketSize = 9, /* max packet size */
3183 HSETW(.idVendor, 0x0000), /* vendor */
3184 HSETW(.idProduct, 0x0000), /* product */
3185 HSETW(.bcdDevice, 0x0100), /* device version */
3189 .bNumConfigurations = 1, /* # of configurations */
3193 struct xhci_bos_desc xhci_bosd = {
3195 .bLength = sizeof(xhci_bosd.bosd),
3196 .bDescriptorType = UDESC_BOS,
3197 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3198 .bNumDeviceCaps = 3,
3201 .bLength = sizeof(xhci_bosd.usb2extd),
3202 .bDescriptorType = 1,
3203 .bDevCapabilityType = 2,
3204 .bmAttributes[0] = 2,
3207 .bLength = sizeof(xhci_bosd.usbdcd),
3208 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3209 .bDevCapabilityType = 3,
3210 .bmAttributes = 0, /* XXX */
3211 HSETW(.wSpeedsSupported, 0x000C),
3212 .bFunctionalitySupport = 8,
3213 .bU1DevExitLat = 255, /* dummy - not used */
3214 .wU2DevExitLat = { 0x00, 0x08 },
3217 .bLength = sizeof(xhci_bosd.cidd),
3218 .bDescriptorType = 1,
3219 .bDevCapabilityType = 4,
3221 .bContainerID = 0, /* XXX */
3226 struct xhci_config_desc xhci_confd = {
3228 .bLength = sizeof(xhci_confd.confd),
3229 .bDescriptorType = UDESC_CONFIG,
3230 .wTotalLength[0] = sizeof(xhci_confd),
3232 .bConfigurationValue = 1,
3233 .iConfiguration = 0,
3234 .bmAttributes = UC_SELF_POWERED,
3235 .bMaxPower = 0 /* max power */
3238 .bLength = sizeof(xhci_confd.ifcd),
3239 .bDescriptorType = UDESC_INTERFACE,
3241 .bInterfaceClass = UICLASS_HUB,
3242 .bInterfaceSubClass = UISUBCLASS_HUB,
3243 .bInterfaceProtocol = 0,
3246 .bLength = sizeof(xhci_confd.endpd),
3247 .bDescriptorType = UDESC_ENDPOINT,
3248 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3249 .bmAttributes = UE_INTERRUPT,
3250 .wMaxPacketSize[0] = 2, /* max 15 ports */
3254 .bLength = sizeof(xhci_confd.endpcd),
3255 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3262 struct usb_hub_ss_descriptor xhci_hubd = {
3263 .bLength = sizeof(xhci_hubd),
3264 .bDescriptorType = UDESC_SS_HUB,
3268 xhci_roothub_exec(struct usb_device *udev,
3269 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3271 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3272 const char *str_ptr;
3283 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3286 ptr = (const void *)&sc->sc_hub_desc;
3290 value = UGETW(req->wValue);
3291 index = UGETW(req->wIndex);
3293 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3294 "wValue=0x%04x wIndex=0x%04x\n",
3295 req->bmRequestType, req->bRequest,
3296 UGETW(req->wLength), value, index);
3298 #define C(x,y) ((x) | ((y) << 8))
3299 switch (C(req->bRequest, req->bmRequestType)) {
3300 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3301 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3302 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3304 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3305 * for the integrated root hub.
3308 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3310 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3312 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3313 switch (value >> 8) {
3315 if ((value & 0xff) != 0) {
3316 err = USB_ERR_IOERROR;
3319 len = sizeof(xhci_devd);
3320 ptr = (const void *)&xhci_devd;
3324 if ((value & 0xff) != 0) {
3325 err = USB_ERR_IOERROR;
3328 len = sizeof(xhci_bosd);
3329 ptr = (const void *)&xhci_bosd;
3333 if ((value & 0xff) != 0) {
3334 err = USB_ERR_IOERROR;
3337 len = sizeof(xhci_confd);
3338 ptr = (const void *)&xhci_confd;
3342 switch (value & 0xff) {
3343 case 0: /* Language table */
3347 case 1: /* Vendor */
3348 str_ptr = sc->sc_vendor;
3351 case 2: /* Product */
3352 str_ptr = "XHCI root HUB";
3360 len = usb_make_str_desc(
3361 sc->sc_hub_desc.temp,
3362 sizeof(sc->sc_hub_desc.temp),
3367 err = USB_ERR_IOERROR;
3371 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3373 sc->sc_hub_desc.temp[0] = 0;
3375 case C(UR_GET_STATUS, UT_READ_DEVICE):
3377 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3379 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3380 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3382 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3384 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3385 if (value >= XHCI_MAX_DEVICES) {
3386 err = USB_ERR_IOERROR;
3390 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3391 if (value != 0 && value != 1) {
3392 err = USB_ERR_IOERROR;
3395 sc->sc_conf = value;
3397 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3399 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3400 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3401 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3402 err = USB_ERR_IOERROR;
3404 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3406 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3409 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3411 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3412 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3415 (index > sc->sc_noport)) {
3416 err = USB_ERR_IOERROR;
3419 port = XHCI_PORTSC(index);
3421 v = XREAD4(sc, oper, port);
3422 i = XHCI_PS_PLS_GET(v);
3423 v &= ~XHCI_PS_CLEAR;
3426 case UHF_C_BH_PORT_RESET:
3427 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3429 case UHF_C_PORT_CONFIG_ERROR:
3430 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3432 case UHF_C_PORT_SUSPEND:
3433 case UHF_C_PORT_LINK_STATE:
3434 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3436 case UHF_C_PORT_CONNECTION:
3437 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3439 case UHF_C_PORT_ENABLE:
3440 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3442 case UHF_C_PORT_OVER_CURRENT:
3443 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3445 case UHF_C_PORT_RESET:
3446 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3448 case UHF_PORT_ENABLE:
3449 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3451 case UHF_PORT_POWER:
3452 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3454 case UHF_PORT_INDICATOR:
3455 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3457 case UHF_PORT_SUSPEND:
3461 XWRITE4(sc, oper, port, v |
3462 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3465 /* wait 20ms for resume sequence to complete */
3466 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3469 XWRITE4(sc, oper, port, v |
3470 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3473 err = USB_ERR_IOERROR;
3478 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3479 if ((value & 0xff) != 0) {
3480 err = USB_ERR_IOERROR;
3484 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3486 sc->sc_hub_desc.hubd = xhci_hubd;
3488 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3490 if (XHCI_HCS0_PPC(v))
3491 i = UHD_PWR_INDIVIDUAL;
3495 if (XHCI_HCS0_PIND(v))
3498 i |= UHD_OC_INDIVIDUAL;
3500 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3502 /* see XHCI section 5.4.9: */
3503 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3505 for (j = 1; j <= sc->sc_noport; j++) {
3507 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3508 if (v & XHCI_PS_DR) {
3509 sc->sc_hub_desc.hubd.
3510 DeviceRemovable[j / 8] |= 1U << (j % 8);
3513 len = sc->sc_hub_desc.hubd.bLength;
3516 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3518 memset(sc->sc_hub_desc.temp, 0, 16);
3521 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3522 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3525 (index > sc->sc_noport)) {
3526 err = USB_ERR_IOERROR;
3530 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3532 DPRINTFN(9, "port status=0x%08x\n", v);
3534 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3536 switch (XHCI_PS_SPEED_GET(v)) {
3538 i |= UPS_HIGH_SPEED;
3547 i |= UPS_OTHER_SPEED;
3551 if (v & XHCI_PS_CCS)
3552 i |= UPS_CURRENT_CONNECT_STATUS;
3553 if (v & XHCI_PS_PED)
3554 i |= UPS_PORT_ENABLED;
3555 if (v & XHCI_PS_OCA)
3556 i |= UPS_OVERCURRENT_INDICATOR;
3559 if (v & XHCI_PS_PP) {
3561 * The USB 3.0 RH is using the
3562 * USB 2.0's power bit
3564 i |= UPS_PORT_POWER;
3566 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3569 if (v & XHCI_PS_CSC)
3570 i |= UPS_C_CONNECT_STATUS;
3571 if (v & XHCI_PS_PEC)
3572 i |= UPS_C_PORT_ENABLED;
3573 if (v & XHCI_PS_OCC)
3574 i |= UPS_C_OVERCURRENT_INDICATOR;
3575 if (v & XHCI_PS_WRC)
3576 i |= UPS_C_BH_PORT_RESET;
3577 if (v & XHCI_PS_PRC)
3578 i |= UPS_C_PORT_RESET;
3579 if (v & XHCI_PS_PLC)
3580 i |= UPS_C_PORT_LINK_STATE;
3581 if (v & XHCI_PS_CEC)
3582 i |= UPS_C_PORT_CONFIG_ERROR;
3584 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3585 len = sizeof(sc->sc_hub_desc.ps);
3588 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3589 err = USB_ERR_IOERROR;
3592 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3595 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3601 (index > sc->sc_noport)) {
3602 err = USB_ERR_IOERROR;
3606 port = XHCI_PORTSC(index);
3607 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3610 case UHF_PORT_U1_TIMEOUT:
3611 if (XHCI_PS_SPEED_GET(v) != 4) {
3612 err = USB_ERR_IOERROR;
3615 port = XHCI_PORTPMSC(index);
3616 v = XREAD4(sc, oper, port);
3617 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3618 v |= XHCI_PM3_U1TO_SET(i);
3619 XWRITE4(sc, oper, port, v);
3621 case UHF_PORT_U2_TIMEOUT:
3622 if (XHCI_PS_SPEED_GET(v) != 4) {
3623 err = USB_ERR_IOERROR;
3626 port = XHCI_PORTPMSC(index);
3627 v = XREAD4(sc, oper, port);
3628 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3629 v |= XHCI_PM3_U2TO_SET(i);
3630 XWRITE4(sc, oper, port, v);
3632 case UHF_BH_PORT_RESET:
3633 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3635 case UHF_PORT_LINK_STATE:
3636 XWRITE4(sc, oper, port, v |
3637 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3638 /* 4ms settle time */
3639 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3641 case UHF_PORT_ENABLE:
3642 DPRINTFN(3, "set port enable %d\n", index);
3644 case UHF_PORT_SUSPEND:
3645 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3646 j = XHCI_PS_SPEED_GET(v);
3647 if ((j < 1) || (j > 3)) {
3648 /* non-supported speed */
3649 err = USB_ERR_IOERROR;
3652 XWRITE4(sc, oper, port, v |
3653 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3655 case UHF_PORT_RESET:
3656 DPRINTFN(6, "reset port %d\n", index);
3657 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3659 case UHF_PORT_POWER:
3660 DPRINTFN(3, "set port power %d\n", index);
3661 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3664 DPRINTFN(3, "set port test %d\n", index);
3666 case UHF_PORT_INDICATOR:
3667 DPRINTFN(3, "set port indicator %d\n", index);
3669 v &= ~XHCI_PS_PIC_SET(3);
3670 v |= XHCI_PS_PIC_SET(1);
3672 XWRITE4(sc, oper, port, v);
3675 err = USB_ERR_IOERROR;
3680 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3681 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3682 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3683 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3686 err = USB_ERR_IOERROR;
3696 xhci_xfer_setup(struct usb_setup_params *parm)
3698 struct usb_page_search page_info;
3699 struct usb_page_cache *pc;
3700 struct xhci_softc *sc;
3701 struct usb_xfer *xfer;
3706 sc = XHCI_BUS2SC(parm->udev->bus);
3707 xfer = parm->curr_xfer;
3710 * The proof for the "ntd" formula is illustrated like this:
3712 * +------------------------------------+
3716 * | | xxx | x | frm 0 |
3718 * | | xxx | xx | frm 1 |
3721 * +------------------------------------+
3723 * "xxx" means a completely full USB transfer descriptor
3725 * "x" and "xx" means a short USB packet
3727 * For the remainder of an USB transfer modulo
3728 * "max_data_length" we need two USB transfer descriptors.
3729 * One to transfer the remaining data and one to finalise with
3730 * a zero length packet in case the "force_short_xfer" flag is
3731 * set. We only need two USB transfer descriptors in the case
3732 * where the transfer length of the first one is a factor of
3733 * "max_frame_size". The rest of the needed USB transfer
3734 * descriptors is given by the buffer size divided by the
3735 * maximum data payload.
3737 parm->hc_max_packet_size = 0x400;
3738 parm->hc_max_packet_count = 16 * 3;
3739 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3741 xfer->flags_int.bdma_enable = 1;
3743 usbd_transfer_setup_sub(parm);
3745 if (xfer->flags_int.isochronous_xfr) {
3746 ntd = ((1 * xfer->nframes)
3747 + (xfer->max_data_length / xfer->max_hc_frame_size));
3748 } else if (xfer->flags_int.control_xfr) {
3749 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3750 + (xfer->max_data_length / xfer->max_hc_frame_size));
3752 ntd = ((2 * xfer->nframes)
3753 + (xfer->max_data_length / xfer->max_hc_frame_size));
3762 * Allocate queue heads and transfer descriptors
3766 if (usbd_transfer_setup_sub_malloc(
3767 parm, &pc, sizeof(struct xhci_td),
3768 XHCI_TD_ALIGN, ntd)) {
3769 parm->err = USB_ERR_NOMEM;
3773 for (n = 0; n != ntd; n++) {
3776 usbd_get_page(pc + n, 0, &page_info);
3778 td = page_info.buffer;
3781 td->td_self = page_info.physaddr;
3782 td->obj_next = last_obj;
3783 td->page_cache = pc + n;
3787 usb_pc_cpu_flush(pc + n);
3790 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3792 if (!xfer->flags_int.curr_dma_set) {
3793 xfer->flags_int.curr_dma_set = 1;
3799 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3801 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3802 struct usb_page_search buf_inp;
3803 struct usb_device *udev;
3804 struct xhci_endpoint_ext *pepext;
3805 struct usb_endpoint_descriptor *edesc;
3806 struct usb_page_cache *pcinp;
3808 usb_stream_t stream_id;
3812 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3813 xfer->endpoint->edesc);
3815 udev = xfer->xroot->udev;
3816 index = udev->controller_slot_id;
3818 pcinp = &sc->sc_hw.devs[index].input_pc;
3820 usbd_get_page(pcinp, 0, &buf_inp);
3822 edesc = xfer->endpoint->edesc;
3824 epno = edesc->bEndpointAddress;
3825 stream_id = xfer->stream_id;
3827 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3830 epno = XHCI_EPNO2EPID(epno);
3833 return (USB_ERR_NO_PIPE); /* invalid */
3837 /* configure endpoint */
3839 err = xhci_configure_endpoint_by_xfer(xfer);
3842 XHCI_CMD_UNLOCK(sc);
3847 * Get the endpoint into the stopped state according to the
3848 * endpoint context state diagram in the XHCI specification:
3851 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3854 DPRINTF("Could not stop endpoint %u\n", epno);
3856 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3859 DPRINTF("Could not reset endpoint %u\n", epno);
3861 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3862 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3863 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3864 stream_id, epno, index);
3867 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3870 * Get the endpoint into the running state according to the
3871 * endpoint context state diagram in the XHCI specification:
3874 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3876 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3879 DPRINTF("Could not configure endpoint %u\n", epno);
3881 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3884 DPRINTF("Could not configure endpoint %u\n", epno);
3886 XHCI_CMD_UNLOCK(sc);
3892 xhci_xfer_unsetup(struct usb_xfer *xfer)
3898 xhci_start_dma_delay(struct usb_xfer *xfer)
3900 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3902 /* put transfer on interrupt queue (again) */
3903 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3905 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3906 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3910 xhci_configure_msg(struct usb_proc_msg *pm)
3912 struct xhci_softc *sc;
3913 struct xhci_endpoint_ext *pepext;
3914 struct usb_xfer *xfer;
3916 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3919 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3921 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3922 xfer->endpoint->edesc);
3924 if ((pepext->trb_halted != 0) ||
3925 (pepext->trb_running == 0)) {
3929 /* clear halted and running */
3930 pepext->trb_halted = 0;
3931 pepext->trb_running = 0;
3933 /* nuke remaining buffered transfers */
3935 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3936 XHCI_MAX_STREAMS); i++) {
3938 * NOTE: We need to use the timeout
3939 * error code here else existing
3940 * isochronous clients can get
3943 if (pepext->xfer[i] != NULL) {
3944 xhci_device_done(pepext->xfer[i],
3950 * NOTE: The USB transfer cannot vanish in
3954 USB_BUS_UNLOCK(&sc->sc_bus);
3956 xhci_configure_reset_endpoint(xfer);
3958 USB_BUS_LOCK(&sc->sc_bus);
3960 /* check if halted is still cleared */
3961 if (pepext->trb_halted == 0) {
3962 pepext->trb_running = 1;
3963 memset(pepext->trb_index, 0,
3964 sizeof(pepext->trb_index));
3969 if (xfer->flags_int.did_dma_delay) {
3971 /* remove transfer from interrupt queue (again) */
3972 usbd_transfer_dequeue(xfer);
3974 /* we are finally done */
3975 usb_dma_delay_done_cb(xfer);
3977 /* queue changed - restart */
3982 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3984 /* try to insert xfer on HW queue */
3985 xhci_transfer_insert(xfer);
3987 /* try to multi buffer */
3988 xhci_device_generic_multi_enter(xfer->endpoint,
3989 xfer->stream_id, NULL);
3994 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3995 struct usb_endpoint *ep)
3997 struct xhci_endpoint_ext *pepext;
3999 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4000 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4002 if (udev->parent_hub == NULL) {
4003 /* root HUB has special endpoint handling */
4007 ep->methods = &xhci_device_generic_methods;
4009 pepext = xhci_get_endpoint_ext(udev, edesc);
4011 USB_BUS_LOCK(udev->bus);
4012 pepext->trb_halted = 1;
4013 pepext->trb_running = 0;
4014 USB_BUS_UNLOCK(udev->bus);
4018 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4024 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4026 struct xhci_endpoint_ext *pepext;
4030 if (udev->flags.usb_mode != USB_MODE_HOST) {
4034 if (udev->parent_hub == NULL) {
4035 /* root HUB has special endpoint handling */
4039 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4041 USB_BUS_LOCK(udev->bus);
4042 pepext->trb_halted = 1;
4043 pepext->trb_running = 0;
4044 USB_BUS_UNLOCK(udev->bus);
4048 xhci_device_init(struct usb_device *udev)
4050 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4054 /* no init for root HUB */
4055 if (udev->parent_hub == NULL)
4060 /* set invalid default */
4062 udev->controller_slot_id = sc->sc_noslot + 1;
4064 /* try to get a new slot ID from the XHCI */
4066 err = xhci_cmd_enable_slot(sc, &temp);
4069 XHCI_CMD_UNLOCK(sc);
4073 if (temp > sc->sc_noslot) {
4074 XHCI_CMD_UNLOCK(sc);
4075 return (USB_ERR_BAD_ADDRESS);
4078 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4079 DPRINTF("slot %u already allocated.\n", temp);
4080 XHCI_CMD_UNLOCK(sc);
4081 return (USB_ERR_BAD_ADDRESS);
4084 /* store slot ID for later reference */
4086 udev->controller_slot_id = temp;
4088 /* reset data structure */
4090 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4092 /* set mark slot allocated */
4094 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4096 err = xhci_alloc_device_ext(udev);
4098 XHCI_CMD_UNLOCK(sc);
4100 /* get device into default state */
4103 err = xhci_set_address(udev, NULL, 0);
4109 xhci_device_uninit(struct usb_device *udev)
4111 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4114 /* no init for root HUB */
4115 if (udev->parent_hub == NULL)
4120 index = udev->controller_slot_id;
4122 if (index <= sc->sc_noslot) {
4123 xhci_cmd_disable_slot(sc, index);
4124 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4126 /* free device extension */
4127 xhci_free_device_ext(udev);
4130 XHCI_CMD_UNLOCK(sc);
4134 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4137 * Wait until the hardware has finished any possible use of
4138 * the transfer descriptor(s)
4140 *pus = 2048; /* microseconds */
4144 xhci_device_resume(struct usb_device *udev)
4146 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4153 /* check for root HUB */
4154 if (udev->parent_hub == NULL)
4157 index = udev->controller_slot_id;
4161 /* blindly resume all endpoints */
4163 USB_BUS_LOCK(udev->bus);
4165 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4166 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4167 XWRITE4(sc, door, XHCI_DOORBELL(index),
4168 n | XHCI_DB_SID_SET(p));
4172 USB_BUS_UNLOCK(udev->bus);
4174 XHCI_CMD_UNLOCK(sc);
4178 xhci_device_suspend(struct usb_device *udev)
4180 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4187 /* check for root HUB */
4188 if (udev->parent_hub == NULL)
4191 index = udev->controller_slot_id;
4195 /* blindly suspend all endpoints */
4197 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4198 err = xhci_cmd_stop_ep(sc, 1, n, index);
4200 DPRINTF("Failed to suspend endpoint "
4201 "%u on slot %u (ignored).\n", n, index);
4205 XHCI_CMD_UNLOCK(sc);
4209 xhci_set_hw_power(struct usb_bus *bus)
4215 xhci_device_state_change(struct usb_device *udev)
4217 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4218 struct usb_page_search buf_inp;
4222 /* check for root HUB */
4223 if (udev->parent_hub == NULL)
4226 index = udev->controller_slot_id;
4230 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4231 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4232 &sc->sc_hw.devs[index].tt);
4234 sc->sc_hw.devs[index].nports = 0;
4239 switch (usb_get_device_state(udev)) {
4240 case USB_STATE_POWERED:
4241 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4244 /* set default state */
4245 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4247 /* reset number of contexts */
4248 sc->sc_hw.devs[index].context_num = 0;
4250 err = xhci_cmd_reset_dev(sc, index);
4253 DPRINTF("Device reset failed "
4254 "for slot %u.\n", index);
4258 case USB_STATE_ADDRESSED:
4259 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4262 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4264 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4267 DPRINTF("Failed to deconfigure "
4268 "slot %u.\n", index);
4272 case USB_STATE_CONFIGURED:
4273 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4276 /* set configured state */
4277 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4279 /* reset number of contexts */
4280 sc->sc_hw.devs[index].context_num = 0;
4282 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4284 xhci_configure_mask(udev, 3, 0);
4286 err = xhci_configure_device(udev);
4288 DPRINTF("Could not configure device "
4289 "at slot %u.\n", index);
4292 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4294 DPRINTF("Could not evaluate device "
4295 "context at slot %u.\n", index);
4302 XHCI_CMD_UNLOCK(sc);
4306 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4310 case USB_EP_MODE_DEFAULT:
4312 case USB_EP_MODE_STREAMS:
4313 if (xhcistreams == 0 ||
4314 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4315 udev->speed != USB_SPEED_SUPER)
4316 return (USB_ERR_INVAL);
4319 return (USB_ERR_INVAL);
4323 struct usb_bus_methods xhci_bus_methods = {
4324 .endpoint_init = xhci_ep_init,
4325 .endpoint_uninit = xhci_ep_uninit,
4326 .xfer_setup = xhci_xfer_setup,
4327 .xfer_unsetup = xhci_xfer_unsetup,
4328 .get_dma_delay = xhci_get_dma_delay,
4329 .device_init = xhci_device_init,
4330 .device_uninit = xhci_device_uninit,
4331 .device_resume = xhci_device_resume,
4332 .device_suspend = xhci_device_suspend,
4333 .set_hw_power = xhci_set_hw_power,
4334 .roothub_exec = xhci_roothub_exec,
4335 .xfer_poll = xhci_do_poll,
4336 .start_dma_delay = xhci_start_dma_delay,
4337 .set_address = xhci_set_address,
4338 .clear_stall = xhci_ep_clear_stall,
4339 .device_state_change = xhci_device_state_change,
4340 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4341 .set_endpoint_mode = xhci_set_endpoint_mode,