2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kmod.h>
38 * kmod.h must be included before module.h since it includes (indirectly) sys/module.h
39 * To use the FBSD macro sys/module.h should define MODULE_VERSION before linux/module does.
41 #include <linux/module.h>
42 #include <linux/errno.h>
43 #include <linux/pci.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <linux/io-mapping.h>
47 #include <linux/delay.h>
48 #include <linux/netdevice.h>
49 #include <linux/string.h>
52 #include <linux/mlx4/device.h>
53 #include <linux/mlx4/doorbell.h>
58 #include "mlx4_stats.h"
60 /* Mellanox ConnectX HCA low-level driver */
62 struct workqueue_struct *mlx4_wq;
64 #ifdef CONFIG_MLX4_DEBUG
66 int mlx4_debug_level = 0;
67 module_param_named(debug_level, mlx4_debug_level, int, 0644);
68 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
70 #endif /* CONFIG_MLX4_DEBUG */
75 module_param(msi_x, int, 0444);
76 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x (non-SRIOV only)");
78 #else /* CONFIG_PCI_MSI */
82 #endif /* CONFIG_PCI_MSI */
84 static int enable_sys_tune = 0;
85 module_param(enable_sys_tune, int, 0444);
86 MODULE_PARM_DESC(enable_sys_tune, "Tune the cpu's for better performance (default 0)");
89 module_param_named(block_loopback, mlx4_blck_lb, int, 0644);
90 MODULE_PARM_DESC(block_loopback, "Block multicast loopback packets if > 0 "
94 BDF_STR_SIZE = 8, /* bb:dd.f- */
95 DBDF_STR_SIZE = 13 /* mmmm:bb:dd.f- */
112 struct mlx4_dbdf2val_lst dbdf2val;
115 static struct param_data num_vfs = {
118 .name = "num_vfs param",
121 .range = {0, MLX4_MAX_NUM_VF}
124 module_param_string(num_vfs, num_vfs.dbdf2val.str,
125 sizeof(num_vfs.dbdf2val.str), 0444);
126 MODULE_PARM_DESC(num_vfs,
127 "Either single value (e.g. '5') to define uniform num_vfs value for all devices functions\n"
128 "\t\tor a string to map device function numbers to their num_vfs values (e.g. '0000:04:00.0-5,002b:1c:0b.a-15').\n"
129 "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for num_vfs value (e.g. 15).");
131 static struct param_data probe_vf = {
134 .name = "probe_vf param",
137 .range = {0, MLX4_MAX_NUM_VF}
140 module_param_string(probe_vf, probe_vf.dbdf2val.str,
141 sizeof(probe_vf.dbdf2val.str), 0444);
142 MODULE_PARM_DESC(probe_vf,
143 "Either single value (e.g. '3') to define uniform number of VFs to probe by the pf driver for all devices functions\n"
144 "\t\tor a string to map device function numbers to their probe_vf values (e.g. '0000:04:00.0-3,002b:1c:0b.a-13').\n"
145 "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for probe_vf value (e.g. 13).");
147 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
149 module_param_named(log_num_mgm_entry_size,
150 mlx4_log_num_mgm_entry_size, int, 0444);
151 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
152 " of qp per mcg, for example:"
153 " 10 gives 248.range: 7 <="
154 " log_num_mgm_entry_size <= 12."
155 " To activate device managed"
156 " flow steering when available, set to -1");
158 static int high_rate_steer;
159 module_param(high_rate_steer, int, 0444);
160 MODULE_PARM_DESC(high_rate_steer, "Enable steering mode for higher packet rate"
163 static int fast_drop;
164 module_param_named(fast_drop, fast_drop, int, 0444);
165 MODULE_PARM_DESC(fast_drop,
166 "Enable fast packet drop when no recieve WQEs are posted");
168 int mlx4_enable_64b_cqe_eqe = 1;
169 module_param_named(enable_64b_cqe_eqe, mlx4_enable_64b_cqe_eqe, int, 0644);
170 MODULE_PARM_DESC(enable_64b_cqe_eqe,
171 "Enable 64 byte CQEs/EQEs when the the FW supports this if non-zero (default: 1)");
173 #define HCA_GLOBAL_CAP_MASK 0
175 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
177 static char mlx4_version[] __devinitdata =
178 DRV_NAME ": Mellanox ConnectX VPI driver v"
179 DRV_VERSION " (" DRV_RELDATE ")\n";
181 static int log_num_mac = 7;
182 module_param_named(log_num_mac, log_num_mac, int, 0444);
183 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
185 static int log_num_vlan;
186 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
187 MODULE_PARM_DESC(log_num_vlan,
188 "(Obsolete) Log2 max number of VLANs per ETH port (0-7)");
189 /* Log2 max number of VLANs per ETH port (0-7) */
190 #define MLX4_LOG_NUM_VLANS 7
192 int log_mtts_per_seg = ilog2(1);
193 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
194 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment "
195 "(0-7) (default: 0)");
197 static struct param_data port_type_array = {
198 .id = PORT_TYPE_ARRAY,
200 .name = "port_type_array param",
202 .def_val = {MLX4_PORT_TYPE_ETH, MLX4_PORT_TYPE_ETH},
203 .range = {MLX4_PORT_TYPE_IB, MLX4_PORT_TYPE_NA}
206 module_param_string(port_type_array, port_type_array.dbdf2val.str,
207 sizeof(port_type_array.dbdf2val.str), 0444);
208 MODULE_PARM_DESC(port_type_array,
209 "Either pair of values (e.g. '1,2') to define uniform port1/port2 types configuration for all devices functions\n"
210 "\t\tor a string to map device function numbers to their pair of port types values (e.g. '0000:04:00.0-1;2,002b:1c:0b.a-1;1').\n"
211 "\t\tValid port types: 1-ib, 2-eth, 3-auto, 4-N/A\n"
212 "\t\tIn case that only one port is available use the N/A port type for port2 (e.g '1,4').");
215 struct mlx4_port_config {
216 struct list_head list;
217 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
218 struct pci_dev *pdev;
221 #define MLX4_LOG_NUM_MTT 20
222 /* We limit to 30 as of a bit map issue which uses int and not uint.
223 see mlx4_buddy_init -> bitmap_zero which gets int.
225 #define MLX4_MAX_LOG_NUM_MTT 30
226 static struct mlx4_profile mod_param_profile = {
233 .num_mtt_segs = 0, /* max(20, 2*MTTs for host memory)) */
236 module_param_named(log_num_qp, mod_param_profile.num_qp, int, 0444);
237 MODULE_PARM_DESC(log_num_qp, "log maximum number of QPs per HCA (default: 19)");
239 module_param_named(log_num_srq, mod_param_profile.num_srq, int, 0444);
240 MODULE_PARM_DESC(log_num_srq, "log maximum number of SRQs per HCA "
243 module_param_named(log_rdmarc_per_qp, mod_param_profile.rdmarc_per_qp, int,
245 MODULE_PARM_DESC(log_rdmarc_per_qp, "log number of RDMARC buffers per QP "
248 module_param_named(log_num_cq, mod_param_profile.num_cq, int, 0444);
249 MODULE_PARM_DESC(log_num_cq, "log maximum number of CQs per HCA (default: 16)");
251 module_param_named(log_num_mcg, mod_param_profile.num_mcg, int, 0444);
252 MODULE_PARM_DESC(log_num_mcg, "log maximum number of multicast groups per HCA "
255 module_param_named(log_num_mpt, mod_param_profile.num_mpt, int, 0444);
256 MODULE_PARM_DESC(log_num_mpt,
257 "log maximum number of memory protection table entries per "
258 "HCA (default: 19)");
260 module_param_named(log_num_mtt, mod_param_profile.num_mtt_segs, int, 0444);
261 MODULE_PARM_DESC(log_num_mtt,
262 "log maximum number of memory translation table segments per "
263 "HCA (default: max(20, 2*MTTs for register all of the host memory limited to 30))");
267 MLX4_IF_STATE_EXTENDED
270 static inline u64 dbdf_to_u64(int domain, int bus, int dev, int fn)
272 return (domain << 20) | (bus << 12) | (dev << 4) | fn;
275 static inline void pr_bdf_err(const char *dbdf, const char *pname)
277 pr_warn("mlx4_core: '%s' is not valid bdf in '%s'\n", dbdf, pname);
280 static inline void pr_val_err(const char *dbdf, const char *pname,
283 pr_warn("mlx4_core: value '%s' of bdf '%s' in '%s' is not valid\n"
287 static inline void pr_out_of_range_bdf(const char *dbdf, int val,
288 struct mlx4_dbdf2val_lst *dbdf2val)
290 pr_warn("mlx4_core: value %d in bdf '%s' of '%s' is out of its valid range (%d,%d)\n"
291 , val, dbdf, dbdf2val->name , dbdf2val->range.min,
292 dbdf2val->range.max);
295 static inline void pr_out_of_range(struct mlx4_dbdf2val_lst *dbdf2val)
297 pr_warn("mlx4_core: value of '%s' is out of its valid range (%d,%d)\n"
298 , dbdf2val->name , dbdf2val->range.min, dbdf2val->range.max);
301 static inline int is_in_range(int val, struct mlx4_range *r)
303 return (val >= r->min && val <= r->max);
306 static int update_defaults(struct param_data *pdata)
308 long int val[MLX4_MAX_BDF_VALS];
310 char *t, *p = pdata->dbdf2val.str;
314 if (!strlen(p) || strchr(p, ':') || strchr(p, '.') || strchr(p, ';'))
318 case PORT_TYPE_ARRAY:
320 if (!t || t == p || (t - p) > sizeof(sval))
324 strncpy(sval, p, val_len);
327 ret = kstrtol(sval, 0, &val[0]);
330 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) {
331 pr_out_of_range(&pdata->dbdf2val);
335 ret = kstrtol(t + 1, 0, &val[1]);
338 if (ret || !is_in_range(val[1], &pdata->dbdf2val.range)) {
339 pr_out_of_range(&pdata->dbdf2val);
343 pdata->dbdf2val.tbl[0].val[0] = val[0];
344 pdata->dbdf2val.tbl[0].val[1] = val[1];
349 ret = kstrtol(p, 0, &val[0]);
352 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) {
353 pr_out_of_range(&pdata->dbdf2val);
356 pdata->dbdf2val.tbl[0].val[0] = val[0];
359 pdata->dbdf2val.tbl[1].dbdf = MLX4_ENDOF_TBL;
364 int mlx4_fill_dbdf2val_tbl(struct mlx4_dbdf2val_lst *dbdf2val_lst)
366 int domain, bus, dev, fn;
372 int j, k, str_size, i = 1;
375 p = dbdf2val_lst->str;
377 for (j = 0; j < dbdf2val_lst->num_vals; j++)
378 dbdf2val_lst->tbl[0].val[j] = dbdf2val_lst->def_val[j];
379 dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL;
381 str_size = strlen(dbdf2val_lst->str);
387 prfx_size = BDF_STR_SIZE;
389 strncpy(sbdf, p, prfx_size);
390 domain = DEFAULT_DOMAIN;
391 if (sscanf(sbdf, "%02x:%02x.%x-", &bus, &dev, &fn) != 3) {
392 prfx_size = DBDF_STR_SIZE;
394 strncpy(sbdf, p, prfx_size);
395 if (sscanf(sbdf, "%04x:%02x:%02x.%x-", &domain, &bus,
397 pr_bdf_err(sbdf, dbdf2val_lst->name);
400 sprintf(tmp, "%04x:%02x:%02x.%x-", domain, bus, dev,
403 sprintf(tmp, "%02x:%02x.%x-", bus, dev, fn);
406 if (strnicmp(sbdf, tmp, sizeof(tmp))) {
407 pr_bdf_err(sbdf, dbdf2val_lst->name);
411 dbdf = dbdf_to_u64(domain, bus, dev, fn);
413 for (j = 1; j < i; j++)
414 if (dbdf2val_lst->tbl[j].dbdf == dbdf) {
415 pr_warn("mlx4_core: in '%s', %s appears multiple times\n"
416 , dbdf2val_lst->name, sbdf);
420 if (i >= MLX4_DEVS_TBL_SIZE) {
421 pr_warn("mlx4_core: Too many devices in '%s'\n"
422 , dbdf2val_lst->name);
428 t = t ? t : p + strlen(p);
430 pr_val_err(sbdf, dbdf2val_lst->name, "");
434 for (k = 0; k < dbdf2val_lst->num_vals; k++) {
440 v = (k == dbdf2val_lst->num_vals - 1) ? t : strchr(p, vsep);
441 if (!v || v > t || v == p || (v - p) > sizeof(sval)) {
442 pr_val_err(sbdf, dbdf2val_lst->name, p);
446 strncpy(sval, p, val_len);
449 ret = kstrtol(sval, 0, &val);
452 pr_warn("mlx4_core: too many vals in bdf '%s' of '%s'\n"
453 , sbdf, dbdf2val_lst->name);
455 pr_val_err(sbdf, dbdf2val_lst->name,
459 if (!is_in_range(val, &dbdf2val_lst->range)) {
460 pr_out_of_range_bdf(sbdf, val, dbdf2val_lst);
464 dbdf2val_lst->tbl[i].val[k] = val;
470 dbdf2val_lst->tbl[i].dbdf = dbdf;
473 pr_warn("mlx4_core: expect separator '%c' before '%s' in '%s'\n"
474 , sep, p, dbdf2val_lst->name);
480 if (i < MLX4_DEVS_TBL_SIZE)
481 dbdf2val_lst->tbl[i].dbdf = MLX4_ENDOF_TBL;
487 dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL;
488 pr_warn("mlx4_core: The value of '%s' is incorrect. The value is discarded!\n"
489 , dbdf2val_lst->name);
493 EXPORT_SYMBOL(mlx4_fill_dbdf2val_tbl);
495 int mlx4_get_val(struct mlx4_dbdf2val *tbl, struct pci_dev *pdev, int idx,
501 *val = tbl[0].val[idx];
505 dbdf = dbdf_to_u64(pci_get_domain(pdev->dev.bsddev), pci_get_bus(pdev->dev.bsddev),
506 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
508 while ((i < MLX4_DEVS_TBL_SIZE) && (tbl[i].dbdf != MLX4_ENDOF_TBL)) {
509 if (tbl[i].dbdf == dbdf) {
510 *val = tbl[i].val[idx];
518 EXPORT_SYMBOL(mlx4_get_val);
520 static void process_mod_param_profile(struct mlx4_profile *profile)
524 TUNABLE_ULONG_FETCH("hw.realmem", (u_long *) &hwphyssz);
526 profile->num_qp = 1 << mod_param_profile.num_qp;
527 profile->num_srq = 1 << mod_param_profile.num_srq;
528 profile->rdmarc_per_qp = 1 << mod_param_profile.rdmarc_per_qp;
529 profile->num_cq = 1 << mod_param_profile.num_cq;
530 profile->num_mcg = 1 << mod_param_profile.num_mcg;
531 profile->num_mpt = 1 << mod_param_profile.num_mpt;
533 * We want to scale the number of MTTs with the size of the
534 * system memory, since it makes sense to register a lot of
535 * memory on a system with a lot of memory. As a heuristic,
536 * make sure we have enough MTTs to register twice the system
537 * memory (with PAGE_SIZE entries).
539 * This number has to be a power of two and fit into 32 bits
540 * due to device limitations. We cap this at 2^30 as of bit map
541 * limitation to work with int instead of uint (mlx4_buddy_init -> bitmap_zero)
542 * That limits us to 4TB of memory registration per HCA with
543 * 4KB pages, which is probably OK for the next few months.
545 if (mod_param_profile.num_mtt_segs)
546 profile->num_mtt_segs = 1 << mod_param_profile.num_mtt_segs;
548 profile->num_mtt_segs =
549 roundup_pow_of_two(max_t(unsigned,
550 1 << (MLX4_LOG_NUM_MTT - log_mtts_per_seg),
552 (MLX4_MAX_LOG_NUM_MTT -
555 >> log_mtts_per_seg)));
556 /* set the actual value, so it will be reflected to the user
558 mod_param_profile.num_mtt_segs = ilog2(profile->num_mtt_segs);
562 int mlx4_check_port_params(struct mlx4_dev *dev,
563 enum mlx4_port_type *port_type)
567 for (i = 0; i < dev->caps.num_ports - 1; i++) {
568 if (port_type[i] != port_type[i + 1]) {
569 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
570 mlx4_err(dev, "Only same port types supported "
571 "on this HCA, aborting.\n");
577 for (i = 0; i < dev->caps.num_ports; i++) {
578 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
579 mlx4_err(dev, "Requested port type for port %d is not "
580 "supported on this HCA\n", i + 1);
587 static void mlx4_set_port_mask(struct mlx4_dev *dev)
591 for (i = 1; i <= dev->caps.num_ports; ++i)
592 dev->caps.port_mask[i] = dev->caps.port_type[i];
596 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
599 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
602 struct mlx4_func func;
604 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
605 err = mlx4_QUERY_FUNC(dev, &func, 0);
607 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
610 dev_cap->max_eqs = func.max_eq;
611 dev_cap->reserved_eqs = func.rsvd_eqs;
612 dev_cap->reserved_uars = func.rsvd_uars;
613 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
618 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
623 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
625 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
629 if (dev_cap->min_page_sz > PAGE_SIZE) {
630 mlx4_err(dev, "HCA minimum page size of %d bigger than "
631 "kernel PAGE_SIZE of %d, aborting.\n",
632 dev_cap->min_page_sz, (int)PAGE_SIZE);
635 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
636 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
638 dev_cap->num_ports, MLX4_MAX_PORTS);
642 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
643 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
644 "PCI resource 2 size of 0x%llx, aborting.\n",
646 (unsigned long long) pci_resource_len(dev->pdev, 2));
650 dev->caps.num_ports = dev_cap->num_ports;
651 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
652 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
653 dev->caps.num_sys_eqs :
655 for (i = 1; i <= dev->caps.num_ports; ++i) {
656 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
657 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
658 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
659 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
660 /* set gid and pkey table operating lengths by default
661 * to non-sriov values */
662 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
663 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
664 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
665 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
666 dev->caps.def_mac[i] = dev_cap->def_mac[i];
667 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
668 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
669 dev->caps.default_sense[i] = dev_cap->default_sense[i];
670 dev->caps.trans_type[i] = dev_cap->trans_type[i];
671 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
672 dev->caps.wavelength[i] = dev_cap->wavelength[i];
673 dev->caps.trans_code[i] = dev_cap->trans_code[i];
676 dev->caps.uar_page_size = PAGE_SIZE;
677 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
678 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
679 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
680 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
681 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
682 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
683 dev->caps.max_wqes = dev_cap->max_qp_sz;
684 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
685 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
686 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
687 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
688 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
689 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
691 * Subtract 1 from the limit because we need to allocate a
692 * spare CQE to enable resizing the CQ
694 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
695 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
696 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
697 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
698 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
700 /* The first 128 UARs are used for EQ doorbells */
701 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
702 dev->caps.reserved_pds = dev_cap->reserved_pds;
703 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
704 dev_cap->reserved_xrcds : 0;
705 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
706 dev_cap->max_xrcds : 0;
707 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
709 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
710 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
711 dev->caps.flags = dev_cap->flags;
712 dev->caps.flags2 = dev_cap->flags2;
713 dev->caps.bmme_flags = dev_cap->bmme_flags;
714 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
715 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
716 dev->caps.cq_timestamp = dev_cap->timestamp_support;
717 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
718 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
720 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
721 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
722 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
723 /* Don't do sense port on multifunction devices (for now at least) */
724 if (mlx4_is_mfunc(dev))
725 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
727 dev->caps.log_num_macs = log_num_mac;
728 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
730 dev->caps.fast_drop = fast_drop ?
731 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FAST_DROP) :
734 for (i = 1; i <= dev->caps.num_ports; ++i) {
735 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
736 if (dev->caps.supported_type[i]) {
737 /* if only ETH is supported - assign ETH */
738 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
739 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
740 /* if only IB is supported, assign IB */
741 else if (dev->caps.supported_type[i] ==
743 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
746 * if IB and ETH are supported, we set the port
747 * type according to user selection of port type;
748 * if there is no user selection, take the FW hint
751 mlx4_get_val(port_type_array.dbdf2val.tbl,
752 pci_physfn(dev->pdev), i - 1,
754 if (pta == MLX4_PORT_TYPE_NONE) {
755 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
756 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
757 } else if (pta == MLX4_PORT_TYPE_NA) {
758 mlx4_err(dev, "Port %d is valid port. "
759 "It is not allowed to configure its type to N/A(%d)\n",
760 i, MLX4_PORT_TYPE_NA);
763 dev->caps.port_type[i] = pta;
768 * Link sensing is allowed on the port if 3 conditions are true:
769 * 1. Both protocols are supported on the port.
770 * 2. Different types are supported on the port
771 * 3. FW declared that it supports link sensing
773 mlx4_priv(dev)->sense.sense_allowed[i] =
774 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
775 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
776 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
778 /* Disablling auto sense for default Eth ports support */
779 mlx4_priv(dev)->sense.sense_allowed[i] = 0;
782 * If "default_sense" bit is set, we move the port to "AUTO" mode
783 * and perform sense_port FW command to try and set the correct
784 * port type from beginning
786 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
787 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
788 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
789 mlx4_SENSE_PORT(dev, i, &sensed_port);
790 if (sensed_port != MLX4_PORT_TYPE_NONE)
791 dev->caps.port_type[i] = sensed_port;
793 dev->caps.possible_type[i] = dev->caps.port_type[i];
796 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
797 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
798 mlx4_warn(dev, "Requested number of MACs is too much "
799 "for port %d, reducing to %d.\n",
800 i, 1 << dev->caps.log_num_macs);
802 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
803 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
804 mlx4_warn(dev, "Requested number of VLANs is too much "
805 "for port %d, reducing to %d.\n",
806 i, 1 << dev->caps.log_num_vlans);
810 dev->caps.max_basic_counters = dev_cap->max_basic_counters;
811 dev->caps.max_extended_counters = dev_cap->max_extended_counters;
812 /* support extended counters if available */
813 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS_EXT)
814 dev->caps.max_counters = dev->caps.max_extended_counters;
816 dev->caps.max_counters = dev->caps.max_basic_counters;
818 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
819 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
820 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
821 (1 << dev->caps.log_num_macs) *
822 (1 << dev->caps.log_num_vlans) *
824 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
826 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
827 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
828 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
829 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
831 dev->caps.sync_qp = dev_cap->sync_qp;
832 if (dev->pdev->device == 0x1003)
833 dev->caps.cq_flags |= MLX4_DEV_CAP_CQ_FLAG_IO;
835 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
837 if (!mlx4_enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
839 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
840 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
841 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
842 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
846 if ((dev->caps.flags &
847 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
849 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
851 if (!mlx4_is_slave(dev)) {
852 for (i = 0; i < dev->caps.num_ports; ++i)
853 dev->caps.def_counter_index[i] = i << 1;
855 dev->caps.alloc_res_qp_mask =
856 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0);
858 dev->caps.alloc_res_qp_mask = 0;
863 /*The function checks if there are live vf, return the num of them*/
864 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
866 struct mlx4_priv *priv = mlx4_priv(dev);
867 struct mlx4_slave_state *s_state;
871 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
872 s_state = &priv->mfunc.master.slave_state[i];
873 if (s_state->active && s_state->last_cmd !=
874 MLX4_COMM_CMD_RESET) {
875 mlx4_warn(dev, "%s: slave: %d is still active\n",
883 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
885 u32 qk = MLX4_RESERVED_QKEY_BASE;
887 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
888 qpn < dev->phys_caps.base_proxy_sqpn)
891 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
893 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
895 qk += qpn - dev->phys_caps.base_proxy_sqpn;
899 EXPORT_SYMBOL(mlx4_get_parav_qkey);
901 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
903 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
905 if (!mlx4_is_master(dev))
908 priv->virt2phys_pkey[slave][port - 1][i] = val;
910 EXPORT_SYMBOL(mlx4_sync_pkey_table);
912 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
914 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
916 if (!mlx4_is_master(dev))
919 priv->slave_node_guids[slave] = guid;
921 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
923 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
925 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
927 if (!mlx4_is_master(dev))
930 return priv->slave_node_guids[slave];
932 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
934 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
936 struct mlx4_priv *priv = mlx4_priv(dev);
937 struct mlx4_slave_state *s_slave;
939 if (!mlx4_is_master(dev))
942 s_slave = &priv->mfunc.master.slave_state[slave];
943 return !!s_slave->active;
945 EXPORT_SYMBOL(mlx4_is_slave_active);
947 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
948 struct mlx4_dev_cap *dev_cap,
949 struct mlx4_init_hca_param *hca_param)
951 dev->caps.steering_mode = hca_param->steering_mode;
952 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED)
953 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
955 dev->caps.num_qp_per_mgm =
956 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
958 mlx4_dbg(dev, "Steering mode is: %s\n",
959 mlx4_steering_mode_str(dev->caps.steering_mode));
962 static int mlx4_slave_cap(struct mlx4_dev *dev)
966 struct mlx4_dev_cap dev_cap;
967 struct mlx4_func_cap func_cap;
968 struct mlx4_init_hca_param hca_param;
971 memset(&hca_param, 0, sizeof(hca_param));
972 err = mlx4_QUERY_HCA(dev, &hca_param);
974 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
978 /*fail if the hca has an unknown capability */
979 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
980 HCA_GLOBAL_CAP_MASK) {
981 mlx4_err(dev, "Unknown hca global capabilities\n");
985 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
987 dev->caps.hca_core_clock = hca_param.hca_core_clock;
989 memset(&dev_cap, 0, sizeof(dev_cap));
990 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
991 err = mlx4_dev_cap(dev, &dev_cap);
993 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
997 err = mlx4_QUERY_FW(dev);
999 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
1001 if (!hca_param.mw_enable) {
1002 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
1003 dev->caps.bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
1006 page_size = ~dev->caps.page_size_cap + 1;
1007 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
1008 if (page_size > PAGE_SIZE) {
1009 mlx4_err(dev, "HCA minimum page size of %d bigger than "
1010 "kernel PAGE_SIZE of %d, aborting.\n",
1011 page_size, (int)PAGE_SIZE);
1015 /* slave gets uar page size from QUERY_HCA fw command */
1016 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
1018 /* TODO: relax this assumption */
1019 if (dev->caps.uar_page_size != PAGE_SIZE) {
1020 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %d\n",
1021 dev->caps.uar_page_size, (int)PAGE_SIZE);
1025 memset(&func_cap, 0, sizeof(func_cap));
1026 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
1028 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
1033 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
1034 PF_CONTEXT_BEHAVIOUR_MASK) {
1035 mlx4_err(dev, "Unknown pf context behaviour\n");
1039 dev->caps.num_ports = func_cap.num_ports;
1040 dev->quotas.qp = func_cap.qp_quota;
1041 dev->quotas.srq = func_cap.srq_quota;
1042 dev->quotas.cq = func_cap.cq_quota;
1043 dev->quotas.mpt = func_cap.mpt_quota;
1044 dev->quotas.mtt = func_cap.mtt_quota;
1045 dev->caps.num_qps = 1 << hca_param.log_num_qps;
1046 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
1047 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
1048 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
1049 dev->caps.num_eqs = func_cap.max_eq;
1050 dev->caps.reserved_eqs = func_cap.reserved_eq;
1051 dev->caps.num_pds = MLX4_NUM_PDS;
1052 dev->caps.num_mgms = 0;
1053 dev->caps.num_amgms = 0;
1055 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1056 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
1057 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
1061 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1062 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1063 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1064 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1066 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
1067 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
1072 for (i = 1; i <= dev->caps.num_ports; ++i) {
1073 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
1075 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
1076 " port %d, aborting (%d).\n", i, err);
1079 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
1080 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
1081 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
1082 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
1083 dev->caps.def_counter_index[i - 1] = func_cap.def_counter_index;
1085 dev->caps.port_mask[i] = dev->caps.port_type[i];
1086 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
1087 &dev->caps.gid_table_len[i],
1088 &dev->caps.pkey_table_len[i]);
1093 if (dev->caps.uar_page_size * (dev->caps.num_uars -
1094 dev->caps.reserved_uars) >
1095 pci_resource_len(dev->pdev, 2)) {
1096 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
1097 "PCI resource 2 size of 0x%llx, aborting.\n",
1098 dev->caps.uar_page_size * dev->caps.num_uars,
1099 (unsigned long long) pci_resource_len(dev->pdev, 2));
1104 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
1105 dev->caps.eqe_size = 64;
1106 dev->caps.eqe_factor = 1;
1108 dev->caps.eqe_size = 32;
1109 dev->caps.eqe_factor = 0;
1112 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
1113 dev->caps.cqe_size = 64;
1114 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1116 dev->caps.cqe_size = 32;
1119 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1120 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
1122 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
1124 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
1125 dev->caps.bf_reg_size)
1126 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
1131 kfree(dev->caps.qp0_tunnel);
1132 kfree(dev->caps.qp0_proxy);
1133 kfree(dev->caps.qp1_tunnel);
1134 kfree(dev->caps.qp1_proxy);
1135 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
1136 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
1141 static void mlx4_request_modules(struct mlx4_dev *dev)
1144 int has_ib_port = false;
1145 int has_eth_port = false;
1146 #define EN_DRV_NAME "mlx4_en"
1147 #define IB_DRV_NAME "mlx4_ib"
1149 for (port = 1; port <= dev->caps.num_ports; port++) {
1150 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1152 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1153 has_eth_port = true;
1157 request_module_nowait(IB_DRV_NAME);
1159 request_module_nowait(EN_DRV_NAME);
1163 * Change the port configuration of the device.
1164 * Every user of this function must hold the port mutex.
1166 int mlx4_change_port_types(struct mlx4_dev *dev,
1167 enum mlx4_port_type *port_types)
1173 for (port = 0; port < dev->caps.num_ports; port++) {
1174 /* Change the port type only if the new type is different
1175 * from the current, and not set to Auto */
1176 if (port_types[port] != dev->caps.port_type[port + 1])
1180 mlx4_unregister_device(dev);
1181 for (port = 1; port <= dev->caps.num_ports; port++) {
1182 mlx4_CLOSE_PORT(dev, port);
1183 dev->caps.port_type[port] = port_types[port - 1];
1184 err = mlx4_SET_PORT(dev, port, -1);
1186 mlx4_err(dev, "Failed to set port %d, "
1187 "aborting\n", port);
1191 mlx4_set_port_mask(dev);
1192 err = mlx4_register_device(dev);
1194 mlx4_err(dev, "Failed to register device\n");
1197 mlx4_request_modules(dev);
1204 static ssize_t show_port_type(struct device *dev,
1205 struct device_attribute *attr,
1208 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1210 struct mlx4_dev *mdev = info->dev;
1214 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1216 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1217 sprintf(buf, "auto (%s)\n", type);
1219 sprintf(buf, "%s\n", type);
1224 static ssize_t set_port_type(struct device *dev,
1225 struct device_attribute *attr,
1226 const char *buf, size_t count)
1228 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1230 struct mlx4_dev *mdev = info->dev;
1231 struct mlx4_priv *priv = mlx4_priv(mdev);
1232 enum mlx4_port_type types[MLX4_MAX_PORTS];
1233 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1237 if (!strcmp(buf, "ib\n"))
1238 info->tmp_type = MLX4_PORT_TYPE_IB;
1239 else if (!strcmp(buf, "eth\n"))
1240 info->tmp_type = MLX4_PORT_TYPE_ETH;
1241 else if (!strcmp(buf, "auto\n"))
1242 info->tmp_type = MLX4_PORT_TYPE_AUTO;
1244 mlx4_err(mdev, "%s is not supported port type\n", buf);
1248 if ((info->tmp_type & mdev->caps.supported_type[info->port]) !=
1250 mlx4_err(mdev, "Requested port type for port %d is not supported on this HCA\n",
1255 mlx4_stop_sense(mdev);
1256 mutex_lock(&priv->port_mutex);
1257 /* Possible type is always the one that was delivered */
1258 mdev->caps.possible_type[info->port] = info->tmp_type;
1260 for (i = 0; i < mdev->caps.num_ports; i++) {
1261 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1262 mdev->caps.possible_type[i+1];
1263 if (types[i] == MLX4_PORT_TYPE_AUTO)
1264 types[i] = mdev->caps.port_type[i+1];
1267 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1268 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1269 for (i = 1; i <= mdev->caps.num_ports; i++) {
1270 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1271 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1277 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
1278 "Set only 'eth' or 'ib' for both ports "
1279 "(should be the same)\n");
1283 mlx4_do_sense_ports(mdev, new_types, types);
1285 err = mlx4_check_port_params(mdev, new_types);
1289 /* We are about to apply the changes after the configuration
1290 * was verified, no need to remember the temporary types
1292 for (i = 0; i < mdev->caps.num_ports; i++)
1293 priv->port[i + 1].tmp_type = 0;
1295 err = mlx4_change_port_types(mdev, new_types);
1298 mlx4_start_sense(mdev);
1299 mutex_unlock(&priv->port_mutex);
1300 return err ? err : count;
1311 static inline int int_to_ibta_mtu(int mtu)
1314 case 256: return IB_MTU_256;
1315 case 512: return IB_MTU_512;
1316 case 1024: return IB_MTU_1024;
1317 case 2048: return IB_MTU_2048;
1318 case 4096: return IB_MTU_4096;
1323 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1326 case IB_MTU_256: return 256;
1327 case IB_MTU_512: return 512;
1328 case IB_MTU_1024: return 1024;
1329 case IB_MTU_2048: return 2048;
1330 case IB_MTU_4096: return 4096;
1336 show_board(struct device *device, struct device_attribute *attr,
1339 struct mlx4_hca_info *info = container_of(attr, struct mlx4_hca_info,
1341 struct mlx4_dev *mdev = info->dev;
1343 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
1348 show_hca(struct device *device, struct device_attribute *attr,
1351 struct mlx4_hca_info *info = container_of(attr, struct mlx4_hca_info,
1353 struct mlx4_dev *mdev = info->dev;
1355 return sprintf(buf, "MT%d\n", mdev->pdev->device);
1359 show_firmware_version(struct device *dev,
1360 struct device_attribute *attr,
1363 struct mlx4_hca_info *info = container_of(attr, struct mlx4_hca_info,
1365 struct mlx4_dev *mdev = info->dev;
1367 return sprintf(buf, "%d.%d.%d\n", (int)(mdev->caps.fw_ver >> 32),
1368 (int)(mdev->caps.fw_ver >> 16) & 0xffff,
1369 (int)mdev->caps.fw_ver & 0xffff);
1372 static ssize_t show_port_ib_mtu(struct device *dev,
1373 struct device_attribute *attr,
1376 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1378 struct mlx4_dev *mdev = info->dev;
1380 /* When port type is eth, port mtu value isn't used. */
1381 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1384 sprintf(buf, "%d\n",
1385 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1389 static ssize_t set_port_ib_mtu(struct device *dev,
1390 struct device_attribute *attr,
1391 const char *buf, size_t count)
1393 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1395 struct mlx4_dev *mdev = info->dev;
1396 struct mlx4_priv *priv = mlx4_priv(mdev);
1397 int err, port, mtu, ibta_mtu = -1;
1399 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1400 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1404 mtu = (int) simple_strtol(buf, NULL, 0);
1405 ibta_mtu = int_to_ibta_mtu(mtu);
1408 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1412 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1414 mlx4_stop_sense(mdev);
1415 mutex_lock(&priv->port_mutex);
1416 mlx4_unregister_device(mdev);
1417 for (port = 1; port <= mdev->caps.num_ports; port++) {
1418 mlx4_CLOSE_PORT(mdev, port);
1419 err = mlx4_SET_PORT(mdev, port, -1);
1421 mlx4_err(mdev, "Failed to set port %d, "
1422 "aborting\n", port);
1426 err = mlx4_register_device(mdev);
1428 mutex_unlock(&priv->port_mutex);
1429 mlx4_start_sense(mdev);
1430 return err ? err : count;
1433 static int mlx4_load_fw(struct mlx4_dev *dev)
1435 struct mlx4_priv *priv = mlx4_priv(dev);
1436 int err, unmap_flag = 0;
1438 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1439 GFP_HIGHUSER | __GFP_NOWARN, 0);
1440 if (!priv->fw.fw_icm) {
1441 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
1445 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1447 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
1451 err = mlx4_RUN_FW(dev);
1453 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1460 unmap_flag = mlx4_UNMAP_FA(dev);
1462 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n");
1466 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1470 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1473 struct mlx4_priv *priv = mlx4_priv(dev);
1477 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1479 ((u64) (MLX4_CMPT_TYPE_QP *
1480 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1481 cmpt_entry_sz, dev->caps.num_qps,
1482 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1487 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1489 ((u64) (MLX4_CMPT_TYPE_SRQ *
1490 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1491 cmpt_entry_sz, dev->caps.num_srqs,
1492 dev->caps.reserved_srqs, 0, 0);
1496 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1498 ((u64) (MLX4_CMPT_TYPE_CQ *
1499 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1500 cmpt_entry_sz, dev->caps.num_cqs,
1501 dev->caps.reserved_cqs, 0, 0);
1505 num_eqs = dev->phys_caps.num_phys_eqs;
1506 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1508 ((u64) (MLX4_CMPT_TYPE_EQ *
1509 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1510 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1517 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1520 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1523 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1529 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1530 struct mlx4_init_hca_param *init_hca, u64 icm_size)
1532 struct mlx4_priv *priv = mlx4_priv(dev);
1535 int err, unmap_flag = 0;
1537 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1539 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1543 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1544 (unsigned long long) icm_size >> 10,
1545 (unsigned long long) aux_pages << 2);
1547 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1548 GFP_HIGHUSER | __GFP_NOWARN, 0);
1549 if (!priv->fw.aux_icm) {
1550 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1554 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1556 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1560 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1562 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1567 num_eqs = dev->phys_caps.num_phys_eqs;
1568 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1569 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1570 num_eqs, num_eqs, 0, 0);
1572 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1573 goto err_unmap_cmpt;
1577 * Reserved MTT entries must be aligned up to a cacheline
1578 * boundary, since the FW will write to them, while the driver
1579 * writes to all other MTT entries. (The variable
1580 * dev->caps.mtt_entry_sz below is really the MTT segment
1581 * size, not the raw entry size)
1583 dev->caps.reserved_mtts =
1584 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1585 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1587 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1589 dev->caps.mtt_entry_sz,
1591 dev->caps.reserved_mtts, 1, 0);
1593 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1597 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1598 init_hca->dmpt_base,
1599 dev_cap->dmpt_entry_sz,
1601 dev->caps.reserved_mrws, 1, 1);
1603 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1607 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1609 dev_cap->qpc_entry_sz,
1611 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1614 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1615 goto err_unmap_dmpt;
1618 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1619 init_hca->auxc_base,
1620 dev_cap->aux_entry_sz,
1622 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1625 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1629 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1630 init_hca->altc_base,
1631 dev_cap->altc_entry_sz,
1633 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1636 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1637 goto err_unmap_auxc;
1640 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1641 init_hca->rdmarc_base,
1642 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1644 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1647 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1648 goto err_unmap_altc;
1651 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1653 dev_cap->cqc_entry_sz,
1655 dev->caps.reserved_cqs, 0, 0);
1657 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1658 goto err_unmap_rdmarc;
1661 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1662 init_hca->srqc_base,
1663 dev_cap->srq_entry_sz,
1665 dev->caps.reserved_srqs, 0, 0);
1667 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1672 * For flow steering device managed mode it is required to use
1673 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1674 * required, but for simplicity just map the whole multicast
1675 * group table now. The table isn't very big and it's a lot
1676 * easier than trying to track ref counts.
1678 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1680 mlx4_get_mgm_entry_size(dev),
1681 dev->caps.num_mgms + dev->caps.num_amgms,
1682 dev->caps.num_mgms + dev->caps.num_amgms,
1685 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1692 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1695 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1698 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1701 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1704 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1707 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1710 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1713 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1716 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1719 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1720 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1721 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1722 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1725 unmap_flag = mlx4_UNMAP_ICM_AUX(dev);
1727 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n");
1731 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1736 static void mlx4_free_icms(struct mlx4_dev *dev)
1738 struct mlx4_priv *priv = mlx4_priv(dev);
1740 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1741 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1742 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1743 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1744 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1745 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1746 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1747 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1748 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1749 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1750 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1751 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1752 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1753 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1755 if (!mlx4_UNMAP_ICM_AUX(dev))
1756 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1758 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n");
1761 static void mlx4_slave_exit(struct mlx4_dev *dev)
1763 struct mlx4_priv *priv = mlx4_priv(dev);
1765 mutex_lock(&priv->cmd.slave_cmd_mutex);
1766 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1767 mlx4_warn(dev, "Failed to close slave function.\n");
1768 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1771 static int map_bf_area(struct mlx4_dev *dev)
1773 struct mlx4_priv *priv = mlx4_priv(dev);
1774 resource_size_t bf_start;
1775 resource_size_t bf_len;
1778 if (!dev->caps.bf_reg_size)
1781 bf_start = pci_resource_start(dev->pdev, 2) +
1782 (dev->caps.num_uars << PAGE_SHIFT);
1783 bf_len = pci_resource_len(dev->pdev, 2) -
1784 (dev->caps.num_uars << PAGE_SHIFT);
1785 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1786 if (!priv->bf_mapping)
1792 static void unmap_bf_area(struct mlx4_dev *dev)
1794 if (mlx4_priv(dev)->bf_mapping)
1795 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1798 int mlx4_read_clock(struct mlx4_dev *dev)
1800 u32 clockhi, clocklo, clockhi1;
1803 struct mlx4_priv *priv = mlx4_priv(dev);
1805 if (!priv->clock_mapping)
1808 for (i = 0; i < 10; i++) {
1809 clockhi = swab32(readl(priv->clock_mapping));
1810 clocklo = swab32(readl(priv->clock_mapping + 4));
1811 clockhi1 = swab32(readl(priv->clock_mapping));
1812 if (clockhi == clockhi1)
1816 cycles = (u64) clockhi << 32 | (u64) clocklo;
1820 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1823 static int map_internal_clock(struct mlx4_dev *dev)
1825 struct mlx4_priv *priv = mlx4_priv(dev);
1827 priv->clock_mapping = ioremap(pci_resource_start(dev->pdev,
1828 priv->fw.clock_bar) +
1829 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1831 if (!priv->clock_mapping)
1838 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1839 struct mlx4_clock_params *params)
1841 struct mlx4_priv *priv = mlx4_priv(dev);
1843 if (mlx4_is_slave(dev))
1848 params->bar = priv->fw.clock_bar;
1849 params->offset = priv->fw.clock_offset;
1850 params->size = MLX4_CLOCK_SIZE;
1854 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1856 static void unmap_internal_clock(struct mlx4_dev *dev)
1858 struct mlx4_priv *priv = mlx4_priv(dev);
1860 if (priv->clock_mapping)
1861 iounmap(priv->clock_mapping);
1864 static void mlx4_close_hca(struct mlx4_dev *dev)
1866 unmap_internal_clock(dev);
1868 if (mlx4_is_slave(dev)) {
1869 mlx4_slave_exit(dev);
1871 mlx4_CLOSE_HCA(dev, 0);
1872 mlx4_free_icms(dev);
1874 if (!mlx4_UNMAP_FA(dev))
1875 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1877 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n");
1881 static int mlx4_init_slave(struct mlx4_dev *dev)
1883 struct mlx4_priv *priv = mlx4_priv(dev);
1884 u64 dma = (u64) priv->mfunc.vhcr_dma;
1885 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1886 int ret_from_reset = 0;
1888 u32 cmd_channel_ver;
1890 mutex_lock(&priv->cmd.slave_cmd_mutex);
1891 priv->cmd.max_cmds = 1;
1892 mlx4_warn(dev, "Sending reset\n");
1893 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1895 /* if we are in the middle of flr the slave will try
1896 * NUM_OF_RESET_RETRIES times before leaving.*/
1897 if (ret_from_reset) {
1898 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1899 msleep(SLEEP_TIME_IN_RESET);
1900 while (ret_from_reset && num_of_reset_retries) {
1901 mlx4_warn(dev, "slave is currently in the"
1902 "middle of FLR. retrying..."
1904 (NUM_OF_RESET_RETRIES -
1905 num_of_reset_retries + 1));
1907 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1909 num_of_reset_retries = num_of_reset_retries - 1;
1915 /* check the driver version - the slave I/F revision
1916 * must match the master's */
1917 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1918 cmd_channel_ver = mlx4_comm_get_version();
1920 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1921 MLX4_COMM_GET_IF_REV(slave_read)) {
1922 mlx4_err(dev, "slave driver version is not supported"
1923 " by the master\n");
1927 mlx4_warn(dev, "Sending vhcr0\n");
1928 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1931 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1934 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1937 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1940 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1944 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1945 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1949 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1953 for (i = 1; i <= dev->caps.num_ports; i++) {
1954 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1955 dev->caps.gid_table_len[i] =
1956 mlx4_get_slave_num_gids(dev, 0);
1958 dev->caps.gid_table_len[i] = 1;
1959 dev->caps.pkey_table_len[i] =
1960 dev->phys_caps.pkey_phys_table_len[i] - 1;
1964 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1966 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1968 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1970 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1974 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1977 static void choose_steering_mode(struct mlx4_dev *dev,
1978 struct mlx4_dev_cap *dev_cap)
1982 mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(dev->pdev), 0, &nvfs);
1983 if (high_rate_steer && !mlx4_is_mfunc(dev)) {
1984 dev->caps.flags &= ~(MLX4_DEV_CAP_FLAG_VEP_MC_STEER |
1985 MLX4_DEV_CAP_FLAG_VEP_UC_STEER);
1986 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_FS_EN;
1989 if (mlx4_log_num_mgm_entry_size == -1 &&
1990 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1991 (!mlx4_is_mfunc(dev) ||
1992 (dev_cap->fs_max_num_qp_per_entry >= (nvfs + 1))) &&
1993 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1994 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1995 dev->oper_log_mgm_entry_size =
1996 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1997 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1998 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2000 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2001 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2002 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2004 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2006 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2007 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2008 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
2009 "set to use B0 steering. Falling back to A0 steering mode.\n");
2011 dev->oper_log_mgm_entry_size =
2012 mlx4_log_num_mgm_entry_size > 0 ?
2013 mlx4_log_num_mgm_entry_size :
2014 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
2015 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2017 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
2018 "log_num_mgm_entry_size = %d\n",
2019 mlx4_steering_mode_str(dev->caps.steering_mode),
2020 dev->oper_log_mgm_entry_size, mlx4_log_num_mgm_entry_size);
2023 static int mlx4_init_hca(struct mlx4_dev *dev)
2025 struct mlx4_priv *priv = mlx4_priv(dev);
2026 struct mlx4_dev_cap *dev_cap = NULL;
2027 struct mlx4_adapter adapter;
2028 struct mlx4_mod_stat_cfg mlx4_cfg;
2029 struct mlx4_profile profile;
2030 struct mlx4_init_hca_param init_hca;
2034 if (!mlx4_is_slave(dev)) {
2035 err = mlx4_QUERY_FW(dev);
2038 mlx4_info(dev, "non-primary physical function, skipping.\n");
2040 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
2044 err = mlx4_load_fw(dev);
2046 mlx4_err(dev, "Failed to start FW, aborting.\n");
2050 mlx4_cfg.log_pg_sz_m = 1;
2051 mlx4_cfg.log_pg_sz = 0;
2052 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2054 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2056 dev_cap = kzalloc(sizeof *dev_cap, GFP_KERNEL);
2058 mlx4_err(dev, "Failed to allocate memory for dev_cap\n");
2063 err = mlx4_dev_cap(dev, dev_cap);
2065 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2069 choose_steering_mode(dev, dev_cap);
2071 if (mlx4_is_master(dev))
2072 mlx4_parav_master_pf_caps(dev);
2074 process_mod_param_profile(&profile);
2075 if (dev->caps.steering_mode ==
2076 MLX4_STEERING_MODE_DEVICE_MANAGED)
2077 profile.num_mcg = MLX4_FS_NUM_MCG;
2079 icm_size = mlx4_make_profile(dev, &profile, dev_cap,
2081 if ((long long) icm_size < 0) {
2086 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2088 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2089 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2091 err = mlx4_init_icm(dev, dev_cap, &init_hca, icm_size);
2095 init_hca.mw_enable = 1;
2097 err = mlx4_INIT_HCA(dev, &init_hca);
2099 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
2103 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2104 err = mlx4_query_func(dev, dev_cap);
2106 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2108 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2109 dev->caps.num_eqs = dev_cap->max_eqs;
2110 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2111 dev->caps.reserved_uars = dev_cap->reserved_uars;
2116 * Read HCA frequency by QUERY_HCA command
2118 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2119 memset(&init_hca, 0, sizeof(init_hca));
2120 err = mlx4_QUERY_HCA(dev, &init_hca);
2122 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
2123 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2125 dev->caps.hca_core_clock =
2126 init_hca.hca_core_clock;
2129 /* In case we got HCA frequency 0 - disable timestamping
2130 * to avoid dividing by zero
2132 if (!dev->caps.hca_core_clock) {
2133 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2134 mlx4_err(dev, "HCA frequency is 0. Timestamping is not supported.");
2135 } else if (map_internal_clock(dev)) {
2136 /* Map internal clock,
2137 * in case of failure disable timestamping
2139 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2140 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
2144 err = mlx4_init_slave(dev);
2146 mlx4_err(dev, "Failed to initialize slave\n");
2150 err = mlx4_slave_cap(dev);
2152 mlx4_err(dev, "Failed to obtain slave caps\n");
2157 if (map_bf_area(dev))
2158 mlx4_dbg(dev, "Failed to map blue flame area\n");
2160 /* Only the master set the ports, all the rest got it from it.*/
2161 if (!mlx4_is_slave(dev))
2162 mlx4_set_port_mask(dev);
2164 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2166 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
2170 priv->eq_table.inta_pin = adapter.inta_pin;
2171 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2172 memcpy(dev->vsd, adapter.vsd, sizeof(dev->vsd));
2173 dev->vsd_vendor_id = adapter.vsd_vendor_id;
2175 if (!mlx4_is_slave(dev))
2181 if (!mlx4_is_slave(dev))
2182 unmap_internal_clock(dev);
2185 if (mlx4_is_slave(dev)) {
2186 kfree(dev->caps.qp0_tunnel);
2187 kfree(dev->caps.qp0_proxy);
2188 kfree(dev->caps.qp1_tunnel);
2189 kfree(dev->caps.qp1_proxy);
2193 if (mlx4_is_slave(dev))
2194 mlx4_slave_exit(dev);
2196 mlx4_CLOSE_HCA(dev, 0);
2199 if (!mlx4_is_slave(dev))
2200 mlx4_free_icms(dev);
2203 if (!mlx4_is_slave(dev)) {
2204 if (!mlx4_UNMAP_FA(dev))
2205 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
2207 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n");
2213 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2215 struct mlx4_priv *priv = mlx4_priv(dev);
2216 int nent_pow2, port_indx, vf_index, num_counters;
2218 struct counter_index *new_counter_index;
2221 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2224 if (!mlx4_is_slave(dev) &&
2225 dev->caps.max_counters == dev->caps.max_extended_counters) {
2226 res = mlx4_cmd(dev, MLX4_IF_STATE_EXTENDED, 0, 0,
2227 MLX4_CMD_SET_IF_STAT,
2228 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2230 mlx4_err(dev, "Failed to set extended counters (err=%d)\n", res);
2235 mutex_init(&priv->counters_table.mutex);
2237 if (mlx4_is_slave(dev)) {
2238 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) {
2239 INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]);
2240 if (dev->caps.def_counter_index[port_indx] != 0xFF) {
2241 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2242 if (!new_counter_index)
2244 new_counter_index->index = dev->caps.def_counter_index[port_indx];
2245 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port_indx]);
2248 mlx4_dbg(dev, "%s: slave allocated %d counters for %d ports\n",
2249 __func__, dev->caps.num_ports, dev->caps.num_ports);
2253 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2255 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) {
2256 INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]);
2257 /* allocating 2 counters per port for PFs */
2258 /* For the PF, the ETH default counters are 0,2; */
2259 /* and the RoCE default counters are 1,3 */
2260 for (num_counters = 0; num_counters < 2; num_counters++, index++) {
2261 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2262 if (!new_counter_index)
2264 new_counter_index->index = index;
2265 list_add_tail(&new_counter_index->list,
2266 &priv->counters_table.global_port_list[port_indx]);
2270 if (mlx4_is_master(dev)) {
2271 for (vf_index = 0; vf_index < dev->num_vfs; vf_index++) {
2272 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) {
2273 INIT_LIST_HEAD(&priv->counters_table.vf_list[vf_index][port_indx]);
2274 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2275 if (!new_counter_index)
2277 if (index < nent_pow2 - 2) {
2278 new_counter_index->index = index;
2281 new_counter_index->index = MLX4_SINK_COUNTER_INDEX;
2284 list_add_tail(&new_counter_index->list,
2285 &priv->counters_table.vf_list[vf_index][port_indx]);
2289 res = mlx4_bitmap_init(&priv->counters_table.bitmap,
2290 nent_pow2, nent_pow2 - 1,
2292 mlx4_dbg(dev, "%s: master allocated %d counters for %d VFs\n",
2293 __func__, index, dev->num_vfs);
2295 res = mlx4_bitmap_init(&priv->counters_table.bitmap,
2296 nent_pow2, nent_pow2 - 1,
2298 mlx4_dbg(dev, "%s: native allocated %d counters for %d ports\n",
2299 __func__, index, dev->caps.num_ports);
2306 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2308 struct mlx4_priv *priv = mlx4_priv(dev);
2310 struct counter_index *port, *tmp_port;
2311 struct counter_index *vf, *tmp_vf;
2313 mutex_lock(&priv->counters_table.mutex);
2315 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) {
2316 for (i = 0; i < dev->caps.num_ports; i++) {
2317 list_for_each_entry_safe(port, tmp_port,
2318 &priv->counters_table.global_port_list[i],
2320 list_del(&port->list);
2324 if (!mlx4_is_slave(dev)) {
2325 for (i = 0; i < dev->num_vfs; i++) {
2326 for (j = 0; j < dev->caps.num_ports; j++) {
2327 list_for_each_entry_safe(vf, tmp_vf,
2328 &priv->counters_table.vf_list[i][j],
2330 /* clear the counter statistic */
2331 if (__mlx4_clear_if_stat(dev, vf->index))
2332 mlx4_dbg(dev, "%s: reset counter %d failed\n",
2333 __func__, vf->index);
2334 list_del(&vf->list);
2339 mlx4_bitmap_cleanup(&priv->counters_table.bitmap);
2342 mutex_unlock(&priv->counters_table.mutex);
2345 int __mlx4_slave_counters_free(struct mlx4_dev *dev, int slave)
2347 struct mlx4_priv *priv = mlx4_priv(dev);
2349 struct counter_index *vf, *tmp_vf;
2351 /* clean VF's counters for the next useg */
2352 if (slave > 0 && slave <= dev->num_vfs) {
2353 mlx4_dbg(dev, "%s: free counters of slave(%d)\n"
2356 mutex_lock(&priv->counters_table.mutex);
2357 for (i = 0; i < dev->caps.num_ports; i++) {
2359 list_for_each_entry_safe(vf, tmp_vf,
2360 &priv->counters_table.vf_list[slave - 1][i],
2362 /* clear the counter statistic */
2363 if (__mlx4_clear_if_stat(dev, vf->index))
2364 mlx4_dbg(dev, "%s: reset counter %d failed\n",
2365 __func__, vf->index);
2366 if (first++ && vf->index != MLX4_SINK_COUNTER_INDEX) {
2367 mlx4_dbg(dev, "%s: delete counter index %d for slave %d and port %d\n"
2368 , __func__, vf->index, slave, i + 1);
2369 mlx4_bitmap_free(&priv->counters_table.bitmap, vf->index, MLX4_USE_RR);
2370 list_del(&vf->list);
2373 mlx4_dbg(dev, "%s: can't delete default counter index %d for slave %d and port %d\n"
2374 , __func__, vf->index, slave, i + 1);
2378 mutex_unlock(&priv->counters_table.mutex);
2384 int __mlx4_counter_alloc(struct mlx4_dev *dev, int slave, int port, u32 *idx)
2386 struct mlx4_priv *priv = mlx4_priv(dev);
2387 struct counter_index *new_counter_index;
2389 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2392 if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) ||
2393 (port < 0) || (port > MLX4_MAX_PORTS)) {
2394 mlx4_dbg(dev, "%s: invalid slave(%d) or port(%d) index\n",
2395 __func__, slave, port);
2399 /* handle old guest request does not support request by port index */
2401 *idx = MLX4_SINK_COUNTER_INDEX;
2402 mlx4_dbg(dev, "%s: allocated default counter index %d for slave %d port %d\n"
2403 , __func__, *idx, slave, port);
2407 mutex_lock(&priv->counters_table.mutex);
2409 *idx = mlx4_bitmap_alloc(&priv->counters_table.bitmap);
2410 /* if no resources return the default counter of the slave and port */
2412 if (slave == 0) { /* its the ethernet counter ?????? */
2413 new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next,
2414 struct counter_index,
2417 new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next,
2418 struct counter_index,
2422 *idx = new_counter_index->index;
2423 mlx4_dbg(dev, "%s: allocated defualt counter index %d for slave %d port %d\n"
2424 , __func__, *idx, slave, port);
2428 if (slave == 0) { /* native or master */
2429 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2430 if (!new_counter_index)
2432 new_counter_index->index = *idx;
2433 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]);
2435 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2436 if (!new_counter_index)
2438 new_counter_index->index = *idx;
2439 list_add_tail(&new_counter_index->list, &priv->counters_table.vf_list[slave - 1][port - 1]);
2442 mlx4_dbg(dev, "%s: allocated counter index %d for slave %d port %d\n"
2443 , __func__, *idx, slave, port);
2445 mutex_unlock(&priv->counters_table.mutex);
2449 mlx4_bitmap_free(&priv->counters_table.bitmap, *idx, MLX4_USE_RR);
2450 mutex_unlock(&priv->counters_table.mutex);
2451 *idx = MLX4_SINK_COUNTER_INDEX;
2452 mlx4_dbg(dev, "%s: failed err (%d)\n"
2453 , __func__, -ENOMEM);
2457 int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx)
2461 struct mlx4_priv *priv = mlx4_priv(dev);
2462 struct counter_index *new_counter_index, *c_index;
2464 if (mlx4_is_mfunc(dev)) {
2465 err = mlx4_cmd_imm(dev, 0, &out_param,
2466 ((u32) port) << 8 | (u32) RES_COUNTER,
2467 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2468 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2470 *idx = get_param_l(&out_param);
2471 if (*idx == MLX4_SINK_COUNTER_INDEX)
2474 mutex_lock(&priv->counters_table.mutex);
2475 c_index = list_entry(priv->counters_table.global_port_list[port - 1].next,
2476 struct counter_index,
2478 mutex_unlock(&priv->counters_table.mutex);
2479 if (c_index->index == *idx)
2482 if (mlx4_is_slave(dev)) {
2483 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2484 if (!new_counter_index) {
2485 mlx4_counter_free(dev, port, *idx);
2488 new_counter_index->index = *idx;
2489 mutex_lock(&priv->counters_table.mutex);
2490 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]);
2491 mutex_unlock(&priv->counters_table.mutex);
2492 mlx4_dbg(dev, "%s: allocated counter index %d for port %d\n"
2493 , __func__, *idx, port);
2498 return __mlx4_counter_alloc(dev, 0, port, idx);
2500 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2502 void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, u32 idx)
2504 /* check if native or slave and deletes acordingly */
2505 struct mlx4_priv *priv = mlx4_priv(dev);
2506 struct counter_index *pf, *tmp_pf;
2507 struct counter_index *vf, *tmp_vf;
2511 if (idx == MLX4_SINK_COUNTER_INDEX) {
2512 mlx4_dbg(dev, "%s: try to delete default counter index %d for port %d\n"
2513 , __func__, idx, port);
2517 if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) ||
2518 (port < 0) || (port > MLX4_MAX_PORTS)) {
2519 mlx4_warn(dev, "%s: deletion failed due to invalid slave(%d) or port(%d) index\n"
2520 , __func__, slave, idx);
2524 mutex_lock(&priv->counters_table.mutex);
2527 list_for_each_entry_safe(pf, tmp_pf,
2528 &priv->counters_table.global_port_list[port - 1],
2530 /* the first 2 counters are reserved */
2531 if (pf->index == idx) {
2532 /* clear the counter statistic */
2533 if (__mlx4_clear_if_stat(dev, pf->index))
2534 mlx4_dbg(dev, "%s: reset counter %d failed\n",
2535 __func__, pf->index);
2536 if (1 < first && idx != MLX4_SINK_COUNTER_INDEX) {
2537 list_del(&pf->list);
2539 mlx4_dbg(dev, "%s: delete counter index %d for native device (%d) port %d\n"
2540 , __func__, idx, slave, port);
2541 mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR);
2544 mlx4_dbg(dev, "%s: can't delete default counter index %d for native device (%d) port %d\n"
2545 , __func__, idx, slave, port);
2551 mlx4_dbg(dev, "%s: can't delete counter index %d for native device (%d) port %d\n"
2552 , __func__, idx, slave, port);
2555 list_for_each_entry_safe(vf, tmp_vf,
2556 &priv->counters_table.vf_list[slave - 1][port - 1],
2558 /* the first element is reserved */
2559 if (vf->index == idx) {
2560 /* clear the counter statistic */
2561 if (__mlx4_clear_if_stat(dev, vf->index))
2562 mlx4_dbg(dev, "%s: reset counter %d failed\n",
2563 __func__, vf->index);
2565 list_del(&vf->list);
2567 mlx4_dbg(dev, "%s: delete counter index %d for slave %d port %d\n",
2568 __func__, idx, slave, port);
2569 mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR);
2572 mlx4_dbg(dev, "%s: can't delete default slave (%d) counter index %d for port %d\n"
2573 , __func__, slave, idx, port);
2579 mlx4_dbg(dev, "%s: can't delete slave (%d) counter index %d for port %d\n"
2580 , __func__, slave, idx, port);
2584 mutex_unlock(&priv->counters_table.mutex);
2587 void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx)
2590 struct mlx4_priv *priv = mlx4_priv(dev);
2591 struct counter_index *counter, *tmp_counter;
2594 if (mlx4_is_mfunc(dev)) {
2595 set_param_l(&in_param, idx);
2596 mlx4_cmd(dev, in_param,
2597 ((u32) port) << 8 | (u32) RES_COUNTER,
2599 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2602 if (mlx4_is_slave(dev) && idx != MLX4_SINK_COUNTER_INDEX) {
2603 mutex_lock(&priv->counters_table.mutex);
2604 list_for_each_entry_safe(counter, tmp_counter,
2605 &priv->counters_table.global_port_list[port - 1],
2607 if (counter->index == idx && first++) {
2608 list_del(&counter->list);
2610 mlx4_dbg(dev, "%s: delete counter index %d for port %d\n"
2611 , __func__, idx, port);
2612 mutex_unlock(&priv->counters_table.mutex);
2616 mutex_unlock(&priv->counters_table.mutex);
2621 __mlx4_counter_free(dev, 0, port, idx);
2623 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2625 int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2628 struct mlx4_cmd_mailbox *if_stat_mailbox = NULL;
2630 u32 if_stat_in_mod = (counter_index & 0xff) | (1 << 31);
2632 if (counter_index == MLX4_SINK_COUNTER_INDEX)
2635 if (mlx4_is_slave(dev))
2638 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2639 if (IS_ERR(if_stat_mailbox)) {
2640 err = PTR_ERR(if_stat_mailbox);
2644 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2645 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2648 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2652 u8 mlx4_get_default_counter_index(struct mlx4_dev *dev, int slave, int port)
2654 struct mlx4_priv *priv = mlx4_priv(dev);
2655 struct counter_index *new_counter_index;
2657 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) {
2658 mlx4_dbg(dev, "%s: return counter index %d for slave %d port (MLX4_PORT_TYPE_IB) %d\n",
2659 __func__, MLX4_SINK_COUNTER_INDEX, slave, port);
2660 return (u8)MLX4_SINK_COUNTER_INDEX;
2663 mutex_lock(&priv->counters_table.mutex);
2665 new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next,
2666 struct counter_index,
2669 new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next,
2670 struct counter_index,
2673 mutex_unlock(&priv->counters_table.mutex);
2675 mlx4_dbg(dev, "%s: return counter index %d for slave %d port %d\n",
2676 __func__, new_counter_index->index, slave, port);
2679 return (u8)new_counter_index->index;
2682 int mlx4_get_vport_ethtool_stats(struct mlx4_dev *dev, int port,
2683 struct mlx4_en_vport_stats *vport_stats,
2686 struct mlx4_priv *priv = mlx4_priv(dev);
2687 struct mlx4_cmd_mailbox *if_stat_mailbox = NULL;
2688 union mlx4_counter *counter;
2691 struct counter_index *vport, *tmp_vport;
2696 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2697 if (IS_ERR(if_stat_mailbox)) {
2698 err = PTR_ERR(if_stat_mailbox);
2702 mutex_lock(&priv->counters_table.mutex);
2703 list_for_each_entry_safe(vport, tmp_vport,
2704 &priv->counters_table.global_port_list[port - 1],
2706 if (vport->index == MLX4_SINK_COUNTER_INDEX)
2709 memset(if_stat_mailbox->buf, 0, sizeof(union mlx4_counter));
2710 if_stat_in_mod = (vport->index & 0xff) | ((reset & 1) << 31);
2711 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma,
2713 MLX4_CMD_QUERY_IF_STAT,
2714 MLX4_CMD_TIME_CLASS_C,
2717 mlx4_dbg(dev, "%s: failed to read statistics for counter index %d\n",
2718 __func__, vport->index);
2721 counter = (union mlx4_counter *)if_stat_mailbox->buf;
2722 if ((counter->control.cnt_mode & 0xf) == 1) {
2723 vport_stats->rx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastFrames);
2724 vport_stats->rx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxUnicastFrames);
2725 vport_stats->rx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxMulticastFrames);
2726 vport_stats->tx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastFrames);
2727 vport_stats->tx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxUnicastFrames);
2728 vport_stats->tx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxMulticastFrames);
2729 vport_stats->rx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastOctets);
2730 vport_stats->rx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxUnicastOctets);
2731 vport_stats->rx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxMulticastOctets);
2732 vport_stats->tx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastOctets);
2733 vport_stats->tx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxUnicastOctets);
2734 vport_stats->tx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxMulticastOctets);
2735 vport_stats->rx_errors += be64_to_cpu(counter->ext.counters[0].IfRxErrorFrames);
2736 vport_stats->rx_dropped += be64_to_cpu(counter->ext.counters[0].IfRxNoBufferFrames);
2737 vport_stats->tx_errors += be64_to_cpu(counter->ext.counters[0].IfTxDroppedFrames);
2742 mutex_unlock(&priv->counters_table.mutex);
2743 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2747 EXPORT_SYMBOL_GPL(mlx4_get_vport_ethtool_stats);
2749 static int mlx4_setup_hca(struct mlx4_dev *dev)
2751 struct mlx4_priv *priv = mlx4_priv(dev);
2754 __be32 ib_port_default_caps;
2756 err = mlx4_init_uar_table(dev);
2758 mlx4_err(dev, "Failed to initialize "
2759 "user access region table (err=%d), aborting.\n",
2764 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2766 mlx4_err(dev, "Failed to allocate driver access region "
2767 "(err=%d), aborting.\n", err);
2768 goto err_uar_table_free;
2771 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2773 mlx4_err(dev, "Couldn't map kernel access region, "
2779 err = mlx4_init_pd_table(dev);
2781 mlx4_err(dev, "Failed to initialize "
2782 "protection domain table (err=%d), aborting.\n", err);
2786 err = mlx4_init_xrcd_table(dev);
2788 mlx4_err(dev, "Failed to initialize "
2789 "reliable connection domain table (err=%d), "
2790 "aborting.\n", err);
2791 goto err_pd_table_free;
2794 err = mlx4_init_mr_table(dev);
2796 mlx4_err(dev, "Failed to initialize "
2797 "memory region table (err=%d), aborting.\n", err);
2798 goto err_xrcd_table_free;
2801 if (!mlx4_is_slave(dev)) {
2802 err = mlx4_init_mcg_table(dev);
2804 mlx4_err(dev, "Failed to initialize "
2805 "multicast group table (err=%d), aborting.\n",
2807 goto err_mr_table_free;
2811 err = mlx4_init_eq_table(dev);
2813 mlx4_err(dev, "Failed to initialize "
2814 "event queue table (err=%d), aborting.\n", err);
2815 goto err_mcg_table_free;
2818 err = mlx4_cmd_use_events(dev);
2820 mlx4_err(dev, "Failed to switch to event-driven "
2821 "firmware commands (err=%d), aborting.\n", err);
2822 goto err_eq_table_free;
2825 err = mlx4_NOP(dev);
2827 if (dev->flags & MLX4_FLAG_MSI_X) {
2828 mlx4_warn(dev, "NOP command failed to generate MSI-X "
2829 "interrupt IRQ %d).\n",
2830 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2831 mlx4_warn(dev, "Trying again without MSI-X.\n");
2833 mlx4_err(dev, "NOP command failed to generate interrupt "
2834 "(IRQ %d), aborting.\n",
2835 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2836 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2842 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2844 err = mlx4_init_cq_table(dev);
2846 mlx4_err(dev, "Failed to initialize "
2847 "completion queue table (err=%d), aborting.\n", err);
2851 err = mlx4_init_srq_table(dev);
2853 mlx4_err(dev, "Failed to initialize "
2854 "shared receive queue table (err=%d), aborting.\n",
2856 goto err_cq_table_free;
2859 err = mlx4_init_qp_table(dev);
2861 mlx4_err(dev, "Failed to initialize "
2862 "queue pair table (err=%d), aborting.\n", err);
2863 goto err_srq_table_free;
2866 err = mlx4_init_counters_table(dev);
2867 if (err && err != -ENOENT) {
2868 mlx4_err(dev, "Failed to initialize counters table (err=%d), "
2869 "aborting.\n", err);
2870 goto err_qp_table_free;
2873 if (!mlx4_is_slave(dev)) {
2874 for (port = 1; port <= dev->caps.num_ports; port++) {
2875 ib_port_default_caps = 0;
2876 err = mlx4_get_port_ib_caps(dev, port,
2877 &ib_port_default_caps);
2879 mlx4_warn(dev, "failed to get port %d default "
2880 "ib capabilities (%d). Continuing "
2881 "with caps = 0\n", port, err);
2882 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2884 /* initialize per-slave default ib port capabilities */
2885 if (mlx4_is_master(dev)) {
2887 for (i = 0; i < dev->num_slaves; i++) {
2888 if (i == mlx4_master_func_num(dev))
2890 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2891 ib_port_default_caps;
2895 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2897 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2898 dev->caps.pkey_table_len[port] : -1);
2900 mlx4_err(dev, "Failed to set port %d (err=%d), "
2901 "aborting\n", port, err);
2902 goto err_counters_table_free;
2909 err_counters_table_free:
2910 mlx4_cleanup_counters_table(dev);
2913 mlx4_cleanup_qp_table(dev);
2916 mlx4_cleanup_srq_table(dev);
2919 mlx4_cleanup_cq_table(dev);
2922 mlx4_cmd_use_polling(dev);
2925 mlx4_cleanup_eq_table(dev);
2928 if (!mlx4_is_slave(dev))
2929 mlx4_cleanup_mcg_table(dev);
2932 mlx4_cleanup_mr_table(dev);
2934 err_xrcd_table_free:
2935 mlx4_cleanup_xrcd_table(dev);
2938 mlx4_cleanup_pd_table(dev);
2944 mlx4_uar_free(dev, &priv->driver_uar);
2947 mlx4_cleanup_uar_table(dev);
2951 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2953 struct mlx4_priv *priv = mlx4_priv(dev);
2954 struct msix_entry *entries;
2959 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2961 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2964 if (msi_x > 1 && !mlx4_is_mfunc(dev))
2965 nreq = min_t(int, nreq, msi_x);
2967 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2971 for (i = 0; i < nreq; ++i)
2972 entries[i].entry = i;
2975 err = pci_enable_msix(dev->pdev, entries, nreq);
2977 /* Try again if at least 2 vectors are available */
2979 mlx4_info(dev, "Requested %d vectors, "
2980 "but only %d MSI-X vectors available, "
2981 "trying again\n", nreq, err);
2986 /* if error, or can't alloc even 1 IRQ */
2988 mlx4_err(dev, "No IRQs left, device can't "
2996 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
2997 /*Working in legacy mode , all EQ's shared*/
2998 dev->caps.comp_pool = 0;
2999 dev->caps.num_comp_vectors = nreq - 1;
3001 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
3002 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
3004 for (i = 0; i < nreq; ++i)
3005 priv->eq_table.eq[i].irq = entries[i].vector;
3007 dev->flags |= MLX4_FLAG_MSI_X;
3014 dev->caps.num_comp_vectors = 1;
3015 dev->caps.comp_pool = 0;
3017 for (i = 0; i < 2; ++i)
3018 priv->eq_table.eq[i].irq = dev->pdev->irq;
3021 dev->caps.num_comp_vectors = 0;
3022 dev->caps.comp_pool = 0;
3027 mlx4_init_hca_info(struct mlx4_dev *dev)
3029 struct mlx4_hca_info *info = &mlx4_priv(dev)->hca_info;
3033 info->firmware_attr = (struct device_attribute)__ATTR(fw_ver, S_IRUGO,
3034 show_firmware_version, NULL);
3035 if (device_create_file(&dev->pdev->dev, &info->firmware_attr))
3036 mlx4_err(dev, "Failed to add file firmware version");
3038 info->hca_attr = (struct device_attribute)__ATTR(hca, S_IRUGO, show_hca,
3040 if (device_create_file(&dev->pdev->dev, &info->hca_attr))
3041 mlx4_err(dev, "Failed to add file hca type");
3043 info->board_attr = (struct device_attribute)__ATTR(board_id, S_IRUGO,
3045 if (device_create_file(&dev->pdev->dev, &info->board_attr))
3046 mlx4_err(dev, "Failed to add file board id type");
3049 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
3051 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
3056 if (!mlx4_is_slave(dev)) {
3057 mlx4_init_mac_table(dev, &info->mac_table);
3058 mlx4_init_vlan_table(dev, &info->vlan_table);
3059 info->base_qpn = mlx4_get_base_qpn(dev, port);
3062 sprintf(info->dev_name, "mlx4_port%d", port);
3063 info->port_attr.attr.name = info->dev_name;
3064 if (mlx4_is_mfunc(dev))
3065 info->port_attr.attr.mode = S_IRUGO;
3067 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
3068 info->port_attr.store = set_port_type;
3070 info->port_attr.show = show_port_type;
3071 sysfs_attr_init(&info->port_attr.attr);
3073 err = device_create_file(&dev->pdev->dev, &info->port_attr);
3075 mlx4_err(dev, "Failed to create file for port %d\n", port);
3079 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
3080 info->port_mtu_attr.attr.name = info->dev_mtu_name;
3081 if (mlx4_is_mfunc(dev))
3082 info->port_mtu_attr.attr.mode = S_IRUGO;
3084 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
3085 info->port_mtu_attr.store = set_port_ib_mtu;
3087 info->port_mtu_attr.show = show_port_ib_mtu;
3088 sysfs_attr_init(&info->port_mtu_attr.attr);
3090 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
3092 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
3093 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
3101 mlx4_cleanup_hca_info(struct mlx4_hca_info *info)
3103 device_remove_file(&info->dev->pdev->dev, &info->firmware_attr);
3104 device_remove_file(&info->dev->pdev->dev, &info->board_attr);
3105 device_remove_file(&info->dev->pdev->dev, &info->hca_attr);
3108 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
3113 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
3114 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
3117 static int mlx4_init_steering(struct mlx4_dev *dev)
3119 struct mlx4_priv *priv = mlx4_priv(dev);
3120 int num_entries = dev->caps.num_ports;
3123 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
3127 for (i = 0; i < num_entries; i++)
3128 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3129 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3130 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3135 static void mlx4_clear_steering(struct mlx4_dev *dev)
3137 struct mlx4_priv *priv = mlx4_priv(dev);
3138 struct mlx4_steer_index *entry, *tmp_entry;
3139 struct mlx4_promisc_qp *pqp, *tmp_pqp;
3140 int num_entries = dev->caps.num_ports;
3143 for (i = 0; i < num_entries; i++) {
3144 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3145 list_for_each_entry_safe(pqp, tmp_pqp,
3146 &priv->steer[i].promisc_qps[j],
3148 list_del(&pqp->list);
3151 list_for_each_entry_safe(entry, tmp_entry,
3152 &priv->steer[i].steer_entries[j],
3154 list_del(&entry->list);
3155 list_for_each_entry_safe(pqp, tmp_pqp,
3158 list_del(&pqp->list);
3168 static int extended_func_num(struct pci_dev *pdev)
3170 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3173 #define MLX4_OWNER_BASE 0x8069c
3174 #define MLX4_OWNER_SIZE 4
3176 static int mlx4_get_ownership(struct mlx4_dev *dev)
3178 void __iomem *owner;
3181 if (pci_channel_offline(dev->pdev))
3184 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
3187 mlx4_err(dev, "Failed to obtain ownership bit\n");
3196 static void mlx4_free_ownership(struct mlx4_dev *dev)
3198 void __iomem *owner;
3200 if (pci_channel_offline(dev->pdev))
3203 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
3206 mlx4_err(dev, "Failed to obtain ownership bit\n");
3214 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
3216 struct mlx4_priv *priv;
3217 struct mlx4_dev *dev;
3222 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3224 err = pci_enable_device(pdev);
3226 dev_err(&pdev->dev, "Cannot enable PCI device, "
3231 mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(pdev), 0, &nvfs);
3232 mlx4_get_val(probe_vf.dbdf2val.tbl, pci_physfn(pdev), 0, &prb_vf);
3233 if (nvfs > MLX4_MAX_NUM_VF) {
3234 dev_err(&pdev->dev, "There are more VF's (%d) than allowed(%d)\n",
3235 nvfs, MLX4_MAX_NUM_VF);
3240 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3246 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3247 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3248 dev_err(&pdev->dev, "Missing DCS, aborting."
3249 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%x)\n",
3250 pci_dev_data, pci_resource_flags(pdev, 0));
3252 goto err_disable_pdev;
3254 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3255 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
3257 goto err_disable_pdev;
3260 err = pci_request_regions(pdev, DRV_NAME);
3262 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3263 goto err_disable_pdev;
3266 pci_set_master(pdev);
3268 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3270 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
3271 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3273 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
3274 goto err_release_regions;
3277 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3279 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
3280 "consistent PCI DMA mask.\n");
3281 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3283 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
3285 goto err_release_regions;
3289 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3290 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3292 priv = kzalloc(sizeof *priv, GFP_KERNEL);
3294 dev_err(&pdev->dev, "Device struct alloc failed, "
3297 goto err_release_regions;
3302 INIT_LIST_HEAD(&priv->dev_list);
3303 INIT_LIST_HEAD(&priv->ctx_list);
3304 spin_lock_init(&priv->ctx_lock);
3306 mutex_init(&priv->port_mutex);
3308 INIT_LIST_HEAD(&priv->pgdir_list);
3309 mutex_init(&priv->pgdir_mutex);
3311 INIT_LIST_HEAD(&priv->bf_list);
3312 mutex_init(&priv->bf_mutex);
3314 dev->rev_id = pdev->revision;
3315 dev->numa_node = dev_to_node(&pdev->dev);
3316 /* Detect if this device is a virtual function */
3317 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3318 /* When acting as pf, we normally skip vfs unless explicitly
3319 * requested to probe them. */
3320 if (nvfs && extended_func_num(pdev) > prb_vf) {
3321 mlx4_warn(dev, "Skipping virtual function:%d\n",
3322 extended_func_num(pdev));
3326 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3327 dev->flags |= MLX4_FLAG_SLAVE;
3329 /* We reset the device and enable SRIOV only for physical
3330 * devices. Try to claim ownership on the device;
3331 * if already taken, skip -- do not allow multiple PFs */
3332 err = mlx4_get_ownership(dev);
3337 mlx4_warn(dev, "Multiple PFs not yet supported."
3345 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", nvfs);
3346 err = pci_enable_sriov(pdev, nvfs);
3348 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
3352 mlx4_warn(dev, "Running in master mode\n");
3353 dev->flags |= MLX4_FLAG_SRIOV |
3355 dev->num_vfs = nvfs;
3359 atomic_set(&priv->opreq_count, 0);
3360 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3363 * Now reset the HCA before we touch the PCI capabilities or
3364 * attempt a firmware command, since a boot ROM may have left
3365 * the HCA in an undefined state.
3367 err = mlx4_reset(dev);
3369 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3375 err = mlx4_cmd_init(dev);
3377 mlx4_err(dev, "Failed to init command interface, aborting.\n");
3381 /* In slave functions, the communication channel must be initialized
3382 * before posting commands. Also, init num_slaves before calling
3384 if (mlx4_is_mfunc(dev)) {
3385 if (mlx4_is_master(dev))
3386 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3388 dev->num_slaves = 0;
3389 err = mlx4_multi_func_init(dev);
3391 mlx4_err(dev, "Failed to init slave mfunc"
3392 " interface, aborting.\n");
3398 err = mlx4_init_hca(dev);
3400 if (err == -EACCES) {
3401 /* Not primary Physical function
3402 * Running in slave mode */
3403 mlx4_cmd_cleanup(dev);
3404 dev->flags |= MLX4_FLAG_SLAVE;
3405 dev->flags &= ~MLX4_FLAG_MASTER;
3411 /* In master functions, the communication channel must be initialized
3412 * after obtaining its address from fw */
3413 if (mlx4_is_master(dev)) {
3414 err = mlx4_multi_func_init(dev);
3416 mlx4_err(dev, "Failed to init master mfunc"
3417 "interface, aborting.\n");
3422 err = mlx4_alloc_eq_table(dev);
3424 goto err_master_mfunc;
3426 priv->msix_ctl.pool_bm = 0;
3427 mutex_init(&priv->msix_ctl.pool_lock);
3429 mlx4_enable_msi_x(dev);
3431 /* no MSIX and no shared IRQ */
3432 if (!dev->caps.num_comp_vectors && !dev->caps.comp_pool) {
3437 if ((mlx4_is_mfunc(dev)) &&
3438 !(dev->flags & MLX4_FLAG_MSI_X)) {
3440 mlx4_err(dev, "INTx is not supported in multi-function mode."
3445 if (!mlx4_is_slave(dev)) {
3446 err = mlx4_init_steering(dev);
3451 err = mlx4_setup_hca(dev);
3452 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3453 !mlx4_is_mfunc(dev)) {
3454 dev->flags &= ~MLX4_FLAG_MSI_X;
3455 dev->caps.num_comp_vectors = 1;
3456 dev->caps.comp_pool = 0;
3457 pci_disable_msix(pdev);
3458 err = mlx4_setup_hca(dev);
3464 mlx4_init_quotas(dev);
3465 mlx4_init_hca_info(dev);
3467 for (port = 1; port <= dev->caps.num_ports; port++) {
3468 err = mlx4_init_port_info(dev, port);
3473 err = mlx4_register_device(dev);
3477 mlx4_request_modules(dev);
3479 mlx4_sense_init(dev);
3480 mlx4_start_sense(dev);
3482 priv->pci_dev_data = pci_dev_data;
3483 pci_set_drvdata(pdev, dev);
3488 for (--port; port >= 1; --port)
3489 mlx4_cleanup_port_info(&priv->port[port]);
3491 mlx4_cleanup_counters_table(dev);
3492 mlx4_cleanup_qp_table(dev);
3493 mlx4_cleanup_srq_table(dev);
3494 mlx4_cleanup_cq_table(dev);
3495 mlx4_cmd_use_polling(dev);
3496 mlx4_cleanup_eq_table(dev);
3497 mlx4_cleanup_mcg_table(dev);
3498 mlx4_cleanup_mr_table(dev);
3499 mlx4_cleanup_xrcd_table(dev);
3500 mlx4_cleanup_pd_table(dev);
3501 mlx4_cleanup_uar_table(dev);
3504 if (!mlx4_is_slave(dev))
3505 mlx4_clear_steering(dev);
3508 mlx4_free_eq_table(dev);
3511 if (mlx4_is_master(dev)) {
3512 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3513 mlx4_multi_func_cleanup(dev);
3516 if (mlx4_is_slave(dev)) {
3517 kfree(dev->caps.qp0_tunnel);
3518 kfree(dev->caps.qp0_proxy);
3519 kfree(dev->caps.qp1_tunnel);
3520 kfree(dev->caps.qp1_proxy);
3524 if (dev->flags & MLX4_FLAG_MSI_X)
3525 pci_disable_msix(pdev);
3527 mlx4_close_hca(dev);
3530 if (mlx4_is_slave(dev))
3531 mlx4_multi_func_cleanup(dev);
3534 mlx4_cmd_cleanup(dev);
3537 if (dev->flags & MLX4_FLAG_SRIOV)
3538 pci_disable_sriov(pdev);
3540 if (!mlx4_is_slave(dev))
3541 mlx4_free_ownership(dev);
3546 err_release_regions:
3547 pci_release_regions(pdev);
3550 pci_disable_device(pdev);
3551 pci_set_drvdata(pdev, NULL);
3555 static int __devinit mlx4_init_one(struct pci_dev *pdev,
3556 const struct pci_device_id *id)
3558 device_set_desc(pdev->dev.bsddev, mlx4_version);
3559 return __mlx4_init_one(pdev, id->driver_data);
3562 static void mlx4_remove_one(struct pci_dev *pdev)
3564 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3565 struct mlx4_priv *priv = mlx4_priv(dev);
3569 /* in SRIOV it is not allowed to unload the pf's
3570 * driver while there are alive vf's */
3571 if (mlx4_is_master(dev)) {
3572 if (mlx4_how_many_lives_vf(dev))
3573 mlx4_err(dev, "Removing PF when there are assigned VF's !!!\n");
3575 mlx4_stop_sense(dev);
3576 mlx4_unregister_device(dev);
3578 mlx4_cleanup_hca_info(&priv->hca_info);
3579 for (p = 1; p <= dev->caps.num_ports; p++) {
3580 mlx4_cleanup_port_info(&priv->port[p]);
3581 mlx4_CLOSE_PORT(dev, p);
3584 if (mlx4_is_master(dev))
3585 mlx4_free_resource_tracker(dev,
3586 RES_TR_FREE_SLAVES_ONLY);
3588 mlx4_cleanup_counters_table(dev);
3589 mlx4_cleanup_qp_table(dev);
3590 mlx4_cleanup_srq_table(dev);
3591 mlx4_cleanup_cq_table(dev);
3592 mlx4_cmd_use_polling(dev);
3593 mlx4_cleanup_eq_table(dev);
3594 mlx4_cleanup_mcg_table(dev);
3595 mlx4_cleanup_mr_table(dev);
3596 mlx4_cleanup_xrcd_table(dev);
3597 mlx4_cleanup_pd_table(dev);
3599 if (mlx4_is_master(dev))
3600 mlx4_free_resource_tracker(dev,
3601 RES_TR_FREE_STRUCTS_ONLY);
3604 mlx4_uar_free(dev, &priv->driver_uar);
3605 mlx4_cleanup_uar_table(dev);
3606 if (!mlx4_is_slave(dev))
3607 mlx4_clear_steering(dev);
3608 mlx4_free_eq_table(dev);
3609 if (mlx4_is_master(dev))
3610 mlx4_multi_func_cleanup(dev);
3611 mlx4_close_hca(dev);
3612 if (mlx4_is_slave(dev))
3613 mlx4_multi_func_cleanup(dev);
3614 mlx4_cmd_cleanup(dev);
3616 if (dev->flags & MLX4_FLAG_MSI_X)
3617 pci_disable_msix(pdev);
3618 if (dev->flags & MLX4_FLAG_SRIOV) {
3619 mlx4_warn(dev, "Disabling SR-IOV\n");
3620 pci_disable_sriov(pdev);
3623 if (!mlx4_is_slave(dev))
3624 mlx4_free_ownership(dev);
3626 kfree(dev->caps.qp0_tunnel);
3627 kfree(dev->caps.qp0_proxy);
3628 kfree(dev->caps.qp1_tunnel);
3629 kfree(dev->caps.qp1_proxy);
3632 pci_release_regions(pdev);
3633 pci_disable_device(pdev);
3634 pci_set_drvdata(pdev, NULL);
3638 static int restore_current_port_types(struct mlx4_dev *dev,
3639 enum mlx4_port_type *types,
3640 enum mlx4_port_type *poss_types)
3642 struct mlx4_priv *priv = mlx4_priv(dev);
3645 mlx4_stop_sense(dev);
3646 mutex_lock(&priv->port_mutex);
3647 for (i = 0; i < dev->caps.num_ports; i++)
3648 dev->caps.possible_type[i + 1] = poss_types[i];
3649 err = mlx4_change_port_types(dev, types);
3650 mlx4_start_sense(dev);
3651 mutex_unlock(&priv->port_mutex);
3655 int mlx4_restart_one(struct pci_dev *pdev)
3657 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3658 struct mlx4_priv *priv = mlx4_priv(dev);
3659 enum mlx4_port_type curr_type[MLX4_MAX_PORTS];
3660 enum mlx4_port_type poss_type[MLX4_MAX_PORTS];
3661 int pci_dev_data, err, i;
3663 pci_dev_data = priv->pci_dev_data;
3664 for (i = 0; i < dev->caps.num_ports; i++) {
3665 curr_type[i] = dev->caps.port_type[i + 1];
3666 poss_type[i] = dev->caps.possible_type[i + 1];
3669 mlx4_remove_one(pdev);
3670 err = __mlx4_init_one(pdev, pci_dev_data);
3674 dev = pci_get_drvdata(pdev);
3675 err = restore_current_port_types(dev, curr_type, poss_type);
3677 mlx4_err(dev, "mlx4_restart_one: could not restore original port types (%d)\n",
3682 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
3683 /* MT25408 "Hermon" SDR */
3684 { PCI_VDEVICE(MELLANOX, 0x6340),
3685 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3686 /* MT25408 "Hermon" DDR */
3687 { PCI_VDEVICE(MELLANOX, 0x634a),
3688 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3689 /* MT25408 "Hermon" QDR */
3690 { PCI_VDEVICE(MELLANOX, 0x6354),
3691 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3692 /* MT25408 "Hermon" DDR PCIe gen2 */
3693 { PCI_VDEVICE(MELLANOX, 0x6732),
3694 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3695 /* MT25408 "Hermon" QDR PCIe gen2 */
3696 { PCI_VDEVICE(MELLANOX, 0x673c),
3697 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3698 /* MT25408 "Hermon" EN 10GigE */
3699 { PCI_VDEVICE(MELLANOX, 0x6368),
3700 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3701 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
3702 { PCI_VDEVICE(MELLANOX, 0x6750),
3703 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3704 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
3705 { PCI_VDEVICE(MELLANOX, 0x6372),
3706 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3707 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
3708 { PCI_VDEVICE(MELLANOX, 0x675a),
3709 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3710 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
3711 { PCI_VDEVICE(MELLANOX, 0x6764),
3712 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3713 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
3714 { PCI_VDEVICE(MELLANOX, 0x6746),
3715 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3716 /* MT26478 ConnectX2 40GigE PCIe gen2 */
3717 { PCI_VDEVICE(MELLANOX, 0x676e),
3718 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT },
3719 /* MT25400 Family [ConnectX-2 Virtual Function] */
3720 { PCI_VDEVICE(MELLANOX, 0x1002),
3721 .driver_data = MLX4_PCI_DEV_IS_VF },
3722 /* MT27500 Family [ConnectX-3] */
3723 { PCI_VDEVICE(MELLANOX, 0x1003) },
3724 /* MT27500 Family [ConnectX-3 Virtual Function] */
3725 { PCI_VDEVICE(MELLANOX, 0x1004),
3726 .driver_data = MLX4_PCI_DEV_IS_VF },
3727 { PCI_VDEVICE(MELLANOX, 0x1005) }, /* MT27510 Family */
3728 { PCI_VDEVICE(MELLANOX, 0x1006) }, /* MT27511 Family */
3729 { PCI_VDEVICE(MELLANOX, 0x1007) }, /* MT27520 Family */
3730 { PCI_VDEVICE(MELLANOX, 0x1008) }, /* MT27521 Family */
3731 { PCI_VDEVICE(MELLANOX, 0x1009) }, /* MT27530 Family */
3732 { PCI_VDEVICE(MELLANOX, 0x100a) }, /* MT27531 Family */
3733 { PCI_VDEVICE(MELLANOX, 0x100b) }, /* MT27540 Family */
3734 { PCI_VDEVICE(MELLANOX, 0x100c) }, /* MT27541 Family */
3735 { PCI_VDEVICE(MELLANOX, 0x100d) }, /* MT27550 Family */
3736 { PCI_VDEVICE(MELLANOX, 0x100e) }, /* MT27551 Family */
3737 { PCI_VDEVICE(MELLANOX, 0x100f) }, /* MT27560 Family */
3738 { PCI_VDEVICE(MELLANOX, 0x1010) }, /* MT27561 Family */
3742 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3744 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3745 pci_channel_state_t state)
3747 mlx4_remove_one(pdev);
3749 return state == pci_channel_io_perm_failure ?
3750 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3753 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3755 int ret = __mlx4_init_one(pdev, 0);
3757 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3760 static const struct pci_error_handlers mlx4_err_handler = {
3761 .error_detected = mlx4_pci_err_detected,
3762 .slot_reset = mlx4_pci_slot_reset,
3765 static int suspend(struct pci_dev *pdev, pm_message_t state)
3767 mlx4_remove_one(pdev);
3772 static int resume(struct pci_dev *pdev)
3774 return __mlx4_init_one(pdev, 0);
3777 static struct pci_driver mlx4_driver = {
3779 .id_table = mlx4_pci_table,
3780 .probe = mlx4_init_one,
3781 .remove = __devexit_p(mlx4_remove_one),
3784 .err_handler = &mlx4_err_handler,
3787 static int __init mlx4_verify_params(void)
3791 status = update_defaults(&port_type_array);
3792 if (status == INVALID_STR) {
3793 if (mlx4_fill_dbdf2val_tbl(&port_type_array.dbdf2val))
3795 } else if (status == INVALID_DATA) {
3799 status = update_defaults(&num_vfs);
3800 if (status == INVALID_STR) {
3801 if (mlx4_fill_dbdf2val_tbl(&num_vfs.dbdf2val))
3803 } else if (status == INVALID_DATA) {
3807 status = update_defaults(&probe_vf);
3808 if (status == INVALID_STR) {
3809 if (mlx4_fill_dbdf2val_tbl(&probe_vf.dbdf2val))
3811 } else if (status == INVALID_DATA) {
3816 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x);
3820 if ((log_num_mac < 0) || (log_num_mac > 7)) {
3821 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
3825 if (log_num_vlan != 0)
3826 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3827 MLX4_LOG_NUM_VLANS);
3829 if (mlx4_set_4k_mtu != -1)
3830 pr_warning("mlx4_core: set_4k_mtu - obsolete module param\n");
3832 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) {
3833 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
3837 if (mlx4_log_num_mgm_entry_size != -1 &&
3838 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3839 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
3840 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
3841 "in legal range (-1 or %d..%d)\n",
3842 mlx4_log_num_mgm_entry_size,
3843 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3844 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3848 if (mod_param_profile.num_qp < 18 || mod_param_profile.num_qp > 23) {
3849 pr_warning("mlx4_core: bad log_num_qp: %d\n",
3850 mod_param_profile.num_qp);
3854 if (mod_param_profile.num_srq < 10) {
3855 pr_warning("mlx4_core: too low log_num_srq: %d\n",
3856 mod_param_profile.num_srq);
3860 if (mod_param_profile.num_cq < 10) {
3861 pr_warning("mlx4_core: too low log_num_cq: %d\n",
3862 mod_param_profile.num_cq);
3866 if (mod_param_profile.num_mpt < 10) {
3867 pr_warning("mlx4_core: too low log_num_mpt: %d\n",
3868 mod_param_profile.num_mpt);
3872 if (mod_param_profile.num_mtt_segs &&
3873 mod_param_profile.num_mtt_segs < 15) {
3874 pr_warning("mlx4_core: too low log_num_mtt: %d\n",
3875 mod_param_profile.num_mtt_segs);
3879 if (mod_param_profile.num_mtt_segs > MLX4_MAX_LOG_NUM_MTT) {
3880 pr_warning("mlx4_core: too high log_num_mtt: %d\n",
3881 mod_param_profile.num_mtt_segs);
3887 static int __init mlx4_init(void)
3891 if (mlx4_verify_params())
3896 mlx4_wq = create_singlethread_workqueue("mlx4");
3900 if (enable_sys_tune)
3903 ret = pci_register_driver(&mlx4_driver);
3910 if (enable_sys_tune)
3913 destroy_workqueue(mlx4_wq);
3918 static void __exit mlx4_cleanup(void)
3920 if (enable_sys_tune)
3923 pci_unregister_driver(&mlx4_driver);
3924 destroy_workqueue(mlx4_wq);
3927 module_init_order(mlx4_init, SI_ORDER_MIDDLE);
3928 module_exit(mlx4_cleanup);
3930 #include <sys/module.h>
3932 mlx4_evhand(module_t mod, int event, void *arg)
3937 static moduledata_t mlx4_mod = {
3939 .evhand = mlx4_evhand,
3941 MODULE_VERSION(mlx4, 1);
3942 DECLARE_MODULE(mlx4, mlx4_mod, SI_SUB_OFED_PREINIT, SI_ORDER_ANY);