2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_atpic.h"
38 #include "opt_hwpmc_hooks.h"
39 #include "opt_kdtrace.h"
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
53 #include <sys/timeet.h>
58 #include <x86/apicreg.h>
59 #include <machine/cputypes.h>
60 #include <machine/frame.h>
61 #include <machine/intr_machdep.h>
62 #include <machine/apicvar.h>
64 #include <machine/md_var.h>
65 #include <machine/smp.h>
66 #include <machine/specialreg.h>
69 #include <sys/interrupt.h>
74 #define SDT_APIC SDT_SYSIGT
75 #define SDT_APICT SDT_SYSIGT
78 #define SDT_APIC SDT_SYS386IGT
79 #define SDT_APICT SDT_SYS386TGT
80 #define GSEL_APIC GSEL(GCODE_SEL, SEL_KPL)
83 /* Sanity checks on IDT vectors. */
84 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
85 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
86 CTASSERT(APIC_LOCAL_INTS == 240);
87 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
89 /* Magic IRQ values for the timer and syscalls. */
90 #define IRQ_TIMER (NUM_IO_INTS + 1)
91 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
92 #define IRQ_DTRACE_RET (NUM_IO_INTS + 3)
93 #define IRQ_EVTCHN (NUM_IO_INTS + 4)
96 * Support for local APICs. Local APICs manage interrupts on each
97 * individual processor as opposed to I/O APICs which receive interrupts
98 * from I/O devices and then forward them on to the local APICs.
100 * Local APICs can also send interrupts to each other thus providing the
101 * mechanism for IPIs.
105 u_int lvt_edgetrigger:1;
106 u_int lvt_activehi:1;
114 struct lvt la_lvts[APIC_LVT_MAX + 1];
117 u_int la_cluster_id:2;
119 u_long *la_timer_count;
120 u_long la_timer_period;
122 uint32_t lvt_timer_cache;
123 /* Include IDT_SYSCALL to make indexing easier. */
124 int la_ioint_irqs[APIC_NUM_IOINTS + 1];
125 } static lapics[MAX_APIC_ID + 1];
127 /* Global defaults for local APIC LVT entries. */
128 static struct lvt lvts[APIC_LVT_MAX + 1] = {
129 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
130 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
131 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
132 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
133 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
134 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
135 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */
138 static inthand_t *ioint_handlers[] = {
140 IDTVEC(apic_isr1), /* 32 - 63 */
141 IDTVEC(apic_isr2), /* 64 - 95 */
142 IDTVEC(apic_isr3), /* 96 - 127 */
143 IDTVEC(apic_isr4), /* 128 - 159 */
144 IDTVEC(apic_isr5), /* 160 - 191 */
145 IDTVEC(apic_isr6), /* 192 - 223 */
146 IDTVEC(apic_isr7), /* 224 - 255 */
150 static u_int32_t lapic_timer_divisors[] = {
151 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
152 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
155 extern inthand_t IDTVEC(rsvd);
157 volatile lapic_t *lapic;
158 vm_paddr_t lapic_paddr;
159 static u_long lapic_timer_divisor;
160 static struct eventtimer lapic_et;
162 static void lapic_enable(void);
163 static void lapic_resume(struct pic *pic, bool suspend_cancelled);
164 static void lapic_timer_oneshot(struct lapic *,
165 u_int count, int enable_int);
166 static void lapic_timer_periodic(struct lapic *,
167 u_int count, int enable_int);
168 static void lapic_timer_stop(struct lapic *);
169 static void lapic_timer_set_divisor(u_int divisor);
170 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
171 static int lapic_et_start(struct eventtimer *et,
172 sbintime_t first, sbintime_t period);
173 static int lapic_et_stop(struct eventtimer *et);
175 struct pic lapic_pic = { .pic_resume = lapic_resume };
178 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
182 KASSERT(pin <= APIC_LVT_MAX, ("%s: pin %u out of range", __func__, pin));
183 if (la->la_lvts[pin].lvt_active)
184 lvt = &la->la_lvts[pin];
188 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
190 if (lvt->lvt_edgetrigger == 0)
191 value |= APIC_LVT_TM;
192 if (lvt->lvt_activehi == 0)
193 value |= APIC_LVT_IIPP_INTALO;
196 value |= lvt->lvt_mode;
197 switch (lvt->lvt_mode) {
198 case APIC_LVT_DM_NMI:
199 case APIC_LVT_DM_SMI:
200 case APIC_LVT_DM_INIT:
201 case APIC_LVT_DM_EXTINT:
202 if (!lvt->lvt_edgetrigger) {
203 printf("lapic%u: Forcing LINT%u to edge trigger\n",
205 value |= APIC_LVT_TM;
207 /* Use a vector of 0. */
209 case APIC_LVT_DM_FIXED:
210 value |= lvt->lvt_vector;
213 panic("bad APIC LVT delivery mode: %#x\n", value);
219 * Map the local APIC and setup necessary interrupt vectors.
222 lapic_init(vm_paddr_t addr)
227 /* Map the local APIC and setup the spurious interrupt handler. */
228 KASSERT(trunc_page(addr) == addr,
229 ("local APIC not aligned on a page boundary"));
231 lapic = pmap_mapdev(addr, sizeof(lapic_t));
232 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL,
235 /* Perform basic initialization of the BSP's local APIC. */
238 /* Set BSP's per-CPU local APIC ID. */
239 PCPU_SET(apic_id, lapic_id());
241 /* Local APIC timer interrupt. */
242 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_APIC, SEL_KPL, GSEL_APIC);
244 /* Local APIC error interrupt. */
245 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_APIC, SEL_KPL, GSEL_APIC);
247 /* XXX: Thermal interrupt */
249 /* Local APIC CMCI. */
250 setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_APICT, SEL_KPL, GSEL_APIC);
252 if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) {
254 /* Intel CPUID 0x06 EAX[2] set if APIC timer runs in C3. */
255 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high >= 6) {
256 do_cpuid(0x06, regs);
257 if ((regs[0] & CPUTPM1_ARAT) != 0)
260 bzero(&lapic_et, sizeof(lapic_et));
261 lapic_et.et_name = "LAPIC";
262 lapic_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
264 lapic_et.et_quality = 600;
266 lapic_et.et_flags |= ET_FLAGS_C3STOP;
267 lapic_et.et_quality -= 200;
269 lapic_et.et_frequency = 0;
270 /* We don't know frequency yet, so trying to guess. */
271 lapic_et.et_min_period = 0x00001000LL;
272 lapic_et.et_max_period = SBT_1S;
273 lapic_et.et_start = lapic_et_start;
274 lapic_et.et_stop = lapic_et_stop;
275 lapic_et.et_priv = NULL;
276 et_register(&lapic_et);
281 * Create a local APIC instance.
284 lapic_create(u_int apic_id, int boot_cpu)
288 if (apic_id > MAX_APIC_ID) {
289 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
291 panic("Can't ignore BSP");
294 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
298 * Assume no local LVT overrides and a cluster of 0 and
299 * intra-cluster ID of 0.
301 lapics[apic_id].la_present = 1;
302 lapics[apic_id].la_id = apic_id;
303 for (i = 0; i <= APIC_LVT_MAX; i++) {
304 lapics[apic_id].la_lvts[i] = lvts[i];
305 lapics[apic_id].la_lvts[i].lvt_active = 0;
307 for (i = 0; i <= APIC_NUM_IOINTS; i++)
308 lapics[apic_id].la_ioint_irqs[i] = -1;
309 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
310 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] =
313 lapics[apic_id].la_ioint_irqs[IDT_DTRACE_RET - APIC_IO_INTS] =
317 lapics[apic_id].la_ioint_irqs[IDT_EVTCHN - APIC_IO_INTS] = IRQ_EVTCHN;
322 cpu_add(apic_id, boot_cpu);
327 * Dump contents of local APIC registers
330 lapic_dump(const char* str)
334 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
335 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
336 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
337 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
338 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
339 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
340 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x",
341 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error);
342 if (maxlvt >= APIC_LVT_PMC)
343 printf(" pmc: 0x%08x", lapic->lvt_pcint);
345 if (maxlvt >= APIC_LVT_CMCI)
346 printf(" cmci: 0x%08x\n", lapic->lvt_cmci);
350 lapic_setup(int boot)
355 char buf[MAXCOMLEN + 1];
357 la = &lapics[lapic_id()];
358 KASSERT(la->la_present, ("missing APIC structure"));
359 saveintr = intr_disable();
360 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
362 /* Initialize the TPR to allow all interrupts. */
365 /* Setup spurious vector and enable the local APIC. */
368 /* Program LINT[01] LVT entries. */
369 lapic->lvt_lint0 = lvt_mode(la, APIC_LVT_LINT0, lapic->lvt_lint0);
370 lapic->lvt_lint1 = lvt_mode(la, APIC_LVT_LINT1, lapic->lvt_lint1);
372 /* Program the PMC LVT entry if present. */
373 if (maxlvt >= APIC_LVT_PMC)
374 lapic->lvt_pcint = lvt_mode(la, APIC_LVT_PMC, lapic->lvt_pcint);
376 /* Program timer LVT and setup handler. */
377 la->lvt_timer_cache = lapic->lvt_timer =
378 lvt_mode(la, APIC_LVT_TIMER, lapic->lvt_timer);
380 snprintf(buf, sizeof(buf), "cpu%d:timer", PCPU_GET(cpuid));
381 intrcnt_add(buf, &la->la_timer_count);
384 /* Setup the timer if configured. */
385 if (la->la_timer_mode != 0) {
386 KASSERT(la->la_timer_period != 0, ("lapic%u: zero divisor",
388 lapic_timer_set_divisor(lapic_timer_divisor);
389 if (la->la_timer_mode == 1)
390 lapic_timer_periodic(la, la->la_timer_period, 1);
392 lapic_timer_oneshot(la, la->la_timer_period, 1);
395 /* Program error LVT and clear any existing errors. */
396 lapic->lvt_error = lvt_mode(la, APIC_LVT_ERROR, lapic->lvt_error);
399 /* XXX: Thermal LVT */
401 /* Program the CMCI LVT entry if present. */
402 if (maxlvt >= APIC_LVT_CMCI)
403 lapic->lvt_cmci = lvt_mode(la, APIC_LVT_CMCI, lapic->lvt_cmci);
405 intr_restore(saveintr);
409 lapic_reenable_pmc(void)
414 value = lapic->lvt_pcint;
415 value &= ~APIC_LVT_M;
416 lapic->lvt_pcint = value;
422 lapic_update_pmc(void *dummy)
426 la = &lapics[lapic_id()];
427 lapic->lvt_pcint = lvt_mode(la, APIC_LVT_PMC, lapic->lvt_pcint);
432 lapic_enable_pmc(void)
437 /* Fail if the local APIC is not present. */
441 /* Fail if the PMC LVT is not present. */
442 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
443 if (maxlvt < APIC_LVT_PMC)
446 lvts[APIC_LVT_PMC].lvt_masked = 0;
450 * If hwpmc was loaded at boot time then the APs may not be
451 * started yet. In that case, don't forward the request to
452 * them as they will program the lvt when they start.
455 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
458 lapic_update_pmc(NULL);
466 lapic_disable_pmc(void)
471 /* Fail if the local APIC is not present. */
475 /* Fail if the PMC LVT is not present. */
476 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
477 if (maxlvt < APIC_LVT_PMC)
480 lvts[APIC_LVT_PMC].lvt_masked = 1;
483 /* The APs should always be started when hwpmc is unloaded. */
484 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
486 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
491 lapic_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
496 la = &lapics[PCPU_GET(apic_id)];
497 if (et->et_frequency == 0) {
498 /* Start off with a divisor of 2 (power on reset default). */
499 lapic_timer_divisor = 2;
500 /* Try to calibrate the local APIC timer. */
502 lapic_timer_set_divisor(lapic_timer_divisor);
503 lapic_timer_oneshot(la, APIC_TIMER_MAX_COUNT, 0);
505 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
506 if (value != APIC_TIMER_MAX_COUNT)
508 lapic_timer_divisor <<= 1;
509 } while (lapic_timer_divisor <= 128);
510 if (lapic_timer_divisor > 128)
511 panic("lapic: Divisor too big");
513 printf("lapic: Divisor %lu, Frequency %lu Hz\n",
514 lapic_timer_divisor, value);
515 et->et_frequency = value;
516 et->et_min_period = (0x00000002LLU << 32) / et->et_frequency;
517 et->et_max_period = (0xfffffffeLLU << 32) / et->et_frequency;
519 if (la->la_timer_mode == 0)
520 lapic_timer_set_divisor(lapic_timer_divisor);
522 la->la_timer_mode = 1;
523 la->la_timer_period = ((uint32_t)et->et_frequency * period) >> 32;
524 lapic_timer_periodic(la, la->la_timer_period, 1);
526 la->la_timer_mode = 2;
527 la->la_timer_period = ((uint32_t)et->et_frequency * first) >> 32;
528 lapic_timer_oneshot(la, la->la_timer_period, 1);
534 lapic_et_stop(struct eventtimer *et)
536 struct lapic *la = &lapics[PCPU_GET(apic_id)];
538 la->la_timer_mode = 0;
539 lapic_timer_stop(la);
548 /* Software disable the local APIC. */
550 value &= ~APIC_SVR_SWEN;
559 /* Program the spurious vector to enable the local APIC. */
561 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
562 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
566 /* Reset the local APIC on the BSP during resume. */
568 lapic_resume(struct pic *pic, bool suspend_cancelled)
578 KASSERT(lapic != NULL, ("local APIC is not mapped"));
579 return (lapic->id >> APIC_ID_SHIFT);
583 lapic_intr_pending(u_int vector)
585 volatile u_int32_t *irr;
588 * The IRR registers are an array of 128-bit registers each of
589 * which only describes 32 interrupts in the low 32 bits.. Thus,
590 * we divide the vector by 32 to get the 128-bit index. We then
591 * multiply that index by 4 to get the equivalent index from
592 * treating the IRR as an array of 32-bit registers. Finally, we
593 * modulus the vector by 32 to determine the individual bit to
597 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
601 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
605 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
607 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
609 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
610 ("%s: intra cluster id %u too big", __func__, cluster_id));
611 la = &lapics[apic_id];
612 la->la_cluster = cluster;
613 la->la_cluster_id = cluster_id;
617 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
620 if (pin > APIC_LVT_MAX)
622 if (apic_id == APIC_ID_ALL) {
623 lvts[pin].lvt_masked = masked;
627 KASSERT(lapics[apic_id].la_present,
628 ("%s: missing APIC %u", __func__, apic_id));
629 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
630 lapics[apic_id].la_lvts[pin].lvt_active = 1;
632 printf("lapic%u:", apic_id);
635 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
640 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
644 if (pin > APIC_LVT_MAX)
646 if (apic_id == APIC_ID_ALL) {
651 KASSERT(lapics[apic_id].la_present,
652 ("%s: missing APIC %u", __func__, apic_id));
653 lvt = &lapics[apic_id].la_lvts[pin];
656 printf("lapic%u:", apic_id);
658 lvt->lvt_mode = mode;
660 case APIC_LVT_DM_NMI:
661 case APIC_LVT_DM_SMI:
662 case APIC_LVT_DM_INIT:
663 case APIC_LVT_DM_EXTINT:
664 lvt->lvt_edgetrigger = 1;
665 lvt->lvt_activehi = 1;
666 if (mode == APIC_LVT_DM_EXTINT)
672 panic("Unsupported delivery mode: 0x%x\n", mode);
677 case APIC_LVT_DM_NMI:
680 case APIC_LVT_DM_SMI:
683 case APIC_LVT_DM_INIT:
686 case APIC_LVT_DM_EXTINT:
690 printf(" -> LINT%u\n", pin);
696 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
699 if (pin > APIC_LVT_MAX || pol == INTR_POLARITY_CONFORM)
701 if (apic_id == APIC_ID_ALL) {
702 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
706 KASSERT(lapics[apic_id].la_present,
707 ("%s: missing APIC %u", __func__, apic_id));
708 lapics[apic_id].la_lvts[pin].lvt_active = 1;
709 lapics[apic_id].la_lvts[pin].lvt_activehi =
710 (pol == INTR_POLARITY_HIGH);
712 printf("lapic%u:", apic_id);
715 printf(" LINT%u polarity: %s\n", pin,
716 pol == INTR_POLARITY_HIGH ? "high" : "low");
721 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
724 if (pin > APIC_LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
726 if (apic_id == APIC_ID_ALL) {
727 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
731 KASSERT(lapics[apic_id].la_present,
732 ("%s: missing APIC %u", __func__, apic_id));
733 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
734 (trigger == INTR_TRIGGER_EDGE);
735 lapics[apic_id].la_lvts[pin].lvt_active = 1;
737 printf("lapic%u:", apic_id);
740 printf(" LINT%u trigger: %s\n", pin,
741 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
746 * Adjust the TPR of the current CPU so that it blocks all interrupts below
747 * the passed in vector.
750 lapic_set_tpr(u_int vector)
757 tpr = lapic->tpr & ~APIC_TPR_PRIO;
771 lapic_handle_intr(int vector, struct trapframe *frame)
775 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
777 intr_execute_handlers(isrc, frame);
781 lapic_handle_timer(struct trapframe *frame)
784 struct trapframe *oldframe;
787 /* Send EOI first thing. */
790 #if defined(SMP) && !defined(SCHED_ULE)
792 * Don't do any accounting for the disabled HTT cores, since it
793 * will provide misleading numbers for the userland.
795 * No locking is necessary here, since even if we lose the race
796 * when hlt_cpus_mask changes it is not a big deal, really.
798 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
799 * and unlike other schedulers it actually schedules threads to
802 if (CPU_ISSET(PCPU_GET(cpuid), &hlt_cpus_mask))
806 /* Look up our local APIC structure for the tick counters. */
807 la = &lapics[PCPU_GET(apic_id)];
808 (*la->la_timer_count)++;
810 if (lapic_et.et_active) {
812 td->td_intr_nesting_level++;
813 oldframe = td->td_intr_frame;
814 td->td_intr_frame = frame;
815 lapic_et.et_event_cb(&lapic_et, lapic_et.et_arg);
816 td->td_intr_frame = oldframe;
817 td->td_intr_nesting_level--;
823 lapic_timer_set_divisor(u_int divisor)
826 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
827 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
828 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
829 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
833 lapic_timer_oneshot(struct lapic *la, u_int count, int enable_int)
837 value = la->lvt_timer_cache;
838 value &= ~APIC_LVTT_TM;
839 value |= APIC_LVTT_TM_ONE_SHOT;
841 value &= ~APIC_LVT_M;
842 lapic->lvt_timer = value;
843 lapic->icr_timer = count;
847 lapic_timer_periodic(struct lapic *la, u_int count, int enable_int)
851 value = la->lvt_timer_cache;
852 value &= ~APIC_LVTT_TM;
853 value |= APIC_LVTT_TM_PERIODIC;
855 value &= ~APIC_LVT_M;
856 lapic->lvt_timer = value;
857 lapic->icr_timer = count;
861 lapic_timer_stop(struct lapic *la)
865 value = la->lvt_timer_cache;
866 value &= ~APIC_LVTT_TM;
868 lapic->lvt_timer = value;
872 lapic_handle_cmc(void)
880 * Called from the mca_init() to activate the CMC interrupt if this CPU is
881 * responsible for monitoring any MC banks for CMC events. Since mca_init()
882 * is called prior to lapic_setup() during boot, this just needs to unmask
883 * this CPU's LVT_CMCI entry.
886 lapic_enable_cmc(void)
894 apic_id = PCPU_GET(apic_id);
895 KASSERT(lapics[apic_id].la_present,
896 ("%s: missing APIC %u", __func__, apic_id));
897 lapics[apic_id].la_lvts[APIC_LVT_CMCI].lvt_masked = 0;
898 lapics[apic_id].la_lvts[APIC_LVT_CMCI].lvt_active = 1;
900 printf("lapic%u: CMCI unmasked\n", apic_id);
904 lapic_handle_error(void)
909 * Read the contents of the error status register. Write to
910 * the register first before reading from it to force the APIC
911 * to update its value to indicate any errors that have
912 * occurred since the previous write to the register.
917 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr);
922 apic_cpuid(u_int apic_id)
925 return apic_cpuids[apic_id];
931 /* Request a free IDT vector to be used by the specified IRQ. */
933 apic_alloc_vector(u_int apic_id, u_int irq)
937 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
940 * Search for a free vector. Currently we just use a very simple
941 * algorithm to find the first free vector.
943 mtx_lock_spin(&icu_lock);
944 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
945 if (lapics[apic_id].la_ioint_irqs[vector] != -1)
947 lapics[apic_id].la_ioint_irqs[vector] = irq;
948 mtx_unlock_spin(&icu_lock);
949 return (vector + APIC_IO_INTS);
951 mtx_unlock_spin(&icu_lock);
956 * Request 'count' free contiguous IDT vectors to be used by 'count'
957 * IRQs. 'count' must be a power of two and the vectors will be
958 * aligned on a boundary of 'align'. If the request cannot be
959 * satisfied, 0 is returned.
962 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
964 u_int first, run, vector;
966 KASSERT(powerof2(count), ("bad count"));
967 KASSERT(powerof2(align), ("bad align"));
968 KASSERT(align >= count, ("align < count"));
970 for (run = 0; run < count; run++)
971 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
976 * Search for 'count' free vectors. As with apic_alloc_vector(),
977 * this just uses a simple first fit algorithm.
981 mtx_lock_spin(&icu_lock);
982 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
984 /* Vector is in use, end run. */
985 if (lapics[apic_id].la_ioint_irqs[vector] != -1) {
991 /* Start a new run if run == 0 and vector is aligned. */
993 if ((vector & (align - 1)) != 0)
999 /* Keep looping if the run isn't long enough yet. */
1003 /* Found a run, assign IRQs and return the first vector. */
1004 for (vector = 0; vector < count; vector++)
1005 lapics[apic_id].la_ioint_irqs[first + vector] =
1007 mtx_unlock_spin(&icu_lock);
1008 return (first + APIC_IO_INTS);
1010 mtx_unlock_spin(&icu_lock);
1011 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
1016 * Enable a vector for a particular apic_id. Since all lapics share idt
1017 * entries and ioint_handlers this enables the vector on all lapics. lapics
1018 * which do not have the vector configured would report spurious interrupts
1022 apic_enable_vector(u_int apic_id, u_int vector)
1025 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1026 KASSERT(ioint_handlers[vector / 32] != NULL,
1027 ("No ISR handler for vector %u", vector));
1028 #ifdef KDTRACE_HOOKS
1029 KASSERT(vector != IDT_DTRACE_RET,
1030 ("Attempt to overwrite DTrace entry"));
1032 setidt(vector, ioint_handlers[vector / 32], SDT_APIC, SEL_KPL,
1037 apic_disable_vector(u_int apic_id, u_int vector)
1040 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1041 #ifdef KDTRACE_HOOKS
1042 KASSERT(vector != IDT_DTRACE_RET,
1043 ("Attempt to overwrite DTrace entry"));
1045 KASSERT(ioint_handlers[vector / 32] != NULL,
1046 ("No ISR handler for vector %u", vector));
1049 * We can not currently clear the idt entry because other cpus
1050 * may have a valid vector at this offset.
1052 setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC);
1056 /* Release an APIC vector when it's no longer in use. */
1058 apic_free_vector(u_int apic_id, u_int vector, u_int irq)
1062 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1063 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1064 ("Vector %u does not map to an IRQ line", vector));
1065 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
1066 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] ==
1067 irq, ("IRQ mismatch"));
1068 #ifdef KDTRACE_HOOKS
1069 KASSERT(vector != IDT_DTRACE_RET,
1070 ("Attempt to overwrite DTrace entry"));
1074 * Bind us to the cpu that owned the vector before freeing it so
1075 * we don't lose an interrupt delivery race.
1080 if (sched_is_bound(td))
1081 panic("apic_free_vector: Thread already bound.\n");
1082 sched_bind(td, apic_cpuid(apic_id));
1085 mtx_lock_spin(&icu_lock);
1086 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1;
1087 mtx_unlock_spin(&icu_lock);
1095 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1097 apic_idt_to_irq(u_int apic_id, u_int vector)
1101 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1102 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1103 ("Vector %u does not map to an IRQ line", vector));
1104 #ifdef KDTRACE_HOOKS
1105 KASSERT(vector != IDT_DTRACE_RET,
1106 ("Attempt to overwrite DTrace entry"));
1108 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS];
1116 * Dump data about APIC IDT vector mappings.
1118 DB_SHOW_COMMAND(apic, db_show_apic)
1120 struct intsrc *isrc;
1125 if (strcmp(modif, "vv") == 0)
1127 else if (strcmp(modif, "v") == 0)
1131 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
1132 if (lapics[apic_id].la_present == 0)
1134 db_printf("Interrupts bound to lapic %u\n", apic_id);
1135 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1136 irq = lapics[apic_id].la_ioint_irqs[i];
1137 if (irq == -1 || irq == IRQ_SYSCALL)
1139 #ifdef KDTRACE_HOOKS
1140 if (irq == IRQ_DTRACE_RET)
1144 if (irq == IRQ_EVTCHN)
1147 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1148 if (irq == IRQ_TIMER)
1149 db_printf("lapic timer\n");
1150 else if (irq < NUM_IO_INTS) {
1151 isrc = intr_lookup_source(irq);
1152 if (isrc == NULL || verbose == 0)
1153 db_printf("IRQ %u\n", irq);
1155 db_dump_intr_event(isrc->is_event,
1158 db_printf("IRQ %u ???\n", irq);
1164 dump_mask(const char *prefix, uint32_t v, int base)
1169 for (i = 0; i < 32; i++)
1172 db_printf("%s:", prefix);
1175 db_printf(" %02x", base + i);
1181 /* Show info from the lapic regs for this CPU. */
1182 DB_SHOW_COMMAND(lapic, db_show_lapic)
1186 db_printf("lapic ID = %d\n", lapic_id());
1188 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1190 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1192 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1193 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1194 db_printf("TPR = %02x\n", lapic->tpr);
1196 #define dump_field(prefix, index) \
1197 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
1200 db_printf("In-service Interrupts:\n");
1210 db_printf("TMR Interrupts:\n");
1220 db_printf("IRR Interrupts:\n");
1235 * APIC probing support code. This includes code to manage enumerators.
1238 static SLIST_HEAD(, apic_enumerator) enumerators =
1239 SLIST_HEAD_INITIALIZER(enumerators);
1240 static struct apic_enumerator *best_enum;
1243 apic_register_enumerator(struct apic_enumerator *enumerator)
1246 struct apic_enumerator *apic_enum;
1248 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1249 if (apic_enum == enumerator)
1250 panic("%s: Duplicate register of %s", __func__,
1251 enumerator->apic_name);
1254 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1258 * We have to look for CPU's very, very early because certain subsystems
1259 * want to know how many CPU's we have extremely early on in the boot
1263 apic_init(void *dummy __unused)
1265 struct apic_enumerator *enumerator;
1268 /* We only support built in local APICs. */
1269 if (!(cpu_feature & CPUID_APIC))
1272 /* Don't probe if APIC mode is disabled. */
1273 if (resource_disabled("apic", 0))
1276 /* Probe all the enumerators to find the best match. */
1279 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1280 retval = enumerator->apic_probe();
1283 if (best_enum == NULL || best < retval) {
1284 best_enum = enumerator;
1288 if (best_enum == NULL) {
1290 printf("APIC: Could not find any APICs.\n");
1292 panic("running without device atpic requires a local APIC");
1298 printf("APIC: Using the %s enumerator.\n",
1299 best_enum->apic_name);
1303 * To work around an errata, we disable the local APIC on some
1304 * CPUs during early startup. We need to turn the local APIC back
1305 * on on such CPUs now.
1307 ppro_reenable_apic();
1310 /* Probe the CPU's in the system. */
1311 retval = best_enum->apic_probe_cpus();
1313 printf("%s: Failed to probe CPUs: returned %d\n",
1314 best_enum->apic_name, retval);
1317 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1320 * Setup the local APIC. We have to do this prior to starting up the APs
1324 apic_setup_local(void *dummy __unused)
1328 if (best_enum == NULL)
1331 /* Initialize the local APIC. */
1332 retval = best_enum->apic_setup_local();
1334 printf("%s: Failed to setup the local APIC: returned %d\n",
1335 best_enum->apic_name, retval);
1337 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, NULL);
1340 * Setup the I/O APICs.
1343 apic_setup_io(void *dummy __unused)
1347 if (best_enum == NULL)
1351 * Local APIC must be registered before other PICs and pseudo PICs
1352 * for proper suspend/resume order.
1355 intr_register_pic(&lapic_pic);
1358 retval = best_enum->apic_setup_io();
1360 printf("%s: Failed to setup I/O APICs: returned %d\n",
1361 best_enum->apic_name, retval);
1366 * Finish setting up the local APIC on the BSP once we know how to
1367 * properly program the LINT pins.
1373 /* Enable the MSI "pic". */
1376 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
1380 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1381 * private to the MD code. The public interface for the rest of the
1382 * kernel is defined in mp_machdep.c.
1385 lapic_ipi_wait(int delay)
1390 * Wait delay microseconds for IPI to be sent. If delay is
1391 * -1, we wait forever.
1394 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != APIC_DELSTAT_IDLE)
1399 for (x = 0; x < delay; x += 5) {
1400 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1408 lapic_ipi_raw(register_t icrlo, u_int dest)
1410 register_t value, saveintr;
1412 /* XXX: Need more sanity checking of icrlo? */
1413 KASSERT(lapic != NULL, ("%s called too early", __func__));
1414 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1415 ("%s: invalid dest field", __func__));
1416 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1417 ("%s: reserved bits set in ICR LO register", __func__));
1419 /* Set destination in ICR HI register if it is being used. */
1420 saveintr = intr_disable();
1421 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1422 value = lapic->icr_hi;
1423 value &= ~APIC_ID_MASK;
1424 value |= dest << APIC_ID_SHIFT;
1425 lapic->icr_hi = value;
1428 /* Program the contents of the IPI and dispatch it. */
1429 value = lapic->icr_lo;
1430 value &= APIC_ICRLO_RESV_MASK;
1432 lapic->icr_lo = value;
1433 intr_restore(saveintr);
1436 #define BEFORE_SPIN 50000
1437 #ifdef DETECT_DEADLOCK
1438 #define AFTER_SPIN 50
1442 lapic_ipi_vectored(u_int vector, int dest)
1444 register_t icrlo, destfield;
1446 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1447 ("%s: invalid vector %d", __func__, vector));
1449 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE | APIC_LEVEL_ASSERT;
1452 * IPI_STOP_HARD is just a "fake" vector used to send a NMI.
1453 * Use special rules regard NMI if passed, otherwise specify
1456 if (vector == IPI_STOP_HARD)
1457 icrlo |= APIC_DELMODE_NMI;
1459 icrlo |= vector | APIC_DELMODE_FIXED;
1462 case APIC_IPI_DEST_SELF:
1463 icrlo |= APIC_DEST_SELF;
1465 case APIC_IPI_DEST_ALL:
1466 icrlo |= APIC_DEST_ALLISELF;
1468 case APIC_IPI_DEST_OTHERS:
1469 icrlo |= APIC_DEST_ALLESELF;
1472 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1473 ("%s: invalid destination 0x%x", __func__, dest));
1477 /* Wait for an earlier IPI to finish. */
1478 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1479 if (panicstr != NULL)
1482 panic("APIC: Previous IPI is stuck");
1485 lapic_ipi_raw(icrlo, destfield);
1487 #ifdef DETECT_DEADLOCK
1488 /* Wait for IPI to be delivered. */
1489 if (!lapic_ipi_wait(AFTER_SPIN)) {
1490 #ifdef needsattention
1494 * The above function waits for the message to actually be
1495 * delivered. It breaks out after an arbitrary timeout
1496 * since the message should eventually be delivered (at
1497 * least in theory) and that if it wasn't we would catch
1498 * the failure with the check above when the next IPI is
1501 * We could skip this wait entirely, EXCEPT it probably
1502 * protects us from other routines that assume that the
1503 * message was delivered and acted upon when this function
1506 printf("APIC: IPI might be stuck\n");
1507 #else /* !needsattention */
1508 /* Wait until mesage is sent without a timeout. */
1509 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1511 #endif /* needsattention */
1513 #endif /* DETECT_DEADLOCK */