1 /***********************license start***************
2 * Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
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7 * modification, are permitted provided that the following conditions are
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32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
35 * For any questions regarding licensing please contact marketing@caviumnetworks.com
37 ***********************license end**************************************/
42 * Configuration and status register (CSR) address and for
43 * Octeon. Include cvmx-csr.h instead of this file directly.
45 * This file is auto generated. Do not edit.
47 * <hr>$Revision: 41586 $<hr>
50 #ifndef __CVMX_CSR_ADDRESSES_H__
51 #define __CVMX_CSR_ADDRESSES_H__
53 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
54 #include "cvmx-warn.h"
57 #define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC()
58 static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
60 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
61 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
62 cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n");
64 return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
67 #define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC()
68 static inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void)
70 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
71 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
72 cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n");
74 return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
77 #define CVMX_AGL_GMX_DRV_CTL CVMX_AGL_GMX_DRV_CTL_FUNC()
78 static inline uint64_t CVMX_AGL_GMX_DRV_CTL_FUNC(void)
80 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
81 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
82 cvmx_warn("CVMX_AGL_GMX_DRV_CTL not supported on this chip\n");
84 return CVMX_ADD_IO_SEG(0x00011800E00007F0ull);
87 #define CVMX_AGL_GMX_INF_MODE CVMX_AGL_GMX_INF_MODE_FUNC()
88 static inline uint64_t CVMX_AGL_GMX_INF_MODE_FUNC(void)
90 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
91 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
92 cvmx_warn("CVMX_AGL_GMX_INF_MODE not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x00011800E00007F8ull);
97 static inline uint64_t CVMX_AGL_GMX_PRTX_CFG(unsigned long offset)
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
101 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
102 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
103 cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset);
105 return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + (offset&1)*2048;
108 static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM0(unsigned long offset)
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
112 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
113 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
114 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset);
116 return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + (offset&1)*2048;
119 static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM1(unsigned long offset)
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
123 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
124 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
125 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset);
127 return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + (offset&1)*2048;
130 static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM2(unsigned long offset)
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
134 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
136 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset);
138 return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + (offset&1)*2048;
141 static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM3(unsigned long offset)
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
145 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
146 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
147 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset);
149 return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + (offset&1)*2048;
152 static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM4(unsigned long offset)
154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
156 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
157 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
158 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset);
160 return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + (offset&1)*2048;
163 static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM5(unsigned long offset)
165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
167 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
169 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset);
171 return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + (offset&1)*2048;
174 static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM_EN(unsigned long offset)
176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
178 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
179 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
180 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset);
182 return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + (offset&1)*2048;
185 static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CTL(unsigned long offset)
187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
189 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
190 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
191 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset);
193 return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + (offset&1)*2048;
196 static inline uint64_t CVMX_AGL_GMX_RXX_DECISION(unsigned long offset)
198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
200 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
201 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
202 cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset);
204 return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + (offset&1)*2048;
207 static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CHK(unsigned long offset)
209 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
211 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
212 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
213 cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset);
215 return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + (offset&1)*2048;
218 static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CTL(unsigned long offset)
220 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
222 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
223 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
224 cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset);
226 return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + (offset&1)*2048;
229 static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MAX(unsigned long offset)
231 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
233 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
234 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
235 cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset);
237 return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + (offset&1)*2048;
240 static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MIN(unsigned long offset)
242 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
244 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
245 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
246 cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset);
248 return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + (offset&1)*2048;
251 static inline uint64_t CVMX_AGL_GMX_RXX_IFG(unsigned long offset)
253 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
255 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
256 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
257 cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset);
259 return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + (offset&1)*2048;
262 static inline uint64_t CVMX_AGL_GMX_RXX_INT_EN(unsigned long offset)
264 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
266 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
267 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
268 cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
270 return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + (offset&1)*2048;
273 static inline uint64_t CVMX_AGL_GMX_RXX_INT_REG(unsigned long offset)
275 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
277 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
278 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
279 cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset);
281 return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + (offset&1)*2048;
284 static inline uint64_t CVMX_AGL_GMX_RXX_JABBER(unsigned long offset)
286 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
288 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
289 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
290 cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset);
292 return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + (offset&1)*2048;
295 static inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset)
297 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
299 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
301 cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset);
303 return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + (offset&1)*2048;
306 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_CTL(unsigned long offset)
308 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
310 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
311 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
312 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
314 return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + (offset&1)*2048;
317 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS(unsigned long offset)
319 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
321 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
322 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
323 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset);
325 return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + (offset&1)*2048;
328 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(unsigned long offset)
330 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
332 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
333 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
334 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset);
336 return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + (offset&1)*2048;
339 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(unsigned long offset)
341 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
343 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
344 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
345 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset);
347 return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + (offset&1)*2048;
350 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(unsigned long offset)
352 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
354 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
355 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
356 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset);
358 return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + (offset&1)*2048;
361 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS(unsigned long offset)
363 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
365 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
366 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
367 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset);
369 return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + (offset&1)*2048;
372 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(unsigned long offset)
374 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
376 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
378 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset);
380 return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + (offset&1)*2048;
383 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(unsigned long offset)
385 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
387 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
388 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
389 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset);
391 return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + (offset&1)*2048;
394 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(unsigned long offset)
396 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
398 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
399 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
400 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset);
402 return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + (offset&1)*2048;
405 static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(unsigned long offset)
407 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
409 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
410 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
411 cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset);
413 return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + (offset&1)*2048;
416 static inline uint64_t CVMX_AGL_GMX_RXX_UDD_SKP(unsigned long offset)
418 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
420 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
421 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
422 cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset);
424 return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + (offset&1)*2048;
427 static inline uint64_t CVMX_AGL_GMX_RX_BP_DROPX(unsigned long offset)
429 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
431 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
432 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
433 cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset);
435 return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + (offset&1)*8;
438 static inline uint64_t CVMX_AGL_GMX_RX_BP_OFFX(unsigned long offset)
440 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
442 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
443 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
444 cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset);
446 return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + (offset&1)*8;
449 static inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset)
451 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
453 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
454 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
455 cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset);
457 return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + (offset&1)*8;
460 #define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC()
461 static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
463 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
464 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
465 cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n");
467 return CVMX_ADD_IO_SEG(0x00011800E00004E8ull);
470 #define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC()
471 static inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void)
473 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
474 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
475 cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n");
477 return CVMX_ADD_IO_SEG(0x00011800E00007E8ull);
480 static inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset)
482 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
484 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
485 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
486 cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset);
488 return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + (offset&1)*2048;
491 #define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC()
492 static inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void)
494 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
495 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
496 cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n");
498 return CVMX_ADD_IO_SEG(0x00011800E0000520ull);
501 static inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset)
503 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
505 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
506 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
507 cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset);
509 return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + (offset&1)*2048;
512 static inline uint64_t CVMX_AGL_GMX_TXX_CTL(unsigned long offset)
514 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
516 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
517 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
518 cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset);
520 return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + (offset&1)*2048;
523 static inline uint64_t CVMX_AGL_GMX_TXX_MIN_PKT(unsigned long offset)
525 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
527 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
528 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
529 cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset);
531 return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + (offset&1)*2048;
534 static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset)
536 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
538 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
539 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
540 cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset);
542 return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + (offset&1)*2048;
545 static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(unsigned long offset)
547 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
549 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
550 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
551 cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset);
553 return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + (offset&1)*2048;
556 static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_TOGO(unsigned long offset)
558 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
560 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
561 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
562 cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset);
564 return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + (offset&1)*2048;
567 static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_ZERO(unsigned long offset)
569 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
571 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
572 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
573 cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset);
575 return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + (offset&1)*2048;
578 static inline uint64_t CVMX_AGL_GMX_TXX_SOFT_PAUSE(unsigned long offset)
580 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
582 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
583 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
584 cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset);
586 return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + (offset&1)*2048;
589 static inline uint64_t CVMX_AGL_GMX_TXX_STAT0(unsigned long offset)
591 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
593 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
594 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
595 cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset);
597 return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + (offset&1)*2048;
600 static inline uint64_t CVMX_AGL_GMX_TXX_STAT1(unsigned long offset)
602 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
604 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
605 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
606 cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset);
608 return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + (offset&1)*2048;
611 static inline uint64_t CVMX_AGL_GMX_TXX_STAT2(unsigned long offset)
613 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
615 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
616 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
617 cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset);
619 return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + (offset&1)*2048;
622 static inline uint64_t CVMX_AGL_GMX_TXX_STAT3(unsigned long offset)
624 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
626 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
627 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
628 cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset);
630 return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + (offset&1)*2048;
633 static inline uint64_t CVMX_AGL_GMX_TXX_STAT4(unsigned long offset)
635 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
637 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
638 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
639 cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset);
641 return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + (offset&1)*2048;
644 static inline uint64_t CVMX_AGL_GMX_TXX_STAT5(unsigned long offset)
646 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
648 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
649 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
650 cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset);
652 return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + (offset&1)*2048;
655 static inline uint64_t CVMX_AGL_GMX_TXX_STAT6(unsigned long offset)
657 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
659 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
660 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
661 cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset);
663 return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + (offset&1)*2048;
666 static inline uint64_t CVMX_AGL_GMX_TXX_STAT7(unsigned long offset)
668 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
670 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
671 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
672 cvmx_warn("CVMX_AGL_GMX_TXX_STAT7(%lu) is invalid on this chip\n", offset);
674 return CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + (offset&1)*2048;
677 static inline uint64_t CVMX_AGL_GMX_TXX_STAT8(unsigned long offset)
679 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
681 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
682 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
683 cvmx_warn("CVMX_AGL_GMX_TXX_STAT8(%lu) is invalid on this chip\n", offset);
685 return CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + (offset&1)*2048;
688 static inline uint64_t CVMX_AGL_GMX_TXX_STAT9(unsigned long offset)
690 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
692 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
693 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
694 cvmx_warn("CVMX_AGL_GMX_TXX_STAT9(%lu) is invalid on this chip\n", offset);
696 return CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + (offset&1)*2048;
699 static inline uint64_t CVMX_AGL_GMX_TXX_STATS_CTL(unsigned long offset)
701 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
703 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
704 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
705 cvmx_warn("CVMX_AGL_GMX_TXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
707 return CVMX_ADD_IO_SEG(0x00011800E0000268ull) + (offset&1)*2048;
710 static inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset)
712 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
714 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
715 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
716 cvmx_warn("CVMX_AGL_GMX_TXX_THRESH(%lu) is invalid on this chip\n", offset);
718 return CVMX_ADD_IO_SEG(0x00011800E0000210ull) + (offset&1)*2048;
721 #define CVMX_AGL_GMX_TX_BP CVMX_AGL_GMX_TX_BP_FUNC()
722 static inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void)
724 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
725 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
726 cvmx_warn("CVMX_AGL_GMX_TX_BP not supported on this chip\n");
728 return CVMX_ADD_IO_SEG(0x00011800E00004D0ull);
731 #define CVMX_AGL_GMX_TX_COL_ATTEMPT CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC()
732 static inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void)
734 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
735 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
736 cvmx_warn("CVMX_AGL_GMX_TX_COL_ATTEMPT not supported on this chip\n");
738 return CVMX_ADD_IO_SEG(0x00011800E0000498ull);
741 #define CVMX_AGL_GMX_TX_IFG CVMX_AGL_GMX_TX_IFG_FUNC()
742 static inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void)
744 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
745 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
746 cvmx_warn("CVMX_AGL_GMX_TX_IFG not supported on this chip\n");
748 return CVMX_ADD_IO_SEG(0x00011800E0000488ull);
751 #define CVMX_AGL_GMX_TX_INT_EN CVMX_AGL_GMX_TX_INT_EN_FUNC()
752 static inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void)
754 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
755 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
756 cvmx_warn("CVMX_AGL_GMX_TX_INT_EN not supported on this chip\n");
758 return CVMX_ADD_IO_SEG(0x00011800E0000508ull);
761 #define CVMX_AGL_GMX_TX_INT_REG CVMX_AGL_GMX_TX_INT_REG_FUNC()
762 static inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void)
764 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
765 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
766 cvmx_warn("CVMX_AGL_GMX_TX_INT_REG not supported on this chip\n");
768 return CVMX_ADD_IO_SEG(0x00011800E0000500ull);
771 #define CVMX_AGL_GMX_TX_JAM CVMX_AGL_GMX_TX_JAM_FUNC()
772 static inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void)
774 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
775 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
776 cvmx_warn("CVMX_AGL_GMX_TX_JAM not supported on this chip\n");
778 return CVMX_ADD_IO_SEG(0x00011800E0000490ull);
781 #define CVMX_AGL_GMX_TX_LFSR CVMX_AGL_GMX_TX_LFSR_FUNC()
782 static inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void)
784 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
785 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
786 cvmx_warn("CVMX_AGL_GMX_TX_LFSR not supported on this chip\n");
788 return CVMX_ADD_IO_SEG(0x00011800E00004F8ull);
791 #define CVMX_AGL_GMX_TX_OVR_BP CVMX_AGL_GMX_TX_OVR_BP_FUNC()
792 static inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void)
794 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
795 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
796 cvmx_warn("CVMX_AGL_GMX_TX_OVR_BP not supported on this chip\n");
798 return CVMX_ADD_IO_SEG(0x00011800E00004C8ull);
801 #define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC()
802 static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void)
804 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
805 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
806 cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC not supported on this chip\n");
808 return CVMX_ADD_IO_SEG(0x00011800E00004A0ull);
811 #define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC()
812 static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void)
814 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
815 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
816 cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE not supported on this chip\n");
818 return CVMX_ADD_IO_SEG(0x00011800E00004A8ull);
821 #define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
822 static inline uint64_t CVMX_ASX0_DBG_DATA_DRV_FUNC(void)
824 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
825 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
826 cvmx_warn("CVMX_ASX0_DBG_DATA_DRV not supported on this chip\n");
828 return CVMX_ADD_IO_SEG(0x00011800B0000208ull);
831 #define CVMX_ASX0_DBG_DATA_ENABLE CVMX_ASX0_DBG_DATA_ENABLE_FUNC()
832 static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
834 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
835 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
836 cvmx_warn("CVMX_ASX0_DBG_DATA_ENABLE not supported on this chip\n");
838 return CVMX_ADD_IO_SEG(0x00011800B0000200ull);
841 static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
843 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
845 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
846 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
847 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
848 cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id);
850 return CVMX_ADD_IO_SEG(0x00011800B0000180ull) + (block_id&0)*0x8000000ull;
853 static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id)
855 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
857 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
858 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
859 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
860 cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
862 return CVMX_ADD_IO_SEG(0x00011800B0000188ull) + (block_id&0)*0x8000000ull;
865 static inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id)
867 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
869 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
870 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
871 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
872 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
873 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
874 cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id);
876 return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + (block_id&1)*0x8000000ull;
879 static inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id)
881 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
883 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
884 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
885 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
886 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
887 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
888 cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id);
890 return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + (block_id&1)*0x8000000ull;
893 static inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id)
895 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
897 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
898 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
899 cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
901 return CVMX_ADD_IO_SEG(0x00011800B0000190ull) + (block_id&0)*0x8000000ull;
904 static inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id)
906 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
908 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
909 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
910 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
911 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
912 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
913 cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id);
915 return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + (block_id&1)*0x8000000ull;
918 static inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id)
920 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
922 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
923 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
924 cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id);
926 return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + (block_id&1)*0x8000000ull;
929 static inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id)
931 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
933 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
934 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
935 cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id);
937 return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + (block_id&1)*0x8000000ull;
940 static inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id)
942 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
944 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
945 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
946 cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id);
948 return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + (block_id&1)*0x8000000ull;
951 static inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id)
953 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
955 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
956 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
957 cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id);
959 return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + (block_id&1)*0x8000000ull;
962 static inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id)
964 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
966 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
967 cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id);
969 return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + (block_id&1)*0x8000000ull;
972 static inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id)
974 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
976 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
977 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
978 cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id);
980 return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + (block_id&1)*0x8000000ull;
983 static inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id)
985 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
987 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
988 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
989 cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id);
991 return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + (block_id&1)*0x8000000ull;
994 static inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id)
996 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
998 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
999 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
1000 cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id);
1002 return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + (block_id&1)*0x8000000ull;
1005 static inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id)
1007 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1009 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
1010 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
1011 cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id);
1013 return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + (block_id&1)*0x8000000ull;
1016 static inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id)
1018 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1020 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
1021 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
1022 cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id);
1024 return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + (block_id&1)*0x8000000ull;
1027 static inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id)
1029 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1031 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1032 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1033 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
1034 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1035 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
1036 cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
1038 return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
1041 static inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id)
1043 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1045 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
1046 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
1047 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
1048 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
1049 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
1050 cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id);
1052 return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + (block_id&1)*0x8000000ull;
1055 static inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id)
1057 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1059 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
1060 cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id);
1062 return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + (block_id&1)*0x8000000ull;
1065 static inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id)
1067 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1069 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
1070 cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id);
1072 return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + (block_id&1)*0x8000000ull;
1075 static inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id)
1077 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1079 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
1080 cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id);
1082 return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + (block_id&1)*0x8000000ull;
1085 static inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id)
1087 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1089 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
1090 cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id);
1092 return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + (block_id&1)*0x8000000ull;
1095 static inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id)
1097 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1099 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1100 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1101 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
1102 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1103 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
1104 cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
1106 return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
1109 static inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id)
1111 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1113 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
1114 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
1115 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
1116 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
1117 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
1118 cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id);
1120 return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + (block_id&1)*0x8000000ull;
1123 static inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id)
1125 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1127 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1128 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1129 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
1130 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1131 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
1132 cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id);
1134 return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
1137 static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
1139 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1141 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
1142 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
1143 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
1144 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
1145 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
1146 cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id);
1148 return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + (block_id&1)*0x8000000ull;
1151 #define CVMX_CIU_BIST CVMX_CIU_BIST_FUNC()
1152 static inline uint64_t CVMX_CIU_BIST_FUNC(void)
1154 return CVMX_ADD_IO_SEG(0x0001070000000730ull);
1157 #define CVMX_CIU_DINT CVMX_CIU_DINT_FUNC()
1158 static inline uint64_t CVMX_CIU_DINT_FUNC(void)
1160 return CVMX_ADD_IO_SEG(0x0001070000000720ull);
1163 #define CVMX_CIU_FUSE CVMX_CIU_FUSE_FUNC()
1164 static inline uint64_t CVMX_CIU_FUSE_FUNC(void)
1166 return CVMX_ADD_IO_SEG(0x0001070000000728ull);
1169 #define CVMX_CIU_GSTOP CVMX_CIU_GSTOP_FUNC()
1170 static inline uint64_t CVMX_CIU_GSTOP_FUNC(void)
1172 return CVMX_ADD_IO_SEG(0x0001070000000710ull);
1175 static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset)
1177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1179 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
1180 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
1181 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
1182 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
1183 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
1184 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
1185 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32)))))
1186 cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset);
1188 return CVMX_ADD_IO_SEG(0x0001070000000200ull) + (offset&63)*16;
1191 static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset)
1193 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1195 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
1196 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
1197 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
1198 cvmx_warn("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n", offset);
1200 return CVMX_ADD_IO_SEG(0x0001070000002200ull) + (offset&63)*16;
1203 static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset)
1205 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1207 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
1208 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
1209 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
1210 cvmx_warn("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n", offset);
1212 return CVMX_ADD_IO_SEG(0x0001070000006200ull) + (offset&63)*16;
1215 static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset)
1217 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1219 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
1220 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
1221 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
1222 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
1223 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
1224 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
1225 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32)))))
1226 cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset);
1228 return CVMX_ADD_IO_SEG(0x0001070000000208ull) + (offset&63)*16;
1231 static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset)
1233 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1235 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
1236 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
1237 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
1238 cvmx_warn("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n", offset);
1240 return CVMX_ADD_IO_SEG(0x0001070000002208ull) + (offset&63)*16;
1243 static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset)
1245 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1247 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
1248 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
1249 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
1250 cvmx_warn("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n", offset);
1252 return CVMX_ADD_IO_SEG(0x0001070000006208ull) + (offset&63)*16;
1255 static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset)
1257 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1259 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1260 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
1261 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1262 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
1263 cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n", offset);
1265 return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + (offset&15)*16;
1268 static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset)
1270 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1272 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1273 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
1274 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
1275 cvmx_warn("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n", offset);
1277 return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + (offset&15)*16;
1280 static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset)
1282 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1284 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1285 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
1286 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
1287 cvmx_warn("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n", offset);
1289 return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + (offset&15)*16;
1292 static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset)
1294 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1296 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1297 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
1298 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1299 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
1300 cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n", offset);
1302 return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + (offset&15)*16;
1305 static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset)
1307 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1309 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1310 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
1311 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
1312 cvmx_warn("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n", offset);
1314 return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + (offset&15)*16;
1317 static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset)
1319 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1321 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1322 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
1323 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
1324 cvmx_warn("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n", offset);
1326 return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + (offset&15)*16;
1329 static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset)
1331 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1333 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
1334 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
1335 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
1336 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
1337 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
1338 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
1339 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32)))))
1340 cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n", offset);
1342 return CVMX_ADD_IO_SEG(0x0001070000000000ull) + (offset&63)*8;
1345 static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
1347 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1349 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1350 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
1351 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1352 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
1353 cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n", offset);
1355 return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + (offset&15)*8;
1358 #define CVMX_CIU_INT_SUM1 CVMX_CIU_INT_SUM1_FUNC()
1359 static inline uint64_t CVMX_CIU_INT_SUM1_FUNC(void)
1361 return CVMX_ADD_IO_SEG(0x0001070000000108ull);
1364 static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
1366 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1368 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1369 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
1370 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1371 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
1372 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1373 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
1374 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
1375 cvmx_warn("CVMX_CIU_MBOX_CLRX(%lu) is invalid on this chip\n", offset);
1377 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset&15)*8;
1380 static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
1382 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1384 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1385 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
1386 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1387 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
1388 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1389 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
1390 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
1391 cvmx_warn("CVMX_CIU_MBOX_SETX(%lu) is invalid on this chip\n", offset);
1393 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset&15)*8;
1396 #define CVMX_CIU_NMI CVMX_CIU_NMI_FUNC()
1397 static inline uint64_t CVMX_CIU_NMI_FUNC(void)
1399 return CVMX_ADD_IO_SEG(0x0001070000000718ull);
1402 #define CVMX_CIU_PCI_INTA CVMX_CIU_PCI_INTA_FUNC()
1403 static inline uint64_t CVMX_CIU_PCI_INTA_FUNC(void)
1405 return CVMX_ADD_IO_SEG(0x0001070000000750ull);
1408 #define CVMX_CIU_PP_DBG CVMX_CIU_PP_DBG_FUNC()
1409 static inline uint64_t CVMX_CIU_PP_DBG_FUNC(void)
1411 return CVMX_ADD_IO_SEG(0x0001070000000708ull);
1414 static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
1416 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1418 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1419 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
1420 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1421 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
1422 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1423 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
1424 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
1425 cvmx_warn("CVMX_CIU_PP_POKEX(%lu) is invalid on this chip\n", offset);
1427 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset&15)*8;
1430 #define CVMX_CIU_PP_RST CVMX_CIU_PP_RST_FUNC()
1431 static inline uint64_t CVMX_CIU_PP_RST_FUNC(void)
1433 return CVMX_ADD_IO_SEG(0x0001070000000700ull);
1436 #define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC()
1437 static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
1439 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1440 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1441 cvmx_warn("CVMX_CIU_QLM_DCOK not supported on this chip\n");
1443 return CVMX_ADD_IO_SEG(0x0001070000000760ull);
1446 #define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC()
1447 static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
1449 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1450 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1451 cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n");
1453 return CVMX_ADD_IO_SEG(0x0001070000000768ull);
1456 #define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC()
1457 static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
1459 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1460 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1461 cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n");
1463 return CVMX_ADD_IO_SEG(0x0001070000000770ull);
1466 #define CVMX_CIU_SOFT_BIST CVMX_CIU_SOFT_BIST_FUNC()
1467 static inline uint64_t CVMX_CIU_SOFT_BIST_FUNC(void)
1469 return CVMX_ADD_IO_SEG(0x0001070000000738ull);
1472 #define CVMX_CIU_SOFT_PRST CVMX_CIU_SOFT_PRST_FUNC()
1473 static inline uint64_t CVMX_CIU_SOFT_PRST_FUNC(void)
1475 return CVMX_ADD_IO_SEG(0x0001070000000748ull);
1478 #define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC()
1479 static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void)
1481 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1482 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1483 cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n");
1485 return CVMX_ADD_IO_SEG(0x0001070000000758ull);
1488 #define CVMX_CIU_SOFT_RST CVMX_CIU_SOFT_RST_FUNC()
1489 static inline uint64_t CVMX_CIU_SOFT_RST_FUNC(void)
1491 return CVMX_ADD_IO_SEG(0x0001070000000740ull);
1494 static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
1496 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1498 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
1499 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
1500 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
1501 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
1502 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
1503 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
1504 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
1505 cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n", offset);
1507 return CVMX_ADD_IO_SEG(0x0001070000000480ull) + (offset&3)*8;
1510 static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
1512 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1514 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
1515 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
1516 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1517 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
1518 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1519 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
1520 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
1521 cvmx_warn("CVMX_CIU_WDOGX(%lu) is invalid on this chip\n", offset);
1523 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset&15)*8;
1526 #define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
1527 static inline uint64_t CVMX_DBG_DATA_FUNC(void)
1529 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1530 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1531 cvmx_warn("CVMX_DBG_DATA not supported on this chip\n");
1533 return CVMX_ADD_IO_SEG(0x00011F00000001E8ull);
1536 #define CVMX_DFA_BST0 CVMX_DFA_BST0_FUNC()
1537 static inline uint64_t CVMX_DFA_BST0_FUNC(void)
1539 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1540 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1541 cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n");
1543 return CVMX_ADD_IO_SEG(0x00011800300007F0ull);
1546 #define CVMX_DFA_BST1 CVMX_DFA_BST1_FUNC()
1547 static inline uint64_t CVMX_DFA_BST1_FUNC(void)
1549 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1550 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1551 cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n");
1553 return CVMX_ADD_IO_SEG(0x00011800300007F8ull);
1556 #define CVMX_DFA_CFG CVMX_DFA_CFG_FUNC()
1557 static inline uint64_t CVMX_DFA_CFG_FUNC(void)
1559 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1560 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1561 cvmx_warn("CVMX_DFA_CFG not supported on this chip\n");
1563 return CVMX_ADD_IO_SEG(0x0001180030000000ull);
1566 #define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC()
1567 static inline uint64_t CVMX_DFA_DBELL_FUNC(void)
1569 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1570 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1571 cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n");
1573 return CVMX_ADD_IO_SEG(0x0001370000000000ull);
1576 #define CVMX_DFA_DDR2_ADDR CVMX_DFA_DDR2_ADDR_FUNC()
1577 static inline uint64_t CVMX_DFA_DDR2_ADDR_FUNC(void)
1579 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1580 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1581 cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n");
1583 return CVMX_ADD_IO_SEG(0x0001180030000210ull);
1586 #define CVMX_DFA_DDR2_BUS CVMX_DFA_DDR2_BUS_FUNC()
1587 static inline uint64_t CVMX_DFA_DDR2_BUS_FUNC(void)
1589 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1590 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1591 cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n");
1593 return CVMX_ADD_IO_SEG(0x0001180030000080ull);
1596 #define CVMX_DFA_DDR2_CFG CVMX_DFA_DDR2_CFG_FUNC()
1597 static inline uint64_t CVMX_DFA_DDR2_CFG_FUNC(void)
1599 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1600 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1601 cvmx_warn("CVMX_DFA_DDR2_CFG not supported on this chip\n");
1603 return CVMX_ADD_IO_SEG(0x0001180030000208ull);
1606 #define CVMX_DFA_DDR2_COMP CVMX_DFA_DDR2_COMP_FUNC()
1607 static inline uint64_t CVMX_DFA_DDR2_COMP_FUNC(void)
1609 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1610 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1611 cvmx_warn("CVMX_DFA_DDR2_COMP not supported on this chip\n");
1613 return CVMX_ADD_IO_SEG(0x0001180030000090ull);
1616 #define CVMX_DFA_DDR2_EMRS CVMX_DFA_DDR2_EMRS_FUNC()
1617 static inline uint64_t CVMX_DFA_DDR2_EMRS_FUNC(void)
1619 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1620 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1621 cvmx_warn("CVMX_DFA_DDR2_EMRS not supported on this chip\n");
1623 return CVMX_ADD_IO_SEG(0x0001180030000268ull);
1626 #define CVMX_DFA_DDR2_FCNT CVMX_DFA_DDR2_FCNT_FUNC()
1627 static inline uint64_t CVMX_DFA_DDR2_FCNT_FUNC(void)
1629 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1630 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1631 cvmx_warn("CVMX_DFA_DDR2_FCNT not supported on this chip\n");
1633 return CVMX_ADD_IO_SEG(0x0001180030000078ull);
1636 #define CVMX_DFA_DDR2_MRS CVMX_DFA_DDR2_MRS_FUNC()
1637 static inline uint64_t CVMX_DFA_DDR2_MRS_FUNC(void)
1639 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1640 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1641 cvmx_warn("CVMX_DFA_DDR2_MRS not supported on this chip\n");
1643 return CVMX_ADD_IO_SEG(0x0001180030000260ull);
1646 #define CVMX_DFA_DDR2_OPT CVMX_DFA_DDR2_OPT_FUNC()
1647 static inline uint64_t CVMX_DFA_DDR2_OPT_FUNC(void)
1649 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1650 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1651 cvmx_warn("CVMX_DFA_DDR2_OPT not supported on this chip\n");
1653 return CVMX_ADD_IO_SEG(0x0001180030000070ull);
1656 #define CVMX_DFA_DDR2_PLL CVMX_DFA_DDR2_PLL_FUNC()
1657 static inline uint64_t CVMX_DFA_DDR2_PLL_FUNC(void)
1659 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1660 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1661 cvmx_warn("CVMX_DFA_DDR2_PLL not supported on this chip\n");
1663 return CVMX_ADD_IO_SEG(0x0001180030000088ull);
1666 #define CVMX_DFA_DDR2_TMG CVMX_DFA_DDR2_TMG_FUNC()
1667 static inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void)
1669 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1670 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1671 cvmx_warn("CVMX_DFA_DDR2_TMG not supported on this chip\n");
1673 return CVMX_ADD_IO_SEG(0x0001180030000218ull);
1676 #define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC()
1677 static inline uint64_t CVMX_DFA_DIFCTL_FUNC(void)
1679 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1680 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1681 cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n");
1683 return CVMX_ADD_IO_SEG(0x0001370600000000ull);
1686 #define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC()
1687 static inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void)
1689 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1690 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1691 cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n");
1693 return CVMX_ADD_IO_SEG(0x0001370200000000ull);
1696 #define CVMX_DFA_ECLKCFG CVMX_DFA_ECLKCFG_FUNC()
1697 static inline uint64_t CVMX_DFA_ECLKCFG_FUNC(void)
1699 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1700 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
1701 cvmx_warn("CVMX_DFA_ECLKCFG not supported on this chip\n");
1703 return CVMX_ADD_IO_SEG(0x0001180030000200ull);
1706 #define CVMX_DFA_ERR CVMX_DFA_ERR_FUNC()
1707 static inline uint64_t CVMX_DFA_ERR_FUNC(void)
1709 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1710 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1711 cvmx_warn("CVMX_DFA_ERR not supported on this chip\n");
1713 return CVMX_ADD_IO_SEG(0x0001180030000028ull);
1716 #define CVMX_DFA_MEMCFG0 CVMX_DFA_MEMCFG0_FUNC()
1717 static inline uint64_t CVMX_DFA_MEMCFG0_FUNC(void)
1719 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1720 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1721 cvmx_warn("CVMX_DFA_MEMCFG0 not supported on this chip\n");
1723 return CVMX_ADD_IO_SEG(0x0001180030000008ull);
1726 #define CVMX_DFA_MEMCFG1 CVMX_DFA_MEMCFG1_FUNC()
1727 static inline uint64_t CVMX_DFA_MEMCFG1_FUNC(void)
1729 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1730 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1731 cvmx_warn("CVMX_DFA_MEMCFG1 not supported on this chip\n");
1733 return CVMX_ADD_IO_SEG(0x0001180030000010ull);
1736 #define CVMX_DFA_MEMCFG2 CVMX_DFA_MEMCFG2_FUNC()
1737 static inline uint64_t CVMX_DFA_MEMCFG2_FUNC(void)
1739 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1740 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1741 cvmx_warn("CVMX_DFA_MEMCFG2 not supported on this chip\n");
1743 return CVMX_ADD_IO_SEG(0x0001180030000060ull);
1746 #define CVMX_DFA_MEMFADR CVMX_DFA_MEMFADR_FUNC()
1747 static inline uint64_t CVMX_DFA_MEMFADR_FUNC(void)
1749 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1750 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1751 cvmx_warn("CVMX_DFA_MEMFADR not supported on this chip\n");
1753 return CVMX_ADD_IO_SEG(0x0001180030000030ull);
1756 #define CVMX_DFA_MEMFCR CVMX_DFA_MEMFCR_FUNC()
1757 static inline uint64_t CVMX_DFA_MEMFCR_FUNC(void)
1759 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1760 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1761 cvmx_warn("CVMX_DFA_MEMFCR not supported on this chip\n");
1763 return CVMX_ADD_IO_SEG(0x0001180030000038ull);
1766 #define CVMX_DFA_MEMRLD CVMX_DFA_MEMRLD_FUNC()
1767 static inline uint64_t CVMX_DFA_MEMRLD_FUNC(void)
1769 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1770 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1771 cvmx_warn("CVMX_DFA_MEMRLD not supported on this chip\n");
1773 return CVMX_ADD_IO_SEG(0x0001180030000018ull);
1776 #define CVMX_DFA_NCBCTL CVMX_DFA_NCBCTL_FUNC()
1777 static inline uint64_t CVMX_DFA_NCBCTL_FUNC(void)
1779 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1780 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1781 cvmx_warn("CVMX_DFA_NCBCTL not supported on this chip\n");
1783 return CVMX_ADD_IO_SEG(0x0001180030000020ull);
1786 #define CVMX_DFA_RODT_COMP_CTL CVMX_DFA_RODT_COMP_CTL_FUNC()
1787 static inline uint64_t CVMX_DFA_RODT_COMP_CTL_FUNC(void)
1789 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1790 if (!(OCTEON_IS_MODEL(OCTEON_CN58XX)))
1791 cvmx_warn("CVMX_DFA_RODT_COMP_CTL not supported on this chip\n");
1793 return CVMX_ADD_IO_SEG(0x0001180030000068ull);
1796 #define CVMX_DFA_SBD_DBG0 CVMX_DFA_SBD_DBG0_FUNC()
1797 static inline uint64_t CVMX_DFA_SBD_DBG0_FUNC(void)
1799 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1800 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1801 cvmx_warn("CVMX_DFA_SBD_DBG0 not supported on this chip\n");
1803 return CVMX_ADD_IO_SEG(0x0001180030000040ull);
1806 #define CVMX_DFA_SBD_DBG1 CVMX_DFA_SBD_DBG1_FUNC()
1807 static inline uint64_t CVMX_DFA_SBD_DBG1_FUNC(void)
1809 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1810 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1811 cvmx_warn("CVMX_DFA_SBD_DBG1 not supported on this chip\n");
1813 return CVMX_ADD_IO_SEG(0x0001180030000048ull);
1816 #define CVMX_DFA_SBD_DBG2 CVMX_DFA_SBD_DBG2_FUNC()
1817 static inline uint64_t CVMX_DFA_SBD_DBG2_FUNC(void)
1819 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1820 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1821 cvmx_warn("CVMX_DFA_SBD_DBG2 not supported on this chip\n");
1823 return CVMX_ADD_IO_SEG(0x0001180030000050ull);
1826 #define CVMX_DFA_SBD_DBG3 CVMX_DFA_SBD_DBG3_FUNC()
1827 static inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void)
1829 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1830 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1831 cvmx_warn("CVMX_DFA_SBD_DBG3 not supported on this chip\n");
1833 return CVMX_ADD_IO_SEG(0x0001180030000058ull);
1836 #define CVMX_FPA_BIST_STATUS CVMX_FPA_BIST_STATUS_FUNC()
1837 static inline uint64_t CVMX_FPA_BIST_STATUS_FUNC(void)
1839 return CVMX_ADD_IO_SEG(0x00011800280000E8ull);
1842 #define CVMX_FPA_CTL_STATUS CVMX_FPA_CTL_STATUS_FUNC()
1843 static inline uint64_t CVMX_FPA_CTL_STATUS_FUNC(void)
1845 return CVMX_ADD_IO_SEG(0x0001180028000050ull);
1848 #define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC()
1849 static inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void)
1851 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1852 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1853 cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n");
1855 return CVMX_ADD_IO_SEG(0x0001180028000000ull);
1858 #define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC()
1859 static inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void)
1861 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1862 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1863 cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n");
1865 return CVMX_ADD_IO_SEG(0x0001180028000058ull);
1868 #define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
1869 #define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
1870 #define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
1871 #define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
1872 #define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
1873 #define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
1874 #define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
1875 static inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset)
1877 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1879 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
1880 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
1881 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7))))))
1882 cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset);
1884 return CVMX_ADD_IO_SEG(0x0001180028000008ull) + (offset&7)*8 - 8*1;
1887 static inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset)
1889 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1891 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
1892 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
1893 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7))))))
1894 cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset);
1896 return CVMX_ADD_IO_SEG(0x0001180028000060ull) + (offset&7)*8 - 8*1;
1899 #define CVMX_FPA_INT_ENB CVMX_FPA_INT_ENB_FUNC()
1900 static inline uint64_t CVMX_FPA_INT_ENB_FUNC(void)
1902 return CVMX_ADD_IO_SEG(0x0001180028000048ull);
1905 #define CVMX_FPA_INT_SUM CVMX_FPA_INT_SUM_FUNC()
1906 static inline uint64_t CVMX_FPA_INT_SUM_FUNC(void)
1908 return CVMX_ADD_IO_SEG(0x0001180028000040ull);
1911 #define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
1912 #define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
1913 #define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
1914 #define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
1915 #define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
1916 #define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
1917 #define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
1918 #define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
1919 static inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset)
1921 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1923 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
1924 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
1925 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
1926 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
1927 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
1928 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
1929 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
1930 cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset);
1932 return CVMX_ADD_IO_SEG(0x0001180028000098ull) + (offset&7)*8;
1935 static inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset)
1937 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1939 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
1940 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
1941 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
1942 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
1943 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
1944 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
1945 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
1946 cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset);
1948 return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + (offset&7)*8;
1951 #define CVMX_FPA_QUE_ACT CVMX_FPA_QUE_ACT_FUNC()
1952 static inline uint64_t CVMX_FPA_QUE_ACT_FUNC(void)
1954 return CVMX_ADD_IO_SEG(0x0001180028000138ull);
1957 #define CVMX_FPA_QUE_EXP CVMX_FPA_QUE_EXP_FUNC()
1958 static inline uint64_t CVMX_FPA_QUE_EXP_FUNC(void)
1960 return CVMX_ADD_IO_SEG(0x0001180028000130ull);
1963 #define CVMX_FPA_WART_CTL CVMX_FPA_WART_CTL_FUNC()
1964 static inline uint64_t CVMX_FPA_WART_CTL_FUNC(void)
1966 return CVMX_ADD_IO_SEG(0x00011800280000D8ull);
1969 #define CVMX_FPA_WART_STATUS CVMX_FPA_WART_STATUS_FUNC()
1970 static inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void)
1972 return CVMX_ADD_IO_SEG(0x00011800280000E0ull);
1975 static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
1977 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1979 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
1980 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
1981 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
1982 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
1983 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
1984 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
1985 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
1986 cvmx_warn("CVMX_GMXX_BAD_REG(%lu) is invalid on this chip\n", block_id);
1988 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id&1)*0x8000000ull;
1991 static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
1993 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1995 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
1996 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
1997 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
1998 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
1999 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
2000 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
2001 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2002 cvmx_warn("CVMX_GMXX_BIST(%lu) is invalid on this chip\n", block_id);
2004 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id&1)*0x8000000ull;
2007 static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
2009 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2011 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2012 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2013 cvmx_warn("CVMX_GMXX_CLK_EN(%lu) is invalid on this chip\n", block_id);
2015 return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id&1)*0x8000000ull;
2018 static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
2020 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2022 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2023 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2024 cvmx_warn("CVMX_GMXX_HG2_CONTROL(%lu) is invalid on this chip\n", block_id);
2026 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id&1)*0x8000000ull;
2029 static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
2031 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2033 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2034 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
2035 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
2036 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
2037 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
2038 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
2039 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2040 cvmx_warn("CVMX_GMXX_INF_MODE(%lu) is invalid on this chip\n", block_id);
2042 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id&1)*0x8000000ull;
2045 static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
2047 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2049 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2050 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
2051 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
2052 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
2053 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
2054 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
2055 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2056 cvmx_warn("CVMX_GMXX_NXA_ADR(%lu) is invalid on this chip\n", block_id);
2058 return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id&1)*0x8000000ull;
2061 static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
2063 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2065 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
2066 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0))))))
2067 cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
2069 return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((offset&0) + (block_id&1)*0x1000000ull)*8;
2072 static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
2074 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2076 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2077 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2078 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2079 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2080 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2081 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2082 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2083 cvmx_warn("CVMX_GMXX_PRTX_CFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
2085 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2088 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
2090 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2092 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2093 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2094 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2095 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2096 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2097 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2098 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2099 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0(%lu,%lu) is invalid on this chip\n", offset, block_id);
2101 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2104 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
2106 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2109 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2110 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2111 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2112 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2113 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2114 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2115 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1(%lu,%lu) is invalid on this chip\n", offset, block_id);
2117 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2120 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
2122 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2124 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2125 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2126 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2127 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2128 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2129 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2130 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2131 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2(%lu,%lu) is invalid on this chip\n", offset, block_id);
2133 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2136 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
2138 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2140 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2141 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2142 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2143 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2144 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2145 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2146 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2147 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3(%lu,%lu) is invalid on this chip\n", offset, block_id);
2149 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2152 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
2154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2156 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2157 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2158 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2159 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2160 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2161 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2162 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2163 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4(%lu,%lu) is invalid on this chip\n", offset, block_id);
2165 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2168 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
2170 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2172 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2173 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2174 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2175 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2176 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2177 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2178 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2179 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5(%lu,%lu) is invalid on this chip\n", offset, block_id);
2181 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2184 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
2186 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2188 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2189 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2190 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2191 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2192 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2193 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2194 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2195 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
2197 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2200 static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
2202 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2204 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2205 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2206 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2207 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2208 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2209 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2210 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2211 cvmx_warn("CVMX_GMXX_RXX_ADR_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
2213 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2216 static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
2218 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2220 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2221 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2222 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2223 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2224 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2225 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2226 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2227 cvmx_warn("CVMX_GMXX_RXX_DECISION(%lu,%lu) is invalid on this chip\n", offset, block_id);
2229 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2232 static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
2234 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2236 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2237 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2238 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2239 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2241 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2242 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2243 cvmx_warn("CVMX_GMXX_RXX_FRM_CHK(%lu,%lu) is invalid on this chip\n", offset, block_id);
2245 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2248 static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
2250 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2252 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2253 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2254 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2255 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2256 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2257 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2258 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2259 cvmx_warn("CVMX_GMXX_RXX_FRM_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
2261 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2264 static inline uint64_t CVMX_GMXX_RXX_FRM_MAX(unsigned long offset, unsigned long block_id)
2266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2268 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2269 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2270 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2271 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
2272 cvmx_warn("CVMX_GMXX_RXX_FRM_MAX(%lu,%lu) is invalid on this chip\n", offset, block_id);
2274 return CVMX_ADD_IO_SEG(0x0001180008000030ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2277 static inline uint64_t CVMX_GMXX_RXX_FRM_MIN(unsigned long offset, unsigned long block_id)
2279 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2281 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2282 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2283 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2284 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
2285 cvmx_warn("CVMX_GMXX_RXX_FRM_MIN(%lu,%lu) is invalid on this chip\n", offset, block_id);
2287 return CVMX_ADD_IO_SEG(0x0001180008000028ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2290 static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
2292 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2294 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2295 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2296 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2297 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2298 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2299 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2300 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2301 cvmx_warn("CVMX_GMXX_RXX_IFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
2303 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2306 static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
2308 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2310 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2311 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2312 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2313 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2314 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2315 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2316 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2317 cvmx_warn("CVMX_GMXX_RXX_INT_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
2319 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2322 static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
2324 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2326 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2327 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2328 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2329 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2330 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2331 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2332 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2333 cvmx_warn("CVMX_GMXX_RXX_INT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
2335 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2338 static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
2340 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2342 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2343 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2344 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2345 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2346 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2347 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2348 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2349 cvmx_warn("CVMX_GMXX_RXX_JABBER(%lu,%lu) is invalid on this chip\n", offset, block_id);
2351 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2354 static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
2356 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2358 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2359 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2360 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2361 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2362 cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
2364 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2367 static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned long block_id)
2369 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2371 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2372 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2373 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2374 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2375 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
2376 cvmx_warn("CVMX_GMXX_RXX_RX_INBND(%lu,%lu) is invalid on this chip\n", offset, block_id);
2378 return CVMX_ADD_IO_SEG(0x0001180008000060ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2381 static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
2383 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2385 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2386 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2387 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2388 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2389 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2390 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2391 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2392 cvmx_warn("CVMX_GMXX_RXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
2394 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2397 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
2399 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2401 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2402 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2403 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2404 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2405 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2406 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2407 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2408 cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
2410 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2413 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
2415 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2417 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2418 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2419 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2420 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2421 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2422 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2423 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2424 cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
2426 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2429 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
2431 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2433 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2434 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2435 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2436 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2437 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2438 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2439 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2440 cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
2442 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2445 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
2447 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2449 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2450 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2451 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2452 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2453 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2454 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2455 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2456 cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
2458 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2461 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
2463 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2465 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2466 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2467 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2468 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2469 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2470 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2471 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2472 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
2474 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2477 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
2479 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2481 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2482 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2483 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2484 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2485 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2486 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2487 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2488 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD(%lu,%lu) is invalid on this chip\n", offset, block_id);
2490 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2493 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
2495 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2497 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2498 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2499 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2500 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2501 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2502 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2503 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2504 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
2506 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2509 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
2511 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2513 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2514 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2515 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2516 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2517 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2518 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2519 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2520 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
2522 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2525 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
2527 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2529 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2530 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2531 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2532 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2533 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2534 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2535 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2536 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
2538 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2541 static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
2543 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2545 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2546 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2547 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2548 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2549 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2550 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2551 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2552 cvmx_warn("CVMX_GMXX_RXX_UDD_SKP(%lu,%lu) is invalid on this chip\n", offset, block_id);
2554 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2557 static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
2559 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2561 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2562 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2563 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2564 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2565 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2566 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2567 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2568 cvmx_warn("CVMX_GMXX_RX_BP_DROPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
2570 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
2573 static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
2575 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2577 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2578 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2579 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2580 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2581 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2582 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2583 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2584 cvmx_warn("CVMX_GMXX_RX_BP_OFFX(%lu,%lu) is invalid on this chip\n", offset, block_id);
2586 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
2589 static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
2591 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2593 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2594 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2595 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2596 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2597 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2598 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2599 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2600 cvmx_warn("CVMX_GMXX_RX_BP_ONX(%lu,%lu) is invalid on this chip\n", offset, block_id);
2602 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
2605 static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
2607 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2609 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2610 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2611 cvmx_warn("CVMX_GMXX_RX_HG2_STATUS(%lu) is invalid on this chip\n", block_id);
2613 return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id&1)*0x8000000ull;
2616 static inline uint64_t CVMX_GMXX_RX_PASS_EN(unsigned long block_id)
2618 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2620 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
2621 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
2622 cvmx_warn("CVMX_GMXX_RX_PASS_EN(%lu) is invalid on this chip\n", block_id);
2624 return CVMX_ADD_IO_SEG(0x00011800080005F8ull) + (block_id&1)*0x8000000ull;
2627 static inline uint64_t CVMX_GMXX_RX_PASS_MAPX(unsigned long offset, unsigned long block_id)
2629 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2631 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
2632 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 15)) && ((block_id <= 1))))))
2633 cvmx_warn("CVMX_GMXX_RX_PASS_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
2635 return CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((offset&15) + (block_id&1)*0x1000000ull)*8;
2638 static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
2640 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2642 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2643 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
2644 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
2645 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
2646 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
2647 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
2648 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2649 cvmx_warn("CVMX_GMXX_RX_PRTS(%lu) is invalid on this chip\n", block_id);
2651 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id&1)*0x8000000ull;
2654 static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
2656 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2658 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
2659 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
2660 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
2661 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
2662 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
2663 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2664 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2665 cvmx_warn("CVMX_GMXX_RX_PRT_INFO(%lu) is invalid on this chip\n", block_id);
2667 return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id&1)*0x8000000ull;
2670 static inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id)
2672 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2674 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
2675 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
2676 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
2677 cvmx_warn("CVMX_GMXX_RX_TX_STATUS(%lu) is invalid on this chip\n", block_id);
2679 return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id&0)*0x8000000ull;
2682 static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
2684 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2686 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2687 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2688 cvmx_warn("CVMX_GMXX_RX_XAUI_BAD_COL(%lu) is invalid on this chip\n", block_id);
2690 return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id&1)*0x8000000ull;
2693 static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
2695 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2697 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2698 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2699 cvmx_warn("CVMX_GMXX_RX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
2701 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id&1)*0x8000000ull;
2704 static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
2706 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2708 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2709 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2710 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2711 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2712 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2713 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2714 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2715 cvmx_warn("CVMX_GMXX_SMACX(%lu,%lu) is invalid on this chip\n", offset, block_id);
2717 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2720 static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
2722 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2724 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
2725 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
2726 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
2727 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
2728 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
2729 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
2730 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
2731 cvmx_warn("CVMX_GMXX_STAT_BP(%lu) is invalid on this chip\n", block_id);
2733 return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id&1)*0x8000000ull;
2736 static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
2738 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2740 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2741 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2742 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2743 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2744 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2745 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2746 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2747 cvmx_warn("CVMX_GMXX_TXX_APPEND(%lu,%lu) is invalid on this chip\n", offset, block_id);
2749 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2752 static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
2754 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2756 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2757 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2758 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2759 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2760 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2761 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2762 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2763 cvmx_warn("CVMX_GMXX_TXX_BURST(%lu,%lu) is invalid on this chip\n", offset, block_id);
2765 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2768 static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
2770 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2772 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
2773 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0))))))
2774 cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF(%lu,%lu) is invalid on this chip\n", offset, block_id);
2776 return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((offset&0) + (block_id&1)*0x1000000ull)*8;
2779 static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
2781 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2783 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
2784 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0))))))
2785 cvmx_warn("CVMX_GMXX_TXX_CBFC_XON(%lu,%lu) is invalid on this chip\n", offset, block_id);
2787 return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((offset&0) + (block_id&1)*0x1000000ull)*8;
2790 static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long block_id)
2792 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2794 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2795 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2796 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2797 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2798 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
2799 cvmx_warn("CVMX_GMXX_TXX_CLK(%lu,%lu) is invalid on this chip\n", offset, block_id);
2801 return CVMX_ADD_IO_SEG(0x0001180008000208ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2804 static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
2806 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2808 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2809 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2810 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2811 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2812 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2813 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2814 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2815 cvmx_warn("CVMX_GMXX_TXX_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
2817 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2820 static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
2822 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2824 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2825 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2826 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2827 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2828 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2829 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2830 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2831 cvmx_warn("CVMX_GMXX_TXX_MIN_PKT(%lu,%lu) is invalid on this chip\n", offset, block_id);
2833 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2836 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
2838 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2840 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2841 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2842 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2843 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2844 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2845 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2846 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2847 cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(%lu,%lu) is invalid on this chip\n", offset, block_id);
2849 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2852 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
2854 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2856 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2857 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2858 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2859 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2860 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2861 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2862 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2863 cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
2865 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2868 static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
2870 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2872 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2873 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2874 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2875 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2876 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2877 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2878 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2879 cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO(%lu,%lu) is invalid on this chip\n", offset, block_id);
2881 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2884 static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
2886 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2888 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2889 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2890 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2891 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2892 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2893 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2894 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2895 cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO(%lu,%lu) is invalid on this chip\n", offset, block_id);
2897 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2900 static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
2902 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2904 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2905 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2906 cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
2908 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2911 static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
2913 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2915 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2916 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2917 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2918 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2919 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2920 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2921 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2922 cvmx_warn("CVMX_GMXX_TXX_SLOT(%lu,%lu) is invalid on this chip\n", offset, block_id);
2924 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2927 static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
2929 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2931 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2932 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2933 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2934 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2935 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2936 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2937 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2938 cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE(%lu,%lu) is invalid on this chip\n", offset, block_id);
2940 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2943 static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
2945 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2947 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2948 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2949 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2950 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2951 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2952 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2953 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2954 cvmx_warn("CVMX_GMXX_TXX_STAT0(%lu,%lu) is invalid on this chip\n", offset, block_id);
2956 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2959 static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
2961 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2963 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2964 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2965 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2966 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2967 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2968 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2969 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2970 cvmx_warn("CVMX_GMXX_TXX_STAT1(%lu,%lu) is invalid on this chip\n", offset, block_id);
2972 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2975 static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
2977 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2979 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2980 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2981 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2982 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2983 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2984 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2985 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
2986 cvmx_warn("CVMX_GMXX_TXX_STAT2(%lu,%lu) is invalid on this chip\n", offset, block_id);
2988 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
2991 static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
2993 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2995 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2996 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2997 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
2998 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
2999 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3000 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3001 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
3002 cvmx_warn("CVMX_GMXX_TXX_STAT3(%lu,%lu) is invalid on this chip\n", offset, block_id);
3004 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
3007 static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
3009 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3011 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3012 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3013 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3014 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3015 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3016 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3017 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
3018 cvmx_warn("CVMX_GMXX_TXX_STAT4(%lu,%lu) is invalid on this chip\n", offset, block_id);
3020 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
3023 static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
3025 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3027 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3028 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3029 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3030 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3031 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3032 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3033 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
3034 cvmx_warn("CVMX_GMXX_TXX_STAT5(%lu,%lu) is invalid on this chip\n", offset, block_id);
3036 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
3039 static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
3041 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3043 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3044 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3045 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3046 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3047 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3048 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3049 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
3050 cvmx_warn("CVMX_GMXX_TXX_STAT6(%lu,%lu) is invalid on this chip\n", offset, block_id);
3052 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
3055 static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
3057 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3059 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3060 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3061 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3062 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3063 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3064 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3065 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
3066 cvmx_warn("CVMX_GMXX_TXX_STAT7(%lu,%lu) is invalid on this chip\n", offset, block_id);
3068 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
3071 static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
3073 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3075 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3076 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3077 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3078 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3079 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3080 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3081 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
3082 cvmx_warn("CVMX_GMXX_TXX_STAT8(%lu,%lu) is invalid on this chip\n", offset, block_id);
3084 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
3087 static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
3089 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3091 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3092 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3093 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3094 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3095 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3096 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3097 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
3098 cvmx_warn("CVMX_GMXX_TXX_STAT9(%lu,%lu) is invalid on this chip\n", offset, block_id);
3100 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
3103 static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
3105 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3107 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3108 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3109 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3110 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3111 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3112 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3113 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
3114 cvmx_warn("CVMX_GMXX_TXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
3116 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
3119 static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
3121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3123 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3124 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3125 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3126 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3127 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
3128 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
3129 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
3130 cvmx_warn("CVMX_GMXX_TXX_THRESH(%lu,%lu) is invalid on this chip\n", offset, block_id);
3132 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
3135 static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
3137 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3139 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3140 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3141 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3142 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3143 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3144 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3145 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3146 cvmx_warn("CVMX_GMXX_TX_BP(%lu) is invalid on this chip\n", block_id);
3148 return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id&1)*0x8000000ull;
3151 static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long block_id)
3153 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3155 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 1)) && ((block_id == 0)))) ||
3156 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 1)) && ((block_id == 0))))))
3157 cvmx_warn("CVMX_GMXX_TX_CLK_MSKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
3159 return CVMX_ADD_IO_SEG(0x0001180008000780ull) + ((offset&1) + (block_id&0)*0x0ull)*8;
3162 static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
3164 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3166 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3167 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3168 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3169 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3170 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3171 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3172 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3173 cvmx_warn("CVMX_GMXX_TX_COL_ATTEMPT(%lu) is invalid on this chip\n", block_id);
3175 return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id&1)*0x8000000ull;
3178 static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
3180 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3182 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3183 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3184 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3185 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3186 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3187 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3188 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3189 cvmx_warn("CVMX_GMXX_TX_CORRUPT(%lu) is invalid on this chip\n", block_id);
3191 return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id&1)*0x8000000ull;
3194 static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
3196 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3198 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3199 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3200 cvmx_warn("CVMX_GMXX_TX_HG2_REG1(%lu) is invalid on this chip\n", block_id);
3202 return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id&1)*0x8000000ull;
3205 static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
3207 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3209 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3210 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3211 cvmx_warn("CVMX_GMXX_TX_HG2_REG2(%lu) is invalid on this chip\n", block_id);
3213 return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id&1)*0x8000000ull;
3216 static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
3218 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3220 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3221 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3222 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3223 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3224 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3225 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3226 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3227 cvmx_warn("CVMX_GMXX_TX_IFG(%lu) is invalid on this chip\n", block_id);
3229 return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id&1)*0x8000000ull;
3232 static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
3234 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3236 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3237 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3238 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3239 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3241 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3242 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3243 cvmx_warn("CVMX_GMXX_TX_INT_EN(%lu) is invalid on this chip\n", block_id);
3245 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id&1)*0x8000000ull;
3248 static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
3250 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3252 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3253 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3254 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3255 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3256 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3257 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3258 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3259 cvmx_warn("CVMX_GMXX_TX_INT_REG(%lu) is invalid on this chip\n", block_id);
3261 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id&1)*0x8000000ull;
3264 static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
3266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3268 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3269 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3270 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3271 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3272 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3273 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3274 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3275 cvmx_warn("CVMX_GMXX_TX_JAM(%lu) is invalid on this chip\n", block_id);
3277 return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id&1)*0x8000000ull;
3280 static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
3282 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3284 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3285 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3287 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3288 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3289 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3290 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3291 cvmx_warn("CVMX_GMXX_TX_LFSR(%lu) is invalid on this chip\n", block_id);
3293 return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id&1)*0x8000000ull;
3296 static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
3298 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3300 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3301 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3302 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3303 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3304 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3305 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3306 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3307 cvmx_warn("CVMX_GMXX_TX_OVR_BP(%lu) is invalid on this chip\n", block_id);
3309 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id&1)*0x8000000ull;
3312 static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
3314 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3316 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3317 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3318 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3319 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3320 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3321 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3322 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3323 cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_DMAC(%lu) is invalid on this chip\n", block_id);
3325 return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id&1)*0x8000000ull;
3328 static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
3330 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3332 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3333 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3334 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3335 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3336 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3337 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3338 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3339 cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_TYPE(%lu) is invalid on this chip\n", block_id);
3341 return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id&1)*0x8000000ull;
3344 static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
3346 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3348 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3349 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
3350 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
3351 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3352 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
3353 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
3354 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3355 cvmx_warn("CVMX_GMXX_TX_PRTS(%lu) is invalid on this chip\n", block_id);
3357 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id&1)*0x8000000ull;
3360 static inline uint64_t CVMX_GMXX_TX_SPI_CTL(unsigned long block_id)
3362 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3364 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3365 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
3366 cvmx_warn("CVMX_GMXX_TX_SPI_CTL(%lu) is invalid on this chip\n", block_id);
3368 return CVMX_ADD_IO_SEG(0x00011800080004C0ull) + (block_id&1)*0x8000000ull;
3371 static inline uint64_t CVMX_GMXX_TX_SPI_DRAIN(unsigned long block_id)
3373 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3375 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3376 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
3377 cvmx_warn("CVMX_GMXX_TX_SPI_DRAIN(%lu) is invalid on this chip\n", block_id);
3379 return CVMX_ADD_IO_SEG(0x00011800080004E0ull) + (block_id&1)*0x8000000ull;
3382 static inline uint64_t CVMX_GMXX_TX_SPI_MAX(unsigned long block_id)
3384 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3386 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3387 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
3388 cvmx_warn("CVMX_GMXX_TX_SPI_MAX(%lu) is invalid on this chip\n", block_id);
3390 return CVMX_ADD_IO_SEG(0x00011800080004B0ull) + (block_id&1)*0x8000000ull;
3393 static inline uint64_t CVMX_GMXX_TX_SPI_ROUNDX(unsigned long offset, unsigned long block_id)
3395 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3397 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
3398 cvmx_warn("CVMX_GMXX_TX_SPI_ROUNDX(%lu,%lu) is invalid on this chip\n", offset, block_id);
3400 return CVMX_ADD_IO_SEG(0x0001180008000680ull) + ((offset&31) + (block_id&1)*0x1000000ull)*8;
3403 static inline uint64_t CVMX_GMXX_TX_SPI_THRESH(unsigned long block_id)
3405 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3407 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
3408 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
3409 cvmx_warn("CVMX_GMXX_TX_SPI_THRESH(%lu) is invalid on this chip\n", block_id);
3411 return CVMX_ADD_IO_SEG(0x00011800080004B8ull) + (block_id&1)*0x8000000ull;
3414 static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
3416 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3418 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3419 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3420 cvmx_warn("CVMX_GMXX_TX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
3422 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id&1)*0x8000000ull;
3425 static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
3427 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3429 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
3430 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
3431 cvmx_warn("CVMX_GMXX_XAUI_EXT_LOOPBACK(%lu) is invalid on this chip\n", block_id);
3433 return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id&1)*0x8000000ull;
3436 static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
3438 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3440 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
3441 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
3442 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
3443 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
3444 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
3445 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
3446 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
3447 cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
3449 return CVMX_ADD_IO_SEG(0x0001070000000800ull) + (offset&15)*8;
3452 #define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC()
3453 static inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void)
3455 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3456 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
3457 cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n");
3459 return CVMX_ADD_IO_SEG(0x00010700000008A8ull);
3462 static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
3464 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3466 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
3467 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
3468 cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
3470 return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + (offset&3)*8;
3473 #define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC()
3474 static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
3476 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3477 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
3478 cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n");
3480 return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
3483 #define CVMX_GPIO_INT_CLR CVMX_GPIO_INT_CLR_FUNC()
3484 static inline uint64_t CVMX_GPIO_INT_CLR_FUNC(void)
3486 return CVMX_ADD_IO_SEG(0x0001070000000898ull);
3489 #define CVMX_GPIO_RX_DAT CVMX_GPIO_RX_DAT_FUNC()
3490 static inline uint64_t CVMX_GPIO_RX_DAT_FUNC(void)
3492 return CVMX_ADD_IO_SEG(0x0001070000000880ull);
3495 #define CVMX_GPIO_TX_CLR CVMX_GPIO_TX_CLR_FUNC()
3496 static inline uint64_t CVMX_GPIO_TX_CLR_FUNC(void)
3498 return CVMX_ADD_IO_SEG(0x0001070000000890ull);
3501 #define CVMX_GPIO_TX_SET CVMX_GPIO_TX_SET_FUNC()
3502 static inline uint64_t CVMX_GPIO_TX_SET_FUNC(void)
3504 return CVMX_ADD_IO_SEG(0x0001070000000888ull);
3507 static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
3509 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3511 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
3512 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
3513 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23))))))
3514 cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
3516 return CVMX_ADD_IO_SEG(0x0001070000000900ull) + (offset&31)*8 - 8*16;
3519 #define CVMX_IOB_BIST_STATUS CVMX_IOB_BIST_STATUS_FUNC()
3520 static inline uint64_t CVMX_IOB_BIST_STATUS_FUNC(void)
3522 return CVMX_ADD_IO_SEG(0x00011800F00007F8ull);
3525 #define CVMX_IOB_CTL_STATUS CVMX_IOB_CTL_STATUS_FUNC()
3526 static inline uint64_t CVMX_IOB_CTL_STATUS_FUNC(void)
3528 return CVMX_ADD_IO_SEG(0x00011800F0000050ull);
3531 #define CVMX_IOB_DWB_PRI_CNT CVMX_IOB_DWB_PRI_CNT_FUNC()
3532 static inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void)
3534 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3535 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3536 cvmx_warn("CVMX_IOB_DWB_PRI_CNT not supported on this chip\n");
3538 return CVMX_ADD_IO_SEG(0x00011800F0000028ull);
3541 #define CVMX_IOB_FAU_TIMEOUT CVMX_IOB_FAU_TIMEOUT_FUNC()
3542 static inline uint64_t CVMX_IOB_FAU_TIMEOUT_FUNC(void)
3544 return CVMX_ADD_IO_SEG(0x00011800F0000000ull);
3547 #define CVMX_IOB_I2C_PRI_CNT CVMX_IOB_I2C_PRI_CNT_FUNC()
3548 static inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void)
3550 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3551 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3552 cvmx_warn("CVMX_IOB_I2C_PRI_CNT not supported on this chip\n");
3554 return CVMX_ADD_IO_SEG(0x00011800F0000010ull);
3557 #define CVMX_IOB_INB_CONTROL_MATCH CVMX_IOB_INB_CONTROL_MATCH_FUNC()
3558 static inline uint64_t CVMX_IOB_INB_CONTROL_MATCH_FUNC(void)
3560 return CVMX_ADD_IO_SEG(0x00011800F0000078ull);
3563 #define CVMX_IOB_INB_CONTROL_MATCH_ENB CVMX_IOB_INB_CONTROL_MATCH_ENB_FUNC()
3564 static inline uint64_t CVMX_IOB_INB_CONTROL_MATCH_ENB_FUNC(void)
3566 return CVMX_ADD_IO_SEG(0x00011800F0000088ull);
3569 #define CVMX_IOB_INB_DATA_MATCH CVMX_IOB_INB_DATA_MATCH_FUNC()
3570 static inline uint64_t CVMX_IOB_INB_DATA_MATCH_FUNC(void)
3572 return CVMX_ADD_IO_SEG(0x00011800F0000070ull);
3575 #define CVMX_IOB_INB_DATA_MATCH_ENB CVMX_IOB_INB_DATA_MATCH_ENB_FUNC()
3576 static inline uint64_t CVMX_IOB_INB_DATA_MATCH_ENB_FUNC(void)
3578 return CVMX_ADD_IO_SEG(0x00011800F0000080ull);
3581 #define CVMX_IOB_INT_ENB CVMX_IOB_INT_ENB_FUNC()
3582 static inline uint64_t CVMX_IOB_INT_ENB_FUNC(void)
3584 return CVMX_ADD_IO_SEG(0x00011800F0000060ull);
3587 #define CVMX_IOB_INT_SUM CVMX_IOB_INT_SUM_FUNC()
3588 static inline uint64_t CVMX_IOB_INT_SUM_FUNC(void)
3590 return CVMX_ADD_IO_SEG(0x00011800F0000058ull);
3593 #define CVMX_IOB_N2C_L2C_PRI_CNT CVMX_IOB_N2C_L2C_PRI_CNT_FUNC()
3594 static inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)
3596 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3597 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3598 cvmx_warn("CVMX_IOB_N2C_L2C_PRI_CNT not supported on this chip\n");
3600 return CVMX_ADD_IO_SEG(0x00011800F0000020ull);
3603 #define CVMX_IOB_N2C_RSP_PRI_CNT CVMX_IOB_N2C_RSP_PRI_CNT_FUNC()
3604 static inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)
3606 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3607 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3608 cvmx_warn("CVMX_IOB_N2C_RSP_PRI_CNT not supported on this chip\n");
3610 return CVMX_ADD_IO_SEG(0x00011800F0000008ull);
3613 #define CVMX_IOB_OUTB_COM_PRI_CNT CVMX_IOB_OUTB_COM_PRI_CNT_FUNC()
3614 static inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)
3616 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3617 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3618 cvmx_warn("CVMX_IOB_OUTB_COM_PRI_CNT not supported on this chip\n");
3620 return CVMX_ADD_IO_SEG(0x00011800F0000040ull);
3623 #define CVMX_IOB_OUTB_CONTROL_MATCH CVMX_IOB_OUTB_CONTROL_MATCH_FUNC()
3624 static inline uint64_t CVMX_IOB_OUTB_CONTROL_MATCH_FUNC(void)
3626 return CVMX_ADD_IO_SEG(0x00011800F0000098ull);
3629 #define CVMX_IOB_OUTB_CONTROL_MATCH_ENB CVMX_IOB_OUTB_CONTROL_MATCH_ENB_FUNC()
3630 static inline uint64_t CVMX_IOB_OUTB_CONTROL_MATCH_ENB_FUNC(void)
3632 return CVMX_ADD_IO_SEG(0x00011800F00000A8ull);
3635 #define CVMX_IOB_OUTB_DATA_MATCH CVMX_IOB_OUTB_DATA_MATCH_FUNC()
3636 static inline uint64_t CVMX_IOB_OUTB_DATA_MATCH_FUNC(void)
3638 return CVMX_ADD_IO_SEG(0x00011800F0000090ull);
3641 #define CVMX_IOB_OUTB_DATA_MATCH_ENB CVMX_IOB_OUTB_DATA_MATCH_ENB_FUNC()
3642 static inline uint64_t CVMX_IOB_OUTB_DATA_MATCH_ENB_FUNC(void)
3644 return CVMX_ADD_IO_SEG(0x00011800F00000A0ull);
3647 #define CVMX_IOB_OUTB_FPA_PRI_CNT CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC()
3648 static inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)
3650 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3651 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3652 cvmx_warn("CVMX_IOB_OUTB_FPA_PRI_CNT not supported on this chip\n");
3654 return CVMX_ADD_IO_SEG(0x00011800F0000048ull);
3657 #define CVMX_IOB_OUTB_REQ_PRI_CNT CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC()
3658 static inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)
3660 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3661 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3662 cvmx_warn("CVMX_IOB_OUTB_REQ_PRI_CNT not supported on this chip\n");
3664 return CVMX_ADD_IO_SEG(0x00011800F0000038ull);
3667 #define CVMX_IOB_P2C_REQ_PRI_CNT CVMX_IOB_P2C_REQ_PRI_CNT_FUNC()
3668 static inline uint64_t CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)
3670 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3671 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3672 cvmx_warn("CVMX_IOB_P2C_REQ_PRI_CNT not supported on this chip\n");
3674 return CVMX_ADD_IO_SEG(0x00011800F0000018ull);
3677 #define CVMX_IOB_PKT_ERR CVMX_IOB_PKT_ERR_FUNC()
3678 static inline uint64_t CVMX_IOB_PKT_ERR_FUNC(void)
3680 return CVMX_ADD_IO_SEG(0x00011800F0000068ull);
3683 #define CVMX_IOB_TO_CMB_CREDITS CVMX_IOB_TO_CMB_CREDITS_FUNC()
3684 static inline uint64_t CVMX_IOB_TO_CMB_CREDITS_FUNC(void)
3686 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3687 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
3688 cvmx_warn("CVMX_IOB_TO_CMB_CREDITS not supported on this chip\n");
3690 return CVMX_ADD_IO_SEG(0x00011800F00000B0ull);
3693 #define CVMX_IPD_1ST_MBUFF_SKIP CVMX_IPD_1ST_MBUFF_SKIP_FUNC()
3694 static inline uint64_t CVMX_IPD_1ST_MBUFF_SKIP_FUNC(void)
3696 return CVMX_ADD_IO_SEG(0x00014F0000000000ull);
3699 #define CVMX_IPD_1st_NEXT_PTR_BACK CVMX_IPD_1st_NEXT_PTR_BACK_FUNC()
3700 static inline uint64_t CVMX_IPD_1st_NEXT_PTR_BACK_FUNC(void)
3702 return CVMX_ADD_IO_SEG(0x00014F0000000150ull);
3705 #define CVMX_IPD_2nd_NEXT_PTR_BACK CVMX_IPD_2nd_NEXT_PTR_BACK_FUNC()
3706 static inline uint64_t CVMX_IPD_2nd_NEXT_PTR_BACK_FUNC(void)
3708 return CVMX_ADD_IO_SEG(0x00014F0000000158ull);
3711 #define CVMX_IPD_BIST_STATUS CVMX_IPD_BIST_STATUS_FUNC()
3712 static inline uint64_t CVMX_IPD_BIST_STATUS_FUNC(void)
3714 return CVMX_ADD_IO_SEG(0x00014F00000007F8ull);
3717 #define CVMX_IPD_BP_PRT_RED_END CVMX_IPD_BP_PRT_RED_END_FUNC()
3718 static inline uint64_t CVMX_IPD_BP_PRT_RED_END_FUNC(void)
3720 return CVMX_ADD_IO_SEG(0x00014F0000000328ull);
3723 #define CVMX_IPD_CLK_COUNT CVMX_IPD_CLK_COUNT_FUNC()
3724 static inline uint64_t CVMX_IPD_CLK_COUNT_FUNC(void)
3726 return CVMX_ADD_IO_SEG(0x00014F0000000338ull);
3729 #define CVMX_IPD_CTL_STATUS CVMX_IPD_CTL_STATUS_FUNC()
3730 static inline uint64_t CVMX_IPD_CTL_STATUS_FUNC(void)
3732 return CVMX_ADD_IO_SEG(0x00014F0000000018ull);
3735 #define CVMX_IPD_INT_ENB CVMX_IPD_INT_ENB_FUNC()
3736 static inline uint64_t CVMX_IPD_INT_ENB_FUNC(void)
3738 return CVMX_ADD_IO_SEG(0x00014F0000000160ull);
3741 #define CVMX_IPD_INT_SUM CVMX_IPD_INT_SUM_FUNC()
3742 static inline uint64_t CVMX_IPD_INT_SUM_FUNC(void)
3744 return CVMX_ADD_IO_SEG(0x00014F0000000168ull);
3747 #define CVMX_IPD_NOT_1ST_MBUFF_SKIP CVMX_IPD_NOT_1ST_MBUFF_SKIP_FUNC()
3748 static inline uint64_t CVMX_IPD_NOT_1ST_MBUFF_SKIP_FUNC(void)
3750 return CVMX_ADD_IO_SEG(0x00014F0000000008ull);
3753 #define CVMX_IPD_PACKET_MBUFF_SIZE CVMX_IPD_PACKET_MBUFF_SIZE_FUNC()
3754 static inline uint64_t CVMX_IPD_PACKET_MBUFF_SIZE_FUNC(void)
3756 return CVMX_ADD_IO_SEG(0x00014F0000000010ull);
3759 #define CVMX_IPD_PKT_PTR_VALID CVMX_IPD_PKT_PTR_VALID_FUNC()
3760 static inline uint64_t CVMX_IPD_PKT_PTR_VALID_FUNC(void)
3762 return CVMX_ADD_IO_SEG(0x00014F0000000358ull);
3765 static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset)
3767 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3769 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
3770 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
3771 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
3772 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
3773 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
3774 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
3775 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
3776 cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n", offset);
3778 return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + (offset&63)*8;
3781 static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset)
3783 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3785 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
3786 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39))))))
3787 cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n", offset);
3789 return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + (offset&63)*8 - 8*36;
3792 static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset)
3794 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3796 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
3797 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39))))))
3798 cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n", offset);
3800 return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + (offset&63)*8 - 8*36;
3803 static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset)
3805 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3807 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
3808 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
3809 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
3810 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
3811 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
3812 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
3813 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
3814 cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n", offset);
3816 return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + (offset&63)*8;
3819 static inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset)
3821 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3823 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
3824 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4)))))
3825 cvmx_warn("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n", offset);
3827 return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + (offset&7)*8;
3830 static inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset)
3832 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3834 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
3835 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4)))))
3836 cvmx_warn("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n", offset);
3838 return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + (offset&7)*8;
3841 static inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset)
3843 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3845 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 319)))) ||
3846 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 319))))))
3847 cvmx_warn("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n", offset);
3849 return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + (offset&511)*8;
3852 #define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC()
3853 static inline uint64_t CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC(void)
3855 return CVMX_ADD_IO_SEG(0x00014F0000000348ull);
3858 #define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC()
3859 static inline uint64_t CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC(void)
3861 return CVMX_ADD_IO_SEG(0x00014F0000000350ull);
3864 #define CVMX_IPD_PTR_COUNT CVMX_IPD_PTR_COUNT_FUNC()
3865 static inline uint64_t CVMX_IPD_PTR_COUNT_FUNC(void)
3867 return CVMX_ADD_IO_SEG(0x00014F0000000320ull);
3870 #define CVMX_IPD_PWP_PTR_FIFO_CTL CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC()
3871 static inline uint64_t CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC(void)
3873 return CVMX_ADD_IO_SEG(0x00014F0000000340ull);
3876 #define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
3877 #define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
3878 #define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
3879 #define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
3880 #define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
3881 #define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
3882 #define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
3883 #define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
3884 static inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset)
3886 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3888 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
3889 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
3890 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
3891 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
3892 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
3893 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
3894 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
3895 cvmx_warn("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n", offset);
3897 return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + (offset&7)*8;
3900 #define CVMX_IPD_QUE0_FREE_PAGE_CNT CVMX_IPD_QUE0_FREE_PAGE_CNT_FUNC()
3901 static inline uint64_t CVMX_IPD_QUE0_FREE_PAGE_CNT_FUNC(void)
3903 return CVMX_ADD_IO_SEG(0x00014F0000000330ull);
3906 #define CVMX_IPD_RED_PORT_ENABLE CVMX_IPD_RED_PORT_ENABLE_FUNC()
3907 static inline uint64_t CVMX_IPD_RED_PORT_ENABLE_FUNC(void)
3909 return CVMX_ADD_IO_SEG(0x00014F00000002D8ull);
3912 #define CVMX_IPD_RED_PORT_ENABLE2 CVMX_IPD_RED_PORT_ENABLE2_FUNC()
3913 static inline uint64_t CVMX_IPD_RED_PORT_ENABLE2_FUNC(void)
3915 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3916 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
3917 cvmx_warn("CVMX_IPD_RED_PORT_ENABLE2 not supported on this chip\n");
3919 return CVMX_ADD_IO_SEG(0x00014F00000003A8ull);
3922 #define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
3923 #define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
3924 #define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
3925 #define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
3926 #define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
3927 #define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
3928 #define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
3929 #define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
3930 static inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset)
3932 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3934 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
3935 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
3936 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
3937 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
3938 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
3939 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
3940 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
3941 cvmx_warn("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n", offset);
3943 return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + (offset&7)*8;
3946 #define CVMX_IPD_SUB_PORT_BP_PAGE_CNT CVMX_IPD_SUB_PORT_BP_PAGE_CNT_FUNC()
3947 static inline uint64_t CVMX_IPD_SUB_PORT_BP_PAGE_CNT_FUNC(void)
3949 return CVMX_ADD_IO_SEG(0x00014F0000000148ull);
3952 #define CVMX_IPD_SUB_PORT_FCS CVMX_IPD_SUB_PORT_FCS_FUNC()
3953 static inline uint64_t CVMX_IPD_SUB_PORT_FCS_FUNC(void)
3955 return CVMX_ADD_IO_SEG(0x00014F0000000170ull);
3958 #define CVMX_IPD_SUB_PORT_QOS_CNT CVMX_IPD_SUB_PORT_QOS_CNT_FUNC()
3959 static inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void)
3961 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3962 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
3963 cvmx_warn("CVMX_IPD_SUB_PORT_QOS_CNT not supported on this chip\n");
3965 return CVMX_ADD_IO_SEG(0x00014F0000000800ull);
3968 #define CVMX_IPD_WQE_FPA_QUEUE CVMX_IPD_WQE_FPA_QUEUE_FUNC()
3969 static inline uint64_t CVMX_IPD_WQE_FPA_QUEUE_FUNC(void)
3971 return CVMX_ADD_IO_SEG(0x00014F0000000020ull);
3974 #define CVMX_IPD_WQE_PTR_VALID CVMX_IPD_WQE_PTR_VALID_FUNC()
3975 static inline uint64_t CVMX_IPD_WQE_PTR_VALID_FUNC(void)
3977 return CVMX_ADD_IO_SEG(0x00014F0000000360ull);
3980 #define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC()
3981 static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
3983 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3984 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3985 cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n");
3987 return CVMX_ADD_IO_SEG(0x0001180020000018ull);
3990 #define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC()
3991 static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
3993 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
3994 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
3995 cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n");
3997 return CVMX_ADD_IO_SEG(0x0001180020000010ull);
4000 #define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC()
4001 static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
4003 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4004 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4005 cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n");
4007 return CVMX_ADD_IO_SEG(0x0001180020000008ull);
4010 #define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC()
4011 static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
4013 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4014 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4015 cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n");
4017 return CVMX_ADD_IO_SEG(0x0001180020000000ull);
4020 #define CVMX_L2C_BST0 CVMX_L2C_BST0_FUNC()
4021 static inline uint64_t CVMX_L2C_BST0_FUNC(void)
4023 return CVMX_ADD_IO_SEG(0x00011800800007F8ull);
4026 #define CVMX_L2C_BST1 CVMX_L2C_BST1_FUNC()
4027 static inline uint64_t CVMX_L2C_BST1_FUNC(void)
4029 return CVMX_ADD_IO_SEG(0x00011800800007F0ull);
4032 #define CVMX_L2C_BST2 CVMX_L2C_BST2_FUNC()
4033 static inline uint64_t CVMX_L2C_BST2_FUNC(void)
4035 return CVMX_ADD_IO_SEG(0x00011800800007E8ull);
4038 #define CVMX_L2C_CFG CVMX_L2C_CFG_FUNC()
4039 static inline uint64_t CVMX_L2C_CFG_FUNC(void)
4041 return CVMX_ADD_IO_SEG(0x0001180080000000ull);
4044 #define CVMX_L2C_DBG CVMX_L2C_DBG_FUNC()
4045 static inline uint64_t CVMX_L2C_DBG_FUNC(void)
4047 return CVMX_ADD_IO_SEG(0x0001180080000030ull);
4050 #define CVMX_L2C_DUT CVMX_L2C_DUT_FUNC()
4051 static inline uint64_t CVMX_L2C_DUT_FUNC(void)
4053 return CVMX_ADD_IO_SEG(0x0001180080000050ull);
4056 #define CVMX_L2C_GRPWRR0 CVMX_L2C_GRPWRR0_FUNC()
4057 static inline uint64_t CVMX_L2C_GRPWRR0_FUNC(void)
4059 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4060 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4061 cvmx_warn("CVMX_L2C_GRPWRR0 not supported on this chip\n");
4063 return CVMX_ADD_IO_SEG(0x00011800800000C8ull);
4066 #define CVMX_L2C_GRPWRR1 CVMX_L2C_GRPWRR1_FUNC()
4067 static inline uint64_t CVMX_L2C_GRPWRR1_FUNC(void)
4069 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4070 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4071 cvmx_warn("CVMX_L2C_GRPWRR1 not supported on this chip\n");
4073 return CVMX_ADD_IO_SEG(0x00011800800000D0ull);
4076 #define CVMX_L2C_INT_EN CVMX_L2C_INT_EN_FUNC()
4077 static inline uint64_t CVMX_L2C_INT_EN_FUNC(void)
4079 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4080 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4081 cvmx_warn("CVMX_L2C_INT_EN not supported on this chip\n");
4083 return CVMX_ADD_IO_SEG(0x0001180080000100ull);
4086 #define CVMX_L2C_INT_STAT CVMX_L2C_INT_STAT_FUNC()
4087 static inline uint64_t CVMX_L2C_INT_STAT_FUNC(void)
4089 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4090 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4091 cvmx_warn("CVMX_L2C_INT_STAT not supported on this chip\n");
4093 return CVMX_ADD_IO_SEG(0x00011800800000F8ull);
4096 #define CVMX_L2C_LCKBASE CVMX_L2C_LCKBASE_FUNC()
4097 static inline uint64_t CVMX_L2C_LCKBASE_FUNC(void)
4099 return CVMX_ADD_IO_SEG(0x0001180080000058ull);
4102 #define CVMX_L2C_LCKOFF CVMX_L2C_LCKOFF_FUNC()
4103 static inline uint64_t CVMX_L2C_LCKOFF_FUNC(void)
4105 return CVMX_ADD_IO_SEG(0x0001180080000060ull);
4108 #define CVMX_L2C_LFB0 CVMX_L2C_LFB0_FUNC()
4109 static inline uint64_t CVMX_L2C_LFB0_FUNC(void)
4111 return CVMX_ADD_IO_SEG(0x0001180080000038ull);
4114 #define CVMX_L2C_LFB1 CVMX_L2C_LFB1_FUNC()
4115 static inline uint64_t CVMX_L2C_LFB1_FUNC(void)
4117 return CVMX_ADD_IO_SEG(0x0001180080000040ull);
4120 #define CVMX_L2C_LFB2 CVMX_L2C_LFB2_FUNC()
4121 static inline uint64_t CVMX_L2C_LFB2_FUNC(void)
4123 return CVMX_ADD_IO_SEG(0x0001180080000048ull);
4126 #define CVMX_L2C_LFB3 CVMX_L2C_LFB3_FUNC()
4127 static inline uint64_t CVMX_L2C_LFB3_FUNC(void)
4129 return CVMX_ADD_IO_SEG(0x00011800800000B8ull);
4132 #define CVMX_L2C_OOB CVMX_L2C_OOB_FUNC()
4133 static inline uint64_t CVMX_L2C_OOB_FUNC(void)
4135 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4136 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4137 cvmx_warn("CVMX_L2C_OOB not supported on this chip\n");
4139 return CVMX_ADD_IO_SEG(0x00011800800000D8ull);
4142 #define CVMX_L2C_OOB1 CVMX_L2C_OOB1_FUNC()
4143 static inline uint64_t CVMX_L2C_OOB1_FUNC(void)
4145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4146 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4147 cvmx_warn("CVMX_L2C_OOB1 not supported on this chip\n");
4149 return CVMX_ADD_IO_SEG(0x00011800800000E0ull);
4152 #define CVMX_L2C_OOB2 CVMX_L2C_OOB2_FUNC()
4153 static inline uint64_t CVMX_L2C_OOB2_FUNC(void)
4155 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4156 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4157 cvmx_warn("CVMX_L2C_OOB2 not supported on this chip\n");
4159 return CVMX_ADD_IO_SEG(0x00011800800000E8ull);
4162 #define CVMX_L2C_OOB3 CVMX_L2C_OOB3_FUNC()
4163 static inline uint64_t CVMX_L2C_OOB3_FUNC(void)
4165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4166 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4167 cvmx_warn("CVMX_L2C_OOB3 not supported on this chip\n");
4169 return CVMX_ADD_IO_SEG(0x00011800800000F0ull);
4172 #define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
4173 #define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
4174 #define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
4175 #define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
4176 #define CVMX_L2C_PFCTL CVMX_L2C_PFCTL_FUNC()
4177 static inline uint64_t CVMX_L2C_PFCTL_FUNC(void)
4179 return CVMX_ADD_IO_SEG(0x0001180080000090ull);
4182 static inline uint64_t CVMX_L2C_PFCX(unsigned long offset)
4184 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4186 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
4187 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
4188 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
4189 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
4190 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
4191 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
4192 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
4193 cvmx_warn("CVMX_L2C_PFCX(%lu) is invalid on this chip\n", offset);
4195 return CVMX_ADD_IO_SEG(0x0001180080000098ull) + (offset&3)*8;
4198 #define CVMX_L2C_PPGRP CVMX_L2C_PPGRP_FUNC()
4199 static inline uint64_t CVMX_L2C_PPGRP_FUNC(void)
4201 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4202 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4203 cvmx_warn("CVMX_L2C_PPGRP not supported on this chip\n");
4205 return CVMX_ADD_IO_SEG(0x00011800800000C0ull);
4208 #define CVMX_L2C_SPAR0 CVMX_L2C_SPAR0_FUNC()
4209 static inline uint64_t CVMX_L2C_SPAR0_FUNC(void)
4211 return CVMX_ADD_IO_SEG(0x0001180080000068ull);
4214 #define CVMX_L2C_SPAR1 CVMX_L2C_SPAR1_FUNC()
4215 static inline uint64_t CVMX_L2C_SPAR1_FUNC(void)
4217 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4218 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4219 cvmx_warn("CVMX_L2C_SPAR1 not supported on this chip\n");
4221 return CVMX_ADD_IO_SEG(0x0001180080000070ull);
4224 #define CVMX_L2C_SPAR2 CVMX_L2C_SPAR2_FUNC()
4225 static inline uint64_t CVMX_L2C_SPAR2_FUNC(void)
4227 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4228 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4229 cvmx_warn("CVMX_L2C_SPAR2 not supported on this chip\n");
4231 return CVMX_ADD_IO_SEG(0x0001180080000078ull);
4234 #define CVMX_L2C_SPAR3 CVMX_L2C_SPAR3_FUNC()
4235 static inline uint64_t CVMX_L2C_SPAR3_FUNC(void)
4237 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4238 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4239 cvmx_warn("CVMX_L2C_SPAR3 not supported on this chip\n");
4241 return CVMX_ADD_IO_SEG(0x0001180080000080ull);
4244 #define CVMX_L2C_SPAR4 CVMX_L2C_SPAR4_FUNC()
4245 static inline uint64_t CVMX_L2C_SPAR4_FUNC(void)
4247 return CVMX_ADD_IO_SEG(0x0001180080000088ull);
4250 #define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
4251 static inline uint64_t CVMX_L2D_BST0_FUNC(void)
4253 return CVMX_ADD_IO_SEG(0x0001180080000780ull);
4256 #define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC()
4257 static inline uint64_t CVMX_L2D_BST1_FUNC(void)
4259 return CVMX_ADD_IO_SEG(0x0001180080000788ull);
4262 #define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC()
4263 static inline uint64_t CVMX_L2D_BST2_FUNC(void)
4265 return CVMX_ADD_IO_SEG(0x0001180080000790ull);
4268 #define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC()
4269 static inline uint64_t CVMX_L2D_BST3_FUNC(void)
4271 return CVMX_ADD_IO_SEG(0x0001180080000798ull);
4274 #define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC()
4275 static inline uint64_t CVMX_L2D_ERR_FUNC(void)
4277 return CVMX_ADD_IO_SEG(0x0001180080000010ull);
4280 #define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC()
4281 static inline uint64_t CVMX_L2D_FADR_FUNC(void)
4283 return CVMX_ADD_IO_SEG(0x0001180080000018ull);
4286 #define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC()
4287 static inline uint64_t CVMX_L2D_FSYN0_FUNC(void)
4289 return CVMX_ADD_IO_SEG(0x0001180080000020ull);
4292 #define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC()
4293 static inline uint64_t CVMX_L2D_FSYN1_FUNC(void)
4295 return CVMX_ADD_IO_SEG(0x0001180080000028ull);
4298 #define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC()
4299 static inline uint64_t CVMX_L2D_FUS0_FUNC(void)
4301 return CVMX_ADD_IO_SEG(0x00011800800007A0ull);
4304 #define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC()
4305 static inline uint64_t CVMX_L2D_FUS1_FUNC(void)
4307 return CVMX_ADD_IO_SEG(0x00011800800007A8ull);
4310 #define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC()
4311 static inline uint64_t CVMX_L2D_FUS2_FUNC(void)
4313 return CVMX_ADD_IO_SEG(0x00011800800007B0ull);
4316 #define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC()
4317 static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
4319 return CVMX_ADD_IO_SEG(0x00011800800007B8ull);
4322 #define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC()
4323 static inline uint64_t CVMX_L2T_ERR_FUNC(void)
4325 return CVMX_ADD_IO_SEG(0x0001180080000008ull);
4328 #define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC()
4329 static inline uint64_t CVMX_LED_BLINK_FUNC(void)
4331 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4332 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4333 cvmx_warn("CVMX_LED_BLINK not supported on this chip\n");
4335 return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
4338 #define CVMX_LED_CLK_PHASE CVMX_LED_CLK_PHASE_FUNC()
4339 static inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void)
4341 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4342 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4343 cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n");
4345 return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
4348 #define CVMX_LED_CYLON CVMX_LED_CYLON_FUNC()
4349 static inline uint64_t CVMX_LED_CYLON_FUNC(void)
4351 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4352 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4353 cvmx_warn("CVMX_LED_CYLON not supported on this chip\n");
4355 return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
4358 #define CVMX_LED_DBG CVMX_LED_DBG_FUNC()
4359 static inline uint64_t CVMX_LED_DBG_FUNC(void)
4361 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4362 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4363 cvmx_warn("CVMX_LED_DBG not supported on this chip\n");
4365 return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
4368 #define CVMX_LED_EN CVMX_LED_EN_FUNC()
4369 static inline uint64_t CVMX_LED_EN_FUNC(void)
4371 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4372 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4373 cvmx_warn("CVMX_LED_EN not supported on this chip\n");
4375 return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
4378 #define CVMX_LED_POLARITY CVMX_LED_POLARITY_FUNC()
4379 static inline uint64_t CVMX_LED_POLARITY_FUNC(void)
4381 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4382 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4383 cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n");
4385 return CVMX_ADD_IO_SEG(0x0001180000001A50ull);
4388 #define CVMX_LED_PRT CVMX_LED_PRT_FUNC()
4389 static inline uint64_t CVMX_LED_PRT_FUNC(void)
4391 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4392 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4393 cvmx_warn("CVMX_LED_PRT not supported on this chip\n");
4395 return CVMX_ADD_IO_SEG(0x0001180000001A10ull);
4398 #define CVMX_LED_PRT_FMT CVMX_LED_PRT_FMT_FUNC()
4399 static inline uint64_t CVMX_LED_PRT_FMT_FUNC(void)
4401 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4402 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
4403 cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n");
4405 return CVMX_ADD_IO_SEG(0x0001180000001A30ull);
4408 static inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset)
4410 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4412 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
4413 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
4414 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7)))))
4415 cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n", offset);
4417 return CVMX_ADD_IO_SEG(0x0001180000001A80ull) + (offset&7)*8;
4420 static inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset)
4422 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4424 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
4425 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
4426 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
4427 cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n", offset);
4429 return CVMX_ADD_IO_SEG(0x0001180000001A20ull) + (offset&1)*8;
4432 static inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset)
4434 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4436 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
4437 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
4438 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
4439 cvmx_warn("CVMX_LED_UDD_DATX(%lu) is invalid on this chip\n", offset);
4441 return CVMX_ADD_IO_SEG(0x0001180000001A38ull) + (offset&1)*8;
4444 static inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset)
4446 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4448 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
4449 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
4450 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
4451 cvmx_warn("CVMX_LED_UDD_DAT_CLRX(%lu) is invalid on this chip\n", offset);
4453 return CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + (offset&1)*16;
4456 static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
4458 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4460 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
4461 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
4462 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
4463 cvmx_warn("CVMX_LED_UDD_DAT_SETX(%lu) is invalid on this chip\n", offset);
4465 return CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + (offset&1)*16;
4468 static inline uint64_t CVMX_LMCX_BIST_CTL(unsigned long block_id)
4470 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4472 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4473 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4474 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4475 cvmx_warn("CVMX_LMCX_BIST_CTL(%lu) is invalid on this chip\n", block_id);
4477 return CVMX_ADD_IO_SEG(0x00011800880000F0ull) + (block_id&1)*0x60000000ull;
4480 static inline uint64_t CVMX_LMCX_BIST_RESULT(unsigned long block_id)
4482 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4484 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4485 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4486 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4487 cvmx_warn("CVMX_LMCX_BIST_RESULT(%lu) is invalid on this chip\n", block_id);
4489 return CVMX_ADD_IO_SEG(0x00011800880000F8ull) + (block_id&1)*0x60000000ull;
4492 static inline uint64_t CVMX_LMCX_COMP_CTL(unsigned long block_id)
4494 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4496 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4497 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4498 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4499 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4500 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4501 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4502 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4503 cvmx_warn("CVMX_LMCX_COMP_CTL(%lu) is invalid on this chip\n", block_id);
4505 return CVMX_ADD_IO_SEG(0x0001180088000028ull) + (block_id&1)*0x60000000ull;
4508 static inline uint64_t CVMX_LMCX_CTL(unsigned long block_id)
4510 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4512 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4513 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4514 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4515 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4516 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4517 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4518 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4519 cvmx_warn("CVMX_LMCX_CTL(%lu) is invalid on this chip\n", block_id);
4521 return CVMX_ADD_IO_SEG(0x0001180088000010ull) + (block_id&1)*0x60000000ull;
4524 static inline uint64_t CVMX_LMCX_CTL1(unsigned long block_id)
4526 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4528 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4529 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4530 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4531 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4532 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4533 cvmx_warn("CVMX_LMCX_CTL1(%lu) is invalid on this chip\n", block_id);
4535 return CVMX_ADD_IO_SEG(0x0001180088000090ull) + (block_id&1)*0x60000000ull;
4538 static inline uint64_t CVMX_LMCX_DCLK_CNT_HI(unsigned long block_id)
4540 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4542 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4543 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4544 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4545 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4546 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4547 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4548 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4549 cvmx_warn("CVMX_LMCX_DCLK_CNT_HI(%lu) is invalid on this chip\n", block_id);
4551 return CVMX_ADD_IO_SEG(0x0001180088000070ull) + (block_id&1)*0x60000000ull;
4554 static inline uint64_t CVMX_LMCX_DCLK_CNT_LO(unsigned long block_id)
4556 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4558 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4559 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4560 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4561 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4562 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4563 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4564 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4565 cvmx_warn("CVMX_LMCX_DCLK_CNT_LO(%lu) is invalid on this chip\n", block_id);
4567 return CVMX_ADD_IO_SEG(0x0001180088000068ull) + (block_id&1)*0x60000000ull;
4570 static inline uint64_t CVMX_LMCX_DCLK_CTL(unsigned long block_id)
4572 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4574 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
4575 cvmx_warn("CVMX_LMCX_DCLK_CTL(%lu) is invalid on this chip\n", block_id);
4577 return CVMX_ADD_IO_SEG(0x00011800880000B8ull) + (block_id&1)*0x60000000ull;
4580 static inline uint64_t CVMX_LMCX_DDR2_CTL(unsigned long block_id)
4582 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4584 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4585 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4586 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4587 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4588 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4589 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4590 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4591 cvmx_warn("CVMX_LMCX_DDR2_CTL(%lu) is invalid on this chip\n", block_id);
4593 return CVMX_ADD_IO_SEG(0x0001180088000018ull) + (block_id&1)*0x60000000ull;
4596 static inline uint64_t CVMX_LMCX_DELAY_CFG(unsigned long block_id)
4598 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4600 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4601 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4602 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4603 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4604 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4605 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4606 cvmx_warn("CVMX_LMCX_DELAY_CFG(%lu) is invalid on this chip\n", block_id);
4608 return CVMX_ADD_IO_SEG(0x0001180088000088ull) + (block_id&1)*0x60000000ull;
4611 static inline uint64_t CVMX_LMCX_DLL_CTL(unsigned long block_id)
4613 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4615 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4616 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4617 cvmx_warn("CVMX_LMCX_DLL_CTL(%lu) is invalid on this chip\n", block_id);
4619 return CVMX_ADD_IO_SEG(0x00011800880000C0ull) + (block_id&1)*0x60000000ull;
4622 static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
4624 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4626 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4627 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4628 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4629 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4630 cvmx_warn("CVMX_LMCX_DUAL_MEMCFG(%lu) is invalid on this chip\n", block_id);
4632 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id&1)*0x60000000ull;
4635 static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
4637 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4639 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4640 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4641 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4642 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4643 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4644 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4645 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4646 cvmx_warn("CVMX_LMCX_ECC_SYND(%lu) is invalid on this chip\n", block_id);
4648 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id&1)*0x60000000ull;
4651 static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
4653 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4655 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4656 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4657 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4658 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4659 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4660 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4661 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4662 cvmx_warn("CVMX_LMCX_FADR(%lu) is invalid on this chip\n", block_id);
4664 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id&1)*0x60000000ull;
4667 static inline uint64_t CVMX_LMCX_IFB_CNT_HI(unsigned long block_id)
4669 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4671 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4672 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4673 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4674 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4675 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4676 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4677 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4678 cvmx_warn("CVMX_LMCX_IFB_CNT_HI(%lu) is invalid on this chip\n", block_id);
4680 return CVMX_ADD_IO_SEG(0x0001180088000050ull) + (block_id&1)*0x60000000ull;
4683 static inline uint64_t CVMX_LMCX_IFB_CNT_LO(unsigned long block_id)
4685 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4687 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4688 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4689 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4690 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4691 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4692 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4693 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4694 cvmx_warn("CVMX_LMCX_IFB_CNT_LO(%lu) is invalid on this chip\n", block_id);
4696 return CVMX_ADD_IO_SEG(0x0001180088000048ull) + (block_id&1)*0x60000000ull;
4699 static inline uint64_t CVMX_LMCX_MEM_CFG0(unsigned long block_id)
4701 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4703 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4704 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4705 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4706 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4707 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4708 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4709 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4710 cvmx_warn("CVMX_LMCX_MEM_CFG0(%lu) is invalid on this chip\n", block_id);
4712 return CVMX_ADD_IO_SEG(0x0001180088000000ull) + (block_id&1)*0x60000000ull;
4715 static inline uint64_t CVMX_LMCX_MEM_CFG1(unsigned long block_id)
4717 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4719 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4720 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4721 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4722 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4723 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4724 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4725 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4726 cvmx_warn("CVMX_LMCX_MEM_CFG1(%lu) is invalid on this chip\n", block_id);
4728 return CVMX_ADD_IO_SEG(0x0001180088000008ull) + (block_id&1)*0x60000000ull;
4731 static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
4733 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4735 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4736 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
4737 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
4738 cvmx_warn("CVMX_LMCX_NXM(%lu) is invalid on this chip\n", block_id);
4740 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id&1)*0x60000000ull;
4743 static inline uint64_t CVMX_LMCX_OPS_CNT_HI(unsigned long block_id)
4745 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4747 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4748 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4749 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4750 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4751 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4752 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4753 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4754 cvmx_warn("CVMX_LMCX_OPS_CNT_HI(%lu) is invalid on this chip\n", block_id);
4756 return CVMX_ADD_IO_SEG(0x0001180088000060ull) + (block_id&1)*0x60000000ull;
4759 static inline uint64_t CVMX_LMCX_OPS_CNT_LO(unsigned long block_id)
4761 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4763 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4764 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4765 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4766 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4767 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4768 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4769 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4770 cvmx_warn("CVMX_LMCX_OPS_CNT_LO(%lu) is invalid on this chip\n", block_id);
4772 return CVMX_ADD_IO_SEG(0x0001180088000058ull) + (block_id&1)*0x60000000ull;
4775 static inline uint64_t CVMX_LMCX_PLL_BWCTL(unsigned long block_id)
4777 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4779 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4780 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4781 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0)))))
4782 cvmx_warn("CVMX_LMCX_PLL_BWCTL(%lu) is invalid on this chip\n", block_id);
4784 return CVMX_ADD_IO_SEG(0x0001180088000040ull) + (block_id&0)*0x8000000ull;
4787 static inline uint64_t CVMX_LMCX_PLL_CTL(unsigned long block_id)
4789 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4791 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4792 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4793 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4794 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4795 cvmx_warn("CVMX_LMCX_PLL_CTL(%lu) is invalid on this chip\n", block_id);
4797 return CVMX_ADD_IO_SEG(0x00011800880000A8ull) + (block_id&1)*0x60000000ull;
4800 static inline uint64_t CVMX_LMCX_PLL_STATUS(unsigned long block_id)
4802 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4804 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4805 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4806 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4807 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4808 cvmx_warn("CVMX_LMCX_PLL_STATUS(%lu) is invalid on this chip\n", block_id);
4810 return CVMX_ADD_IO_SEG(0x00011800880000B0ull) + (block_id&1)*0x60000000ull;
4813 static inline uint64_t CVMX_LMCX_READ_LEVEL_CTL(unsigned long block_id)
4815 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4817 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4818 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4819 cvmx_warn("CVMX_LMCX_READ_LEVEL_CTL(%lu) is invalid on this chip\n", block_id);
4821 return CVMX_ADD_IO_SEG(0x0001180088000140ull) + (block_id&1)*0x60000000ull;
4824 static inline uint64_t CVMX_LMCX_READ_LEVEL_DBG(unsigned long block_id)
4826 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4828 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4829 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4830 cvmx_warn("CVMX_LMCX_READ_LEVEL_DBG(%lu) is invalid on this chip\n", block_id);
4832 return CVMX_ADD_IO_SEG(0x0001180088000148ull) + (block_id&1)*0x60000000ull;
4835 static inline uint64_t CVMX_LMCX_READ_LEVEL_RANKX(unsigned long offset, unsigned long block_id)
4837 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4839 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
4840 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
4841 cvmx_warn("CVMX_LMCX_READ_LEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
4843 return CVMX_ADD_IO_SEG(0x0001180088000100ull) + ((offset&3) + (block_id&1)*0xC000000ull)*8;
4846 static inline uint64_t CVMX_LMCX_RODT_COMP_CTL(unsigned long block_id)
4848 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4850 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4851 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4852 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4853 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4854 cvmx_warn("CVMX_LMCX_RODT_COMP_CTL(%lu) is invalid on this chip\n", block_id);
4856 return CVMX_ADD_IO_SEG(0x00011800880000A0ull) + (block_id&1)*0x60000000ull;
4859 static inline uint64_t CVMX_LMCX_RODT_CTL(unsigned long block_id)
4861 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4863 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4864 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4865 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4866 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4867 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4868 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4869 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4870 cvmx_warn("CVMX_LMCX_RODT_CTL(%lu) is invalid on this chip\n", block_id);
4872 return CVMX_ADD_IO_SEG(0x0001180088000078ull) + (block_id&1)*0x60000000ull;
4875 static inline uint64_t CVMX_LMCX_WODT_CTL0(unsigned long block_id)
4877 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4879 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4880 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4881 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
4882 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
4883 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4884 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
4885 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4886 cvmx_warn("CVMX_LMCX_WODT_CTL0(%lu) is invalid on this chip\n", block_id);
4888 return CVMX_ADD_IO_SEG(0x0001180088000030ull) + (block_id&1)*0x60000000ull;
4891 static inline uint64_t CVMX_LMCX_WODT_CTL1(unsigned long block_id)
4893 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4895 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
4896 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
4897 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
4898 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
4899 cvmx_warn("CVMX_LMCX_WODT_CTL1(%lu) is invalid on this chip\n", block_id);
4901 return CVMX_ADD_IO_SEG(0x0001180088000080ull) + (block_id&1)*0x60000000ull;
4904 #define CVMX_MIO_BOOT_BIST_STAT CVMX_MIO_BOOT_BIST_STAT_FUNC()
4905 static inline uint64_t CVMX_MIO_BOOT_BIST_STAT_FUNC(void)
4907 return CVMX_ADD_IO_SEG(0x00011800000000F8ull);
4910 #define CVMX_MIO_BOOT_COMP CVMX_MIO_BOOT_COMP_FUNC()
4911 static inline uint64_t CVMX_MIO_BOOT_COMP_FUNC(void)
4913 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4914 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
4915 cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n");
4917 return CVMX_ADD_IO_SEG(0x00011800000000B8ull);
4920 static inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset)
4922 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4924 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
4925 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
4926 cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset);
4928 return CVMX_ADD_IO_SEG(0x0001180000000100ull) + (offset&3)*8;
4931 static inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset)
4933 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4935 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
4936 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
4937 cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset);
4939 return CVMX_ADD_IO_SEG(0x0001180000000138ull) + (offset&3)*8;
4942 static inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset)
4944 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4946 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
4947 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
4948 cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset);
4950 return CVMX_ADD_IO_SEG(0x0001180000000150ull) + (offset&3)*8;
4953 static inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset)
4955 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4957 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
4958 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
4959 cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset);
4961 return CVMX_ADD_IO_SEG(0x0001180000000120ull) + (offset&3)*8;
4964 #define CVMX_MIO_BOOT_ERR CVMX_MIO_BOOT_ERR_FUNC()
4965 static inline uint64_t CVMX_MIO_BOOT_ERR_FUNC(void)
4967 return CVMX_ADD_IO_SEG(0x00011800000000A0ull);
4970 #define CVMX_MIO_BOOT_INT CVMX_MIO_BOOT_INT_FUNC()
4971 static inline uint64_t CVMX_MIO_BOOT_INT_FUNC(void)
4973 return CVMX_ADD_IO_SEG(0x00011800000000A8ull);
4976 #define CVMX_MIO_BOOT_LOC_ADR CVMX_MIO_BOOT_LOC_ADR_FUNC()
4977 static inline uint64_t CVMX_MIO_BOOT_LOC_ADR_FUNC(void)
4979 return CVMX_ADD_IO_SEG(0x0001180000000090ull);
4982 static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset)
4984 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
4986 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
4987 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
4988 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
4989 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
4990 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
4991 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
4992 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
4993 cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset);
4995 return CVMX_ADD_IO_SEG(0x0001180000000080ull) + (offset&1)*8;
4998 #define CVMX_MIO_BOOT_LOC_DAT CVMX_MIO_BOOT_LOC_DAT_FUNC()
4999 static inline uint64_t CVMX_MIO_BOOT_LOC_DAT_FUNC(void)
5001 return CVMX_ADD_IO_SEG(0x0001180000000098ull);
5004 #define CVMX_MIO_BOOT_PIN_DEFS CVMX_MIO_BOOT_PIN_DEFS_FUNC()
5005 static inline uint64_t CVMX_MIO_BOOT_PIN_DEFS_FUNC(void)
5007 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5008 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
5009 cvmx_warn("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n");
5011 return CVMX_ADD_IO_SEG(0x00011800000000C0ull);
5014 static inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset)
5016 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5018 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
5019 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
5020 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
5021 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
5022 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
5023 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
5024 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
5025 cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset);
5027 return CVMX_ADD_IO_SEG(0x0001180000000000ull) + (offset&7)*8;
5030 static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset)
5032 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5034 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
5035 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
5036 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
5037 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
5038 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
5039 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
5040 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
5041 cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset);
5043 return CVMX_ADD_IO_SEG(0x0001180000000040ull) + (offset&7)*8;
5046 #define CVMX_MIO_BOOT_THR CVMX_MIO_BOOT_THR_FUNC()
5047 static inline uint64_t CVMX_MIO_BOOT_THR_FUNC(void)
5049 return CVMX_ADD_IO_SEG(0x00011800000000B0ull);
5052 static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
5054 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5056 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
5057 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
5058 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
5059 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
5060 cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset);
5062 return CVMX_ADD_IO_SEG(0x0001180000001520ull) + (offset&3)*8;
5065 #define CVMX_MIO_FUS_DAT0 CVMX_MIO_FUS_DAT0_FUNC()
5066 static inline uint64_t CVMX_MIO_FUS_DAT0_FUNC(void)
5068 return CVMX_ADD_IO_SEG(0x0001180000001400ull);
5071 #define CVMX_MIO_FUS_DAT1 CVMX_MIO_FUS_DAT1_FUNC()
5072 static inline uint64_t CVMX_MIO_FUS_DAT1_FUNC(void)
5074 return CVMX_ADD_IO_SEG(0x0001180000001408ull);
5077 #define CVMX_MIO_FUS_DAT2 CVMX_MIO_FUS_DAT2_FUNC()
5078 static inline uint64_t CVMX_MIO_FUS_DAT2_FUNC(void)
5080 return CVMX_ADD_IO_SEG(0x0001180000001410ull);
5083 #define CVMX_MIO_FUS_DAT3 CVMX_MIO_FUS_DAT3_FUNC()
5084 static inline uint64_t CVMX_MIO_FUS_DAT3_FUNC(void)
5086 return CVMX_ADD_IO_SEG(0x0001180000001418ull);
5089 #define CVMX_MIO_FUS_EMA CVMX_MIO_FUS_EMA_FUNC()
5090 static inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void)
5092 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5093 if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
5094 cvmx_warn("CVMX_MIO_FUS_EMA not supported on this chip\n");
5096 return CVMX_ADD_IO_SEG(0x0001180000001550ull);
5099 #define CVMX_MIO_FUS_PDF CVMX_MIO_FUS_PDF_FUNC()
5100 static inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void)
5102 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5103 if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
5104 cvmx_warn("CVMX_MIO_FUS_PDF not supported on this chip\n");
5106 return CVMX_ADD_IO_SEG(0x0001180000001420ull);
5109 #define CVMX_MIO_FUS_PLL CVMX_MIO_FUS_PLL_FUNC()
5110 static inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void)
5112 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5113 if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
5114 cvmx_warn("CVMX_MIO_FUS_PLL not supported on this chip\n");
5116 return CVMX_ADD_IO_SEG(0x0001180000001580ull);
5119 #define CVMX_MIO_FUS_PROG CVMX_MIO_FUS_PROG_FUNC()
5120 static inline uint64_t CVMX_MIO_FUS_PROG_FUNC(void)
5122 return CVMX_ADD_IO_SEG(0x0001180000001510ull);
5125 #define CVMX_MIO_FUS_PROG_TIMES CVMX_MIO_FUS_PROG_TIMES_FUNC()
5126 static inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void)
5128 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5129 if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
5130 cvmx_warn("CVMX_MIO_FUS_PROG_TIMES not supported on this chip\n");
5132 return CVMX_ADD_IO_SEG(0x0001180000001518ull);
5135 #define CVMX_MIO_FUS_RCMD CVMX_MIO_FUS_RCMD_FUNC()
5136 static inline uint64_t CVMX_MIO_FUS_RCMD_FUNC(void)
5138 return CVMX_ADD_IO_SEG(0x0001180000001500ull);
5141 #define CVMX_MIO_FUS_SPR_REPAIR_RES CVMX_MIO_FUS_SPR_REPAIR_RES_FUNC()
5142 static inline uint64_t CVMX_MIO_FUS_SPR_REPAIR_RES_FUNC(void)
5144 return CVMX_ADD_IO_SEG(0x0001180000001548ull);
5147 #define CVMX_MIO_FUS_SPR_REPAIR_SUM CVMX_MIO_FUS_SPR_REPAIR_SUM_FUNC()
5148 static inline uint64_t CVMX_MIO_FUS_SPR_REPAIR_SUM_FUNC(void)
5150 return CVMX_ADD_IO_SEG(0x0001180000001540ull);
5153 #define CVMX_MIO_FUS_UNLOCK CVMX_MIO_FUS_UNLOCK_FUNC()
5154 static inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void)
5156 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5157 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
5158 cvmx_warn("CVMX_MIO_FUS_UNLOCK not supported on this chip\n");
5160 return CVMX_ADD_IO_SEG(0x0001180000001578ull);
5163 #define CVMX_MIO_FUS_WADR CVMX_MIO_FUS_WADR_FUNC()
5164 static inline uint64_t CVMX_MIO_FUS_WADR_FUNC(void)
5166 return CVMX_ADD_IO_SEG(0x0001180000001508ull);
5169 #define CVMX_MIO_NDF_DMA_CFG CVMX_MIO_NDF_DMA_CFG_FUNC()
5170 static inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void)
5172 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5173 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5174 cvmx_warn("CVMX_MIO_NDF_DMA_CFG not supported on this chip\n");
5176 return CVMX_ADD_IO_SEG(0x0001180000000168ull);
5179 #define CVMX_MIO_NDF_DMA_INT CVMX_MIO_NDF_DMA_INT_FUNC()
5180 static inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void)
5182 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5183 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5184 cvmx_warn("CVMX_MIO_NDF_DMA_INT not supported on this chip\n");
5186 return CVMX_ADD_IO_SEG(0x0001180000000170ull);
5189 #define CVMX_MIO_NDF_DMA_INT_EN CVMX_MIO_NDF_DMA_INT_EN_FUNC()
5190 static inline uint64_t CVMX_MIO_NDF_DMA_INT_EN_FUNC(void)
5192 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5193 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5194 cvmx_warn("CVMX_MIO_NDF_DMA_INT_EN not supported on this chip\n");
5196 return CVMX_ADD_IO_SEG(0x0001180000000178ull);
5199 #define CVMX_MIO_PLL_CTL CVMX_MIO_PLL_CTL_FUNC()
5200 static inline uint64_t CVMX_MIO_PLL_CTL_FUNC(void)
5202 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5203 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
5204 cvmx_warn("CVMX_MIO_PLL_CTL not supported on this chip\n");
5206 return CVMX_ADD_IO_SEG(0x0001180000001448ull);
5209 #define CVMX_MIO_PLL_SETTING CVMX_MIO_PLL_SETTING_FUNC()
5210 static inline uint64_t CVMX_MIO_PLL_SETTING_FUNC(void)
5212 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5213 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
5214 cvmx_warn("CVMX_MIO_PLL_SETTING not supported on this chip\n");
5216 return CVMX_ADD_IO_SEG(0x0001180000001440ull);
5219 static inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset)
5221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5223 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5224 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
5225 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
5226 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
5227 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
5228 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
5229 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5230 cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n", offset);
5232 return CVMX_ADD_IO_SEG(0x0001180000001010ull) + (offset&1)*512;
5235 static inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset)
5237 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5239 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5240 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
5241 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
5242 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
5243 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
5244 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
5245 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5246 cvmx_warn("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n", offset);
5248 return CVMX_ADD_IO_SEG(0x0001180000001000ull) + (offset&1)*512;
5251 static inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset)
5253 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5255 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5256 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
5257 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
5258 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
5259 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
5260 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
5261 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5262 cvmx_warn("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n", offset);
5264 return CVMX_ADD_IO_SEG(0x0001180000001018ull) + (offset&1)*512;
5267 static inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset)
5269 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5271 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5272 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
5273 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
5274 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
5275 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
5276 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
5277 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5278 cvmx_warn("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n", offset);
5280 return CVMX_ADD_IO_SEG(0x0001180000001008ull) + (offset&1)*512;
5283 #define CVMX_MIO_UART2_DLH CVMX_MIO_UART2_DLH_FUNC()
5284 static inline uint64_t CVMX_MIO_UART2_DLH_FUNC(void)
5286 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5287 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5288 cvmx_warn("CVMX_MIO_UART2_DLH not supported on this chip\n");
5290 return CVMX_ADD_IO_SEG(0x0001180000000488ull);
5293 #define CVMX_MIO_UART2_DLL CVMX_MIO_UART2_DLL_FUNC()
5294 static inline uint64_t CVMX_MIO_UART2_DLL_FUNC(void)
5296 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5297 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5298 cvmx_warn("CVMX_MIO_UART2_DLL not supported on this chip\n");
5300 return CVMX_ADD_IO_SEG(0x0001180000000480ull);
5303 #define CVMX_MIO_UART2_FAR CVMX_MIO_UART2_FAR_FUNC()
5304 static inline uint64_t CVMX_MIO_UART2_FAR_FUNC(void)
5306 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5307 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5308 cvmx_warn("CVMX_MIO_UART2_FAR not supported on this chip\n");
5310 return CVMX_ADD_IO_SEG(0x0001180000000520ull);
5313 #define CVMX_MIO_UART2_FCR CVMX_MIO_UART2_FCR_FUNC()
5314 static inline uint64_t CVMX_MIO_UART2_FCR_FUNC(void)
5316 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5317 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5318 cvmx_warn("CVMX_MIO_UART2_FCR not supported on this chip\n");
5320 return CVMX_ADD_IO_SEG(0x0001180000000450ull);
5323 #define CVMX_MIO_UART2_HTX CVMX_MIO_UART2_HTX_FUNC()
5324 static inline uint64_t CVMX_MIO_UART2_HTX_FUNC(void)
5326 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5327 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5328 cvmx_warn("CVMX_MIO_UART2_HTX not supported on this chip\n");
5330 return CVMX_ADD_IO_SEG(0x0001180000000708ull);
5333 #define CVMX_MIO_UART2_IER CVMX_MIO_UART2_IER_FUNC()
5334 static inline uint64_t CVMX_MIO_UART2_IER_FUNC(void)
5336 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5337 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5338 cvmx_warn("CVMX_MIO_UART2_IER not supported on this chip\n");
5340 return CVMX_ADD_IO_SEG(0x0001180000000408ull);
5343 #define CVMX_MIO_UART2_IIR CVMX_MIO_UART2_IIR_FUNC()
5344 static inline uint64_t CVMX_MIO_UART2_IIR_FUNC(void)
5346 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5347 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5348 cvmx_warn("CVMX_MIO_UART2_IIR not supported on this chip\n");
5350 return CVMX_ADD_IO_SEG(0x0001180000000410ull);
5353 #define CVMX_MIO_UART2_LCR CVMX_MIO_UART2_LCR_FUNC()
5354 static inline uint64_t CVMX_MIO_UART2_LCR_FUNC(void)
5356 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5357 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5358 cvmx_warn("CVMX_MIO_UART2_LCR not supported on this chip\n");
5360 return CVMX_ADD_IO_SEG(0x0001180000000418ull);
5363 #define CVMX_MIO_UART2_LSR CVMX_MIO_UART2_LSR_FUNC()
5364 static inline uint64_t CVMX_MIO_UART2_LSR_FUNC(void)
5366 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5367 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5368 cvmx_warn("CVMX_MIO_UART2_LSR not supported on this chip\n");
5370 return CVMX_ADD_IO_SEG(0x0001180000000428ull);
5373 #define CVMX_MIO_UART2_MCR CVMX_MIO_UART2_MCR_FUNC()
5374 static inline uint64_t CVMX_MIO_UART2_MCR_FUNC(void)
5376 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5377 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5378 cvmx_warn("CVMX_MIO_UART2_MCR not supported on this chip\n");
5380 return CVMX_ADD_IO_SEG(0x0001180000000420ull);
5383 #define CVMX_MIO_UART2_MSR CVMX_MIO_UART2_MSR_FUNC()
5384 static inline uint64_t CVMX_MIO_UART2_MSR_FUNC(void)
5386 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5387 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5388 cvmx_warn("CVMX_MIO_UART2_MSR not supported on this chip\n");
5390 return CVMX_ADD_IO_SEG(0x0001180000000430ull);
5393 #define CVMX_MIO_UART2_RBR CVMX_MIO_UART2_RBR_FUNC()
5394 static inline uint64_t CVMX_MIO_UART2_RBR_FUNC(void)
5396 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5397 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5398 cvmx_warn("CVMX_MIO_UART2_RBR not supported on this chip\n");
5400 return CVMX_ADD_IO_SEG(0x0001180000000400ull);
5403 #define CVMX_MIO_UART2_RFL CVMX_MIO_UART2_RFL_FUNC()
5404 static inline uint64_t CVMX_MIO_UART2_RFL_FUNC(void)
5406 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5407 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5408 cvmx_warn("CVMX_MIO_UART2_RFL not supported on this chip\n");
5410 return CVMX_ADD_IO_SEG(0x0001180000000608ull);
5413 #define CVMX_MIO_UART2_RFW CVMX_MIO_UART2_RFW_FUNC()
5414 static inline uint64_t CVMX_MIO_UART2_RFW_FUNC(void)
5416 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5417 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5418 cvmx_warn("CVMX_MIO_UART2_RFW not supported on this chip\n");
5420 return CVMX_ADD_IO_SEG(0x0001180000000530ull);
5423 #define CVMX_MIO_UART2_SBCR CVMX_MIO_UART2_SBCR_FUNC()
5424 static inline uint64_t CVMX_MIO_UART2_SBCR_FUNC(void)
5426 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5427 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5428 cvmx_warn("CVMX_MIO_UART2_SBCR not supported on this chip\n");
5430 return CVMX_ADD_IO_SEG(0x0001180000000620ull);
5433 #define CVMX_MIO_UART2_SCR CVMX_MIO_UART2_SCR_FUNC()
5434 static inline uint64_t CVMX_MIO_UART2_SCR_FUNC(void)
5436 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5437 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5438 cvmx_warn("CVMX_MIO_UART2_SCR not supported on this chip\n");
5440 return CVMX_ADD_IO_SEG(0x0001180000000438ull);
5443 #define CVMX_MIO_UART2_SFE CVMX_MIO_UART2_SFE_FUNC()
5444 static inline uint64_t CVMX_MIO_UART2_SFE_FUNC(void)
5446 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5447 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5448 cvmx_warn("CVMX_MIO_UART2_SFE not supported on this chip\n");
5450 return CVMX_ADD_IO_SEG(0x0001180000000630ull);
5453 #define CVMX_MIO_UART2_SRR CVMX_MIO_UART2_SRR_FUNC()
5454 static inline uint64_t CVMX_MIO_UART2_SRR_FUNC(void)
5456 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5457 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5458 cvmx_warn("CVMX_MIO_UART2_SRR not supported on this chip\n");
5460 return CVMX_ADD_IO_SEG(0x0001180000000610ull);
5463 #define CVMX_MIO_UART2_SRT CVMX_MIO_UART2_SRT_FUNC()
5464 static inline uint64_t CVMX_MIO_UART2_SRT_FUNC(void)
5466 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5467 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5468 cvmx_warn("CVMX_MIO_UART2_SRT not supported on this chip\n");
5470 return CVMX_ADD_IO_SEG(0x0001180000000638ull);
5473 #define CVMX_MIO_UART2_SRTS CVMX_MIO_UART2_SRTS_FUNC()
5474 static inline uint64_t CVMX_MIO_UART2_SRTS_FUNC(void)
5476 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5477 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5478 cvmx_warn("CVMX_MIO_UART2_SRTS not supported on this chip\n");
5480 return CVMX_ADD_IO_SEG(0x0001180000000618ull);
5483 #define CVMX_MIO_UART2_STT CVMX_MIO_UART2_STT_FUNC()
5484 static inline uint64_t CVMX_MIO_UART2_STT_FUNC(void)
5486 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5487 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5488 cvmx_warn("CVMX_MIO_UART2_STT not supported on this chip\n");
5490 return CVMX_ADD_IO_SEG(0x0001180000000700ull);
5493 #define CVMX_MIO_UART2_TFL CVMX_MIO_UART2_TFL_FUNC()
5494 static inline uint64_t CVMX_MIO_UART2_TFL_FUNC(void)
5496 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5497 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5498 cvmx_warn("CVMX_MIO_UART2_TFL not supported on this chip\n");
5500 return CVMX_ADD_IO_SEG(0x0001180000000600ull);
5503 #define CVMX_MIO_UART2_TFR CVMX_MIO_UART2_TFR_FUNC()
5504 static inline uint64_t CVMX_MIO_UART2_TFR_FUNC(void)
5506 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5507 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5508 cvmx_warn("CVMX_MIO_UART2_TFR not supported on this chip\n");
5510 return CVMX_ADD_IO_SEG(0x0001180000000528ull);
5513 #define CVMX_MIO_UART2_THR CVMX_MIO_UART2_THR_FUNC()
5514 static inline uint64_t CVMX_MIO_UART2_THR_FUNC(void)
5516 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5517 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5518 cvmx_warn("CVMX_MIO_UART2_THR not supported on this chip\n");
5520 return CVMX_ADD_IO_SEG(0x0001180000000440ull);
5523 #define CVMX_MIO_UART2_USR CVMX_MIO_UART2_USR_FUNC()
5524 static inline uint64_t CVMX_MIO_UART2_USR_FUNC(void)
5526 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5527 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
5528 cvmx_warn("CVMX_MIO_UART2_USR not supported on this chip\n");
5530 return CVMX_ADD_IO_SEG(0x0001180000000538ull);
5533 static inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset)
5535 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5537 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5538 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5539 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5540 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5541 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5542 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5543 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5544 cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n", offset);
5546 return CVMX_ADD_IO_SEG(0x0001180000000888ull) + (offset&1)*1024;
5549 static inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset)
5551 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5553 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5554 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5555 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5556 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5557 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5558 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5559 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5560 cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n", offset);
5562 return CVMX_ADD_IO_SEG(0x0001180000000880ull) + (offset&1)*1024;
5565 static inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset)
5567 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5569 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5570 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5571 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5572 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5573 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5574 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5575 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5576 cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n", offset);
5578 return CVMX_ADD_IO_SEG(0x0001180000000920ull) + (offset&1)*1024;
5581 static inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset)
5583 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5585 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5586 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5587 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5588 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5589 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5590 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5591 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5592 cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n", offset);
5594 return CVMX_ADD_IO_SEG(0x0001180000000850ull) + (offset&1)*1024;
5597 static inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset)
5599 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5601 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5602 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5603 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5604 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5605 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5606 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5607 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5608 cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n", offset);
5610 return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + (offset&1)*1024;
5613 static inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset)
5615 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5617 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5618 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5619 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5620 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5621 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5622 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5623 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5624 cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n", offset);
5626 return CVMX_ADD_IO_SEG(0x0001180000000808ull) + (offset&1)*1024;
5629 static inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset)
5631 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5633 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5634 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5635 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5636 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5637 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5638 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5639 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5640 cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n", offset);
5642 return CVMX_ADD_IO_SEG(0x0001180000000810ull) + (offset&1)*1024;
5645 static inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset)
5647 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5649 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5650 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5651 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5652 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5653 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5654 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5655 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5656 cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n", offset);
5658 return CVMX_ADD_IO_SEG(0x0001180000000818ull) + (offset&1)*1024;
5661 static inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset)
5663 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5665 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5666 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5667 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5668 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5669 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5670 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5671 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5672 cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n", offset);
5674 return CVMX_ADD_IO_SEG(0x0001180000000828ull) + (offset&1)*1024;
5677 static inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset)
5679 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5681 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5682 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5683 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5684 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5685 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5686 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5687 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5688 cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n", offset);
5690 return CVMX_ADD_IO_SEG(0x0001180000000820ull) + (offset&1)*1024;
5693 static inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset)
5695 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5697 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5698 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5699 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5700 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5701 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5702 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5703 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5704 cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n", offset);
5706 return CVMX_ADD_IO_SEG(0x0001180000000830ull) + (offset&1)*1024;
5709 static inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset)
5711 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5713 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5714 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5715 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5716 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5717 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5718 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5719 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5720 cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n", offset);
5722 return CVMX_ADD_IO_SEG(0x0001180000000800ull) + (offset&1)*1024;
5725 static inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset)
5727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5729 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5730 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5731 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5732 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5733 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5734 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5735 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5736 cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n", offset);
5738 return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + (offset&1)*1024;
5741 static inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset)
5743 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5745 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5746 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5747 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5748 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5749 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5750 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5751 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5752 cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n", offset);
5754 return CVMX_ADD_IO_SEG(0x0001180000000930ull) + (offset&1)*1024;
5757 static inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset)
5759 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5761 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5762 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5763 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5764 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5765 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5766 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5767 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5768 cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n", offset);
5770 return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + (offset&1)*1024;
5773 static inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset)
5775 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5777 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5778 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5779 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5780 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5781 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5782 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5783 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5784 cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n", offset);
5786 return CVMX_ADD_IO_SEG(0x0001180000000838ull) + (offset&1)*1024;
5789 static inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset)
5791 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5793 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5794 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5795 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5796 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5797 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5798 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5799 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5800 cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n", offset);
5802 return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + (offset&1)*1024;
5805 static inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset)
5807 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5809 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5810 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5811 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5812 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5813 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5814 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5815 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5816 cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n", offset);
5818 return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + (offset&1)*1024;
5821 static inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset)
5823 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5825 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5826 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5827 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5828 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5829 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5830 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5831 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5832 cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n", offset);
5834 return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + (offset&1)*1024;
5837 static inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset)
5839 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5841 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5842 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5843 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5844 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5845 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5846 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5847 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5848 cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n", offset);
5850 return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + (offset&1)*1024;
5853 static inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset)
5855 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5857 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5858 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5859 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5860 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5861 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5862 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5863 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5864 cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n", offset);
5866 return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + (offset&1)*1024;
5869 static inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset)
5871 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5873 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5874 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5875 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5876 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5877 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5878 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5879 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5880 cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n", offset);
5882 return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + (offset&1)*1024;
5885 static inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset)
5887 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5889 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5890 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5891 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5892 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5893 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5894 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5895 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5896 cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n", offset);
5898 return CVMX_ADD_IO_SEG(0x0001180000000928ull) + (offset&1)*1024;
5901 static inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset)
5903 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5905 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5906 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5907 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5908 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5909 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5910 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5911 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5912 cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n", offset);
5914 return CVMX_ADD_IO_SEG(0x0001180000000840ull) + (offset&1)*1024;
5917 static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset)
5919 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5921 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
5922 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
5923 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
5924 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
5925 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
5926 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
5927 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5928 cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n", offset);
5930 return CVMX_ADD_IO_SEG(0x0001180000000938ull) + (offset&1)*1024;
5933 static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
5935 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5937 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
5938 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5939 cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset);
5941 return CVMX_ADD_IO_SEG(0x0001070000100078ull) + (offset&1)*2048;
5944 static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
5946 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5948 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
5949 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5950 cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset);
5952 return CVMX_ADD_IO_SEG(0x0001070000100020ull) + (offset&1)*2048;
5955 static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
5957 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5959 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
5960 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5961 cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset);
5963 return CVMX_ADD_IO_SEG(0x0001070000100050ull) + (offset&1)*2048;
5966 static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
5968 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5970 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
5971 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5972 cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset);
5974 return CVMX_ADD_IO_SEG(0x0001070000100030ull) + (offset&1)*2048;
5977 static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
5979 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5981 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
5982 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5983 cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset);
5985 return CVMX_ADD_IO_SEG(0x0001070000100028ull) + (offset&1)*2048;
5988 static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
5990 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5992 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
5993 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
5994 cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset);
5996 return CVMX_ADD_IO_SEG(0x0001070000100010ull) + (offset&1)*2048;
5999 static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
6001 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6003 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
6004 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
6005 cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset);
6007 return CVMX_ADD_IO_SEG(0x0001070000100018ull) + (offset&1)*2048;
6010 static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
6012 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6014 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
6015 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
6016 cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset);
6018 return CVMX_ADD_IO_SEG(0x0001070000100048ull) + (offset&1)*2048;
6021 static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
6023 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6025 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
6026 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
6027 cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset);
6029 return CVMX_ADD_IO_SEG(0x0001070000100040ull) + (offset&1)*2048;
6032 static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
6034 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6036 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
6037 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
6038 cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset);
6040 return CVMX_ADD_IO_SEG(0x0001070000100038ull) + (offset&1)*2048;
6043 static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
6045 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6047 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
6048 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
6049 cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset);
6051 return CVMX_ADD_IO_SEG(0x0001070000100000ull) + (offset&1)*2048;
6054 static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
6056 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6058 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
6059 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
6060 cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset);
6062 return CVMX_ADD_IO_SEG(0x0001070000100008ull) + (offset&1)*2048;
6065 static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
6067 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6069 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
6070 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
6071 cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset);
6073 return CVMX_ADD_IO_SEG(0x0001070000100058ull) + (offset&1)*2048;
6076 #define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
6077 static inline uint64_t CVMX_MPI_CFG_FUNC(void)
6079 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6080 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
6081 cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
6083 return CVMX_ADD_IO_SEG(0x0001070000001000ull);
6086 static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
6088 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6090 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
6091 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
6092 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8)))))
6093 cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset);
6095 return CVMX_ADD_IO_SEG(0x0001070000001080ull) + (offset&15)*8;
6098 #define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
6099 static inline uint64_t CVMX_MPI_STS_FUNC(void)
6101 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6102 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
6103 cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
6105 return CVMX_ADD_IO_SEG(0x0001070000001008ull);
6108 #define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
6109 static inline uint64_t CVMX_MPI_TX_FUNC(void)
6111 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6112 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
6113 cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
6115 return CVMX_ADD_IO_SEG(0x0001070000001010ull);
6118 #define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC()
6119 static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
6121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6122 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6123 cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n");
6125 return CVMX_ADD_IO_SEG(0x0001070001000018ull);
6128 #define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC()
6129 static inline uint64_t CVMX_NDF_CMD_FUNC(void)
6131 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6132 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6133 cvmx_warn("CVMX_NDF_CMD not supported on this chip\n");
6135 return CVMX_ADD_IO_SEG(0x0001070001000000ull);
6138 #define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC()
6139 static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
6141 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6142 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6143 cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n");
6145 return CVMX_ADD_IO_SEG(0x0001070001000030ull);
6148 #define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC()
6149 static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
6151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6152 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6153 cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n");
6155 return CVMX_ADD_IO_SEG(0x0001070001000010ull);
6158 #define CVMX_NDF_INT CVMX_NDF_INT_FUNC()
6159 static inline uint64_t CVMX_NDF_INT_FUNC(void)
6161 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6162 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6163 cvmx_warn("CVMX_NDF_INT not supported on this chip\n");
6165 return CVMX_ADD_IO_SEG(0x0001070001000020ull);
6168 #define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC()
6169 static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
6171 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6172 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6173 cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n");
6175 return CVMX_ADD_IO_SEG(0x0001070001000028ull);
6178 #define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC()
6179 static inline uint64_t CVMX_NDF_MISC_FUNC(void)
6181 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6182 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6183 cvmx_warn("CVMX_NDF_MISC not supported on this chip\n");
6185 return CVMX_ADD_IO_SEG(0x0001070001000008ull);
6188 #define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC()
6189 static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
6191 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6192 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6193 cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n");
6195 return CVMX_ADD_IO_SEG(0x0001070001000038ull);
6198 static inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset)
6200 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6202 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6203 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6204 cvmx_warn("CVMX_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
6206 return 0x0000000000000000ull + (offset&31)*16;
6209 #define CVMX_NPEI_BIST_STATUS CVMX_NPEI_BIST_STATUS_FUNC()
6210 static inline uint64_t CVMX_NPEI_BIST_STATUS_FUNC(void)
6212 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6213 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6214 cvmx_warn("CVMX_NPEI_BIST_STATUS not supported on this chip\n");
6216 return 0x0000000000000580ull;
6219 #define CVMX_NPEI_BIST_STATUS2 CVMX_NPEI_BIST_STATUS2_FUNC()
6220 static inline uint64_t CVMX_NPEI_BIST_STATUS2_FUNC(void)
6222 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6223 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6224 cvmx_warn("CVMX_NPEI_BIST_STATUS2 not supported on this chip\n");
6226 return 0x0000000000000680ull;
6229 #define CVMX_NPEI_CTL_PORT0 CVMX_NPEI_CTL_PORT0_FUNC()
6230 static inline uint64_t CVMX_NPEI_CTL_PORT0_FUNC(void)
6232 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6233 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6234 cvmx_warn("CVMX_NPEI_CTL_PORT0 not supported on this chip\n");
6236 return 0x0000000000000250ull;
6239 #define CVMX_NPEI_CTL_PORT1 CVMX_NPEI_CTL_PORT1_FUNC()
6240 static inline uint64_t CVMX_NPEI_CTL_PORT1_FUNC(void)
6242 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6243 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6244 cvmx_warn("CVMX_NPEI_CTL_PORT1 not supported on this chip\n");
6246 return 0x0000000000000260ull;
6249 #define CVMX_NPEI_CTL_STATUS CVMX_NPEI_CTL_STATUS_FUNC()
6250 static inline uint64_t CVMX_NPEI_CTL_STATUS_FUNC(void)
6252 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6253 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6254 cvmx_warn("CVMX_NPEI_CTL_STATUS not supported on this chip\n");
6256 return 0x0000000000000570ull;
6259 #define CVMX_NPEI_CTL_STATUS2 CVMX_NPEI_CTL_STATUS2_FUNC()
6260 static inline uint64_t CVMX_NPEI_CTL_STATUS2_FUNC(void)
6262 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6263 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6264 cvmx_warn("CVMX_NPEI_CTL_STATUS2 not supported on this chip\n");
6266 return 0x0000000000003C00ull;
6269 #define CVMX_NPEI_DATA_OUT_CNT CVMX_NPEI_DATA_OUT_CNT_FUNC()
6270 static inline uint64_t CVMX_NPEI_DATA_OUT_CNT_FUNC(void)
6272 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6273 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6274 cvmx_warn("CVMX_NPEI_DATA_OUT_CNT not supported on this chip\n");
6276 return 0x00000000000005F0ull;
6279 #define CVMX_NPEI_DBG_DATA CVMX_NPEI_DBG_DATA_FUNC()
6280 static inline uint64_t CVMX_NPEI_DBG_DATA_FUNC(void)
6282 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6283 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6284 cvmx_warn("CVMX_NPEI_DBG_DATA not supported on this chip\n");
6286 return 0x0000000000000510ull;
6289 #define CVMX_NPEI_DBG_SELECT CVMX_NPEI_DBG_SELECT_FUNC()
6290 static inline uint64_t CVMX_NPEI_DBG_SELECT_FUNC(void)
6292 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6293 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6294 cvmx_warn("CVMX_NPEI_DBG_SELECT not supported on this chip\n");
6296 return 0x0000000000000500ull;
6299 #define CVMX_NPEI_DMA0_INT_LEVEL CVMX_NPEI_DMA0_INT_LEVEL_FUNC()
6300 static inline uint64_t CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void)
6302 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6303 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6304 cvmx_warn("CVMX_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
6306 return 0x00000000000005C0ull;
6309 #define CVMX_NPEI_DMA1_INT_LEVEL CVMX_NPEI_DMA1_INT_LEVEL_FUNC()
6310 static inline uint64_t CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void)
6312 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6313 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6314 cvmx_warn("CVMX_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
6316 return 0x00000000000005D0ull;
6319 static inline uint64_t CVMX_NPEI_DMAX_COUNTS(unsigned long offset)
6321 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6323 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
6324 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
6325 cvmx_warn("CVMX_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
6327 return 0x0000000000000450ull + (offset&7)*16;
6330 static inline uint64_t CVMX_NPEI_DMAX_DBELL(unsigned long offset)
6332 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6334 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
6335 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
6336 cvmx_warn("CVMX_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
6338 return 0x00000000000003B0ull + (offset&7)*16;
6341 static inline uint64_t CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
6343 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6345 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
6346 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
6347 cvmx_warn("CVMX_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
6349 return 0x0000000000000400ull + (offset&7)*16;
6352 static inline uint64_t CVMX_NPEI_DMAX_NADDR(unsigned long offset)
6354 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6356 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
6357 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
6358 cvmx_warn("CVMX_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
6360 return 0x00000000000004A0ull + (offset&7)*16;
6363 #define CVMX_NPEI_DMA_CNTS CVMX_NPEI_DMA_CNTS_FUNC()
6364 static inline uint64_t CVMX_NPEI_DMA_CNTS_FUNC(void)
6366 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6367 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6368 cvmx_warn("CVMX_NPEI_DMA_CNTS not supported on this chip\n");
6370 return 0x00000000000005E0ull;
6373 #define CVMX_NPEI_DMA_CONTROL CVMX_NPEI_DMA_CONTROL_FUNC()
6374 static inline uint64_t CVMX_NPEI_DMA_CONTROL_FUNC(void)
6376 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6377 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6378 cvmx_warn("CVMX_NPEI_DMA_CONTROL not supported on this chip\n");
6380 return 0x00000000000003A0ull;
6383 #define CVMX_NPEI_DMA_PCIE_REQ_NUM CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC()
6384 static inline uint64_t CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
6386 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6387 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6388 cvmx_warn("CVMX_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
6390 return 0x00000000000005B0ull;
6393 #define CVMX_NPEI_DMA_STATE1 CVMX_NPEI_DMA_STATE1_FUNC()
6394 static inline uint64_t CVMX_NPEI_DMA_STATE1_FUNC(void)
6396 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6397 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6398 cvmx_warn("CVMX_NPEI_DMA_STATE1 not supported on this chip\n");
6400 return 0x00000000000006C0ull;
6403 #define CVMX_NPEI_DMA_STATE1_P1 CVMX_NPEI_DMA_STATE1_P1_FUNC()
6404 static inline uint64_t CVMX_NPEI_DMA_STATE1_P1_FUNC(void)
6406 return 0x0000000000000680ull;
6409 #define CVMX_NPEI_DMA_STATE2 CVMX_NPEI_DMA_STATE2_FUNC()
6410 static inline uint64_t CVMX_NPEI_DMA_STATE2_FUNC(void)
6412 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6413 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
6414 cvmx_warn("CVMX_NPEI_DMA_STATE2 not supported on this chip\n");
6416 return 0x00000000000006D0ull;
6419 #define CVMX_NPEI_DMA_STATE2_P1 CVMX_NPEI_DMA_STATE2_P1_FUNC()
6420 static inline uint64_t CVMX_NPEI_DMA_STATE2_P1_FUNC(void)
6422 return 0x0000000000000690ull;
6425 #define CVMX_NPEI_DMA_STATE3_P1 CVMX_NPEI_DMA_STATE3_P1_FUNC()
6426 static inline uint64_t CVMX_NPEI_DMA_STATE3_P1_FUNC(void)
6428 return 0x00000000000006A0ull;
6431 #define CVMX_NPEI_DMA_STATE4_P1 CVMX_NPEI_DMA_STATE4_P1_FUNC()
6432 static inline uint64_t CVMX_NPEI_DMA_STATE4_P1_FUNC(void)
6434 return 0x00000000000006B0ull;
6437 #define CVMX_NPEI_DMA_STATE5_P1 CVMX_NPEI_DMA_STATE5_P1_FUNC()
6438 static inline uint64_t CVMX_NPEI_DMA_STATE5_P1_FUNC(void)
6440 return 0x00000000000006C0ull;
6443 #define CVMX_NPEI_INT_A_ENB CVMX_NPEI_INT_A_ENB_FUNC()
6444 static inline uint64_t CVMX_NPEI_INT_A_ENB_FUNC(void)
6446 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6447 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6448 cvmx_warn("CVMX_NPEI_INT_A_ENB not supported on this chip\n");
6450 return 0x0000000000000560ull;
6453 #define CVMX_NPEI_INT_A_ENB2 CVMX_NPEI_INT_A_ENB2_FUNC()
6454 static inline uint64_t CVMX_NPEI_INT_A_ENB2_FUNC(void)
6456 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6457 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6458 cvmx_warn("CVMX_NPEI_INT_A_ENB2 not supported on this chip\n");
6460 return 0x0000000000003CE0ull;
6463 #define CVMX_NPEI_INT_A_SUM CVMX_NPEI_INT_A_SUM_FUNC()
6464 static inline uint64_t CVMX_NPEI_INT_A_SUM_FUNC(void)
6466 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6467 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6468 cvmx_warn("CVMX_NPEI_INT_A_SUM not supported on this chip\n");
6470 return 0x0000000000000550ull;
6473 #define CVMX_NPEI_INT_ENB CVMX_NPEI_INT_ENB_FUNC()
6474 static inline uint64_t CVMX_NPEI_INT_ENB_FUNC(void)
6476 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6477 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6478 cvmx_warn("CVMX_NPEI_INT_ENB not supported on this chip\n");
6480 return 0x0000000000000540ull;
6483 #define CVMX_NPEI_INT_ENB2 CVMX_NPEI_INT_ENB2_FUNC()
6484 static inline uint64_t CVMX_NPEI_INT_ENB2_FUNC(void)
6486 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6487 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6488 cvmx_warn("CVMX_NPEI_INT_ENB2 not supported on this chip\n");
6490 return 0x0000000000003CD0ull;
6493 #define CVMX_NPEI_INT_INFO CVMX_NPEI_INT_INFO_FUNC()
6494 static inline uint64_t CVMX_NPEI_INT_INFO_FUNC(void)
6496 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6497 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6498 cvmx_warn("CVMX_NPEI_INT_INFO not supported on this chip\n");
6500 return 0x0000000000000590ull;
6503 #define CVMX_NPEI_INT_SUM CVMX_NPEI_INT_SUM_FUNC()
6504 static inline uint64_t CVMX_NPEI_INT_SUM_FUNC(void)
6506 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6507 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6508 cvmx_warn("CVMX_NPEI_INT_SUM not supported on this chip\n");
6510 return 0x0000000000000530ull;
6513 #define CVMX_NPEI_INT_SUM2 CVMX_NPEI_INT_SUM2_FUNC()
6514 static inline uint64_t CVMX_NPEI_INT_SUM2_FUNC(void)
6516 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6517 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6518 cvmx_warn("CVMX_NPEI_INT_SUM2 not supported on this chip\n");
6520 return 0x0000000000003CC0ull;
6523 #define CVMX_NPEI_LAST_WIN_RDATA0 CVMX_NPEI_LAST_WIN_RDATA0_FUNC()
6524 static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void)
6526 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6527 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6528 cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
6530 return 0x0000000000000600ull;
6533 #define CVMX_NPEI_LAST_WIN_RDATA1 CVMX_NPEI_LAST_WIN_RDATA1_FUNC()
6534 static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void)
6536 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6537 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6538 cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
6540 return 0x0000000000000610ull;
6543 #define CVMX_NPEI_MEM_ACCESS_CTL CVMX_NPEI_MEM_ACCESS_CTL_FUNC()
6544 static inline uint64_t CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void)
6546 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6547 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6548 cvmx_warn("CVMX_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
6550 return 0x00000000000004F0ull;
6553 static inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
6555 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6557 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))) ||
6558 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27))))))
6559 cvmx_warn("CVMX_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
6561 return 0x0000000000000340ull + (offset&31)*16 - 16*12;
6564 #define CVMX_NPEI_MSI_ENB0 CVMX_NPEI_MSI_ENB0_FUNC()
6565 static inline uint64_t CVMX_NPEI_MSI_ENB0_FUNC(void)
6567 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6568 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6569 cvmx_warn("CVMX_NPEI_MSI_ENB0 not supported on this chip\n");
6571 return 0x0000000000003C50ull;
6574 #define CVMX_NPEI_MSI_ENB1 CVMX_NPEI_MSI_ENB1_FUNC()
6575 static inline uint64_t CVMX_NPEI_MSI_ENB1_FUNC(void)
6577 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6578 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6579 cvmx_warn("CVMX_NPEI_MSI_ENB1 not supported on this chip\n");
6581 return 0x0000000000003C60ull;
6584 #define CVMX_NPEI_MSI_ENB2 CVMX_NPEI_MSI_ENB2_FUNC()
6585 static inline uint64_t CVMX_NPEI_MSI_ENB2_FUNC(void)
6587 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6588 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6589 cvmx_warn("CVMX_NPEI_MSI_ENB2 not supported on this chip\n");
6591 return 0x0000000000003C70ull;
6594 #define CVMX_NPEI_MSI_ENB3 CVMX_NPEI_MSI_ENB3_FUNC()
6595 static inline uint64_t CVMX_NPEI_MSI_ENB3_FUNC(void)
6597 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6598 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6599 cvmx_warn("CVMX_NPEI_MSI_ENB3 not supported on this chip\n");
6601 return 0x0000000000003C80ull;
6604 #define CVMX_NPEI_MSI_RCV0 CVMX_NPEI_MSI_RCV0_FUNC()
6605 static inline uint64_t CVMX_NPEI_MSI_RCV0_FUNC(void)
6607 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6608 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6609 cvmx_warn("CVMX_NPEI_MSI_RCV0 not supported on this chip\n");
6611 return 0x0000000000003C10ull;
6614 #define CVMX_NPEI_MSI_RCV1 CVMX_NPEI_MSI_RCV1_FUNC()
6615 static inline uint64_t CVMX_NPEI_MSI_RCV1_FUNC(void)
6617 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6618 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6619 cvmx_warn("CVMX_NPEI_MSI_RCV1 not supported on this chip\n");
6621 return 0x0000000000003C20ull;
6624 #define CVMX_NPEI_MSI_RCV2 CVMX_NPEI_MSI_RCV2_FUNC()
6625 static inline uint64_t CVMX_NPEI_MSI_RCV2_FUNC(void)
6627 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6628 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6629 cvmx_warn("CVMX_NPEI_MSI_RCV2 not supported on this chip\n");
6631 return 0x0000000000003C30ull;
6634 #define CVMX_NPEI_MSI_RCV3 CVMX_NPEI_MSI_RCV3_FUNC()
6635 static inline uint64_t CVMX_NPEI_MSI_RCV3_FUNC(void)
6637 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6638 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6639 cvmx_warn("CVMX_NPEI_MSI_RCV3 not supported on this chip\n");
6641 return 0x0000000000003C40ull;
6644 #define CVMX_NPEI_MSI_RD_MAP CVMX_NPEI_MSI_RD_MAP_FUNC()
6645 static inline uint64_t CVMX_NPEI_MSI_RD_MAP_FUNC(void)
6647 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6648 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6649 cvmx_warn("CVMX_NPEI_MSI_RD_MAP not supported on this chip\n");
6651 return 0x0000000000003CA0ull;
6654 #define CVMX_NPEI_MSI_W1C_ENB0 CVMX_NPEI_MSI_W1C_ENB0_FUNC()
6655 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB0_FUNC(void)
6657 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6658 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6659 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
6661 return 0x0000000000003CF0ull;
6664 #define CVMX_NPEI_MSI_W1C_ENB1 CVMX_NPEI_MSI_W1C_ENB1_FUNC()
6665 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB1_FUNC(void)
6667 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6668 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6669 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
6671 return 0x0000000000003D00ull;
6674 #define CVMX_NPEI_MSI_W1C_ENB2 CVMX_NPEI_MSI_W1C_ENB2_FUNC()
6675 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB2_FUNC(void)
6677 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6678 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6679 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
6681 return 0x0000000000003D10ull;
6684 #define CVMX_NPEI_MSI_W1C_ENB3 CVMX_NPEI_MSI_W1C_ENB3_FUNC()
6685 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB3_FUNC(void)
6687 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6688 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6689 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
6691 return 0x0000000000003D20ull;
6694 #define CVMX_NPEI_MSI_W1S_ENB0 CVMX_NPEI_MSI_W1S_ENB0_FUNC()
6695 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB0_FUNC(void)
6697 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6698 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6699 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
6701 return 0x0000000000003D30ull;
6704 #define CVMX_NPEI_MSI_W1S_ENB1 CVMX_NPEI_MSI_W1S_ENB1_FUNC()
6705 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB1_FUNC(void)
6707 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6708 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6709 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
6711 return 0x0000000000003D40ull;
6714 #define CVMX_NPEI_MSI_W1S_ENB2 CVMX_NPEI_MSI_W1S_ENB2_FUNC()
6715 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB2_FUNC(void)
6717 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6718 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6719 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
6721 return 0x0000000000003D50ull;
6724 #define CVMX_NPEI_MSI_W1S_ENB3 CVMX_NPEI_MSI_W1S_ENB3_FUNC()
6725 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB3_FUNC(void)
6727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6728 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6729 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
6731 return 0x0000000000003D60ull;
6734 #define CVMX_NPEI_MSI_WR_MAP CVMX_NPEI_MSI_WR_MAP_FUNC()
6735 static inline uint64_t CVMX_NPEI_MSI_WR_MAP_FUNC(void)
6737 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6738 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6739 cvmx_warn("CVMX_NPEI_MSI_WR_MAP not supported on this chip\n");
6741 return 0x0000000000003C90ull;
6744 #define CVMX_NPEI_PCIE_CREDIT_CNT CVMX_NPEI_PCIE_CREDIT_CNT_FUNC()
6745 static inline uint64_t CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void)
6747 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6748 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6749 cvmx_warn("CVMX_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
6751 return 0x0000000000003D70ull;
6754 #define CVMX_NPEI_PCIE_MSI_RCV CVMX_NPEI_PCIE_MSI_RCV_FUNC()
6755 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_FUNC(void)
6757 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6758 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6759 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV not supported on this chip\n");
6761 return 0x0000000000003CB0ull;
6764 #define CVMX_NPEI_PCIE_MSI_RCV_B1 CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC()
6765 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
6767 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6768 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6769 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
6771 return 0x0000000000000650ull;
6774 #define CVMX_NPEI_PCIE_MSI_RCV_B2 CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC()
6775 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
6777 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6778 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6779 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
6781 return 0x0000000000000660ull;
6784 #define CVMX_NPEI_PCIE_MSI_RCV_B3 CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC()
6785 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
6787 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6788 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6789 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
6791 return 0x0000000000000670ull;
6794 static inline uint64_t CVMX_NPEI_PKTX_CNTS(unsigned long offset)
6796 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6798 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6799 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6800 cvmx_warn("CVMX_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
6802 return 0x0000000000002400ull + (offset&31)*16;
6805 static inline uint64_t CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
6807 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6809 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6810 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6811 cvmx_warn("CVMX_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
6813 return 0x0000000000002800ull + (offset&31)*16;
6816 static inline uint64_t CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
6818 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6820 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6821 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6822 cvmx_warn("CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
6824 return 0x0000000000002C00ull + (offset&31)*16;
6827 static inline uint64_t CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
6829 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6831 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6832 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6833 cvmx_warn("CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
6835 return 0x0000000000003000ull + (offset&31)*16;
6838 static inline uint64_t CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
6840 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6842 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6843 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6844 cvmx_warn("CVMX_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
6846 return 0x0000000000003400ull + (offset&31)*16;
6849 static inline uint64_t CVMX_NPEI_PKTX_IN_BP(unsigned long offset)
6851 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6853 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6854 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6855 cvmx_warn("CVMX_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
6857 return 0x0000000000003800ull + (offset&31)*16;
6860 static inline uint64_t CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
6862 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6864 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6865 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6866 cvmx_warn("CVMX_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
6868 return 0x0000000000001400ull + (offset&31)*16;
6871 static inline uint64_t CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
6873 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6875 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6876 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6877 cvmx_warn("CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
6879 return 0x0000000000001800ull + (offset&31)*16;
6882 static inline uint64_t CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
6884 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6886 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
6887 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
6888 cvmx_warn("CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
6890 return 0x0000000000001C00ull + (offset&31)*16;
6893 #define CVMX_NPEI_PKT_CNT_INT CVMX_NPEI_PKT_CNT_INT_FUNC()
6894 static inline uint64_t CVMX_NPEI_PKT_CNT_INT_FUNC(void)
6896 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6897 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6898 cvmx_warn("CVMX_NPEI_PKT_CNT_INT not supported on this chip\n");
6900 return 0x0000000000001110ull;
6903 #define CVMX_NPEI_PKT_CNT_INT_ENB CVMX_NPEI_PKT_CNT_INT_ENB_FUNC()
6904 static inline uint64_t CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void)
6906 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6907 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6908 cvmx_warn("CVMX_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
6910 return 0x0000000000001130ull;
6913 #define CVMX_NPEI_PKT_DATA_OUT_ES CVMX_NPEI_PKT_DATA_OUT_ES_FUNC()
6914 static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void)
6916 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6917 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6918 cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
6920 return 0x00000000000010B0ull;
6923 #define CVMX_NPEI_PKT_DATA_OUT_NS CVMX_NPEI_PKT_DATA_OUT_NS_FUNC()
6924 static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void)
6926 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6927 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6928 cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
6930 return 0x00000000000010A0ull;
6933 #define CVMX_NPEI_PKT_DATA_OUT_ROR CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC()
6934 static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
6936 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6937 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6938 cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
6940 return 0x0000000000001090ull;
6943 #define CVMX_NPEI_PKT_DPADDR CVMX_NPEI_PKT_DPADDR_FUNC()
6944 static inline uint64_t CVMX_NPEI_PKT_DPADDR_FUNC(void)
6946 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6947 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6948 cvmx_warn("CVMX_NPEI_PKT_DPADDR not supported on this chip\n");
6950 return 0x0000000000001080ull;
6953 #define CVMX_NPEI_PKT_INPUT_CONTROL CVMX_NPEI_PKT_INPUT_CONTROL_FUNC()
6954 static inline uint64_t CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void)
6956 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6957 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6958 cvmx_warn("CVMX_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
6960 return 0x0000000000001150ull;
6963 #define CVMX_NPEI_PKT_INSTR_ENB CVMX_NPEI_PKT_INSTR_ENB_FUNC()
6964 static inline uint64_t CVMX_NPEI_PKT_INSTR_ENB_FUNC(void)
6966 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6967 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6968 cvmx_warn("CVMX_NPEI_PKT_INSTR_ENB not supported on this chip\n");
6970 return 0x0000000000001000ull;
6973 #define CVMX_NPEI_PKT_INSTR_RD_SIZE CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC()
6974 static inline uint64_t CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
6976 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6977 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6978 cvmx_warn("CVMX_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
6980 return 0x0000000000001190ull;
6983 #define CVMX_NPEI_PKT_INSTR_SIZE CVMX_NPEI_PKT_INSTR_SIZE_FUNC()
6984 static inline uint64_t CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void)
6986 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6987 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6988 cvmx_warn("CVMX_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
6990 return 0x0000000000001020ull;
6993 #define CVMX_NPEI_PKT_INT_LEVELS CVMX_NPEI_PKT_INT_LEVELS_FUNC()
6994 static inline uint64_t CVMX_NPEI_PKT_INT_LEVELS_FUNC(void)
6996 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6997 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
6998 cvmx_warn("CVMX_NPEI_PKT_INT_LEVELS not supported on this chip\n");
7000 return 0x0000000000001100ull;
7003 #define CVMX_NPEI_PKT_IN_BP CVMX_NPEI_PKT_IN_BP_FUNC()
7004 static inline uint64_t CVMX_NPEI_PKT_IN_BP_FUNC(void)
7006 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7007 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7008 cvmx_warn("CVMX_NPEI_PKT_IN_BP not supported on this chip\n");
7010 return 0x00000000000006B0ull;
7013 static inline uint64_t CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
7015 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7017 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
7018 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
7019 cvmx_warn("CVMX_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
7021 return 0x0000000000002000ull + (offset&31)*16;
7024 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
7025 static inline uint64_t CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
7027 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7028 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7029 cvmx_warn("CVMX_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
7031 return 0x00000000000006A0ull;
7034 #define CVMX_NPEI_PKT_IN_PCIE_PORT CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC()
7035 static inline uint64_t CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
7037 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7038 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7039 cvmx_warn("CVMX_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
7041 return 0x00000000000011A0ull;
7044 #define CVMX_NPEI_PKT_IPTR CVMX_NPEI_PKT_IPTR_FUNC()
7045 static inline uint64_t CVMX_NPEI_PKT_IPTR_FUNC(void)
7047 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7048 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7049 cvmx_warn("CVMX_NPEI_PKT_IPTR not supported on this chip\n");
7051 return 0x0000000000001070ull;
7054 #define CVMX_NPEI_PKT_OUTPUT_WMARK CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC()
7055 static inline uint64_t CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
7057 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7058 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7059 cvmx_warn("CVMX_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
7061 return 0x0000000000001160ull;
7064 #define CVMX_NPEI_PKT_OUT_BMODE CVMX_NPEI_PKT_OUT_BMODE_FUNC()
7065 static inline uint64_t CVMX_NPEI_PKT_OUT_BMODE_FUNC(void)
7067 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7068 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7069 cvmx_warn("CVMX_NPEI_PKT_OUT_BMODE not supported on this chip\n");
7071 return 0x00000000000010D0ull;
7074 #define CVMX_NPEI_PKT_OUT_ENB CVMX_NPEI_PKT_OUT_ENB_FUNC()
7075 static inline uint64_t CVMX_NPEI_PKT_OUT_ENB_FUNC(void)
7077 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7078 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7079 cvmx_warn("CVMX_NPEI_PKT_OUT_ENB not supported on this chip\n");
7081 return 0x0000000000001010ull;
7084 #define CVMX_NPEI_PKT_PCIE_PORT CVMX_NPEI_PKT_PCIE_PORT_FUNC()
7085 static inline uint64_t CVMX_NPEI_PKT_PCIE_PORT_FUNC(void)
7087 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7088 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7089 cvmx_warn("CVMX_NPEI_PKT_PCIE_PORT not supported on this chip\n");
7091 return 0x00000000000010E0ull;
7094 #define CVMX_NPEI_PKT_PORT_IN_RST CVMX_NPEI_PKT_PORT_IN_RST_FUNC()
7095 static inline uint64_t CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void)
7097 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7098 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7099 cvmx_warn("CVMX_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
7101 return 0x0000000000000690ull;
7104 #define CVMX_NPEI_PKT_SLIST_ES CVMX_NPEI_PKT_SLIST_ES_FUNC()
7105 static inline uint64_t CVMX_NPEI_PKT_SLIST_ES_FUNC(void)
7107 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7108 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7109 cvmx_warn("CVMX_NPEI_PKT_SLIST_ES not supported on this chip\n");
7111 return 0x0000000000001050ull;
7114 #define CVMX_NPEI_PKT_SLIST_ID_SIZE CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC()
7115 static inline uint64_t CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
7117 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7118 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7119 cvmx_warn("CVMX_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
7121 return 0x0000000000001180ull;
7124 #define CVMX_NPEI_PKT_SLIST_NS CVMX_NPEI_PKT_SLIST_NS_FUNC()
7125 static inline uint64_t CVMX_NPEI_PKT_SLIST_NS_FUNC(void)
7127 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7128 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7129 cvmx_warn("CVMX_NPEI_PKT_SLIST_NS not supported on this chip\n");
7131 return 0x0000000000001040ull;
7134 #define CVMX_NPEI_PKT_SLIST_ROR CVMX_NPEI_PKT_SLIST_ROR_FUNC()
7135 static inline uint64_t CVMX_NPEI_PKT_SLIST_ROR_FUNC(void)
7137 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7138 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7139 cvmx_warn("CVMX_NPEI_PKT_SLIST_ROR not supported on this chip\n");
7141 return 0x0000000000001030ull;
7144 #define CVMX_NPEI_PKT_TIME_INT CVMX_NPEI_PKT_TIME_INT_FUNC()
7145 static inline uint64_t CVMX_NPEI_PKT_TIME_INT_FUNC(void)
7147 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7148 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7149 cvmx_warn("CVMX_NPEI_PKT_TIME_INT not supported on this chip\n");
7151 return 0x0000000000001120ull;
7154 #define CVMX_NPEI_PKT_TIME_INT_ENB CVMX_NPEI_PKT_TIME_INT_ENB_FUNC()
7155 static inline uint64_t CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void)
7157 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7158 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7159 cvmx_warn("CVMX_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
7161 return 0x0000000000001140ull;
7164 #define CVMX_NPEI_RSL_INT_BLOCKS CVMX_NPEI_RSL_INT_BLOCKS_FUNC()
7165 static inline uint64_t CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void)
7167 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7168 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7169 cvmx_warn("CVMX_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
7171 return 0x0000000000000520ull;
7174 #define CVMX_NPEI_SCRATCH_1 CVMX_NPEI_SCRATCH_1_FUNC()
7175 static inline uint64_t CVMX_NPEI_SCRATCH_1_FUNC(void)
7177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7178 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7179 cvmx_warn("CVMX_NPEI_SCRATCH_1 not supported on this chip\n");
7181 return 0x0000000000000270ull;
7184 #define CVMX_NPEI_STATE1 CVMX_NPEI_STATE1_FUNC()
7185 static inline uint64_t CVMX_NPEI_STATE1_FUNC(void)
7187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7188 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7189 cvmx_warn("CVMX_NPEI_STATE1 not supported on this chip\n");
7191 return 0x0000000000000620ull;
7194 #define CVMX_NPEI_STATE2 CVMX_NPEI_STATE2_FUNC()
7195 static inline uint64_t CVMX_NPEI_STATE2_FUNC(void)
7197 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7198 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7199 cvmx_warn("CVMX_NPEI_STATE2 not supported on this chip\n");
7201 return 0x0000000000000630ull;
7204 #define CVMX_NPEI_STATE3 CVMX_NPEI_STATE3_FUNC()
7205 static inline uint64_t CVMX_NPEI_STATE3_FUNC(void)
7207 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7208 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7209 cvmx_warn("CVMX_NPEI_STATE3 not supported on this chip\n");
7211 return 0x0000000000000640ull;
7214 #define CVMX_NPEI_WINDOW_CTL CVMX_NPEI_WINDOW_CTL_FUNC()
7215 static inline uint64_t CVMX_NPEI_WINDOW_CTL_FUNC(void)
7217 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7218 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7219 cvmx_warn("CVMX_NPEI_WINDOW_CTL not supported on this chip\n");
7221 return 0x0000000000000380ull;
7224 #define CVMX_NPEI_WIN_RD_ADDR CVMX_NPEI_WIN_RD_ADDR_FUNC()
7225 static inline uint64_t CVMX_NPEI_WIN_RD_ADDR_FUNC(void)
7227 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7228 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7229 cvmx_warn("CVMX_NPEI_WIN_RD_ADDR not supported on this chip\n");
7231 return 0x0000000000000210ull;
7234 #define CVMX_NPEI_WIN_RD_DATA CVMX_NPEI_WIN_RD_DATA_FUNC()
7235 static inline uint64_t CVMX_NPEI_WIN_RD_DATA_FUNC(void)
7237 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7238 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7239 cvmx_warn("CVMX_NPEI_WIN_RD_DATA not supported on this chip\n");
7241 return 0x0000000000000240ull;
7244 #define CVMX_NPEI_WIN_WR_ADDR CVMX_NPEI_WIN_WR_ADDR_FUNC()
7245 static inline uint64_t CVMX_NPEI_WIN_WR_ADDR_FUNC(void)
7247 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7248 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7249 cvmx_warn("CVMX_NPEI_WIN_WR_ADDR not supported on this chip\n");
7251 return 0x0000000000000200ull;
7254 #define CVMX_NPEI_WIN_WR_DATA CVMX_NPEI_WIN_WR_DATA_FUNC()
7255 static inline uint64_t CVMX_NPEI_WIN_WR_DATA_FUNC(void)
7257 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7258 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7259 cvmx_warn("CVMX_NPEI_WIN_WR_DATA not supported on this chip\n");
7261 return 0x0000000000000220ull;
7264 #define CVMX_NPEI_WIN_WR_MASK CVMX_NPEI_WIN_WR_MASK_FUNC()
7265 static inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void)
7267 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7268 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
7269 cvmx_warn("CVMX_NPEI_WIN_WR_MASK not supported on this chip\n");
7271 return 0x0000000000000230ull;
7274 #define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
7275 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
7276 #define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
7277 #define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
7278 static inline uint64_t CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset)
7280 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7282 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
7283 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
7284 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
7285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
7286 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
7287 cvmx_warn("CVMX_NPI_BASE_ADDR_INPUTX(%lu) is invalid on this chip\n", offset);
7289 return CVMX_ADD_IO_SEG(0x00011F0000000070ull) + (offset&3)*16;
7292 #define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
7293 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
7294 #define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
7295 #define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
7296 static inline uint64_t CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset)
7298 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7300 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
7301 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
7302 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
7303 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
7304 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
7305 cvmx_warn("CVMX_NPI_BASE_ADDR_OUTPUTX(%lu) is invalid on this chip\n", offset);
7307 return CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + (offset&3)*8;
7310 #define CVMX_NPI_BIST_STATUS CVMX_NPI_BIST_STATUS_FUNC()
7311 static inline uint64_t CVMX_NPI_BIST_STATUS_FUNC(void)
7313 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7314 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7315 cvmx_warn("CVMX_NPI_BIST_STATUS not supported on this chip\n");
7317 return CVMX_ADD_IO_SEG(0x00011F00000003F8ull);
7320 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
7321 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
7322 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
7323 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
7324 static inline uint64_t CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset)
7326 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7328 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
7329 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
7330 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
7331 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
7332 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
7333 cvmx_warn("CVMX_NPI_BUFF_SIZE_OUTPUTX(%lu) is invalid on this chip\n", offset);
7335 return CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + (offset&3)*8;
7338 #define CVMX_NPI_COMP_CTL CVMX_NPI_COMP_CTL_FUNC()
7339 static inline uint64_t CVMX_NPI_COMP_CTL_FUNC(void)
7341 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7342 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7343 cvmx_warn("CVMX_NPI_COMP_CTL not supported on this chip\n");
7345 return CVMX_ADD_IO_SEG(0x00011F0000000218ull);
7348 #define CVMX_NPI_CTL_STATUS CVMX_NPI_CTL_STATUS_FUNC()
7349 static inline uint64_t CVMX_NPI_CTL_STATUS_FUNC(void)
7351 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7352 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7353 cvmx_warn("CVMX_NPI_CTL_STATUS not supported on this chip\n");
7355 return CVMX_ADD_IO_SEG(0x00011F0000000010ull);
7358 #define CVMX_NPI_DBG_SELECT CVMX_NPI_DBG_SELECT_FUNC()
7359 static inline uint64_t CVMX_NPI_DBG_SELECT_FUNC(void)
7361 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7362 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7363 cvmx_warn("CVMX_NPI_DBG_SELECT not supported on this chip\n");
7365 return CVMX_ADD_IO_SEG(0x00011F0000000008ull);
7368 #define CVMX_NPI_DMA_CONTROL CVMX_NPI_DMA_CONTROL_FUNC()
7369 static inline uint64_t CVMX_NPI_DMA_CONTROL_FUNC(void)
7371 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7372 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7373 cvmx_warn("CVMX_NPI_DMA_CONTROL not supported on this chip\n");
7375 return CVMX_ADD_IO_SEG(0x00011F0000000128ull);
7378 #define CVMX_NPI_DMA_HIGHP_COUNTS CVMX_NPI_DMA_HIGHP_COUNTS_FUNC()
7379 static inline uint64_t CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void)
7381 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7382 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7383 cvmx_warn("CVMX_NPI_DMA_HIGHP_COUNTS not supported on this chip\n");
7385 return CVMX_ADD_IO_SEG(0x00011F0000000148ull);
7388 #define CVMX_NPI_DMA_HIGHP_NADDR CVMX_NPI_DMA_HIGHP_NADDR_FUNC()
7389 static inline uint64_t CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void)
7391 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7392 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7393 cvmx_warn("CVMX_NPI_DMA_HIGHP_NADDR not supported on this chip\n");
7395 return CVMX_ADD_IO_SEG(0x00011F0000000158ull);
7398 #define CVMX_NPI_DMA_LOWP_COUNTS CVMX_NPI_DMA_LOWP_COUNTS_FUNC()
7399 static inline uint64_t CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void)
7401 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7402 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7403 cvmx_warn("CVMX_NPI_DMA_LOWP_COUNTS not supported on this chip\n");
7405 return CVMX_ADD_IO_SEG(0x00011F0000000140ull);
7408 #define CVMX_NPI_DMA_LOWP_NADDR CVMX_NPI_DMA_LOWP_NADDR_FUNC()
7409 static inline uint64_t CVMX_NPI_DMA_LOWP_NADDR_FUNC(void)
7411 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7412 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7413 cvmx_warn("CVMX_NPI_DMA_LOWP_NADDR not supported on this chip\n");
7415 return CVMX_ADD_IO_SEG(0x00011F0000000150ull);
7418 #define CVMX_NPI_HIGHP_DBELL CVMX_NPI_HIGHP_DBELL_FUNC()
7419 static inline uint64_t CVMX_NPI_HIGHP_DBELL_FUNC(void)
7421 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7422 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7423 cvmx_warn("CVMX_NPI_HIGHP_DBELL not supported on this chip\n");
7425 return CVMX_ADD_IO_SEG(0x00011F0000000120ull);
7428 #define CVMX_NPI_HIGHP_IBUFF_SADDR CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC()
7429 static inline uint64_t CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void)
7431 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7432 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7433 cvmx_warn("CVMX_NPI_HIGHP_IBUFF_SADDR not supported on this chip\n");
7435 return CVMX_ADD_IO_SEG(0x00011F0000000110ull);
7438 #define CVMX_NPI_INPUT_CONTROL CVMX_NPI_INPUT_CONTROL_FUNC()
7439 static inline uint64_t CVMX_NPI_INPUT_CONTROL_FUNC(void)
7441 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7442 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7443 cvmx_warn("CVMX_NPI_INPUT_CONTROL not supported on this chip\n");
7445 return CVMX_ADD_IO_SEG(0x00011F0000000138ull);
7448 #define CVMX_NPI_INT_ENB CVMX_NPI_INT_ENB_FUNC()
7449 static inline uint64_t CVMX_NPI_INT_ENB_FUNC(void)
7451 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7452 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7453 cvmx_warn("CVMX_NPI_INT_ENB not supported on this chip\n");
7455 return CVMX_ADD_IO_SEG(0x00011F0000000020ull);
7458 #define CVMX_NPI_INT_SUM CVMX_NPI_INT_SUM_FUNC()
7459 static inline uint64_t CVMX_NPI_INT_SUM_FUNC(void)
7461 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7462 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7463 cvmx_warn("CVMX_NPI_INT_SUM not supported on this chip\n");
7465 return CVMX_ADD_IO_SEG(0x00011F0000000018ull);
7468 #define CVMX_NPI_LOWP_DBELL CVMX_NPI_LOWP_DBELL_FUNC()
7469 static inline uint64_t CVMX_NPI_LOWP_DBELL_FUNC(void)
7471 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7472 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7473 cvmx_warn("CVMX_NPI_LOWP_DBELL not supported on this chip\n");
7475 return CVMX_ADD_IO_SEG(0x00011F0000000118ull);
7478 #define CVMX_NPI_LOWP_IBUFF_SADDR CVMX_NPI_LOWP_IBUFF_SADDR_FUNC()
7479 static inline uint64_t CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void)
7481 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7482 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7483 cvmx_warn("CVMX_NPI_LOWP_IBUFF_SADDR not supported on this chip\n");
7485 return CVMX_ADD_IO_SEG(0x00011F0000000108ull);
7488 #define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
7489 #define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
7490 #define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
7491 #define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
7492 static inline uint64_t CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset)
7494 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7496 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 3) && (offset <= 6)))) ||
7497 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 3) && (offset <= 6)))) ||
7498 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 3) && (offset <= 6)))) ||
7499 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 3) && (offset <= 6)))) ||
7500 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 3) && (offset <= 6))))))
7501 cvmx_warn("CVMX_NPI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
7503 return CVMX_ADD_IO_SEG(0x00011F0000000028ull) + (offset&7)*8 - 8*3;
7506 #define CVMX_NPI_MSI_RCV CVMX_NPI_MSI_RCV_FUNC()
7507 static inline uint64_t CVMX_NPI_MSI_RCV_FUNC(void)
7509 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7510 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7511 cvmx_warn("CVMX_NPI_MSI_RCV not supported on this chip\n");
7513 return 0x0000000000000190ull;
7516 #define CVMX_NPI_NPI_MSI_RCV CVMX_NPI_NPI_MSI_RCV_FUNC()
7517 static inline uint64_t CVMX_NPI_NPI_MSI_RCV_FUNC(void)
7519 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7520 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7521 cvmx_warn("CVMX_NPI_NPI_MSI_RCV not supported on this chip\n");
7523 return CVMX_ADD_IO_SEG(0x00011F0000001190ull);
7526 #define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
7527 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
7528 #define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
7529 #define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
7530 static inline uint64_t CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset)
7532 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7534 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
7535 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
7536 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
7537 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
7538 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
7539 cvmx_warn("CVMX_NPI_NUM_DESC_OUTPUTX(%lu) is invalid on this chip\n", offset);
7541 return CVMX_ADD_IO_SEG(0x00011F0000000050ull) + (offset&3)*8;
7544 #define CVMX_NPI_OUTPUT_CONTROL CVMX_NPI_OUTPUT_CONTROL_FUNC()
7545 static inline uint64_t CVMX_NPI_OUTPUT_CONTROL_FUNC(void)
7547 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7548 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7549 cvmx_warn("CVMX_NPI_OUTPUT_CONTROL not supported on this chip\n");
7551 return CVMX_ADD_IO_SEG(0x00011F0000000100ull);
7554 #define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
7555 #define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
7556 #define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
7557 #define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
7558 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
7559 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
7560 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
7561 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
7562 #define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
7563 #define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
7564 #define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
7565 #define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
7566 #define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
7567 #define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
7568 #define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
7569 #define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
7570 static inline uint64_t CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset)
7572 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7574 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
7575 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
7576 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
7577 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
7578 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
7579 cvmx_warn("CVMX_NPI_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
7581 return CVMX_ADD_IO_SEG(0x00011F0000001100ull) + (offset&31)*4;
7584 #define CVMX_NPI_PCI_BIST_REG CVMX_NPI_PCI_BIST_REG_FUNC()
7585 static inline uint64_t CVMX_NPI_PCI_BIST_REG_FUNC(void)
7587 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7588 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
7589 cvmx_warn("CVMX_NPI_PCI_BIST_REG not supported on this chip\n");
7591 return CVMX_ADD_IO_SEG(0x00011F00000011C0ull);
7594 #define CVMX_NPI_PCI_BURST_SIZE CVMX_NPI_PCI_BURST_SIZE_FUNC()
7595 static inline uint64_t CVMX_NPI_PCI_BURST_SIZE_FUNC(void)
7597 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7598 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7599 cvmx_warn("CVMX_NPI_PCI_BURST_SIZE not supported on this chip\n");
7601 return CVMX_ADD_IO_SEG(0x00011F00000000D8ull);
7604 #define CVMX_NPI_PCI_CFG00 CVMX_NPI_PCI_CFG00_FUNC()
7605 static inline uint64_t CVMX_NPI_PCI_CFG00_FUNC(void)
7607 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7608 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7609 cvmx_warn("CVMX_NPI_PCI_CFG00 not supported on this chip\n");
7611 return CVMX_ADD_IO_SEG(0x00011F0000001800ull);
7614 #define CVMX_NPI_PCI_CFG01 CVMX_NPI_PCI_CFG01_FUNC()
7615 static inline uint64_t CVMX_NPI_PCI_CFG01_FUNC(void)
7617 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7618 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7619 cvmx_warn("CVMX_NPI_PCI_CFG01 not supported on this chip\n");
7621 return CVMX_ADD_IO_SEG(0x00011F0000001804ull);
7624 #define CVMX_NPI_PCI_CFG02 CVMX_NPI_PCI_CFG02_FUNC()
7625 static inline uint64_t CVMX_NPI_PCI_CFG02_FUNC(void)
7627 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7628 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7629 cvmx_warn("CVMX_NPI_PCI_CFG02 not supported on this chip\n");
7631 return CVMX_ADD_IO_SEG(0x00011F0000001808ull);
7634 #define CVMX_NPI_PCI_CFG03 CVMX_NPI_PCI_CFG03_FUNC()
7635 static inline uint64_t CVMX_NPI_PCI_CFG03_FUNC(void)
7637 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7638 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7639 cvmx_warn("CVMX_NPI_PCI_CFG03 not supported on this chip\n");
7641 return CVMX_ADD_IO_SEG(0x00011F000000180Cull);
7644 #define CVMX_NPI_PCI_CFG04 CVMX_NPI_PCI_CFG04_FUNC()
7645 static inline uint64_t CVMX_NPI_PCI_CFG04_FUNC(void)
7647 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7648 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7649 cvmx_warn("CVMX_NPI_PCI_CFG04 not supported on this chip\n");
7651 return CVMX_ADD_IO_SEG(0x00011F0000001810ull);
7654 #define CVMX_NPI_PCI_CFG05 CVMX_NPI_PCI_CFG05_FUNC()
7655 static inline uint64_t CVMX_NPI_PCI_CFG05_FUNC(void)
7657 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7658 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7659 cvmx_warn("CVMX_NPI_PCI_CFG05 not supported on this chip\n");
7661 return CVMX_ADD_IO_SEG(0x00011F0000001814ull);
7664 #define CVMX_NPI_PCI_CFG06 CVMX_NPI_PCI_CFG06_FUNC()
7665 static inline uint64_t CVMX_NPI_PCI_CFG06_FUNC(void)
7667 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7668 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7669 cvmx_warn("CVMX_NPI_PCI_CFG06 not supported on this chip\n");
7671 return CVMX_ADD_IO_SEG(0x00011F0000001818ull);
7674 #define CVMX_NPI_PCI_CFG07 CVMX_NPI_PCI_CFG07_FUNC()
7675 static inline uint64_t CVMX_NPI_PCI_CFG07_FUNC(void)
7677 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7678 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7679 cvmx_warn("CVMX_NPI_PCI_CFG07 not supported on this chip\n");
7681 return CVMX_ADD_IO_SEG(0x00011F000000181Cull);
7684 #define CVMX_NPI_PCI_CFG08 CVMX_NPI_PCI_CFG08_FUNC()
7685 static inline uint64_t CVMX_NPI_PCI_CFG08_FUNC(void)
7687 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7688 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7689 cvmx_warn("CVMX_NPI_PCI_CFG08 not supported on this chip\n");
7691 return CVMX_ADD_IO_SEG(0x00011F0000001820ull);
7694 #define CVMX_NPI_PCI_CFG09 CVMX_NPI_PCI_CFG09_FUNC()
7695 static inline uint64_t CVMX_NPI_PCI_CFG09_FUNC(void)
7697 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7698 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7699 cvmx_warn("CVMX_NPI_PCI_CFG09 not supported on this chip\n");
7701 return CVMX_ADD_IO_SEG(0x00011F0000001824ull);
7704 #define CVMX_NPI_PCI_CFG10 CVMX_NPI_PCI_CFG10_FUNC()
7705 static inline uint64_t CVMX_NPI_PCI_CFG10_FUNC(void)
7707 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7708 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7709 cvmx_warn("CVMX_NPI_PCI_CFG10 not supported on this chip\n");
7711 return CVMX_ADD_IO_SEG(0x00011F0000001828ull);
7714 #define CVMX_NPI_PCI_CFG11 CVMX_NPI_PCI_CFG11_FUNC()
7715 static inline uint64_t CVMX_NPI_PCI_CFG11_FUNC(void)
7717 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7718 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7719 cvmx_warn("CVMX_NPI_PCI_CFG11 not supported on this chip\n");
7721 return CVMX_ADD_IO_SEG(0x00011F000000182Cull);
7724 #define CVMX_NPI_PCI_CFG12 CVMX_NPI_PCI_CFG12_FUNC()
7725 static inline uint64_t CVMX_NPI_PCI_CFG12_FUNC(void)
7727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7728 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7729 cvmx_warn("CVMX_NPI_PCI_CFG12 not supported on this chip\n");
7731 return CVMX_ADD_IO_SEG(0x00011F0000001830ull);
7734 #define CVMX_NPI_PCI_CFG13 CVMX_NPI_PCI_CFG13_FUNC()
7735 static inline uint64_t CVMX_NPI_PCI_CFG13_FUNC(void)
7737 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7738 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7739 cvmx_warn("CVMX_NPI_PCI_CFG13 not supported on this chip\n");
7741 return CVMX_ADD_IO_SEG(0x00011F0000001834ull);
7744 #define CVMX_NPI_PCI_CFG15 CVMX_NPI_PCI_CFG15_FUNC()
7745 static inline uint64_t CVMX_NPI_PCI_CFG15_FUNC(void)
7747 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7748 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7749 cvmx_warn("CVMX_NPI_PCI_CFG15 not supported on this chip\n");
7751 return CVMX_ADD_IO_SEG(0x00011F000000183Cull);
7754 #define CVMX_NPI_PCI_CFG16 CVMX_NPI_PCI_CFG16_FUNC()
7755 static inline uint64_t CVMX_NPI_PCI_CFG16_FUNC(void)
7757 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7758 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7759 cvmx_warn("CVMX_NPI_PCI_CFG16 not supported on this chip\n");
7761 return CVMX_ADD_IO_SEG(0x00011F0000001840ull);
7764 #define CVMX_NPI_PCI_CFG17 CVMX_NPI_PCI_CFG17_FUNC()
7765 static inline uint64_t CVMX_NPI_PCI_CFG17_FUNC(void)
7767 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7768 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7769 cvmx_warn("CVMX_NPI_PCI_CFG17 not supported on this chip\n");
7771 return CVMX_ADD_IO_SEG(0x00011F0000001844ull);
7774 #define CVMX_NPI_PCI_CFG18 CVMX_NPI_PCI_CFG18_FUNC()
7775 static inline uint64_t CVMX_NPI_PCI_CFG18_FUNC(void)
7777 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7778 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7779 cvmx_warn("CVMX_NPI_PCI_CFG18 not supported on this chip\n");
7781 return CVMX_ADD_IO_SEG(0x00011F0000001848ull);
7784 #define CVMX_NPI_PCI_CFG19 CVMX_NPI_PCI_CFG19_FUNC()
7785 static inline uint64_t CVMX_NPI_PCI_CFG19_FUNC(void)
7787 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7788 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7789 cvmx_warn("CVMX_NPI_PCI_CFG19 not supported on this chip\n");
7791 return CVMX_ADD_IO_SEG(0x00011F000000184Cull);
7794 #define CVMX_NPI_PCI_CFG20 CVMX_NPI_PCI_CFG20_FUNC()
7795 static inline uint64_t CVMX_NPI_PCI_CFG20_FUNC(void)
7797 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7798 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7799 cvmx_warn("CVMX_NPI_PCI_CFG20 not supported on this chip\n");
7801 return CVMX_ADD_IO_SEG(0x00011F0000001850ull);
7804 #define CVMX_NPI_PCI_CFG21 CVMX_NPI_PCI_CFG21_FUNC()
7805 static inline uint64_t CVMX_NPI_PCI_CFG21_FUNC(void)
7807 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7808 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7809 cvmx_warn("CVMX_NPI_PCI_CFG21 not supported on this chip\n");
7811 return CVMX_ADD_IO_SEG(0x00011F0000001854ull);
7814 #define CVMX_NPI_PCI_CFG22 CVMX_NPI_PCI_CFG22_FUNC()
7815 static inline uint64_t CVMX_NPI_PCI_CFG22_FUNC(void)
7817 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7818 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7819 cvmx_warn("CVMX_NPI_PCI_CFG22 not supported on this chip\n");
7821 return CVMX_ADD_IO_SEG(0x00011F0000001858ull);
7824 #define CVMX_NPI_PCI_CFG56 CVMX_NPI_PCI_CFG56_FUNC()
7825 static inline uint64_t CVMX_NPI_PCI_CFG56_FUNC(void)
7827 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7828 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7829 cvmx_warn("CVMX_NPI_PCI_CFG56 not supported on this chip\n");
7831 return CVMX_ADD_IO_SEG(0x00011F00000018E0ull);
7834 #define CVMX_NPI_PCI_CFG57 CVMX_NPI_PCI_CFG57_FUNC()
7835 static inline uint64_t CVMX_NPI_PCI_CFG57_FUNC(void)
7837 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7838 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7839 cvmx_warn("CVMX_NPI_PCI_CFG57 not supported on this chip\n");
7841 return CVMX_ADD_IO_SEG(0x00011F00000018E4ull);
7844 #define CVMX_NPI_PCI_CFG58 CVMX_NPI_PCI_CFG58_FUNC()
7845 static inline uint64_t CVMX_NPI_PCI_CFG58_FUNC(void)
7847 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7848 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7849 cvmx_warn("CVMX_NPI_PCI_CFG58 not supported on this chip\n");
7851 return CVMX_ADD_IO_SEG(0x00011F00000018E8ull);
7854 #define CVMX_NPI_PCI_CFG59 CVMX_NPI_PCI_CFG59_FUNC()
7855 static inline uint64_t CVMX_NPI_PCI_CFG59_FUNC(void)
7857 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7858 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7859 cvmx_warn("CVMX_NPI_PCI_CFG59 not supported on this chip\n");
7861 return CVMX_ADD_IO_SEG(0x00011F00000018ECull);
7864 #define CVMX_NPI_PCI_CFG60 CVMX_NPI_PCI_CFG60_FUNC()
7865 static inline uint64_t CVMX_NPI_PCI_CFG60_FUNC(void)
7867 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7868 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7869 cvmx_warn("CVMX_NPI_PCI_CFG60 not supported on this chip\n");
7871 return CVMX_ADD_IO_SEG(0x00011F00000018F0ull);
7874 #define CVMX_NPI_PCI_CFG61 CVMX_NPI_PCI_CFG61_FUNC()
7875 static inline uint64_t CVMX_NPI_PCI_CFG61_FUNC(void)
7877 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7878 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7879 cvmx_warn("CVMX_NPI_PCI_CFG61 not supported on this chip\n");
7881 return CVMX_ADD_IO_SEG(0x00011F00000018F4ull);
7884 #define CVMX_NPI_PCI_CFG62 CVMX_NPI_PCI_CFG62_FUNC()
7885 static inline uint64_t CVMX_NPI_PCI_CFG62_FUNC(void)
7887 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7888 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7889 cvmx_warn("CVMX_NPI_PCI_CFG62 not supported on this chip\n");
7891 return CVMX_ADD_IO_SEG(0x00011F00000018F8ull);
7894 #define CVMX_NPI_PCI_CFG63 CVMX_NPI_PCI_CFG63_FUNC()
7895 static inline uint64_t CVMX_NPI_PCI_CFG63_FUNC(void)
7897 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7898 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7899 cvmx_warn("CVMX_NPI_PCI_CFG63 not supported on this chip\n");
7901 return CVMX_ADD_IO_SEG(0x00011F00000018FCull);
7904 #define CVMX_NPI_PCI_CNT_REG CVMX_NPI_PCI_CNT_REG_FUNC()
7905 static inline uint64_t CVMX_NPI_PCI_CNT_REG_FUNC(void)
7907 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7908 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7909 cvmx_warn("CVMX_NPI_PCI_CNT_REG not supported on this chip\n");
7911 return CVMX_ADD_IO_SEG(0x00011F00000011B8ull);
7914 #define CVMX_NPI_PCI_CTL_STATUS_2 CVMX_NPI_PCI_CTL_STATUS_2_FUNC()
7915 static inline uint64_t CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void)
7917 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7918 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7919 cvmx_warn("CVMX_NPI_PCI_CTL_STATUS_2 not supported on this chip\n");
7921 return CVMX_ADD_IO_SEG(0x00011F000000118Cull);
7924 #define CVMX_NPI_PCI_INT_ARB_CFG CVMX_NPI_PCI_INT_ARB_CFG_FUNC()
7925 static inline uint64_t CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void)
7927 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7928 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7929 cvmx_warn("CVMX_NPI_PCI_INT_ARB_CFG not supported on this chip\n");
7931 return CVMX_ADD_IO_SEG(0x00011F0000000130ull);
7934 #define CVMX_NPI_PCI_INT_ENB2 CVMX_NPI_PCI_INT_ENB2_FUNC()
7935 static inline uint64_t CVMX_NPI_PCI_INT_ENB2_FUNC(void)
7937 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7938 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7939 cvmx_warn("CVMX_NPI_PCI_INT_ENB2 not supported on this chip\n");
7941 return CVMX_ADD_IO_SEG(0x00011F00000011A0ull);
7944 #define CVMX_NPI_PCI_INT_SUM2 CVMX_NPI_PCI_INT_SUM2_FUNC()
7945 static inline uint64_t CVMX_NPI_PCI_INT_SUM2_FUNC(void)
7947 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7948 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7949 cvmx_warn("CVMX_NPI_PCI_INT_SUM2 not supported on this chip\n");
7951 return CVMX_ADD_IO_SEG(0x00011F0000001198ull);
7954 #define CVMX_NPI_PCI_READ_CMD CVMX_NPI_PCI_READ_CMD_FUNC()
7955 static inline uint64_t CVMX_NPI_PCI_READ_CMD_FUNC(void)
7957 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7958 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7959 cvmx_warn("CVMX_NPI_PCI_READ_CMD not supported on this chip\n");
7961 return CVMX_ADD_IO_SEG(0x00011F0000000048ull);
7964 #define CVMX_NPI_PCI_READ_CMD_6 CVMX_NPI_PCI_READ_CMD_6_FUNC()
7965 static inline uint64_t CVMX_NPI_PCI_READ_CMD_6_FUNC(void)
7967 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7968 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7969 cvmx_warn("CVMX_NPI_PCI_READ_CMD_6 not supported on this chip\n");
7971 return CVMX_ADD_IO_SEG(0x00011F0000001180ull);
7974 #define CVMX_NPI_PCI_READ_CMD_C CVMX_NPI_PCI_READ_CMD_C_FUNC()
7975 static inline uint64_t CVMX_NPI_PCI_READ_CMD_C_FUNC(void)
7977 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7978 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7979 cvmx_warn("CVMX_NPI_PCI_READ_CMD_C not supported on this chip\n");
7981 return CVMX_ADD_IO_SEG(0x00011F0000001184ull);
7984 #define CVMX_NPI_PCI_READ_CMD_E CVMX_NPI_PCI_READ_CMD_E_FUNC()
7985 static inline uint64_t CVMX_NPI_PCI_READ_CMD_E_FUNC(void)
7987 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7988 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7989 cvmx_warn("CVMX_NPI_PCI_READ_CMD_E not supported on this chip\n");
7991 return CVMX_ADD_IO_SEG(0x00011F0000001188ull);
7994 #define CVMX_NPI_PCI_SCM_REG CVMX_NPI_PCI_SCM_REG_FUNC()
7995 static inline uint64_t CVMX_NPI_PCI_SCM_REG_FUNC(void)
7997 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
7998 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
7999 cvmx_warn("CVMX_NPI_PCI_SCM_REG not supported on this chip\n");
8001 return CVMX_ADD_IO_SEG(0x00011F00000011A8ull);
8004 #define CVMX_NPI_PCI_TSR_REG CVMX_NPI_PCI_TSR_REG_FUNC()
8005 static inline uint64_t CVMX_NPI_PCI_TSR_REG_FUNC(void)
8007 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8008 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
8009 cvmx_warn("CVMX_NPI_PCI_TSR_REG not supported on this chip\n");
8011 return CVMX_ADD_IO_SEG(0x00011F00000011B0ull);
8014 #define CVMX_NPI_PORT32_INSTR_HDR CVMX_NPI_PORT32_INSTR_HDR_FUNC()
8015 static inline uint64_t CVMX_NPI_PORT32_INSTR_HDR_FUNC(void)
8017 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8018 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
8019 cvmx_warn("CVMX_NPI_PORT32_INSTR_HDR not supported on this chip\n");
8021 return CVMX_ADD_IO_SEG(0x00011F00000001F8ull);
8024 #define CVMX_NPI_PORT33_INSTR_HDR CVMX_NPI_PORT33_INSTR_HDR_FUNC()
8025 static inline uint64_t CVMX_NPI_PORT33_INSTR_HDR_FUNC(void)
8027 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8028 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
8029 cvmx_warn("CVMX_NPI_PORT33_INSTR_HDR not supported on this chip\n");
8031 return CVMX_ADD_IO_SEG(0x00011F0000000200ull);
8034 #define CVMX_NPI_PORT34_INSTR_HDR CVMX_NPI_PORT34_INSTR_HDR_FUNC()
8035 static inline uint64_t CVMX_NPI_PORT34_INSTR_HDR_FUNC(void)
8037 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8038 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
8039 cvmx_warn("CVMX_NPI_PORT34_INSTR_HDR not supported on this chip\n");
8041 return CVMX_ADD_IO_SEG(0x00011F0000000208ull);
8044 #define CVMX_NPI_PORT35_INSTR_HDR CVMX_NPI_PORT35_INSTR_HDR_FUNC()
8045 static inline uint64_t CVMX_NPI_PORT35_INSTR_HDR_FUNC(void)
8047 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8048 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
8049 cvmx_warn("CVMX_NPI_PORT35_INSTR_HDR not supported on this chip\n");
8051 return CVMX_ADD_IO_SEG(0x00011F0000000210ull);
8054 #define CVMX_NPI_PORT_BP_CONTROL CVMX_NPI_PORT_BP_CONTROL_FUNC()
8055 static inline uint64_t CVMX_NPI_PORT_BP_CONTROL_FUNC(void)
8057 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8058 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
8059 cvmx_warn("CVMX_NPI_PORT_BP_CONTROL not supported on this chip\n");
8061 return CVMX_ADD_IO_SEG(0x00011F00000001F0ull);
8064 static inline uint64_t CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset)
8066 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8068 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
8069 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
8070 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
8071 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
8072 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
8073 cvmx_warn("CVMX_NPI_PX_DBPAIR_ADDR(%lu) is invalid on this chip\n", offset);
8075 return CVMX_ADD_IO_SEG(0x00011F0000000180ull) + (offset&3)*8;
8078 static inline uint64_t CVMX_NPI_PX_INSTR_ADDR(unsigned long offset)
8080 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8082 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
8083 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
8084 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
8085 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
8086 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
8087 cvmx_warn("CVMX_NPI_PX_INSTR_ADDR(%lu) is invalid on this chip\n", offset);
8089 return CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + (offset&3)*8;
8092 static inline uint64_t CVMX_NPI_PX_INSTR_CNTS(unsigned long offset)
8094 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8096 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
8097 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
8098 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
8099 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
8100 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
8101 cvmx_warn("CVMX_NPI_PX_INSTR_CNTS(%lu) is invalid on this chip\n", offset);
8103 return CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + (offset&3)*8;
8106 static inline uint64_t CVMX_NPI_PX_PAIR_CNTS(unsigned long offset)
8108 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8110 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
8111 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
8112 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
8113 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
8114 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
8115 cvmx_warn("CVMX_NPI_PX_PAIR_CNTS(%lu) is invalid on this chip\n", offset);
8117 return CVMX_ADD_IO_SEG(0x00011F0000000160ull) + (offset&3)*8;
8120 #define CVMX_NPI_RSL_INT_BLOCKS CVMX_NPI_RSL_INT_BLOCKS_FUNC()
8121 static inline uint64_t CVMX_NPI_RSL_INT_BLOCKS_FUNC(void)
8123 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8124 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
8125 cvmx_warn("CVMX_NPI_RSL_INT_BLOCKS not supported on this chip\n");
8127 return CVMX_ADD_IO_SEG(0x00011F0000000000ull);
8130 #define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
8131 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
8132 #define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
8133 #define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
8134 static inline uint64_t CVMX_NPI_SIZE_INPUTX(unsigned long offset)
8136 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8138 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
8139 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
8140 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
8141 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
8142 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
8143 cvmx_warn("CVMX_NPI_SIZE_INPUTX(%lu) is invalid on this chip\n", offset);
8145 return CVMX_ADD_IO_SEG(0x00011F0000000078ull) + (offset&3)*16;
8148 #define CVMX_NPI_WIN_READ_TO CVMX_NPI_WIN_READ_TO_FUNC()
8149 static inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void)
8151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8152 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
8153 cvmx_warn("CVMX_NPI_WIN_READ_TO not supported on this chip\n");
8155 return CVMX_ADD_IO_SEG(0x00011F00000001E0ull);
8158 #define CVMX_PCIEEP_CFG000 CVMX_PCIEEP_CFG000_FUNC()
8159 static inline uint64_t CVMX_PCIEEP_CFG000_FUNC(void)
8161 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8162 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8163 cvmx_warn("CVMX_PCIEEP_CFG000 not supported on this chip\n");
8165 return 0x0000000000000000ull;
8168 #define CVMX_PCIEEP_CFG001 CVMX_PCIEEP_CFG001_FUNC()
8169 static inline uint64_t CVMX_PCIEEP_CFG001_FUNC(void)
8171 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8172 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8173 cvmx_warn("CVMX_PCIEEP_CFG001 not supported on this chip\n");
8175 return 0x0000000000000004ull;
8178 #define CVMX_PCIEEP_CFG002 CVMX_PCIEEP_CFG002_FUNC()
8179 static inline uint64_t CVMX_PCIEEP_CFG002_FUNC(void)
8181 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8182 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8183 cvmx_warn("CVMX_PCIEEP_CFG002 not supported on this chip\n");
8185 return 0x0000000000000008ull;
8188 #define CVMX_PCIEEP_CFG003 CVMX_PCIEEP_CFG003_FUNC()
8189 static inline uint64_t CVMX_PCIEEP_CFG003_FUNC(void)
8191 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8192 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8193 cvmx_warn("CVMX_PCIEEP_CFG003 not supported on this chip\n");
8195 return 0x000000000000000Cull;
8198 #define CVMX_PCIEEP_CFG004 CVMX_PCIEEP_CFG004_FUNC()
8199 static inline uint64_t CVMX_PCIEEP_CFG004_FUNC(void)
8201 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8202 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8203 cvmx_warn("CVMX_PCIEEP_CFG004 not supported on this chip\n");
8205 return 0x0000000000000010ull;
8208 #define CVMX_PCIEEP_CFG004_MASK CVMX_PCIEEP_CFG004_MASK_FUNC()
8209 static inline uint64_t CVMX_PCIEEP_CFG004_MASK_FUNC(void)
8211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8212 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8213 cvmx_warn("CVMX_PCIEEP_CFG004_MASK not supported on this chip\n");
8215 return 0x0000000080000010ull;
8218 #define CVMX_PCIEEP_CFG005 CVMX_PCIEEP_CFG005_FUNC()
8219 static inline uint64_t CVMX_PCIEEP_CFG005_FUNC(void)
8221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8222 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8223 cvmx_warn("CVMX_PCIEEP_CFG005 not supported on this chip\n");
8225 return 0x0000000000000014ull;
8228 #define CVMX_PCIEEP_CFG005_MASK CVMX_PCIEEP_CFG005_MASK_FUNC()
8229 static inline uint64_t CVMX_PCIEEP_CFG005_MASK_FUNC(void)
8231 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8232 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8233 cvmx_warn("CVMX_PCIEEP_CFG005_MASK not supported on this chip\n");
8235 return 0x0000000080000014ull;
8238 #define CVMX_PCIEEP_CFG006 CVMX_PCIEEP_CFG006_FUNC()
8239 static inline uint64_t CVMX_PCIEEP_CFG006_FUNC(void)
8241 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8242 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8243 cvmx_warn("CVMX_PCIEEP_CFG006 not supported on this chip\n");
8245 return 0x0000000000000018ull;
8248 #define CVMX_PCIEEP_CFG006_MASK CVMX_PCIEEP_CFG006_MASK_FUNC()
8249 static inline uint64_t CVMX_PCIEEP_CFG006_MASK_FUNC(void)
8251 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8252 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8253 cvmx_warn("CVMX_PCIEEP_CFG006_MASK not supported on this chip\n");
8255 return 0x0000000080000018ull;
8258 #define CVMX_PCIEEP_CFG007 CVMX_PCIEEP_CFG007_FUNC()
8259 static inline uint64_t CVMX_PCIEEP_CFG007_FUNC(void)
8261 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8262 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8263 cvmx_warn("CVMX_PCIEEP_CFG007 not supported on this chip\n");
8265 return 0x000000000000001Cull;
8268 #define CVMX_PCIEEP_CFG007_MASK CVMX_PCIEEP_CFG007_MASK_FUNC()
8269 static inline uint64_t CVMX_PCIEEP_CFG007_MASK_FUNC(void)
8271 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8272 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8273 cvmx_warn("CVMX_PCIEEP_CFG007_MASK not supported on this chip\n");
8275 return 0x000000008000001Cull;
8278 #define CVMX_PCIEEP_CFG008 CVMX_PCIEEP_CFG008_FUNC()
8279 static inline uint64_t CVMX_PCIEEP_CFG008_FUNC(void)
8281 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8282 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8283 cvmx_warn("CVMX_PCIEEP_CFG008 not supported on this chip\n");
8285 return 0x0000000000000020ull;
8288 #define CVMX_PCIEEP_CFG008_MASK CVMX_PCIEEP_CFG008_MASK_FUNC()
8289 static inline uint64_t CVMX_PCIEEP_CFG008_MASK_FUNC(void)
8291 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8292 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8293 cvmx_warn("CVMX_PCIEEP_CFG008_MASK not supported on this chip\n");
8295 return 0x0000000080000020ull;
8298 #define CVMX_PCIEEP_CFG009 CVMX_PCIEEP_CFG009_FUNC()
8299 static inline uint64_t CVMX_PCIEEP_CFG009_FUNC(void)
8301 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8302 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8303 cvmx_warn("CVMX_PCIEEP_CFG009 not supported on this chip\n");
8305 return 0x0000000000000024ull;
8308 #define CVMX_PCIEEP_CFG009_MASK CVMX_PCIEEP_CFG009_MASK_FUNC()
8309 static inline uint64_t CVMX_PCIEEP_CFG009_MASK_FUNC(void)
8311 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8312 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8313 cvmx_warn("CVMX_PCIEEP_CFG009_MASK not supported on this chip\n");
8315 return 0x0000000080000024ull;
8318 #define CVMX_PCIEEP_CFG010 CVMX_PCIEEP_CFG010_FUNC()
8319 static inline uint64_t CVMX_PCIEEP_CFG010_FUNC(void)
8321 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8322 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8323 cvmx_warn("CVMX_PCIEEP_CFG010 not supported on this chip\n");
8325 return 0x0000000000000028ull;
8328 #define CVMX_PCIEEP_CFG011 CVMX_PCIEEP_CFG011_FUNC()
8329 static inline uint64_t CVMX_PCIEEP_CFG011_FUNC(void)
8331 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8332 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8333 cvmx_warn("CVMX_PCIEEP_CFG011 not supported on this chip\n");
8335 return 0x000000000000002Cull;
8338 #define CVMX_PCIEEP_CFG012 CVMX_PCIEEP_CFG012_FUNC()
8339 static inline uint64_t CVMX_PCIEEP_CFG012_FUNC(void)
8341 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8342 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8343 cvmx_warn("CVMX_PCIEEP_CFG012 not supported on this chip\n");
8345 return 0x0000000000000030ull;
8348 #define CVMX_PCIEEP_CFG012_MASK CVMX_PCIEEP_CFG012_MASK_FUNC()
8349 static inline uint64_t CVMX_PCIEEP_CFG012_MASK_FUNC(void)
8351 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8352 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8353 cvmx_warn("CVMX_PCIEEP_CFG012_MASK not supported on this chip\n");
8355 return 0x0000000080000030ull;
8358 #define CVMX_PCIEEP_CFG013 CVMX_PCIEEP_CFG013_FUNC()
8359 static inline uint64_t CVMX_PCIEEP_CFG013_FUNC(void)
8361 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8362 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8363 cvmx_warn("CVMX_PCIEEP_CFG013 not supported on this chip\n");
8365 return 0x0000000000000034ull;
8368 #define CVMX_PCIEEP_CFG015 CVMX_PCIEEP_CFG015_FUNC()
8369 static inline uint64_t CVMX_PCIEEP_CFG015_FUNC(void)
8371 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8372 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8373 cvmx_warn("CVMX_PCIEEP_CFG015 not supported on this chip\n");
8375 return 0x000000000000003Cull;
8378 #define CVMX_PCIEEP_CFG016 CVMX_PCIEEP_CFG016_FUNC()
8379 static inline uint64_t CVMX_PCIEEP_CFG016_FUNC(void)
8381 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8382 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8383 cvmx_warn("CVMX_PCIEEP_CFG016 not supported on this chip\n");
8385 return 0x0000000000000040ull;
8388 #define CVMX_PCIEEP_CFG017 CVMX_PCIEEP_CFG017_FUNC()
8389 static inline uint64_t CVMX_PCIEEP_CFG017_FUNC(void)
8391 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8392 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8393 cvmx_warn("CVMX_PCIEEP_CFG017 not supported on this chip\n");
8395 return 0x0000000000000044ull;
8398 #define CVMX_PCIEEP_CFG020 CVMX_PCIEEP_CFG020_FUNC()
8399 static inline uint64_t CVMX_PCIEEP_CFG020_FUNC(void)
8401 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8402 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8403 cvmx_warn("CVMX_PCIEEP_CFG020 not supported on this chip\n");
8405 return 0x0000000000000050ull;
8408 #define CVMX_PCIEEP_CFG021 CVMX_PCIEEP_CFG021_FUNC()
8409 static inline uint64_t CVMX_PCIEEP_CFG021_FUNC(void)
8411 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8412 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8413 cvmx_warn("CVMX_PCIEEP_CFG021 not supported on this chip\n");
8415 return 0x0000000000000054ull;
8418 #define CVMX_PCIEEP_CFG022 CVMX_PCIEEP_CFG022_FUNC()
8419 static inline uint64_t CVMX_PCIEEP_CFG022_FUNC(void)
8421 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8422 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8423 cvmx_warn("CVMX_PCIEEP_CFG022 not supported on this chip\n");
8425 return 0x0000000000000058ull;
8428 #define CVMX_PCIEEP_CFG023 CVMX_PCIEEP_CFG023_FUNC()
8429 static inline uint64_t CVMX_PCIEEP_CFG023_FUNC(void)
8431 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8432 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8433 cvmx_warn("CVMX_PCIEEP_CFG023 not supported on this chip\n");
8435 return 0x000000000000005Cull;
8438 #define CVMX_PCIEEP_CFG028 CVMX_PCIEEP_CFG028_FUNC()
8439 static inline uint64_t CVMX_PCIEEP_CFG028_FUNC(void)
8441 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8442 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8443 cvmx_warn("CVMX_PCIEEP_CFG028 not supported on this chip\n");
8445 return 0x0000000000000070ull;
8448 #define CVMX_PCIEEP_CFG029 CVMX_PCIEEP_CFG029_FUNC()
8449 static inline uint64_t CVMX_PCIEEP_CFG029_FUNC(void)
8451 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8452 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8453 cvmx_warn("CVMX_PCIEEP_CFG029 not supported on this chip\n");
8455 return 0x0000000000000074ull;
8458 #define CVMX_PCIEEP_CFG030 CVMX_PCIEEP_CFG030_FUNC()
8459 static inline uint64_t CVMX_PCIEEP_CFG030_FUNC(void)
8461 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8462 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8463 cvmx_warn("CVMX_PCIEEP_CFG030 not supported on this chip\n");
8465 return 0x0000000000000078ull;
8468 #define CVMX_PCIEEP_CFG031 CVMX_PCIEEP_CFG031_FUNC()
8469 static inline uint64_t CVMX_PCIEEP_CFG031_FUNC(void)
8471 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8472 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8473 cvmx_warn("CVMX_PCIEEP_CFG031 not supported on this chip\n");
8475 return 0x000000000000007Cull;
8478 #define CVMX_PCIEEP_CFG032 CVMX_PCIEEP_CFG032_FUNC()
8479 static inline uint64_t CVMX_PCIEEP_CFG032_FUNC(void)
8481 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8482 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8483 cvmx_warn("CVMX_PCIEEP_CFG032 not supported on this chip\n");
8485 return 0x0000000000000080ull;
8488 #define CVMX_PCIEEP_CFG033 CVMX_PCIEEP_CFG033_FUNC()
8489 static inline uint64_t CVMX_PCIEEP_CFG033_FUNC(void)
8491 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8492 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8493 cvmx_warn("CVMX_PCIEEP_CFG033 not supported on this chip\n");
8495 return 0x0000000000000084ull;
8498 #define CVMX_PCIEEP_CFG034 CVMX_PCIEEP_CFG034_FUNC()
8499 static inline uint64_t CVMX_PCIEEP_CFG034_FUNC(void)
8501 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8502 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8503 cvmx_warn("CVMX_PCIEEP_CFG034 not supported on this chip\n");
8505 return 0x0000000000000088ull;
8508 #define CVMX_PCIEEP_CFG037 CVMX_PCIEEP_CFG037_FUNC()
8509 static inline uint64_t CVMX_PCIEEP_CFG037_FUNC(void)
8511 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8512 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8513 cvmx_warn("CVMX_PCIEEP_CFG037 not supported on this chip\n");
8515 return 0x0000000000000094ull;
8518 #define CVMX_PCIEEP_CFG038 CVMX_PCIEEP_CFG038_FUNC()
8519 static inline uint64_t CVMX_PCIEEP_CFG038_FUNC(void)
8521 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8522 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8523 cvmx_warn("CVMX_PCIEEP_CFG038 not supported on this chip\n");
8525 return 0x0000000000000098ull;
8528 #define CVMX_PCIEEP_CFG039 CVMX_PCIEEP_CFG039_FUNC()
8529 static inline uint64_t CVMX_PCIEEP_CFG039_FUNC(void)
8531 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8532 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8533 cvmx_warn("CVMX_PCIEEP_CFG039 not supported on this chip\n");
8535 return 0x000000000000009Cull;
8538 #define CVMX_PCIEEP_CFG040 CVMX_PCIEEP_CFG040_FUNC()
8539 static inline uint64_t CVMX_PCIEEP_CFG040_FUNC(void)
8541 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8542 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8543 cvmx_warn("CVMX_PCIEEP_CFG040 not supported on this chip\n");
8545 return 0x00000000000000A0ull;
8548 #define CVMX_PCIEEP_CFG041 CVMX_PCIEEP_CFG041_FUNC()
8549 static inline uint64_t CVMX_PCIEEP_CFG041_FUNC(void)
8551 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8552 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8553 cvmx_warn("CVMX_PCIEEP_CFG041 not supported on this chip\n");
8555 return 0x00000000000000A4ull;
8558 #define CVMX_PCIEEP_CFG042 CVMX_PCIEEP_CFG042_FUNC()
8559 static inline uint64_t CVMX_PCIEEP_CFG042_FUNC(void)
8561 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8562 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8563 cvmx_warn("CVMX_PCIEEP_CFG042 not supported on this chip\n");
8565 return 0x00000000000000A8ull;
8568 #define CVMX_PCIEEP_CFG064 CVMX_PCIEEP_CFG064_FUNC()
8569 static inline uint64_t CVMX_PCIEEP_CFG064_FUNC(void)
8571 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8572 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8573 cvmx_warn("CVMX_PCIEEP_CFG064 not supported on this chip\n");
8575 return 0x0000000000000100ull;
8578 #define CVMX_PCIEEP_CFG065 CVMX_PCIEEP_CFG065_FUNC()
8579 static inline uint64_t CVMX_PCIEEP_CFG065_FUNC(void)
8581 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8582 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8583 cvmx_warn("CVMX_PCIEEP_CFG065 not supported on this chip\n");
8585 return 0x0000000000000104ull;
8588 #define CVMX_PCIEEP_CFG066 CVMX_PCIEEP_CFG066_FUNC()
8589 static inline uint64_t CVMX_PCIEEP_CFG066_FUNC(void)
8591 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8592 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8593 cvmx_warn("CVMX_PCIEEP_CFG066 not supported on this chip\n");
8595 return 0x0000000000000108ull;
8598 #define CVMX_PCIEEP_CFG067 CVMX_PCIEEP_CFG067_FUNC()
8599 static inline uint64_t CVMX_PCIEEP_CFG067_FUNC(void)
8601 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8602 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8603 cvmx_warn("CVMX_PCIEEP_CFG067 not supported on this chip\n");
8605 return 0x000000000000010Cull;
8608 #define CVMX_PCIEEP_CFG068 CVMX_PCIEEP_CFG068_FUNC()
8609 static inline uint64_t CVMX_PCIEEP_CFG068_FUNC(void)
8611 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8612 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8613 cvmx_warn("CVMX_PCIEEP_CFG068 not supported on this chip\n");
8615 return 0x0000000000000110ull;
8618 #define CVMX_PCIEEP_CFG069 CVMX_PCIEEP_CFG069_FUNC()
8619 static inline uint64_t CVMX_PCIEEP_CFG069_FUNC(void)
8621 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8622 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8623 cvmx_warn("CVMX_PCIEEP_CFG069 not supported on this chip\n");
8625 return 0x0000000000000114ull;
8628 #define CVMX_PCIEEP_CFG070 CVMX_PCIEEP_CFG070_FUNC()
8629 static inline uint64_t CVMX_PCIEEP_CFG070_FUNC(void)
8631 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8632 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8633 cvmx_warn("CVMX_PCIEEP_CFG070 not supported on this chip\n");
8635 return 0x0000000000000118ull;
8638 #define CVMX_PCIEEP_CFG071 CVMX_PCIEEP_CFG071_FUNC()
8639 static inline uint64_t CVMX_PCIEEP_CFG071_FUNC(void)
8641 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8642 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8643 cvmx_warn("CVMX_PCIEEP_CFG071 not supported on this chip\n");
8645 return 0x000000000000011Cull;
8648 #define CVMX_PCIEEP_CFG072 CVMX_PCIEEP_CFG072_FUNC()
8649 static inline uint64_t CVMX_PCIEEP_CFG072_FUNC(void)
8651 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8652 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8653 cvmx_warn("CVMX_PCIEEP_CFG072 not supported on this chip\n");
8655 return 0x0000000000000120ull;
8658 #define CVMX_PCIEEP_CFG073 CVMX_PCIEEP_CFG073_FUNC()
8659 static inline uint64_t CVMX_PCIEEP_CFG073_FUNC(void)
8661 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8662 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8663 cvmx_warn("CVMX_PCIEEP_CFG073 not supported on this chip\n");
8665 return 0x0000000000000124ull;
8668 #define CVMX_PCIEEP_CFG074 CVMX_PCIEEP_CFG074_FUNC()
8669 static inline uint64_t CVMX_PCIEEP_CFG074_FUNC(void)
8671 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8672 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8673 cvmx_warn("CVMX_PCIEEP_CFG074 not supported on this chip\n");
8675 return 0x0000000000000128ull;
8678 #define CVMX_PCIEEP_CFG448 CVMX_PCIEEP_CFG448_FUNC()
8679 static inline uint64_t CVMX_PCIEEP_CFG448_FUNC(void)
8681 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8682 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8683 cvmx_warn("CVMX_PCIEEP_CFG448 not supported on this chip\n");
8685 return 0x0000000000000700ull;
8688 #define CVMX_PCIEEP_CFG449 CVMX_PCIEEP_CFG449_FUNC()
8689 static inline uint64_t CVMX_PCIEEP_CFG449_FUNC(void)
8691 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8692 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8693 cvmx_warn("CVMX_PCIEEP_CFG449 not supported on this chip\n");
8695 return 0x0000000000000704ull;
8698 #define CVMX_PCIEEP_CFG450 CVMX_PCIEEP_CFG450_FUNC()
8699 static inline uint64_t CVMX_PCIEEP_CFG450_FUNC(void)
8701 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8702 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8703 cvmx_warn("CVMX_PCIEEP_CFG450 not supported on this chip\n");
8705 return 0x0000000000000708ull;
8708 #define CVMX_PCIEEP_CFG451 CVMX_PCIEEP_CFG451_FUNC()
8709 static inline uint64_t CVMX_PCIEEP_CFG451_FUNC(void)
8711 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8712 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8713 cvmx_warn("CVMX_PCIEEP_CFG451 not supported on this chip\n");
8715 return 0x000000000000070Cull;
8718 #define CVMX_PCIEEP_CFG452 CVMX_PCIEEP_CFG452_FUNC()
8719 static inline uint64_t CVMX_PCIEEP_CFG452_FUNC(void)
8721 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8722 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8723 cvmx_warn("CVMX_PCIEEP_CFG452 not supported on this chip\n");
8725 return 0x0000000000000710ull;
8728 #define CVMX_PCIEEP_CFG453 CVMX_PCIEEP_CFG453_FUNC()
8729 static inline uint64_t CVMX_PCIEEP_CFG453_FUNC(void)
8731 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8732 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8733 cvmx_warn("CVMX_PCIEEP_CFG453 not supported on this chip\n");
8735 return 0x0000000000000714ull;
8738 #define CVMX_PCIEEP_CFG454 CVMX_PCIEEP_CFG454_FUNC()
8739 static inline uint64_t CVMX_PCIEEP_CFG454_FUNC(void)
8741 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8742 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8743 cvmx_warn("CVMX_PCIEEP_CFG454 not supported on this chip\n");
8745 return 0x0000000000000718ull;
8748 #define CVMX_PCIEEP_CFG455 CVMX_PCIEEP_CFG455_FUNC()
8749 static inline uint64_t CVMX_PCIEEP_CFG455_FUNC(void)
8751 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8752 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8753 cvmx_warn("CVMX_PCIEEP_CFG455 not supported on this chip\n");
8755 return 0x000000000000071Cull;
8758 #define CVMX_PCIEEP_CFG456 CVMX_PCIEEP_CFG456_FUNC()
8759 static inline uint64_t CVMX_PCIEEP_CFG456_FUNC(void)
8761 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8762 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8763 cvmx_warn("CVMX_PCIEEP_CFG456 not supported on this chip\n");
8765 return 0x0000000000000720ull;
8768 #define CVMX_PCIEEP_CFG458 CVMX_PCIEEP_CFG458_FUNC()
8769 static inline uint64_t CVMX_PCIEEP_CFG458_FUNC(void)
8771 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8772 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8773 cvmx_warn("CVMX_PCIEEP_CFG458 not supported on this chip\n");
8775 return 0x0000000000000728ull;
8778 #define CVMX_PCIEEP_CFG459 CVMX_PCIEEP_CFG459_FUNC()
8779 static inline uint64_t CVMX_PCIEEP_CFG459_FUNC(void)
8781 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8782 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8783 cvmx_warn("CVMX_PCIEEP_CFG459 not supported on this chip\n");
8785 return 0x000000000000072Cull;
8788 #define CVMX_PCIEEP_CFG460 CVMX_PCIEEP_CFG460_FUNC()
8789 static inline uint64_t CVMX_PCIEEP_CFG460_FUNC(void)
8791 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8792 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8793 cvmx_warn("CVMX_PCIEEP_CFG460 not supported on this chip\n");
8795 return 0x0000000000000730ull;
8798 #define CVMX_PCIEEP_CFG461 CVMX_PCIEEP_CFG461_FUNC()
8799 static inline uint64_t CVMX_PCIEEP_CFG461_FUNC(void)
8801 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8802 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8803 cvmx_warn("CVMX_PCIEEP_CFG461 not supported on this chip\n");
8805 return 0x0000000000000734ull;
8808 #define CVMX_PCIEEP_CFG462 CVMX_PCIEEP_CFG462_FUNC()
8809 static inline uint64_t CVMX_PCIEEP_CFG462_FUNC(void)
8811 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8812 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8813 cvmx_warn("CVMX_PCIEEP_CFG462 not supported on this chip\n");
8815 return 0x0000000000000738ull;
8818 #define CVMX_PCIEEP_CFG463 CVMX_PCIEEP_CFG463_FUNC()
8819 static inline uint64_t CVMX_PCIEEP_CFG463_FUNC(void)
8821 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8822 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8823 cvmx_warn("CVMX_PCIEEP_CFG463 not supported on this chip\n");
8825 return 0x000000000000073Cull;
8828 #define CVMX_PCIEEP_CFG464 CVMX_PCIEEP_CFG464_FUNC()
8829 static inline uint64_t CVMX_PCIEEP_CFG464_FUNC(void)
8831 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8832 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8833 cvmx_warn("CVMX_PCIEEP_CFG464 not supported on this chip\n");
8835 return 0x0000000000000740ull;
8838 #define CVMX_PCIEEP_CFG465 CVMX_PCIEEP_CFG465_FUNC()
8839 static inline uint64_t CVMX_PCIEEP_CFG465_FUNC(void)
8841 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8842 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8843 cvmx_warn("CVMX_PCIEEP_CFG465 not supported on this chip\n");
8845 return 0x0000000000000744ull;
8848 #define CVMX_PCIEEP_CFG466 CVMX_PCIEEP_CFG466_FUNC()
8849 static inline uint64_t CVMX_PCIEEP_CFG466_FUNC(void)
8851 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8852 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8853 cvmx_warn("CVMX_PCIEEP_CFG466 not supported on this chip\n");
8855 return 0x0000000000000748ull;
8858 #define CVMX_PCIEEP_CFG467 CVMX_PCIEEP_CFG467_FUNC()
8859 static inline uint64_t CVMX_PCIEEP_CFG467_FUNC(void)
8861 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8862 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8863 cvmx_warn("CVMX_PCIEEP_CFG467 not supported on this chip\n");
8865 return 0x000000000000074Cull;
8868 #define CVMX_PCIEEP_CFG468 CVMX_PCIEEP_CFG468_FUNC()
8869 static inline uint64_t CVMX_PCIEEP_CFG468_FUNC(void)
8871 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8872 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8873 cvmx_warn("CVMX_PCIEEP_CFG468 not supported on this chip\n");
8875 return 0x0000000000000750ull;
8878 #define CVMX_PCIEEP_CFG490 CVMX_PCIEEP_CFG490_FUNC()
8879 static inline uint64_t CVMX_PCIEEP_CFG490_FUNC(void)
8881 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8882 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8883 cvmx_warn("CVMX_PCIEEP_CFG490 not supported on this chip\n");
8885 return 0x00000000000007A8ull;
8888 #define CVMX_PCIEEP_CFG491 CVMX_PCIEEP_CFG491_FUNC()
8889 static inline uint64_t CVMX_PCIEEP_CFG491_FUNC(void)
8891 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8892 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8893 cvmx_warn("CVMX_PCIEEP_CFG491 not supported on this chip\n");
8895 return 0x00000000000007ACull;
8898 #define CVMX_PCIEEP_CFG492 CVMX_PCIEEP_CFG492_FUNC()
8899 static inline uint64_t CVMX_PCIEEP_CFG492_FUNC(void)
8901 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8902 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8903 cvmx_warn("CVMX_PCIEEP_CFG492 not supported on this chip\n");
8905 return 0x00000000000007B0ull;
8908 #define CVMX_PCIEEP_CFG516 CVMX_PCIEEP_CFG516_FUNC()
8909 static inline uint64_t CVMX_PCIEEP_CFG516_FUNC(void)
8911 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8912 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8913 cvmx_warn("CVMX_PCIEEP_CFG516 not supported on this chip\n");
8915 return 0x0000000000000810ull;
8918 #define CVMX_PCIEEP_CFG517 CVMX_PCIEEP_CFG517_FUNC()
8919 static inline uint64_t CVMX_PCIEEP_CFG517_FUNC(void)
8921 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8922 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
8923 cvmx_warn("CVMX_PCIEEP_CFG517 not supported on this chip\n");
8925 return 0x0000000000000814ull;
8928 static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long offset)
8930 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8932 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
8933 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
8934 cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", offset);
8936 return 0x0000000000000000ull + (offset&1)*0;
8939 static inline uint64_t CVMX_PCIERCX_CFG001(unsigned long offset)
8941 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8943 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
8944 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
8945 cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", offset);
8947 return 0x0000000000000004ull + (offset&1)*0;
8950 static inline uint64_t CVMX_PCIERCX_CFG002(unsigned long offset)
8952 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8954 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
8955 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
8956 cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", offset);
8958 return 0x0000000000000008ull + (offset&1)*0;
8961 static inline uint64_t CVMX_PCIERCX_CFG003(unsigned long offset)
8963 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8965 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
8966 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
8967 cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", offset);
8969 return 0x000000000000000Cull + (offset&1)*0;
8972 static inline uint64_t CVMX_PCIERCX_CFG004(unsigned long offset)
8974 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8976 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
8977 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
8978 cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", offset);
8980 return 0x0000000000000010ull + (offset&1)*0;
8983 static inline uint64_t CVMX_PCIERCX_CFG005(unsigned long offset)
8985 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8987 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
8988 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
8989 cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", offset);
8991 return 0x0000000000000014ull + (offset&1)*0;
8994 static inline uint64_t CVMX_PCIERCX_CFG006(unsigned long offset)
8996 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8998 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
8999 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9000 cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", offset);
9002 return 0x0000000000000018ull + (offset&1)*0;
9005 static inline uint64_t CVMX_PCIERCX_CFG007(unsigned long offset)
9007 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9009 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9010 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9011 cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", offset);
9013 return 0x000000000000001Cull + (offset&1)*0;
9016 static inline uint64_t CVMX_PCIERCX_CFG008(unsigned long offset)
9018 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9020 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9021 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9022 cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", offset);
9024 return 0x0000000000000020ull + (offset&1)*0;
9027 static inline uint64_t CVMX_PCIERCX_CFG009(unsigned long offset)
9029 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9031 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9032 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9033 cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", offset);
9035 return 0x0000000000000024ull + (offset&1)*0;
9038 static inline uint64_t CVMX_PCIERCX_CFG010(unsigned long offset)
9040 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9042 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9043 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9044 cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n", offset);
9046 return 0x0000000000000028ull + (offset&1)*0;
9049 static inline uint64_t CVMX_PCIERCX_CFG011(unsigned long offset)
9051 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9053 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9054 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9055 cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n", offset);
9057 return 0x000000000000002Cull + (offset&1)*0;
9060 static inline uint64_t CVMX_PCIERCX_CFG012(unsigned long offset)
9062 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9064 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9065 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9066 cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n", offset);
9068 return 0x0000000000000030ull + (offset&1)*0;
9071 static inline uint64_t CVMX_PCIERCX_CFG013(unsigned long offset)
9073 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9075 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9076 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9077 cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n", offset);
9079 return 0x0000000000000034ull + (offset&1)*0;
9082 static inline uint64_t CVMX_PCIERCX_CFG014(unsigned long offset)
9084 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9086 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9087 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9088 cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n", offset);
9090 return 0x0000000000000038ull + (offset&1)*0;
9093 static inline uint64_t CVMX_PCIERCX_CFG015(unsigned long offset)
9095 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9097 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9098 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9099 cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n", offset);
9101 return 0x000000000000003Cull + (offset&1)*0;
9104 static inline uint64_t CVMX_PCIERCX_CFG016(unsigned long offset)
9106 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9109 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9110 cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n", offset);
9112 return 0x0000000000000040ull + (offset&1)*0;
9115 static inline uint64_t CVMX_PCIERCX_CFG017(unsigned long offset)
9117 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9119 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9120 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9121 cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n", offset);
9123 return 0x0000000000000044ull + (offset&1)*0;
9126 static inline uint64_t CVMX_PCIERCX_CFG020(unsigned long offset)
9128 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9130 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9131 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9132 cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n", offset);
9134 return 0x0000000000000050ull + (offset&1)*0;
9137 static inline uint64_t CVMX_PCIERCX_CFG021(unsigned long offset)
9139 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9141 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9142 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9143 cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n", offset);
9145 return 0x0000000000000054ull + (offset&1)*0;
9148 static inline uint64_t CVMX_PCIERCX_CFG022(unsigned long offset)
9150 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9152 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9153 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9154 cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n", offset);
9156 return 0x0000000000000058ull + (offset&1)*0;
9159 static inline uint64_t CVMX_PCIERCX_CFG023(unsigned long offset)
9161 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9163 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9164 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9165 cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n", offset);
9167 return 0x000000000000005Cull + (offset&1)*0;
9170 static inline uint64_t CVMX_PCIERCX_CFG028(unsigned long offset)
9172 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9174 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9175 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9176 cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n", offset);
9178 return 0x0000000000000070ull + (offset&1)*0;
9181 static inline uint64_t CVMX_PCIERCX_CFG029(unsigned long offset)
9183 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9185 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9186 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9187 cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n", offset);
9189 return 0x0000000000000074ull + (offset&1)*0;
9192 static inline uint64_t CVMX_PCIERCX_CFG030(unsigned long offset)
9194 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9196 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9197 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9198 cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n", offset);
9200 return 0x0000000000000078ull + (offset&1)*0;
9203 static inline uint64_t CVMX_PCIERCX_CFG031(unsigned long offset)
9205 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9207 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9208 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9209 cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n", offset);
9211 return 0x000000000000007Cull + (offset&1)*0;
9214 static inline uint64_t CVMX_PCIERCX_CFG032(unsigned long offset)
9216 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9218 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9219 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9220 cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n", offset);
9222 return 0x0000000000000080ull + (offset&1)*0;
9225 static inline uint64_t CVMX_PCIERCX_CFG033(unsigned long offset)
9227 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9229 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9230 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9231 cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n", offset);
9233 return 0x0000000000000084ull + (offset&1)*0;
9236 static inline uint64_t CVMX_PCIERCX_CFG034(unsigned long offset)
9238 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9240 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9241 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9242 cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n", offset);
9244 return 0x0000000000000088ull + (offset&1)*0;
9247 static inline uint64_t CVMX_PCIERCX_CFG035(unsigned long offset)
9249 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9251 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9252 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9253 cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n", offset);
9255 return 0x000000000000008Cull + (offset&1)*0;
9258 static inline uint64_t CVMX_PCIERCX_CFG036(unsigned long offset)
9260 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9262 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9263 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9264 cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n", offset);
9266 return 0x0000000000000090ull + (offset&1)*0;
9269 static inline uint64_t CVMX_PCIERCX_CFG037(unsigned long offset)
9271 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9273 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9274 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9275 cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n", offset);
9277 return 0x0000000000000094ull + (offset&1)*0;
9280 static inline uint64_t CVMX_PCIERCX_CFG038(unsigned long offset)
9282 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9284 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9285 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9286 cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n", offset);
9288 return 0x0000000000000098ull + (offset&1)*0;
9291 static inline uint64_t CVMX_PCIERCX_CFG039(unsigned long offset)
9293 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9295 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9296 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9297 cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n", offset);
9299 return 0x000000000000009Cull + (offset&1)*0;
9302 static inline uint64_t CVMX_PCIERCX_CFG040(unsigned long offset)
9304 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9306 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9307 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9308 cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n", offset);
9310 return 0x00000000000000A0ull + (offset&1)*0;
9313 static inline uint64_t CVMX_PCIERCX_CFG041(unsigned long offset)
9315 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9317 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9318 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9319 cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n", offset);
9321 return 0x00000000000000A4ull + (offset&1)*0;
9324 static inline uint64_t CVMX_PCIERCX_CFG042(unsigned long offset)
9326 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9328 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9329 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9330 cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n", offset);
9332 return 0x00000000000000A8ull + (offset&1)*0;
9335 static inline uint64_t CVMX_PCIERCX_CFG064(unsigned long offset)
9337 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9339 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9340 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9341 cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n", offset);
9343 return 0x0000000000000100ull + (offset&1)*0;
9346 static inline uint64_t CVMX_PCIERCX_CFG065(unsigned long offset)
9348 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9350 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9351 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9352 cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n", offset);
9354 return 0x0000000000000104ull + (offset&1)*0;
9357 static inline uint64_t CVMX_PCIERCX_CFG066(unsigned long offset)
9359 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9361 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9362 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9363 cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n", offset);
9365 return 0x0000000000000108ull + (offset&1)*0;
9368 static inline uint64_t CVMX_PCIERCX_CFG067(unsigned long offset)
9370 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9372 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9373 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9374 cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n", offset);
9376 return 0x000000000000010Cull + (offset&1)*0;
9379 static inline uint64_t CVMX_PCIERCX_CFG068(unsigned long offset)
9381 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9383 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9384 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9385 cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n", offset);
9387 return 0x0000000000000110ull + (offset&1)*0;
9390 static inline uint64_t CVMX_PCIERCX_CFG069(unsigned long offset)
9392 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9394 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9395 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9396 cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n", offset);
9398 return 0x0000000000000114ull + (offset&1)*0;
9401 static inline uint64_t CVMX_PCIERCX_CFG070(unsigned long offset)
9403 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9405 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9406 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9407 cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n", offset);
9409 return 0x0000000000000118ull + (offset&1)*0;
9412 static inline uint64_t CVMX_PCIERCX_CFG071(unsigned long offset)
9414 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9416 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9417 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9418 cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n", offset);
9420 return 0x000000000000011Cull + (offset&1)*0;
9423 static inline uint64_t CVMX_PCIERCX_CFG072(unsigned long offset)
9425 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9427 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9428 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9429 cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n", offset);
9431 return 0x0000000000000120ull + (offset&1)*0;
9434 static inline uint64_t CVMX_PCIERCX_CFG073(unsigned long offset)
9436 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9438 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9439 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9440 cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n", offset);
9442 return 0x0000000000000124ull + (offset&1)*0;
9445 static inline uint64_t CVMX_PCIERCX_CFG074(unsigned long offset)
9447 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9449 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9450 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9451 cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n", offset);
9453 return 0x0000000000000128ull + (offset&1)*0;
9456 static inline uint64_t CVMX_PCIERCX_CFG075(unsigned long offset)
9458 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9460 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9461 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9462 cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n", offset);
9464 return 0x000000000000012Cull + (offset&1)*0;
9467 static inline uint64_t CVMX_PCIERCX_CFG076(unsigned long offset)
9469 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9471 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9472 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9473 cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n", offset);
9475 return 0x0000000000000130ull + (offset&1)*0;
9478 static inline uint64_t CVMX_PCIERCX_CFG077(unsigned long offset)
9480 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9482 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9483 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9484 cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n", offset);
9486 return 0x0000000000000134ull + (offset&1)*0;
9489 static inline uint64_t CVMX_PCIERCX_CFG448(unsigned long offset)
9491 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9493 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9494 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9495 cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n", offset);
9497 return 0x0000000000000700ull + (offset&1)*0;
9500 static inline uint64_t CVMX_PCIERCX_CFG449(unsigned long offset)
9502 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9504 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9505 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9506 cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n", offset);
9508 return 0x0000000000000704ull + (offset&1)*0;
9511 static inline uint64_t CVMX_PCIERCX_CFG450(unsigned long offset)
9513 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9515 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9516 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9517 cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n", offset);
9519 return 0x0000000000000708ull + (offset&1)*0;
9522 static inline uint64_t CVMX_PCIERCX_CFG451(unsigned long offset)
9524 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9526 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9527 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9528 cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n", offset);
9530 return 0x000000000000070Cull + (offset&1)*0;
9533 static inline uint64_t CVMX_PCIERCX_CFG452(unsigned long offset)
9535 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9537 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9538 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9539 cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n", offset);
9541 return 0x0000000000000710ull + (offset&1)*0;
9544 static inline uint64_t CVMX_PCIERCX_CFG453(unsigned long offset)
9546 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9548 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9549 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9550 cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n", offset);
9552 return 0x0000000000000714ull + (offset&1)*0;
9555 static inline uint64_t CVMX_PCIERCX_CFG454(unsigned long offset)
9557 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9559 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9560 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9561 cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n", offset);
9563 return 0x0000000000000718ull + (offset&1)*0;
9566 static inline uint64_t CVMX_PCIERCX_CFG455(unsigned long offset)
9568 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9570 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9571 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9572 cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n", offset);
9574 return 0x000000000000071Cull + (offset&1)*0;
9577 static inline uint64_t CVMX_PCIERCX_CFG456(unsigned long offset)
9579 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9581 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9582 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9583 cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n", offset);
9585 return 0x0000000000000720ull + (offset&1)*0;
9588 static inline uint64_t CVMX_PCIERCX_CFG458(unsigned long offset)
9590 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9592 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9593 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9594 cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n", offset);
9596 return 0x0000000000000728ull + (offset&1)*0;
9599 static inline uint64_t CVMX_PCIERCX_CFG459(unsigned long offset)
9601 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9603 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9604 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9605 cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n", offset);
9607 return 0x000000000000072Cull + (offset&1)*0;
9610 static inline uint64_t CVMX_PCIERCX_CFG460(unsigned long offset)
9612 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9614 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9615 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9616 cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n", offset);
9618 return 0x0000000000000730ull + (offset&1)*0;
9621 static inline uint64_t CVMX_PCIERCX_CFG461(unsigned long offset)
9623 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9625 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9626 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9627 cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n", offset);
9629 return 0x0000000000000734ull + (offset&1)*0;
9632 static inline uint64_t CVMX_PCIERCX_CFG462(unsigned long offset)
9634 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9636 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9637 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9638 cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n", offset);
9640 return 0x0000000000000738ull + (offset&1)*0;
9643 static inline uint64_t CVMX_PCIERCX_CFG463(unsigned long offset)
9645 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9647 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9648 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9649 cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n", offset);
9651 return 0x000000000000073Cull + (offset&1)*0;
9654 static inline uint64_t CVMX_PCIERCX_CFG464(unsigned long offset)
9656 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9658 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9659 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9660 cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n", offset);
9662 return 0x0000000000000740ull + (offset&1)*0;
9665 static inline uint64_t CVMX_PCIERCX_CFG465(unsigned long offset)
9667 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9669 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9670 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9671 cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n", offset);
9673 return 0x0000000000000744ull + (offset&1)*0;
9676 static inline uint64_t CVMX_PCIERCX_CFG466(unsigned long offset)
9678 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9680 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9681 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9682 cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n", offset);
9684 return 0x0000000000000748ull + (offset&1)*0;
9687 static inline uint64_t CVMX_PCIERCX_CFG467(unsigned long offset)
9689 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9691 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9692 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9693 cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n", offset);
9695 return 0x000000000000074Cull + (offset&1)*0;
9698 static inline uint64_t CVMX_PCIERCX_CFG468(unsigned long offset)
9700 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9702 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9703 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9704 cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n", offset);
9706 return 0x0000000000000750ull + (offset&1)*0;
9709 static inline uint64_t CVMX_PCIERCX_CFG490(unsigned long offset)
9711 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9713 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9714 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9715 cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n", offset);
9717 return 0x00000000000007A8ull + (offset&1)*0;
9720 static inline uint64_t CVMX_PCIERCX_CFG491(unsigned long offset)
9722 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9724 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9725 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9726 cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n", offset);
9728 return 0x00000000000007ACull + (offset&1)*0;
9731 static inline uint64_t CVMX_PCIERCX_CFG492(unsigned long offset)
9733 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9735 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9736 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9737 cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n", offset);
9739 return 0x00000000000007B0ull + (offset&1)*0;
9742 static inline uint64_t CVMX_PCIERCX_CFG516(unsigned long offset)
9744 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9746 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9747 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9748 cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n", offset);
9750 return 0x0000000000000810ull + (offset&1)*0;
9753 static inline uint64_t CVMX_PCIERCX_CFG517(unsigned long offset)
9755 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9757 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
9758 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
9759 cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n", offset);
9761 return 0x0000000000000814ull + (offset&1)*0;
9764 static inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset)
9766 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9768 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
9769 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
9770 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
9771 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
9772 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
9773 cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
9775 return 0x0000000000000100ull + (offset&31)*4;
9778 #define CVMX_PCI_BIST_REG CVMX_PCI_BIST_REG_FUNC()
9779 static inline uint64_t CVMX_PCI_BIST_REG_FUNC(void)
9781 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9782 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
9783 cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n");
9785 return 0x00000000000001C0ull;
9788 #define CVMX_PCI_CFG00 CVMX_PCI_CFG00_FUNC()
9789 static inline uint64_t CVMX_PCI_CFG00_FUNC(void)
9791 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9792 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9793 cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n");
9795 return 0x0000000000000000ull;
9798 #define CVMX_PCI_CFG01 CVMX_PCI_CFG01_FUNC()
9799 static inline uint64_t CVMX_PCI_CFG01_FUNC(void)
9801 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9802 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9803 cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n");
9805 return 0x0000000000000004ull;
9808 #define CVMX_PCI_CFG02 CVMX_PCI_CFG02_FUNC()
9809 static inline uint64_t CVMX_PCI_CFG02_FUNC(void)
9811 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9812 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9813 cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n");
9815 return 0x0000000000000008ull;
9818 #define CVMX_PCI_CFG03 CVMX_PCI_CFG03_FUNC()
9819 static inline uint64_t CVMX_PCI_CFG03_FUNC(void)
9821 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9822 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9823 cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n");
9825 return 0x000000000000000Cull;
9828 #define CVMX_PCI_CFG04 CVMX_PCI_CFG04_FUNC()
9829 static inline uint64_t CVMX_PCI_CFG04_FUNC(void)
9831 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9832 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9833 cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n");
9835 return 0x0000000000000010ull;
9838 #define CVMX_PCI_CFG05 CVMX_PCI_CFG05_FUNC()
9839 static inline uint64_t CVMX_PCI_CFG05_FUNC(void)
9841 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9842 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9843 cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n");
9845 return 0x0000000000000014ull;
9848 #define CVMX_PCI_CFG06 CVMX_PCI_CFG06_FUNC()
9849 static inline uint64_t CVMX_PCI_CFG06_FUNC(void)
9851 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9852 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9853 cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n");
9855 return 0x0000000000000018ull;
9858 #define CVMX_PCI_CFG07 CVMX_PCI_CFG07_FUNC()
9859 static inline uint64_t CVMX_PCI_CFG07_FUNC(void)
9861 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9862 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9863 cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n");
9865 return 0x000000000000001Cull;
9868 #define CVMX_PCI_CFG08 CVMX_PCI_CFG08_FUNC()
9869 static inline uint64_t CVMX_PCI_CFG08_FUNC(void)
9871 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9872 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9873 cvmx_warn("CVMX_PCI_CFG08 not supported on this chip\n");
9875 return 0x0000000000000020ull;
9878 #define CVMX_PCI_CFG09 CVMX_PCI_CFG09_FUNC()
9879 static inline uint64_t CVMX_PCI_CFG09_FUNC(void)
9881 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9882 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9883 cvmx_warn("CVMX_PCI_CFG09 not supported on this chip\n");
9885 return 0x0000000000000024ull;
9888 #define CVMX_PCI_CFG10 CVMX_PCI_CFG10_FUNC()
9889 static inline uint64_t CVMX_PCI_CFG10_FUNC(void)
9891 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9892 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9893 cvmx_warn("CVMX_PCI_CFG10 not supported on this chip\n");
9895 return 0x0000000000000028ull;
9898 #define CVMX_PCI_CFG11 CVMX_PCI_CFG11_FUNC()
9899 static inline uint64_t CVMX_PCI_CFG11_FUNC(void)
9901 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9902 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9903 cvmx_warn("CVMX_PCI_CFG11 not supported on this chip\n");
9905 return 0x000000000000002Cull;
9908 #define CVMX_PCI_CFG12 CVMX_PCI_CFG12_FUNC()
9909 static inline uint64_t CVMX_PCI_CFG12_FUNC(void)
9911 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9912 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9913 cvmx_warn("CVMX_PCI_CFG12 not supported on this chip\n");
9915 return 0x0000000000000030ull;
9918 #define CVMX_PCI_CFG13 CVMX_PCI_CFG13_FUNC()
9919 static inline uint64_t CVMX_PCI_CFG13_FUNC(void)
9921 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9922 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9923 cvmx_warn("CVMX_PCI_CFG13 not supported on this chip\n");
9925 return 0x0000000000000034ull;
9928 #define CVMX_PCI_CFG15 CVMX_PCI_CFG15_FUNC()
9929 static inline uint64_t CVMX_PCI_CFG15_FUNC(void)
9931 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9932 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9933 cvmx_warn("CVMX_PCI_CFG15 not supported on this chip\n");
9935 return 0x000000000000003Cull;
9938 #define CVMX_PCI_CFG16 CVMX_PCI_CFG16_FUNC()
9939 static inline uint64_t CVMX_PCI_CFG16_FUNC(void)
9941 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9942 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9943 cvmx_warn("CVMX_PCI_CFG16 not supported on this chip\n");
9945 return 0x0000000000000040ull;
9948 #define CVMX_PCI_CFG17 CVMX_PCI_CFG17_FUNC()
9949 static inline uint64_t CVMX_PCI_CFG17_FUNC(void)
9951 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9952 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9953 cvmx_warn("CVMX_PCI_CFG17 not supported on this chip\n");
9955 return 0x0000000000000044ull;
9958 #define CVMX_PCI_CFG18 CVMX_PCI_CFG18_FUNC()
9959 static inline uint64_t CVMX_PCI_CFG18_FUNC(void)
9961 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9962 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9963 cvmx_warn("CVMX_PCI_CFG18 not supported on this chip\n");
9965 return 0x0000000000000048ull;
9968 #define CVMX_PCI_CFG19 CVMX_PCI_CFG19_FUNC()
9969 static inline uint64_t CVMX_PCI_CFG19_FUNC(void)
9971 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9972 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9973 cvmx_warn("CVMX_PCI_CFG19 not supported on this chip\n");
9975 return 0x000000000000004Cull;
9978 #define CVMX_PCI_CFG20 CVMX_PCI_CFG20_FUNC()
9979 static inline uint64_t CVMX_PCI_CFG20_FUNC(void)
9981 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9982 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9983 cvmx_warn("CVMX_PCI_CFG20 not supported on this chip\n");
9985 return 0x0000000000000050ull;
9988 #define CVMX_PCI_CFG21 CVMX_PCI_CFG21_FUNC()
9989 static inline uint64_t CVMX_PCI_CFG21_FUNC(void)
9991 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9992 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
9993 cvmx_warn("CVMX_PCI_CFG21 not supported on this chip\n");
9995 return 0x0000000000000054ull;
9998 #define CVMX_PCI_CFG22 CVMX_PCI_CFG22_FUNC()
9999 static inline uint64_t CVMX_PCI_CFG22_FUNC(void)
10001 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10002 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10003 cvmx_warn("CVMX_PCI_CFG22 not supported on this chip\n");
10005 return 0x0000000000000058ull;
10008 #define CVMX_PCI_CFG56 CVMX_PCI_CFG56_FUNC()
10009 static inline uint64_t CVMX_PCI_CFG56_FUNC(void)
10011 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10012 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10013 cvmx_warn("CVMX_PCI_CFG56 not supported on this chip\n");
10015 return 0x00000000000000E0ull;
10018 #define CVMX_PCI_CFG57 CVMX_PCI_CFG57_FUNC()
10019 static inline uint64_t CVMX_PCI_CFG57_FUNC(void)
10021 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10022 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10023 cvmx_warn("CVMX_PCI_CFG57 not supported on this chip\n");
10025 return 0x00000000000000E4ull;
10028 #define CVMX_PCI_CFG58 CVMX_PCI_CFG58_FUNC()
10029 static inline uint64_t CVMX_PCI_CFG58_FUNC(void)
10031 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10032 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10033 cvmx_warn("CVMX_PCI_CFG58 not supported on this chip\n");
10035 return 0x00000000000000E8ull;
10038 #define CVMX_PCI_CFG59 CVMX_PCI_CFG59_FUNC()
10039 static inline uint64_t CVMX_PCI_CFG59_FUNC(void)
10041 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10042 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10043 cvmx_warn("CVMX_PCI_CFG59 not supported on this chip\n");
10045 return 0x00000000000000ECull;
10048 #define CVMX_PCI_CFG60 CVMX_PCI_CFG60_FUNC()
10049 static inline uint64_t CVMX_PCI_CFG60_FUNC(void)
10051 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10052 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10053 cvmx_warn("CVMX_PCI_CFG60 not supported on this chip\n");
10055 return 0x00000000000000F0ull;
10058 #define CVMX_PCI_CFG61 CVMX_PCI_CFG61_FUNC()
10059 static inline uint64_t CVMX_PCI_CFG61_FUNC(void)
10061 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10062 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10063 cvmx_warn("CVMX_PCI_CFG61 not supported on this chip\n");
10065 return 0x00000000000000F4ull;
10068 #define CVMX_PCI_CFG62 CVMX_PCI_CFG62_FUNC()
10069 static inline uint64_t CVMX_PCI_CFG62_FUNC(void)
10071 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10072 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10073 cvmx_warn("CVMX_PCI_CFG62 not supported on this chip\n");
10075 return 0x00000000000000F8ull;
10078 #define CVMX_PCI_CFG63 CVMX_PCI_CFG63_FUNC()
10079 static inline uint64_t CVMX_PCI_CFG63_FUNC(void)
10081 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10082 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10083 cvmx_warn("CVMX_PCI_CFG63 not supported on this chip\n");
10085 return 0x00000000000000FCull;
10088 #define CVMX_PCI_CNT_REG CVMX_PCI_CNT_REG_FUNC()
10089 static inline uint64_t CVMX_PCI_CNT_REG_FUNC(void)
10091 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10092 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10093 cvmx_warn("CVMX_PCI_CNT_REG not supported on this chip\n");
10095 return 0x00000000000001B8ull;
10098 #define CVMX_PCI_CTL_STATUS_2 CVMX_PCI_CTL_STATUS_2_FUNC()
10099 static inline uint64_t CVMX_PCI_CTL_STATUS_2_FUNC(void)
10101 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10102 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10103 cvmx_warn("CVMX_PCI_CTL_STATUS_2 not supported on this chip\n");
10105 return 0x000000000000018Cull;
10108 static inline uint64_t CVMX_PCI_DBELL_X(unsigned long offset)
10110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10112 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
10113 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
10114 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
10115 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10116 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
10117 cvmx_warn("CVMX_PCI_DBELL_X(%lu) is invalid on this chip\n", offset);
10119 return 0x0000000000000080ull + (offset&3)*8;
10122 #define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
10123 #define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
10124 static inline uint64_t CVMX_PCI_DMA_CNTX(unsigned long offset)
10126 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10128 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
10129 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
10130 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
10131 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10132 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
10133 cvmx_warn("CVMX_PCI_DMA_CNTX(%lu) is invalid on this chip\n", offset);
10135 return 0x00000000000000A0ull + (offset&1)*8;
10138 #define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
10139 #define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
10140 static inline uint64_t CVMX_PCI_DMA_INT_LEVX(unsigned long offset)
10142 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10144 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
10145 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
10146 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
10147 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10148 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
10149 cvmx_warn("CVMX_PCI_DMA_INT_LEVX(%lu) is invalid on this chip\n", offset);
10151 return 0x00000000000000A4ull + (offset&1)*8;
10154 #define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
10155 #define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
10156 static inline uint64_t CVMX_PCI_DMA_TIMEX(unsigned long offset)
10158 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10160 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
10161 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
10162 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
10163 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10164 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
10165 cvmx_warn("CVMX_PCI_DMA_TIMEX(%lu) is invalid on this chip\n", offset);
10167 return 0x00000000000000B0ull + (offset&1)*4;
10170 #define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
10171 #define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
10172 #define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
10173 #define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
10174 static inline uint64_t CVMX_PCI_INSTR_COUNTX(unsigned long offset)
10176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10178 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
10179 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
10180 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
10181 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10182 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
10183 cvmx_warn("CVMX_PCI_INSTR_COUNTX(%lu) is invalid on this chip\n", offset);
10185 return 0x0000000000000084ull + (offset&3)*8;
10188 #define CVMX_PCI_INT_ENB CVMX_PCI_INT_ENB_FUNC()
10189 static inline uint64_t CVMX_PCI_INT_ENB_FUNC(void)
10191 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10192 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10193 cvmx_warn("CVMX_PCI_INT_ENB not supported on this chip\n");
10195 return 0x0000000000000038ull;
10198 #define CVMX_PCI_INT_ENB2 CVMX_PCI_INT_ENB2_FUNC()
10199 static inline uint64_t CVMX_PCI_INT_ENB2_FUNC(void)
10201 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10202 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10203 cvmx_warn("CVMX_PCI_INT_ENB2 not supported on this chip\n");
10205 return 0x00000000000001A0ull;
10208 #define CVMX_PCI_INT_SUM CVMX_PCI_INT_SUM_FUNC()
10209 static inline uint64_t CVMX_PCI_INT_SUM_FUNC(void)
10211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10212 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10213 cvmx_warn("CVMX_PCI_INT_SUM not supported on this chip\n");
10215 return 0x0000000000000030ull;
10218 #define CVMX_PCI_INT_SUM2 CVMX_PCI_INT_SUM2_FUNC()
10219 static inline uint64_t CVMX_PCI_INT_SUM2_FUNC(void)
10221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10222 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10223 cvmx_warn("CVMX_PCI_INT_SUM2 not supported on this chip\n");
10225 return 0x0000000000000198ull;
10228 #define CVMX_PCI_MSI_RCV CVMX_PCI_MSI_RCV_FUNC()
10229 static inline uint64_t CVMX_PCI_MSI_RCV_FUNC(void)
10231 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10232 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10233 cvmx_warn("CVMX_PCI_MSI_RCV not supported on this chip\n");
10235 return 0x00000000000000F0ull;
10238 #define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
10239 #define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
10240 #define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
10241 #define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
10242 static inline uint64_t CVMX_PCI_PKTS_SENTX(unsigned long offset)
10244 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10246 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
10247 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
10248 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
10249 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10250 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
10251 cvmx_warn("CVMX_PCI_PKTS_SENTX(%lu) is invalid on this chip\n", offset);
10253 return 0x0000000000000040ull + (offset&3)*16;
10256 #define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
10257 #define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
10258 #define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
10259 #define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
10260 static inline uint64_t CVMX_PCI_PKTS_SENT_INT_LEVX(unsigned long offset)
10262 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10264 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
10265 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
10266 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
10267 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10268 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
10269 cvmx_warn("CVMX_PCI_PKTS_SENT_INT_LEVX(%lu) is invalid on this chip\n", offset);
10271 return 0x0000000000000048ull + (offset&3)*16;
10274 #define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
10275 #define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
10276 #define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
10277 #define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
10278 static inline uint64_t CVMX_PCI_PKTS_SENT_TIMEX(unsigned long offset)
10280 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10282 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
10283 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
10284 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
10285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10286 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
10287 cvmx_warn("CVMX_PCI_PKTS_SENT_TIMEX(%lu) is invalid on this chip\n", offset);
10289 return 0x000000000000004Cull + (offset&3)*16;
10292 #define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
10293 #define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
10294 #define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
10295 #define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
10296 static inline uint64_t CVMX_PCI_PKT_CREDITSX(unsigned long offset)
10298 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10300 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
10301 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
10302 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
10303 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10304 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
10305 cvmx_warn("CVMX_PCI_PKT_CREDITSX(%lu) is invalid on this chip\n", offset);
10307 return 0x0000000000000044ull + (offset&3)*16;
10310 #define CVMX_PCI_READ_CMD_6 CVMX_PCI_READ_CMD_6_FUNC()
10311 static inline uint64_t CVMX_PCI_READ_CMD_6_FUNC(void)
10313 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10314 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10315 cvmx_warn("CVMX_PCI_READ_CMD_6 not supported on this chip\n");
10317 return 0x0000000000000180ull;
10320 #define CVMX_PCI_READ_CMD_C CVMX_PCI_READ_CMD_C_FUNC()
10321 static inline uint64_t CVMX_PCI_READ_CMD_C_FUNC(void)
10323 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10324 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10325 cvmx_warn("CVMX_PCI_READ_CMD_C not supported on this chip\n");
10327 return 0x0000000000000184ull;
10330 #define CVMX_PCI_READ_CMD_E CVMX_PCI_READ_CMD_E_FUNC()
10331 static inline uint64_t CVMX_PCI_READ_CMD_E_FUNC(void)
10333 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10334 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10335 cvmx_warn("CVMX_PCI_READ_CMD_E not supported on this chip\n");
10337 return 0x0000000000000188ull;
10340 #define CVMX_PCI_READ_TIMEOUT CVMX_PCI_READ_TIMEOUT_FUNC()
10341 static inline uint64_t CVMX_PCI_READ_TIMEOUT_FUNC(void)
10343 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10344 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10345 cvmx_warn("CVMX_PCI_READ_TIMEOUT not supported on this chip\n");
10347 return CVMX_ADD_IO_SEG(0x00011F00000000B0ull);
10350 #define CVMX_PCI_SCM_REG CVMX_PCI_SCM_REG_FUNC()
10351 static inline uint64_t CVMX_PCI_SCM_REG_FUNC(void)
10353 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10354 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10355 cvmx_warn("CVMX_PCI_SCM_REG not supported on this chip\n");
10357 return 0x00000000000001A8ull;
10360 #define CVMX_PCI_TSR_REG CVMX_PCI_TSR_REG_FUNC()
10361 static inline uint64_t CVMX_PCI_TSR_REG_FUNC(void)
10363 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10364 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10365 cvmx_warn("CVMX_PCI_TSR_REG not supported on this chip\n");
10367 return 0x00000000000001B0ull;
10370 #define CVMX_PCI_WIN_RD_ADDR CVMX_PCI_WIN_RD_ADDR_FUNC()
10371 static inline uint64_t CVMX_PCI_WIN_RD_ADDR_FUNC(void)
10373 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10374 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10375 cvmx_warn("CVMX_PCI_WIN_RD_ADDR not supported on this chip\n");
10377 return 0x0000000000000008ull;
10380 #define CVMX_PCI_WIN_RD_DATA CVMX_PCI_WIN_RD_DATA_FUNC()
10381 static inline uint64_t CVMX_PCI_WIN_RD_DATA_FUNC(void)
10383 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10384 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10385 cvmx_warn("CVMX_PCI_WIN_RD_DATA not supported on this chip\n");
10387 return 0x0000000000000020ull;
10390 #define CVMX_PCI_WIN_WR_ADDR CVMX_PCI_WIN_WR_ADDR_FUNC()
10391 static inline uint64_t CVMX_PCI_WIN_WR_ADDR_FUNC(void)
10393 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10394 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10395 cvmx_warn("CVMX_PCI_WIN_WR_ADDR not supported on this chip\n");
10397 return 0x0000000000000000ull;
10400 #define CVMX_PCI_WIN_WR_DATA CVMX_PCI_WIN_WR_DATA_FUNC()
10401 static inline uint64_t CVMX_PCI_WIN_WR_DATA_FUNC(void)
10403 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10404 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10405 cvmx_warn("CVMX_PCI_WIN_WR_DATA not supported on this chip\n");
10407 return 0x0000000000000010ull;
10410 #define CVMX_PCI_WIN_WR_MASK CVMX_PCI_WIN_WR_MASK_FUNC()
10411 static inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void)
10413 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10414 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
10415 cvmx_warn("CVMX_PCI_WIN_WR_MASK not supported on this chip\n");
10417 return 0x0000000000000018ull;
10420 static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
10422 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10424 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10425 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10426 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10427 cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset);
10429 return CVMX_ADD_IO_SEG(0x0001070000010018ull) + (offset&3)*16384;
10432 static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
10434 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10436 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10437 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10438 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10439 cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset);
10441 return CVMX_ADD_IO_SEG(0x0001070000010020ull) + (offset&3)*16384;
10444 static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
10446 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10448 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10449 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10450 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10451 cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset);
10453 return CVMX_ADD_IO_SEG(0x0001070000010028ull) + (offset&3)*16384;
10456 static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
10458 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10460 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10461 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10462 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10463 cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset);
10465 return CVMX_ADD_IO_SEG(0x0001070000010068ull) + (offset&3)*16384;
10468 static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
10470 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10472 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10473 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10474 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10475 cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset);
10477 return CVMX_ADD_IO_SEG(0x0001070000010060ull) + (offset&3)*16384;
10480 static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
10482 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10484 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10485 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10486 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10487 cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset);
10489 return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + (offset&3)*16384;
10492 static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
10494 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10496 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10497 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10498 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10499 cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset);
10501 return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + (offset&3)*16384;
10504 static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
10506 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10508 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10509 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10510 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10511 cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset);
10513 return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + (offset&3)*16384;
10516 static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
10518 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10520 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10521 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10522 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10523 cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset);
10525 return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + (offset&3)*16384;
10528 static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
10530 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10532 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10533 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10534 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10535 cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset);
10537 return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + (offset&3)*16384;
10540 static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
10542 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10544 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10545 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10546 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10547 cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset);
10549 return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + (offset&3)*16384;
10552 static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
10554 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10556 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10557 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10558 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10559 cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset);
10561 return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + (offset&3)*16384;
10564 static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
10566 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10568 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10569 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10570 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10571 cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset);
10573 return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + (offset&3)*16384;
10576 static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
10578 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10580 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10581 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10582 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10583 cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset);
10585 return CVMX_ADD_IO_SEG(0x0001070000010058ull) + (offset&3)*16384;
10588 static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
10590 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10592 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10593 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10594 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10595 cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset);
10597 return CVMX_ADD_IO_SEG(0x0001070000010010ull) + (offset&3)*16384;
10600 static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
10602 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10604 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10605 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10606 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10607 cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset);
10609 return CVMX_ADD_IO_SEG(0x0001070000010030ull) + (offset&3)*16384;
10612 static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
10614 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10616 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10617 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10618 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10619 cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset);
10621 return CVMX_ADD_IO_SEG(0x0001070000010050ull) + (offset&3)*16384;
10624 static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
10626 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10628 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10629 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10630 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10631 cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset);
10633 return CVMX_ADD_IO_SEG(0x0001070000010048ull) + (offset&3)*16384;
10636 static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
10638 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10640 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10641 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10642 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10643 cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset);
10645 return CVMX_ADD_IO_SEG(0x0001070000010080ull) + (offset&3)*16384;
10648 static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
10650 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10652 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10653 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10654 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10655 cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset);
10657 return CVMX_ADD_IO_SEG(0x0001070000010088ull) + (offset&3)*16384;
10660 static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
10662 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10664 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10665 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10666 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10667 cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset);
10669 return CVMX_ADD_IO_SEG(0x0001070000010090ull) + (offset&3)*16384;
10672 static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
10674 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10676 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10677 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10678 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10679 cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset);
10681 return CVMX_ADD_IO_SEG(0x0001070000010098ull) + (offset&3)*16384;
10684 static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
10686 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10688 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10689 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10690 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10691 cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset);
10693 return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + (offset&3)*16384;
10696 static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
10698 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10700 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10701 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10702 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10703 cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset);
10705 return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + (offset&3)*16384;
10708 static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
10710 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10712 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10713 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10714 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10715 cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset);
10717 return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + (offset&3)*16384;
10720 static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
10722 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10724 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10725 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10726 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10727 cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset);
10729 return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + (offset&3)*16384;
10732 static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
10734 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10736 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
10737 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
10738 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
10739 cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset);
10741 return CVMX_ADD_IO_SEG(0x0001070000010040ull) + (offset&3)*16384;
10744 static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
10746 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10748 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
10749 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10750 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
10751 cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset);
10753 return CVMX_ADD_IO_SEG(0x0001070000010000ull) + (offset&1)*16384;
10756 static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
10758 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10760 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
10761 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10762 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
10763 cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset);
10765 return CVMX_ADD_IO_SEG(0x0001070000010038ull) + (offset&1)*16384;
10768 static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
10770 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10772 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
10773 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
10774 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
10775 cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset);
10777 return CVMX_ADD_IO_SEG(0x0001070000010008ull) + (offset&1)*16384;
10780 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
10782 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10784 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10785 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10786 cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG(%lu) is invalid on this chip\n", block_id);
10788 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id&1)*0x8000000ull;
10791 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
10793 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10795 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10796 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10797 cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG(%lu) is invalid on this chip\n", block_id);
10799 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id&1)*0x8000000ull;
10802 static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
10804 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10806 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10807 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10808 cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG(%lu) is invalid on this chip\n", block_id);
10810 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id&1)*0x8000000ull;
10813 static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
10815 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10817 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10818 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10819 cvmx_warn("CVMX_PCSXX_CONTROL1_REG(%lu) is invalid on this chip\n", block_id);
10821 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id&1)*0x8000000ull;
10824 static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
10826 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10828 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10829 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10830 cvmx_warn("CVMX_PCSXX_CONTROL2_REG(%lu) is invalid on this chip\n", block_id);
10832 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id&1)*0x8000000ull;
10835 static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
10837 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10839 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10840 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10841 cvmx_warn("CVMX_PCSXX_INT_EN_REG(%lu) is invalid on this chip\n", block_id);
10843 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id&1)*0x8000000ull;
10846 static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
10848 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10850 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10851 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10852 cvmx_warn("CVMX_PCSXX_INT_REG(%lu) is invalid on this chip\n", block_id);
10854 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id&1)*0x8000000ull;
10857 static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
10859 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10861 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10862 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10863 cvmx_warn("CVMX_PCSXX_LOG_ANL_REG(%lu) is invalid on this chip\n", block_id);
10865 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id&1)*0x8000000ull;
10868 static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
10870 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10872 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10873 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10874 cvmx_warn("CVMX_PCSXX_MISC_CTL_REG(%lu) is invalid on this chip\n", block_id);
10876 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id&1)*0x8000000ull;
10879 static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
10881 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10883 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10884 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10885 cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG(%lu) is invalid on this chip\n", block_id);
10887 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id&1)*0x8000000ull;
10890 static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
10892 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10894 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10895 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10896 cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG(%lu) is invalid on this chip\n", block_id);
10898 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id&1)*0x8000000ull;
10901 static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
10903 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10905 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10906 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10907 cvmx_warn("CVMX_PCSXX_STATUS1_REG(%lu) is invalid on this chip\n", block_id);
10909 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id&1)*0x8000000ull;
10912 static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
10914 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10916 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10917 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10918 cvmx_warn("CVMX_PCSXX_STATUS2_REG(%lu) is invalid on this chip\n", block_id);
10920 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id&1)*0x8000000ull;
10923 static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
10925 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10927 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10928 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10929 cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG(%lu) is invalid on this chip\n", block_id);
10931 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id&1)*0x8000000ull;
10934 static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
10936 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10938 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
10939 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
10940 cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG(%lu) is invalid on this chip\n", block_id);
10942 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id&1)*0x8000000ull;
10945 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
10947 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10949 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
10950 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
10951 cvmx_warn("CVMX_PCSX_ANX_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
10953 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
10956 static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
10958 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10960 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
10961 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
10962 cvmx_warn("CVMX_PCSX_ANX_EXT_ST_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
10964 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
10967 static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
10969 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10971 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
10972 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
10973 cvmx_warn("CVMX_PCSX_ANX_LP_ABIL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
10975 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
10978 static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
10980 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10982 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
10983 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
10984 cvmx_warn("CVMX_PCSX_ANX_RESULTS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
10986 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
10989 static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
10991 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10993 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
10994 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
10995 cvmx_warn("CVMX_PCSX_INTX_EN_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
10997 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11000 static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
11002 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11004 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11005 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11006 cvmx_warn("CVMX_PCSX_INTX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11008 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11011 static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
11013 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11015 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11016 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11017 cvmx_warn("CVMX_PCSX_LINKX_TIMER_COUNT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11019 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11022 static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
11024 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11026 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11027 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11028 cvmx_warn("CVMX_PCSX_LOG_ANLX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11030 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11033 static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
11035 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11037 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11038 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11039 cvmx_warn("CVMX_PCSX_MISCX_CTL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11041 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11044 static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
11046 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11048 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11049 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11050 cvmx_warn("CVMX_PCSX_MRX_CONTROL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11052 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11055 static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
11057 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11059 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11060 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11061 cvmx_warn("CVMX_PCSX_MRX_STATUS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11063 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11066 static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
11068 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11070 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11071 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11072 cvmx_warn("CVMX_PCSX_RXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11074 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11077 static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
11079 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11081 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11082 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11083 cvmx_warn("CVMX_PCSX_RXX_SYNC_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11085 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11088 static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
11090 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11092 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11093 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11094 cvmx_warn("CVMX_PCSX_SGMX_AN_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11096 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11099 static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
11101 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11103 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11104 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11105 cvmx_warn("CVMX_PCSX_SGMX_LP_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11107 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11110 static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
11112 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11114 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11115 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11116 cvmx_warn("CVMX_PCSX_TXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11118 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11121 static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
11123 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11125 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11126 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
11127 cvmx_warn("CVMX_PCSX_TX_RXX_POLARITY_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
11129 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
11132 static inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id)
11134 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11136 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11138 cvmx_warn("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
11140 return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + (block_id&1)*0x8000000ull;
11143 static inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id)
11145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11147 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11148 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11149 cvmx_warn("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
11151 return CVMX_ADD_IO_SEG(0x00011800C8000418ull) + (block_id&1)*0x8000000ull;
11154 static inline uint64_t CVMX_PESCX_CFG_RD(unsigned long block_id)
11156 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11158 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11159 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11160 cvmx_warn("CVMX_PESCX_CFG_RD(%lu) is invalid on this chip\n", block_id);
11162 return CVMX_ADD_IO_SEG(0x00011800C8000030ull) + (block_id&1)*0x8000000ull;
11165 static inline uint64_t CVMX_PESCX_CFG_WR(unsigned long block_id)
11167 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11169 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11170 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11171 cvmx_warn("CVMX_PESCX_CFG_WR(%lu) is invalid on this chip\n", block_id);
11173 return CVMX_ADD_IO_SEG(0x00011800C8000028ull) + (block_id&1)*0x8000000ull;
11176 static inline uint64_t CVMX_PESCX_CPL_LUT_VALID(unsigned long block_id)
11178 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11180 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11181 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11182 cvmx_warn("CVMX_PESCX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
11184 return CVMX_ADD_IO_SEG(0x00011800C8000098ull) + (block_id&1)*0x8000000ull;
11187 static inline uint64_t CVMX_PESCX_CTL_STATUS(unsigned long block_id)
11189 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11191 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11192 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11193 cvmx_warn("CVMX_PESCX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
11195 return CVMX_ADD_IO_SEG(0x00011800C8000000ull) + (block_id&1)*0x8000000ull;
11198 static inline uint64_t CVMX_PESCX_CTL_STATUS2(unsigned long block_id)
11200 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11202 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11203 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11204 cvmx_warn("CVMX_PESCX_CTL_STATUS2(%lu) is invalid on this chip\n", block_id);
11206 return CVMX_ADD_IO_SEG(0x00011800C8000400ull) + (block_id&1)*0x8000000ull;
11209 static inline uint64_t CVMX_PESCX_DBG_INFO(unsigned long block_id)
11211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11213 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11214 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11215 cvmx_warn("CVMX_PESCX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
11217 return CVMX_ADD_IO_SEG(0x00011800C8000008ull) + (block_id&1)*0x8000000ull;
11220 static inline uint64_t CVMX_PESCX_DBG_INFO_EN(unsigned long block_id)
11222 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11224 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11225 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11226 cvmx_warn("CVMX_PESCX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
11228 return CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + (block_id&1)*0x8000000ull;
11231 static inline uint64_t CVMX_PESCX_DIAG_STATUS(unsigned long block_id)
11233 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11235 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11236 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11237 cvmx_warn("CVMX_PESCX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
11239 return CVMX_ADD_IO_SEG(0x00011800C8000020ull) + (block_id&1)*0x8000000ull;
11242 static inline uint64_t CVMX_PESCX_P2N_BAR0_START(unsigned long block_id)
11244 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11246 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11247 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11248 cvmx_warn("CVMX_PESCX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
11250 return CVMX_ADD_IO_SEG(0x00011800C8000080ull) + (block_id&1)*0x8000000ull;
11253 static inline uint64_t CVMX_PESCX_P2N_BAR1_START(unsigned long block_id)
11255 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11257 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11258 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11259 cvmx_warn("CVMX_PESCX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
11261 return CVMX_ADD_IO_SEG(0x00011800C8000088ull) + (block_id&1)*0x8000000ull;
11264 static inline uint64_t CVMX_PESCX_P2N_BAR2_START(unsigned long block_id)
11266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11268 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11269 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11270 cvmx_warn("CVMX_PESCX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
11272 return CVMX_ADD_IO_SEG(0x00011800C8000090ull) + (block_id&1)*0x8000000ull;
11275 static inline uint64_t CVMX_PESCX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
11277 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11279 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11280 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1))))))
11281 cvmx_warn("CVMX_PESCX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
11283 return CVMX_ADD_IO_SEG(0x00011800C8000048ull) + ((offset&3) + (block_id&1)*0x800000ull)*16;
11286 static inline uint64_t CVMX_PESCX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
11288 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11290 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
11291 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1))))))
11292 cvmx_warn("CVMX_PESCX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
11294 return CVMX_ADD_IO_SEG(0x00011800C8000040ull) + ((offset&3) + (block_id&1)*0x800000ull)*16;
11297 static inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id)
11299 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11301 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
11302 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
11303 cvmx_warn("CVMX_PESCX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
11305 return CVMX_ADD_IO_SEG(0x00011800C8000038ull) + (block_id&1)*0x8000000ull;
11308 static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)
11310 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11312 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11313 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11314 cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
11316 return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + (offset&31)*16;
11319 #define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC()
11320 static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void)
11322 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11323 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11324 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n");
11326 return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
11329 #define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC()
11330 static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void)
11332 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11333 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11334 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n");
11336 return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
11339 #define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC()
11340 static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void)
11342 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11343 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11344 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n");
11346 return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
11349 #define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC()
11350 static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void)
11352 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11353 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11354 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n");
11356 return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
11359 #define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC()
11360 static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void)
11362 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11363 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11364 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n");
11366 return CVMX_ADD_IO_SEG(0x00011F0000008570ull);
11369 #define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC()
11370 static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void)
11372 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11373 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11374 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n");
11376 return CVMX_ADD_IO_SEG(0x00011F000000BC00ull);
11379 #define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC()
11380 static inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void)
11382 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11383 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11384 cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n");
11386 return CVMX_ADD_IO_SEG(0x00011F00000085F0ull);
11389 #define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC()
11390 static inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void)
11392 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11393 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11394 cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n");
11396 return CVMX_ADD_IO_SEG(0x00011F0000008510ull);
11399 #define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC()
11400 static inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void)
11402 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11403 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11404 cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n");
11406 return CVMX_ADD_IO_SEG(0x00011F0000008500ull);
11409 #define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC()
11410 static inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void)
11412 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11413 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11414 cvmx_warn("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
11416 return CVMX_ADD_IO_SEG(0x00011F00000085C0ull);
11419 #define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC()
11420 static inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void)
11422 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11423 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11424 cvmx_warn("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
11426 return CVMX_ADD_IO_SEG(0x00011F00000085D0ull);
11429 static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)
11431 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11433 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
11434 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
11435 cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
11437 return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + (offset&7)*16;
11440 static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)
11442 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11444 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
11445 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
11446 cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
11448 return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + (offset&7)*16;
11451 static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
11453 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11455 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
11456 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
11457 cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
11459 return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + (offset&7)*16;
11462 static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)
11464 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11466 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
11467 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
11468 cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
11470 return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + (offset&7)*16;
11473 #define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC()
11474 static inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void)
11476 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11477 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11478 cvmx_warn("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n");
11480 return CVMX_ADD_IO_SEG(0x00011F00000085E0ull);
11483 #define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC()
11484 static inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void)
11486 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11487 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11488 cvmx_warn("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n");
11490 return CVMX_ADD_IO_SEG(0x00011F00000083A0ull);
11493 #define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC()
11494 static inline uint64_t CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
11496 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11497 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11498 cvmx_warn("CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
11500 return CVMX_ADD_IO_SEG(0x00011F00000085B0ull);
11503 #define CVMX_PEXP_NPEI_DMA_STATE1 CVMX_PEXP_NPEI_DMA_STATE1_FUNC()
11504 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void)
11506 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11507 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
11508 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE1 not supported on this chip\n");
11510 return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
11513 #define CVMX_PEXP_NPEI_DMA_STATE1_P1 CVMX_PEXP_NPEI_DMA_STATE1_P1_FUNC()
11514 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_P1_FUNC(void)
11516 return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
11519 #define CVMX_PEXP_NPEI_DMA_STATE2 CVMX_PEXP_NPEI_DMA_STATE2_FUNC()
11520 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void)
11522 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11523 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
11524 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE2 not supported on this chip\n");
11526 return CVMX_ADD_IO_SEG(0x00011F00000086D0ull);
11529 #define CVMX_PEXP_NPEI_DMA_STATE2_P1 CVMX_PEXP_NPEI_DMA_STATE2_P1_FUNC()
11530 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_P1_FUNC(void)
11532 return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
11535 #define CVMX_PEXP_NPEI_DMA_STATE3_P1 CVMX_PEXP_NPEI_DMA_STATE3_P1_FUNC()
11536 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE3_P1_FUNC(void)
11538 return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
11541 #define CVMX_PEXP_NPEI_DMA_STATE4_P1 CVMX_PEXP_NPEI_DMA_STATE4_P1_FUNC()
11542 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE4_P1_FUNC(void)
11544 return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
11547 #define CVMX_PEXP_NPEI_DMA_STATE5_P1 CVMX_PEXP_NPEI_DMA_STATE5_P1_FUNC()
11548 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE5_P1_FUNC(void)
11550 return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
11553 #define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC()
11554 static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void)
11556 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11557 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11558 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n");
11560 return CVMX_ADD_IO_SEG(0x00011F0000008560ull);
11563 #define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC()
11564 static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void)
11566 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11567 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11568 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n");
11570 return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull);
11573 #define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC()
11574 static inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void)
11576 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11577 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11578 cvmx_warn("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n");
11580 return CVMX_ADD_IO_SEG(0x00011F0000008550ull);
11583 #define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC()
11584 static inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void)
11586 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11587 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11588 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n");
11590 return CVMX_ADD_IO_SEG(0x00011F0000008540ull);
11593 #define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC()
11594 static inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void)
11596 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11597 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11598 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n");
11600 return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull);
11603 #define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC()
11604 static inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void)
11606 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11607 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11608 cvmx_warn("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n");
11610 return CVMX_ADD_IO_SEG(0x00011F0000008590ull);
11613 #define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC()
11614 static inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void)
11616 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11617 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11618 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n");
11620 return CVMX_ADD_IO_SEG(0x00011F0000008530ull);
11623 #define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC()
11624 static inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void)
11626 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11627 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11628 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n");
11630 return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull);
11633 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC()
11634 static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void)
11636 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11637 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11638 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
11640 return CVMX_ADD_IO_SEG(0x00011F0000008600ull);
11643 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC()
11644 static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void)
11646 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11647 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11648 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
11650 return CVMX_ADD_IO_SEG(0x00011F0000008610ull);
11653 #define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC()
11654 static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void)
11656 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11657 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11658 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
11660 return CVMX_ADD_IO_SEG(0x00011F00000084F0ull);
11663 static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
11665 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11667 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))) ||
11668 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27))))))
11669 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
11671 return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + (offset&31)*16 - 16*12;
11674 #define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC()
11675 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void)
11677 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11678 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11679 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n");
11681 return CVMX_ADD_IO_SEG(0x00011F000000BC50ull);
11684 #define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC()
11685 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void)
11687 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11688 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11689 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n");
11691 return CVMX_ADD_IO_SEG(0x00011F000000BC60ull);
11694 #define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC()
11695 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void)
11697 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11698 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11699 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n");
11701 return CVMX_ADD_IO_SEG(0x00011F000000BC70ull);
11704 #define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC()
11705 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void)
11707 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11708 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11709 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n");
11711 return CVMX_ADD_IO_SEG(0x00011F000000BC80ull);
11714 #define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC()
11715 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void)
11717 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11718 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11719 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n");
11721 return CVMX_ADD_IO_SEG(0x00011F000000BC10ull);
11724 #define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC()
11725 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void)
11727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11728 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11729 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n");
11731 return CVMX_ADD_IO_SEG(0x00011F000000BC20ull);
11734 #define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC()
11735 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void)
11737 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11738 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11739 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n");
11741 return CVMX_ADD_IO_SEG(0x00011F000000BC30ull);
11744 #define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC()
11745 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void)
11747 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11748 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11749 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n");
11751 return CVMX_ADD_IO_SEG(0x00011F000000BC40ull);
11754 #define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC()
11755 static inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void)
11757 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11758 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11759 cvmx_warn("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n");
11761 return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull);
11764 #define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC()
11765 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void)
11767 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11768 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11769 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
11771 return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull);
11774 #define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC()
11775 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void)
11777 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11778 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11779 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
11781 return CVMX_ADD_IO_SEG(0x00011F000000BD00ull);
11784 #define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC()
11785 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void)
11787 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11788 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11789 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
11791 return CVMX_ADD_IO_SEG(0x00011F000000BD10ull);
11794 #define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC()
11795 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void)
11797 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11798 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11799 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
11801 return CVMX_ADD_IO_SEG(0x00011F000000BD20ull);
11804 #define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC()
11805 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void)
11807 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11808 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11809 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
11811 return CVMX_ADD_IO_SEG(0x00011F000000BD30ull);
11814 #define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC()
11815 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void)
11817 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11818 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11819 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
11821 return CVMX_ADD_IO_SEG(0x00011F000000BD40ull);
11824 #define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC()
11825 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void)
11827 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11828 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11829 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
11831 return CVMX_ADD_IO_SEG(0x00011F000000BD50ull);
11834 #define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC()
11835 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void)
11837 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11838 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11839 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
11841 return CVMX_ADD_IO_SEG(0x00011F000000BD60ull);
11844 #define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC()
11845 static inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void)
11847 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11848 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11849 cvmx_warn("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n");
11851 return CVMX_ADD_IO_SEG(0x00011F000000BC90ull);
11854 #define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC()
11855 static inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void)
11857 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11858 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11859 cvmx_warn("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
11861 return CVMX_ADD_IO_SEG(0x00011F000000BD70ull);
11864 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC()
11865 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void)
11867 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11868 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11869 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n");
11871 return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull);
11874 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC()
11875 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
11877 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11878 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11879 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
11881 return CVMX_ADD_IO_SEG(0x00011F0000008650ull);
11884 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC()
11885 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
11887 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11888 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11889 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
11891 return CVMX_ADD_IO_SEG(0x00011F0000008660ull);
11894 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC()
11895 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
11897 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11898 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
11899 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
11901 return CVMX_ADD_IO_SEG(0x00011F0000008670ull);
11904 static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)
11906 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11908 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11909 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11910 cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
11912 return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + (offset&31)*16;
11915 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
11917 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11919 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11920 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11921 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
11923 return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + (offset&31)*16;
11926 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
11928 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11930 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11931 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11932 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
11934 return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + (offset&31)*16;
11937 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
11939 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11941 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11942 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11943 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
11945 return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + (offset&31)*16;
11948 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
11950 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11952 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11953 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11954 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
11956 return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + (offset&31)*16;
11959 static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)
11961 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11963 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11964 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11965 cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
11967 return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + (offset&31)*16;
11970 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
11972 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11974 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11975 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11976 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
11978 return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + (offset&31)*16;
11981 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
11983 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11985 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11986 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11987 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
11989 return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + (offset&31)*16;
11992 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
11994 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11996 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
11997 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
11998 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
12000 return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + (offset&31)*16;
12003 #define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC()
12004 static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void)
12006 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12007 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12008 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n");
12010 return CVMX_ADD_IO_SEG(0x00011F0000009110ull);
12013 #define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC()
12014 static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void)
12016 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12017 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12018 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
12020 return CVMX_ADD_IO_SEG(0x00011F0000009130ull);
12023 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC()
12024 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void)
12026 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12027 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12028 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
12030 return CVMX_ADD_IO_SEG(0x00011F00000090B0ull);
12033 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC()
12034 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void)
12036 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12037 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12038 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
12040 return CVMX_ADD_IO_SEG(0x00011F00000090A0ull);
12043 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC()
12044 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
12046 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12047 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12048 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
12050 return CVMX_ADD_IO_SEG(0x00011F0000009090ull);
12053 #define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC()
12054 static inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void)
12056 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12057 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12058 cvmx_warn("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n");
12060 return CVMX_ADD_IO_SEG(0x00011F0000009080ull);
12063 #define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC()
12064 static inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void)
12066 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12067 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12068 cvmx_warn("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
12070 return CVMX_ADD_IO_SEG(0x00011F0000009150ull);
12073 #define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC()
12074 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void)
12076 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12077 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12078 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n");
12080 return CVMX_ADD_IO_SEG(0x00011F0000009000ull);
12083 #define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC()
12084 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
12086 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12087 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12088 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
12090 return CVMX_ADD_IO_SEG(0x00011F0000009190ull);
12093 #define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC()
12094 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void)
12096 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12097 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12098 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
12100 return CVMX_ADD_IO_SEG(0x00011F0000009020ull);
12103 #define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC()
12104 static inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void)
12106 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12107 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12108 cvmx_warn("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n");
12110 return CVMX_ADD_IO_SEG(0x00011F0000009100ull);
12113 #define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC()
12114 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void)
12116 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12117 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12118 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n");
12120 return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
12123 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
12125 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12127 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
12128 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
12129 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
12131 return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + (offset&31)*16;
12134 #define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
12135 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
12137 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12138 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12139 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
12141 return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
12144 #define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC()
12145 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
12147 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12148 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12149 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
12151 return CVMX_ADD_IO_SEG(0x00011F00000091A0ull);
12154 #define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC()
12155 static inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void)
12157 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12158 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12159 cvmx_warn("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n");
12161 return CVMX_ADD_IO_SEG(0x00011F0000009070ull);
12164 #define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC()
12165 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
12167 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12168 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12169 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
12171 return CVMX_ADD_IO_SEG(0x00011F0000009160ull);
12174 #define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC()
12175 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void)
12177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12178 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12179 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n");
12181 return CVMX_ADD_IO_SEG(0x00011F00000090D0ull);
12184 #define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC()
12185 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void)
12187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12188 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12189 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n");
12191 return CVMX_ADD_IO_SEG(0x00011F0000009010ull);
12194 #define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC()
12195 static inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void)
12197 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12198 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12199 cvmx_warn("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n");
12201 return CVMX_ADD_IO_SEG(0x00011F00000090E0ull);
12204 #define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC()
12205 static inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void)
12207 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12208 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12209 cvmx_warn("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
12211 return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
12214 #define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC()
12215 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void)
12217 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12218 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12219 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n");
12221 return CVMX_ADD_IO_SEG(0x00011F0000009050ull);
12224 #define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC()
12225 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
12227 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12228 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12229 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
12231 return CVMX_ADD_IO_SEG(0x00011F0000009180ull);
12234 #define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC()
12235 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void)
12237 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12238 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12239 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n");
12241 return CVMX_ADD_IO_SEG(0x00011F0000009040ull);
12244 #define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC()
12245 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void)
12247 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12248 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12249 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n");
12251 return CVMX_ADD_IO_SEG(0x00011F0000009030ull);
12254 #define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC()
12255 static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void)
12257 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12258 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12259 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n");
12261 return CVMX_ADD_IO_SEG(0x00011F0000009120ull);
12264 #define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC()
12265 static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void)
12267 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12268 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12269 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
12271 return CVMX_ADD_IO_SEG(0x00011F0000009140ull);
12274 #define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC()
12275 static inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void)
12277 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12278 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12279 cvmx_warn("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
12281 return CVMX_ADD_IO_SEG(0x00011F0000008520ull);
12284 #define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC()
12285 static inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void)
12287 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12288 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12289 cvmx_warn("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n");
12291 return CVMX_ADD_IO_SEG(0x00011F0000008270ull);
12294 #define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC()
12295 static inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void)
12297 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12298 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12299 cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n");
12301 return CVMX_ADD_IO_SEG(0x00011F0000008620ull);
12304 #define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC()
12305 static inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void)
12307 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12308 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12309 cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n");
12311 return CVMX_ADD_IO_SEG(0x00011F0000008630ull);
12314 #define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC()
12315 static inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void)
12317 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12318 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12319 cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n");
12321 return CVMX_ADD_IO_SEG(0x00011F0000008640ull);
12324 #define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC()
12325 static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)
12327 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12328 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12329 cvmx_warn("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n");
12331 return CVMX_ADD_IO_SEG(0x00011F0000008380ull);
12334 #define CVMX_PIP_BCK_PRS CVMX_PIP_BCK_PRS_FUNC()
12335 static inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void)
12337 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12338 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
12339 cvmx_warn("CVMX_PIP_BCK_PRS not supported on this chip\n");
12341 return CVMX_ADD_IO_SEG(0x00011800A0000038ull);
12344 #define CVMX_PIP_BIST_STATUS CVMX_PIP_BIST_STATUS_FUNC()
12345 static inline uint64_t CVMX_PIP_BIST_STATUS_FUNC(void)
12347 return CVMX_ADD_IO_SEG(0x00011800A0000000ull);
12350 static inline uint64_t CVMX_PIP_CRC_CTLX(unsigned long offset)
12352 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12354 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
12355 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
12356 cvmx_warn("CVMX_PIP_CRC_CTLX(%lu) is invalid on this chip\n", offset);
12358 return CVMX_ADD_IO_SEG(0x00011800A0000040ull) + (offset&1)*8;
12361 static inline uint64_t CVMX_PIP_CRC_IVX(unsigned long offset)
12363 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12365 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
12366 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
12367 cvmx_warn("CVMX_PIP_CRC_IVX(%lu) is invalid on this chip\n", offset);
12369 return CVMX_ADD_IO_SEG(0x00011800A0000050ull) + (offset&1)*8;
12372 static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset)
12374 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12376 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
12377 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
12378 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
12379 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
12380 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
12381 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
12382 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
12383 cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n", offset);
12385 return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + (offset&3)*8;
12388 #define CVMX_PIP_DSA_SRC_GRP CVMX_PIP_DSA_SRC_GRP_FUNC()
12389 static inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void)
12391 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12392 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12393 cvmx_warn("CVMX_PIP_DSA_SRC_GRP not supported on this chip\n");
12395 return CVMX_ADD_IO_SEG(0x00011800A0000190ull);
12398 #define CVMX_PIP_DSA_VID_GRP CVMX_PIP_DSA_VID_GRP_FUNC()
12399 static inline uint64_t CVMX_PIP_DSA_VID_GRP_FUNC(void)
12401 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12402 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12403 cvmx_warn("CVMX_PIP_DSA_VID_GRP not supported on this chip\n");
12405 return CVMX_ADD_IO_SEG(0x00011800A0000198ull);
12408 static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)
12410 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12412 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
12413 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
12414 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
12415 cvmx_warn("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n", offset);
12417 return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + (offset&1)*8;
12420 #define CVMX_PIP_GBL_CFG CVMX_PIP_GBL_CFG_FUNC()
12421 static inline uint64_t CVMX_PIP_GBL_CFG_FUNC(void)
12423 return CVMX_ADD_IO_SEG(0x00011800A0000028ull);
12426 #define CVMX_PIP_GBL_CTL CVMX_PIP_GBL_CTL_FUNC()
12427 static inline uint64_t CVMX_PIP_GBL_CTL_FUNC(void)
12429 return CVMX_ADD_IO_SEG(0x00011800A0000020ull);
12432 #define CVMX_PIP_HG_PRI_QOS CVMX_PIP_HG_PRI_QOS_FUNC()
12433 static inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void)
12435 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12436 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12437 cvmx_warn("CVMX_PIP_HG_PRI_QOS not supported on this chip\n");
12439 return CVMX_ADD_IO_SEG(0x00011800A00001A0ull);
12442 #define CVMX_PIP_INT_EN CVMX_PIP_INT_EN_FUNC()
12443 static inline uint64_t CVMX_PIP_INT_EN_FUNC(void)
12445 return CVMX_ADD_IO_SEG(0x00011800A0000010ull);
12448 #define CVMX_PIP_INT_REG CVMX_PIP_INT_REG_FUNC()
12449 static inline uint64_t CVMX_PIP_INT_REG_FUNC(void)
12451 return CVMX_ADD_IO_SEG(0x00011800A0000008ull);
12454 #define CVMX_PIP_IP_OFFSET CVMX_PIP_IP_OFFSET_FUNC()
12455 static inline uint64_t CVMX_PIP_IP_OFFSET_FUNC(void)
12457 return CVMX_ADD_IO_SEG(0x00011800A0000060ull);
12460 static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset)
12462 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12464 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12465 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12466 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12467 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12468 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12469 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12470 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12471 cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n", offset);
12473 return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + (offset&63)*8;
12476 static inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset)
12478 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12480 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12481 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12482 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12483 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12484 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12485 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12486 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12487 cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n", offset);
12489 return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + (offset&63)*8;
12492 static inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset)
12494 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12496 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
12497 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
12498 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
12499 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
12500 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
12501 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
12502 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63)))))
12503 cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n", offset);
12505 return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + (offset&63)*8;
12508 static inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset)
12510 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12512 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
12513 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
12514 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
12515 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
12516 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
12517 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
12518 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
12519 cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n", offset);
12521 return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + (offset&7)*8;
12524 static inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset)
12526 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12528 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
12529 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
12530 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
12531 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
12532 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
12533 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
12534 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
12535 cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n", offset);
12537 return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + (offset&7)*8;
12540 #define CVMX_PIP_RAW_WORD CVMX_PIP_RAW_WORD_FUNC()
12541 static inline uint64_t CVMX_PIP_RAW_WORD_FUNC(void)
12543 return CVMX_ADD_IO_SEG(0x00011800A00000B0ull);
12546 #define CVMX_PIP_SFT_RST CVMX_PIP_SFT_RST_FUNC()
12547 static inline uint64_t CVMX_PIP_SFT_RST_FUNC(void)
12549 return CVMX_ADD_IO_SEG(0x00011800A0000030ull);
12552 static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset)
12554 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12556 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12557 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12558 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12559 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12560 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12561 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12562 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12563 cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n", offset);
12565 return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + (offset&63)*80;
12568 static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
12570 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12572 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12573 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12574 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12575 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12576 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12577 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12578 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12579 cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n", offset);
12581 return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + (offset&63)*80;
12584 static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
12586 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12588 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12589 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12590 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12591 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12592 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12593 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12594 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12595 cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n", offset);
12597 return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + (offset&63)*80;
12600 static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
12602 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12604 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12605 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12606 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12607 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12608 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12609 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12610 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12611 cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n", offset);
12613 return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + (offset&63)*80;
12616 static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
12618 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12620 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12621 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12622 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12623 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12624 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12625 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12626 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12627 cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n", offset);
12629 return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + (offset&63)*80;
12632 static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
12634 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12636 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12637 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12638 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12639 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12640 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12641 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12642 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12643 cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n", offset);
12645 return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + (offset&63)*80;
12648 static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
12650 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12652 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12653 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12654 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12655 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12656 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12657 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12658 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12659 cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n", offset);
12661 return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + (offset&63)*80;
12664 static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
12666 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12668 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12669 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12670 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12671 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12672 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12673 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12674 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12675 cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n", offset);
12677 return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + (offset&63)*80;
12680 static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
12682 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12685 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12686 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12687 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12688 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12689 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12690 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12691 cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n", offset);
12693 return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + (offset&63)*80;
12696 static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset)
12698 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12700 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12701 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12702 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12703 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12704 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12705 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12706 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12707 cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n", offset);
12709 return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + (offset&63)*80;
12712 #define CVMX_PIP_STAT_CTL CVMX_PIP_STAT_CTL_FUNC()
12713 static inline uint64_t CVMX_PIP_STAT_CTL_FUNC(void)
12715 return CVMX_ADD_IO_SEG(0x00011800A0000018ull);
12718 static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
12720 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12722 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12723 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12724 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12725 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12726 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12727 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12728 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12729 cvmx_warn("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n", offset);
12731 return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + (offset&63)*32;
12734 static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
12736 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12738 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12739 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12740 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12741 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12742 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12743 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12744 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12745 cvmx_warn("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n", offset);
12747 return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + (offset&63)*32;
12750 static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
12752 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12754 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
12755 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12756 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12757 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
12758 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
12759 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
12760 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
12761 cvmx_warn("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n", offset);
12763 return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + (offset&63)*32;
12766 static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
12768 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12770 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
12771 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
12772 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
12773 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
12774 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
12775 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
12776 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63)))))
12777 cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n", offset);
12779 return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + (offset&63)*8;
12782 #define CVMX_PIP_TAG_MASK CVMX_PIP_TAG_MASK_FUNC()
12783 static inline uint64_t CVMX_PIP_TAG_MASK_FUNC(void)
12785 return CVMX_ADD_IO_SEG(0x00011800A0000070ull);
12788 #define CVMX_PIP_TAG_SECRET CVMX_PIP_TAG_SECRET_FUNC()
12789 static inline uint64_t CVMX_PIP_TAG_SECRET_FUNC(void)
12791 return CVMX_ADD_IO_SEG(0x00011800A0000068ull);
12794 #define CVMX_PIP_TODO_ENTRY CVMX_PIP_TODO_ENTRY_FUNC()
12795 static inline uint64_t CVMX_PIP_TODO_ENTRY_FUNC(void)
12797 return CVMX_ADD_IO_SEG(0x00011800A0000078ull);
12800 #define CVMX_PKO_MEM_COUNT0 CVMX_PKO_MEM_COUNT0_FUNC()
12801 static inline uint64_t CVMX_PKO_MEM_COUNT0_FUNC(void)
12803 return CVMX_ADD_IO_SEG(0x0001180050001080ull);
12806 #define CVMX_PKO_MEM_COUNT1 CVMX_PKO_MEM_COUNT1_FUNC()
12807 static inline uint64_t CVMX_PKO_MEM_COUNT1_FUNC(void)
12809 return CVMX_ADD_IO_SEG(0x0001180050001088ull);
12812 #define CVMX_PKO_MEM_DEBUG0 CVMX_PKO_MEM_DEBUG0_FUNC()
12813 static inline uint64_t CVMX_PKO_MEM_DEBUG0_FUNC(void)
12815 return CVMX_ADD_IO_SEG(0x0001180050001100ull);
12818 #define CVMX_PKO_MEM_DEBUG1 CVMX_PKO_MEM_DEBUG1_FUNC()
12819 static inline uint64_t CVMX_PKO_MEM_DEBUG1_FUNC(void)
12821 return CVMX_ADD_IO_SEG(0x0001180050001108ull);
12824 #define CVMX_PKO_MEM_DEBUG10 CVMX_PKO_MEM_DEBUG10_FUNC()
12825 static inline uint64_t CVMX_PKO_MEM_DEBUG10_FUNC(void)
12827 return CVMX_ADD_IO_SEG(0x0001180050001150ull);
12830 #define CVMX_PKO_MEM_DEBUG11 CVMX_PKO_MEM_DEBUG11_FUNC()
12831 static inline uint64_t CVMX_PKO_MEM_DEBUG11_FUNC(void)
12833 return CVMX_ADD_IO_SEG(0x0001180050001158ull);
12836 #define CVMX_PKO_MEM_DEBUG12 CVMX_PKO_MEM_DEBUG12_FUNC()
12837 static inline uint64_t CVMX_PKO_MEM_DEBUG12_FUNC(void)
12839 return CVMX_ADD_IO_SEG(0x0001180050001160ull);
12842 #define CVMX_PKO_MEM_DEBUG13 CVMX_PKO_MEM_DEBUG13_FUNC()
12843 static inline uint64_t CVMX_PKO_MEM_DEBUG13_FUNC(void)
12845 return CVMX_ADD_IO_SEG(0x0001180050001168ull);
12848 #define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC()
12849 static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
12851 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12852 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12853 cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n");
12855 return CVMX_ADD_IO_SEG(0x0001180050001170ull);
12858 #define CVMX_PKO_MEM_DEBUG2 CVMX_PKO_MEM_DEBUG2_FUNC()
12859 static inline uint64_t CVMX_PKO_MEM_DEBUG2_FUNC(void)
12861 return CVMX_ADD_IO_SEG(0x0001180050001110ull);
12864 #define CVMX_PKO_MEM_DEBUG3 CVMX_PKO_MEM_DEBUG3_FUNC()
12865 static inline uint64_t CVMX_PKO_MEM_DEBUG3_FUNC(void)
12867 return CVMX_ADD_IO_SEG(0x0001180050001118ull);
12870 #define CVMX_PKO_MEM_DEBUG4 CVMX_PKO_MEM_DEBUG4_FUNC()
12871 static inline uint64_t CVMX_PKO_MEM_DEBUG4_FUNC(void)
12873 return CVMX_ADD_IO_SEG(0x0001180050001120ull);
12876 #define CVMX_PKO_MEM_DEBUG5 CVMX_PKO_MEM_DEBUG5_FUNC()
12877 static inline uint64_t CVMX_PKO_MEM_DEBUG5_FUNC(void)
12879 return CVMX_ADD_IO_SEG(0x0001180050001128ull);
12882 #define CVMX_PKO_MEM_DEBUG6 CVMX_PKO_MEM_DEBUG6_FUNC()
12883 static inline uint64_t CVMX_PKO_MEM_DEBUG6_FUNC(void)
12885 return CVMX_ADD_IO_SEG(0x0001180050001130ull);
12888 #define CVMX_PKO_MEM_DEBUG7 CVMX_PKO_MEM_DEBUG7_FUNC()
12889 static inline uint64_t CVMX_PKO_MEM_DEBUG7_FUNC(void)
12891 return CVMX_ADD_IO_SEG(0x0001180050001138ull);
12894 #define CVMX_PKO_MEM_DEBUG8 CVMX_PKO_MEM_DEBUG8_FUNC()
12895 static inline uint64_t CVMX_PKO_MEM_DEBUG8_FUNC(void)
12897 return CVMX_ADD_IO_SEG(0x0001180050001140ull);
12900 #define CVMX_PKO_MEM_DEBUG9 CVMX_PKO_MEM_DEBUG9_FUNC()
12901 static inline uint64_t CVMX_PKO_MEM_DEBUG9_FUNC(void)
12903 return CVMX_ADD_IO_SEG(0x0001180050001148ull);
12906 #define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC()
12907 static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
12909 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12910 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12911 cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n");
12913 return CVMX_ADD_IO_SEG(0x0001180050001010ull);
12916 #define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC()
12917 static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
12919 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12920 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12921 cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n");
12923 return CVMX_ADD_IO_SEG(0x0001180050001018ull);
12926 #define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC()
12927 static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
12929 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12930 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12931 cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n");
12933 return CVMX_ADD_IO_SEG(0x0001180050001020ull);
12936 #define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC()
12937 static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void)
12939 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12940 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
12941 cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n");
12943 return CVMX_ADD_IO_SEG(0x0001180050001028ull);
12946 #define CVMX_PKO_MEM_QUEUE_PTRS CVMX_PKO_MEM_QUEUE_PTRS_FUNC()
12947 static inline uint64_t CVMX_PKO_MEM_QUEUE_PTRS_FUNC(void)
12949 return CVMX_ADD_IO_SEG(0x0001180050001000ull);
12952 #define CVMX_PKO_MEM_QUEUE_QOS CVMX_PKO_MEM_QUEUE_QOS_FUNC()
12953 static inline uint64_t CVMX_PKO_MEM_QUEUE_QOS_FUNC(void)
12955 return CVMX_ADD_IO_SEG(0x0001180050001008ull);
12958 #define CVMX_PKO_REG_BIST_RESULT CVMX_PKO_REG_BIST_RESULT_FUNC()
12959 static inline uint64_t CVMX_PKO_REG_BIST_RESULT_FUNC(void)
12961 return CVMX_ADD_IO_SEG(0x0001180050000080ull);
12964 #define CVMX_PKO_REG_CMD_BUF CVMX_PKO_REG_CMD_BUF_FUNC()
12965 static inline uint64_t CVMX_PKO_REG_CMD_BUF_FUNC(void)
12967 return CVMX_ADD_IO_SEG(0x0001180050000010ull);
12970 static inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset)
12972 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12974 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
12975 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
12976 cvmx_warn("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n", offset);
12978 return CVMX_ADD_IO_SEG(0x0001180050000028ull) + (offset&1)*8;
12981 #define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC()
12982 static inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void)
12984 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12985 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
12986 cvmx_warn("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n");
12988 return CVMX_ADD_IO_SEG(0x0001180050000020ull);
12991 static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset)
12993 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12995 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
12996 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
12997 cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n", offset);
12999 return CVMX_ADD_IO_SEG(0x0001180050000038ull) + (offset&1)*8;
13002 #define CVMX_PKO_REG_DEBUG0 CVMX_PKO_REG_DEBUG0_FUNC()
13003 static inline uint64_t CVMX_PKO_REG_DEBUG0_FUNC(void)
13005 return CVMX_ADD_IO_SEG(0x0001180050000098ull);
13008 #define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC()
13009 static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
13011 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13012 if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
13013 cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n");
13015 return CVMX_ADD_IO_SEG(0x00011800500000A0ull);
13018 #define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC()
13019 static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
13021 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13022 if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
13023 cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n");
13025 return CVMX_ADD_IO_SEG(0x00011800500000A8ull);
13028 #define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC()
13029 static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
13031 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13032 if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
13033 cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n");
13035 return CVMX_ADD_IO_SEG(0x00011800500000B0ull);
13038 #define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC()
13039 static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
13041 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13042 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13043 cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n");
13045 return CVMX_ADD_IO_SEG(0x0001180050000050ull);
13048 #define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC()
13049 static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
13051 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13052 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13053 cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n");
13055 return CVMX_ADD_IO_SEG(0x0001180050000058ull);
13058 #define CVMX_PKO_REG_ERROR CVMX_PKO_REG_ERROR_FUNC()
13059 static inline uint64_t CVMX_PKO_REG_ERROR_FUNC(void)
13061 return CVMX_ADD_IO_SEG(0x0001180050000088ull);
13064 #define CVMX_PKO_REG_FLAGS CVMX_PKO_REG_FLAGS_FUNC()
13065 static inline uint64_t CVMX_PKO_REG_FLAGS_FUNC(void)
13067 return CVMX_ADD_IO_SEG(0x0001180050000000ull);
13070 #define CVMX_PKO_REG_GMX_PORT_MODE CVMX_PKO_REG_GMX_PORT_MODE_FUNC()
13071 static inline uint64_t CVMX_PKO_REG_GMX_PORT_MODE_FUNC(void)
13073 return CVMX_ADD_IO_SEG(0x0001180050000018ull);
13076 #define CVMX_PKO_REG_INT_MASK CVMX_PKO_REG_INT_MASK_FUNC()
13077 static inline uint64_t CVMX_PKO_REG_INT_MASK_FUNC(void)
13079 return CVMX_ADD_IO_SEG(0x0001180050000090ull);
13082 #define CVMX_PKO_REG_QUEUE_MODE CVMX_PKO_REG_QUEUE_MODE_FUNC()
13083 static inline uint64_t CVMX_PKO_REG_QUEUE_MODE_FUNC(void)
13085 return CVMX_ADD_IO_SEG(0x0001180050000048ull);
13088 #define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC()
13089 static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
13091 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13092 if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
13093 cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n");
13095 return CVMX_ADD_IO_SEG(0x0001180050000100ull);
13098 #define CVMX_PKO_REG_READ_IDX CVMX_PKO_REG_READ_IDX_FUNC()
13099 static inline uint64_t CVMX_PKO_REG_READ_IDX_FUNC(void)
13101 return CVMX_ADD_IO_SEG(0x0001180050000008ull);
13104 #define CVMX_POW_BIST_STAT CVMX_POW_BIST_STAT_FUNC()
13105 static inline uint64_t CVMX_POW_BIST_STAT_FUNC(void)
13107 return CVMX_ADD_IO_SEG(0x00016700000003F8ull);
13110 #define CVMX_POW_DS_PC CVMX_POW_DS_PC_FUNC()
13111 static inline uint64_t CVMX_POW_DS_PC_FUNC(void)
13113 return CVMX_ADD_IO_SEG(0x0001670000000398ull);
13116 #define CVMX_POW_ECC_ERR CVMX_POW_ECC_ERR_FUNC()
13117 static inline uint64_t CVMX_POW_ECC_ERR_FUNC(void)
13119 return CVMX_ADD_IO_SEG(0x0001670000000218ull);
13122 #define CVMX_POW_INT_CTL CVMX_POW_INT_CTL_FUNC()
13123 static inline uint64_t CVMX_POW_INT_CTL_FUNC(void)
13125 return CVMX_ADD_IO_SEG(0x0001670000000220ull);
13128 static inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset)
13130 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13132 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
13133 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
13134 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
13135 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
13136 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
13137 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
13138 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
13139 cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n", offset);
13141 return CVMX_ADD_IO_SEG(0x0001670000000340ull) + (offset&7)*8;
13144 #define CVMX_POW_IQ_COM_CNT CVMX_POW_IQ_COM_CNT_FUNC()
13145 static inline uint64_t CVMX_POW_IQ_COM_CNT_FUNC(void)
13147 return CVMX_ADD_IO_SEG(0x0001670000000388ull);
13150 #define CVMX_POW_IQ_INT CVMX_POW_IQ_INT_FUNC()
13151 static inline uint64_t CVMX_POW_IQ_INT_FUNC(void)
13153 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13154 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13155 cvmx_warn("CVMX_POW_IQ_INT not supported on this chip\n");
13157 return CVMX_ADD_IO_SEG(0x0001670000000238ull);
13160 #define CVMX_POW_IQ_INT_EN CVMX_POW_IQ_INT_EN_FUNC()
13161 static inline uint64_t CVMX_POW_IQ_INT_EN_FUNC(void)
13163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13164 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13165 cvmx_warn("CVMX_POW_IQ_INT_EN not supported on this chip\n");
13167 return CVMX_ADD_IO_SEG(0x0001670000000240ull);
13170 static inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset)
13172 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13174 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
13175 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
13176 cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n", offset);
13178 return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + (offset&7)*8;
13181 #define CVMX_POW_NOS_CNT CVMX_POW_NOS_CNT_FUNC()
13182 static inline uint64_t CVMX_POW_NOS_CNT_FUNC(void)
13184 return CVMX_ADD_IO_SEG(0x0001670000000228ull);
13187 #define CVMX_POW_NW_TIM CVMX_POW_NW_TIM_FUNC()
13188 static inline uint64_t CVMX_POW_NW_TIM_FUNC(void)
13190 return CVMX_ADD_IO_SEG(0x0001670000000210ull);
13193 #define CVMX_POW_PF_RST_MSK CVMX_POW_PF_RST_MSK_FUNC()
13194 static inline uint64_t CVMX_POW_PF_RST_MSK_FUNC(void)
13196 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13197 if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
13198 cvmx_warn("CVMX_POW_PF_RST_MSK not supported on this chip\n");
13200 return CVMX_ADD_IO_SEG(0x0001670000000230ull);
13203 static inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset)
13205 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13207 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
13208 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
13209 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
13210 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
13211 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
13212 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
13213 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
13214 cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n", offset);
13216 return CVMX_ADD_IO_SEG(0x0001670000000000ull) + (offset&15)*8;
13219 static inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset)
13221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13223 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
13224 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
13225 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
13226 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
13227 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
13228 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
13229 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
13230 cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n", offset);
13232 return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + (offset&7)*8;
13235 static inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset)
13237 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13239 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
13240 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
13241 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
13242 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
13243 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
13244 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
13245 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
13246 cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n", offset);
13248 return CVMX_ADD_IO_SEG(0x0001670000000180ull) + (offset&7)*8;
13251 #define CVMX_POW_TS_PC CVMX_POW_TS_PC_FUNC()
13252 static inline uint64_t CVMX_POW_TS_PC_FUNC(void)
13254 return CVMX_ADD_IO_SEG(0x0001670000000390ull);
13257 #define CVMX_POW_WA_COM_PC CVMX_POW_WA_COM_PC_FUNC()
13258 static inline uint64_t CVMX_POW_WA_COM_PC_FUNC(void)
13260 return CVMX_ADD_IO_SEG(0x0001670000000380ull);
13263 static inline uint64_t CVMX_POW_WA_PCX(unsigned long offset)
13265 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13267 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
13268 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
13269 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
13270 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
13271 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
13272 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
13273 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
13274 cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n", offset);
13276 return CVMX_ADD_IO_SEG(0x0001670000000300ull) + (offset&7)*8;
13279 #define CVMX_POW_WQ_INT CVMX_POW_WQ_INT_FUNC()
13280 static inline uint64_t CVMX_POW_WQ_INT_FUNC(void)
13282 return CVMX_ADD_IO_SEG(0x0001670000000200ull);
13285 static inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset)
13287 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13289 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
13290 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
13291 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
13292 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
13293 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
13294 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
13295 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
13296 cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset);
13298 return CVMX_ADD_IO_SEG(0x0001670000000100ull) + (offset&15)*8;
13301 #define CVMX_POW_WQ_INT_PC CVMX_POW_WQ_INT_PC_FUNC()
13302 static inline uint64_t CVMX_POW_WQ_INT_PC_FUNC(void)
13304 return CVMX_ADD_IO_SEG(0x0001670000000208ull);
13307 static inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset)
13309 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13311 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
13312 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
13313 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
13314 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
13315 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
13316 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
13317 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
13318 cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n", offset);
13320 return CVMX_ADD_IO_SEG(0x0001670000000080ull) + (offset&15)*8;
13323 static inline uint64_t CVMX_POW_WS_PCX(unsigned long offset)
13325 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13327 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
13328 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
13329 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
13330 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
13331 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
13332 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
13333 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
13334 cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n", offset);
13336 return CVMX_ADD_IO_SEG(0x0001670000000280ull) + (offset&15)*8;
13339 #define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC()
13340 static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
13342 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13343 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13344 cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n");
13346 return CVMX_ADD_IO_SEG(0x0001180070001000ull);
13349 #define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC()
13350 static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
13352 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13353 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13354 cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n");
13356 return CVMX_ADD_IO_SEG(0x0001180070001008ull);
13359 #define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC()
13360 static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
13362 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13363 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13364 cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n");
13366 return CVMX_ADD_IO_SEG(0x0001180070001010ull);
13369 #define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC()
13370 static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
13372 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13373 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13374 cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n");
13376 return CVMX_ADD_IO_SEG(0x0001180070000080ull);
13379 #define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC()
13380 static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
13382 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13383 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13384 cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n");
13386 return CVMX_ADD_IO_SEG(0x0001180070000008ull);
13389 #define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC()
13390 static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
13392 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13393 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13394 cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n");
13396 return CVMX_ADD_IO_SEG(0x0001180070000000ull);
13399 #define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC()
13400 static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
13402 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13403 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13404 cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n");
13406 return CVMX_ADD_IO_SEG(0x0001180070000100ull);
13409 #define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC()
13410 static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
13412 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13413 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13414 cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n");
13416 return CVMX_ADD_IO_SEG(0x0001180070000108ull);
13419 #define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC()
13420 static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
13422 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13423 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13424 cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n");
13426 return CVMX_ADD_IO_SEG(0x0001180070000150ull);
13429 #define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC()
13430 static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
13432 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13433 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13434 cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n");
13436 return CVMX_ADD_IO_SEG(0x0001180070000158ull);
13439 #define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC()
13440 static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
13442 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13443 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13444 cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n");
13446 return CVMX_ADD_IO_SEG(0x0001180070000160ull);
13449 #define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC()
13450 static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
13452 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13453 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13454 cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n");
13456 return CVMX_ADD_IO_SEG(0x0001180070000110ull);
13459 #define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC()
13460 static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
13462 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13463 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13464 cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n");
13466 return CVMX_ADD_IO_SEG(0x0001180070000118ull);
13469 #define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC()
13470 static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
13472 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13473 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13474 cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n");
13476 return CVMX_ADD_IO_SEG(0x0001180070000120ull);
13479 #define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC()
13480 static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
13482 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13483 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13484 cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n");
13486 return CVMX_ADD_IO_SEG(0x0001180070000128ull);
13489 #define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC()
13490 static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
13492 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13493 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13494 cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n");
13496 return CVMX_ADD_IO_SEG(0x0001180070000130ull);
13499 #define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC()
13500 static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
13502 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13503 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13504 cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n");
13506 return CVMX_ADD_IO_SEG(0x0001180070000138ull);
13509 #define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC()
13510 static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
13512 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13513 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13514 cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n");
13516 return CVMX_ADD_IO_SEG(0x0001180070000140ull);
13519 #define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC()
13520 static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
13522 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13523 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13524 cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n");
13526 return CVMX_ADD_IO_SEG(0x0001180070000148ull);
13529 #define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC()
13530 static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
13532 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13533 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13534 cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n");
13536 return CVMX_ADD_IO_SEG(0x0001180070000088ull);
13539 #define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC()
13540 static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
13542 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13543 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13544 cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n");
13546 return CVMX_ADD_IO_SEG(0x0001180070000090ull);
13549 #define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC()
13550 static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
13552 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13553 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13554 cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n");
13556 return CVMX_ADD_IO_SEG(0x0001180070000010ull);
13559 #define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC()
13560 static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
13562 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13563 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
13564 cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n");
13566 return CVMX_ADD_IO_SEG(0x0001180070000018ull);
13569 #define CVMX_RNM_BIST_STATUS CVMX_RNM_BIST_STATUS_FUNC()
13570 static inline uint64_t CVMX_RNM_BIST_STATUS_FUNC(void)
13572 return CVMX_ADD_IO_SEG(0x0001180040000008ull);
13575 #define CVMX_RNM_CTL_STATUS CVMX_RNM_CTL_STATUS_FUNC()
13576 static inline uint64_t CVMX_RNM_CTL_STATUS_FUNC(void)
13578 return CVMX_ADD_IO_SEG(0x0001180040000000ull);
13581 static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
13583 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13585 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
13586 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
13587 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
13588 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
13589 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
13590 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
13591 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
13592 cvmx_warn("CVMX_SMIX_CLK(%lu) is invalid on this chip\n", offset);
13594 return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset&1)*256;
13597 static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
13599 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13601 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
13602 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
13603 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
13604 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
13605 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
13606 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
13607 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
13608 cvmx_warn("CVMX_SMIX_CMD(%lu) is invalid on this chip\n", offset);
13610 return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset&1)*256;
13613 static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
13615 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13617 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
13618 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
13619 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
13620 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
13621 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
13622 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
13623 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
13624 cvmx_warn("CVMX_SMIX_EN(%lu) is invalid on this chip\n", offset);
13626 return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset&1)*256;
13629 static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
13631 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13633 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
13634 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
13635 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
13636 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
13637 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
13638 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
13639 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
13640 cvmx_warn("CVMX_SMIX_RD_DAT(%lu) is invalid on this chip\n", offset);
13642 return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset&1)*256;
13645 static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
13647 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13649 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
13650 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
13651 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
13652 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
13653 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
13654 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
13655 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
13656 cvmx_warn("CVMX_SMIX_WR_DAT(%lu) is invalid on this chip\n", offset);
13658 return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset&1)*256;
13661 #define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
13662 static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
13664 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13665 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
13666 cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
13668 return CVMX_ADD_IO_SEG(0x0001180090000388ull);
13671 #define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
13672 static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
13674 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13675 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
13676 cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
13678 return CVMX_ADD_IO_SEG(0x0001180090000380ull);
13681 static inline uint64_t CVMX_SPXX_BCKPRS_CNT(unsigned long block_id)
13683 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13685 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13686 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13687 cvmx_warn("CVMX_SPXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
13689 return CVMX_ADD_IO_SEG(0x0001180090000340ull) + (block_id&1)*0x8000000ull;
13692 static inline uint64_t CVMX_SPXX_BIST_STAT(unsigned long block_id)
13694 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13696 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13697 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13698 cvmx_warn("CVMX_SPXX_BIST_STAT(%lu) is invalid on this chip\n", block_id);
13700 return CVMX_ADD_IO_SEG(0x00011800900007F8ull) + (block_id&1)*0x8000000ull;
13703 static inline uint64_t CVMX_SPXX_CLK_CTL(unsigned long block_id)
13705 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13707 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13708 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13709 cvmx_warn("CVMX_SPXX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
13711 return CVMX_ADD_IO_SEG(0x0001180090000348ull) + (block_id&1)*0x8000000ull;
13714 static inline uint64_t CVMX_SPXX_CLK_STAT(unsigned long block_id)
13716 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13718 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13719 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13720 cvmx_warn("CVMX_SPXX_CLK_STAT(%lu) is invalid on this chip\n", block_id);
13722 return CVMX_ADD_IO_SEG(0x0001180090000350ull) + (block_id&1)*0x8000000ull;
13725 static inline uint64_t CVMX_SPXX_DBG_DESKEW_CTL(unsigned long block_id)
13727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13729 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13730 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13731 cvmx_warn("CVMX_SPXX_DBG_DESKEW_CTL(%lu) is invalid on this chip\n", block_id);
13733 return CVMX_ADD_IO_SEG(0x0001180090000368ull) + (block_id&1)*0x8000000ull;
13736 static inline uint64_t CVMX_SPXX_DBG_DESKEW_STATE(unsigned long block_id)
13738 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13740 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13741 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13742 cvmx_warn("CVMX_SPXX_DBG_DESKEW_STATE(%lu) is invalid on this chip\n", block_id);
13744 return CVMX_ADD_IO_SEG(0x0001180090000370ull) + (block_id&1)*0x8000000ull;
13747 static inline uint64_t CVMX_SPXX_DRV_CTL(unsigned long block_id)
13749 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13751 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13752 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13753 cvmx_warn("CVMX_SPXX_DRV_CTL(%lu) is invalid on this chip\n", block_id);
13755 return CVMX_ADD_IO_SEG(0x0001180090000358ull) + (block_id&1)*0x8000000ull;
13758 static inline uint64_t CVMX_SPXX_ERR_CTL(unsigned long block_id)
13760 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13762 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13763 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13764 cvmx_warn("CVMX_SPXX_ERR_CTL(%lu) is invalid on this chip\n", block_id);
13766 return CVMX_ADD_IO_SEG(0x0001180090000320ull) + (block_id&1)*0x8000000ull;
13769 static inline uint64_t CVMX_SPXX_INT_DAT(unsigned long block_id)
13771 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13773 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13774 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13775 cvmx_warn("CVMX_SPXX_INT_DAT(%lu) is invalid on this chip\n", block_id);
13777 return CVMX_ADD_IO_SEG(0x0001180090000318ull) + (block_id&1)*0x8000000ull;
13780 static inline uint64_t CVMX_SPXX_INT_MSK(unsigned long block_id)
13782 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13784 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13785 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13786 cvmx_warn("CVMX_SPXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
13788 return CVMX_ADD_IO_SEG(0x0001180090000308ull) + (block_id&1)*0x8000000ull;
13791 static inline uint64_t CVMX_SPXX_INT_REG(unsigned long block_id)
13793 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13795 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13796 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13797 cvmx_warn("CVMX_SPXX_INT_REG(%lu) is invalid on this chip\n", block_id);
13799 return CVMX_ADD_IO_SEG(0x0001180090000300ull) + (block_id&1)*0x8000000ull;
13802 static inline uint64_t CVMX_SPXX_INT_SYNC(unsigned long block_id)
13804 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13806 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13807 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13808 cvmx_warn("CVMX_SPXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
13810 return CVMX_ADD_IO_SEG(0x0001180090000310ull) + (block_id&1)*0x8000000ull;
13813 static inline uint64_t CVMX_SPXX_TPA_ACC(unsigned long block_id)
13815 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13817 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13818 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13819 cvmx_warn("CVMX_SPXX_TPA_ACC(%lu) is invalid on this chip\n", block_id);
13821 return CVMX_ADD_IO_SEG(0x0001180090000338ull) + (block_id&1)*0x8000000ull;
13824 static inline uint64_t CVMX_SPXX_TPA_MAX(unsigned long block_id)
13826 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13828 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13829 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13830 cvmx_warn("CVMX_SPXX_TPA_MAX(%lu) is invalid on this chip\n", block_id);
13832 return CVMX_ADD_IO_SEG(0x0001180090000330ull) + (block_id&1)*0x8000000ull;
13835 static inline uint64_t CVMX_SPXX_TPA_SEL(unsigned long block_id)
13837 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13839 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13840 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13841 cvmx_warn("CVMX_SPXX_TPA_SEL(%lu) is invalid on this chip\n", block_id);
13843 return CVMX_ADD_IO_SEG(0x0001180090000328ull) + (block_id&1)*0x8000000ull;
13846 static inline uint64_t CVMX_SPXX_TRN4_CTL(unsigned long block_id)
13848 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13850 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13851 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13852 cvmx_warn("CVMX_SPXX_TRN4_CTL(%lu) is invalid on this chip\n", block_id);
13854 return CVMX_ADD_IO_SEG(0x0001180090000360ull) + (block_id&1)*0x8000000ull;
13857 static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id)
13859 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13861 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13862 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13863 cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
13865 return CVMX_ADD_IO_SEG(0x0001180090000200ull) + (block_id&1)*0x8000000ull;
13868 static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id)
13870 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13872 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13873 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13874 cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id);
13876 return CVMX_ADD_IO_SEG(0x0001180090000218ull) + (block_id&1)*0x8000000ull;
13879 static inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
13881 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13883 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
13884 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
13885 cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
13887 return CVMX_ADD_IO_SEG(0x0001180090000000ull) + ((offset&31) + (block_id&1)*0x1000000ull)*8;
13890 static inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id)
13892 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13894 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13895 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13896 cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
13898 return CVMX_ADD_IO_SEG(0x0001180090000208ull) + (block_id&1)*0x8000000ull;
13901 static inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id)
13903 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13905 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13906 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13907 cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id);
13909 return CVMX_ADD_IO_SEG(0x0001180090000220ull) + (block_id&1)*0x8000000ull;
13912 static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id)
13914 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13916 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13917 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13918 cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id);
13920 return CVMX_ADD_IO_SEG(0x0001180090000228ull) + (block_id&1)*0x8000000ull;
13923 static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id)
13925 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13927 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13928 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13929 cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id);
13931 return CVMX_ADD_IO_SEG(0x0001180090000608ull) + (block_id&1)*0x8000000ull;
13934 static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id)
13936 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13938 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13939 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13940 cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
13942 return CVMX_ADD_IO_SEG(0x0001180090000688ull) + (block_id&1)*0x8000000ull;
13945 static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id)
13947 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13949 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13950 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13951 cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
13953 return CVMX_ADD_IO_SEG(0x0001180090000600ull) + (block_id&1)*0x8000000ull;
13956 static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id)
13958 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13960 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13961 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13962 cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id);
13964 return CVMX_ADD_IO_SEG(0x0001180090000690ull) + (block_id&1)*0x8000000ull;
13967 static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id)
13969 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13971 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13972 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13973 cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id);
13975 return CVMX_ADD_IO_SEG(0x0001180090000610ull) + (block_id&1)*0x8000000ull;
13978 static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id)
13980 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13982 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13983 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13984 cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
13986 return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + (block_id&1)*0x8000000ull;
13989 static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id)
13991 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
13993 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
13994 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
13995 cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id);
13997 return CVMX_ADD_IO_SEG(0x0001180090000698ull) + (block_id&1)*0x8000000ull;
14000 static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id)
14002 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14004 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
14005 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
14006 cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
14008 return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + (block_id&1)*0x8000000ull;
14011 static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id)
14013 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14015 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
14016 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
14017 cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id);
14019 return CVMX_ADD_IO_SEG(0x0001180090000618ull) + (block_id&1)*0x8000000ull;
14022 static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
14024 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14026 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
14027 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
14028 cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14030 return CVMX_ADD_IO_SEG(0x0001180090000400ull) + ((offset&31) + (block_id&1)*0x1000000ull)*8;
14033 static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id)
14035 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14037 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
14038 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
14039 cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id);
14041 return CVMX_ADD_IO_SEG(0x0001180090000628ull) + (block_id&1)*0x8000000ull;
14044 static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id)
14046 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14048 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
14049 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
14050 cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
14052 return CVMX_ADD_IO_SEG(0x0001180090000630ull) + (block_id&1)*0x8000000ull;
14055 static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id)
14057 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14059 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
14060 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
14061 cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id);
14063 return CVMX_ADD_IO_SEG(0x0001180090000648ull) + (block_id&1)*0x8000000ull;
14066 static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id)
14068 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14070 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
14071 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
14072 cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id);
14074 return CVMX_ADD_IO_SEG(0x0001180090000680ull) + (block_id&1)*0x8000000ull;
14077 static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id)
14079 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14081 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
14082 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
14083 cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id);
14085 return CVMX_ADD_IO_SEG(0x0001180090000638ull) + (block_id&1)*0x8000000ull;
14088 static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id)
14090 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14092 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
14093 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
14094 cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id);
14096 return CVMX_ADD_IO_SEG(0x0001180090000640ull) + (block_id&1)*0x8000000ull;
14099 #define CVMX_TIM_MEM_DEBUG0 CVMX_TIM_MEM_DEBUG0_FUNC()
14100 static inline uint64_t CVMX_TIM_MEM_DEBUG0_FUNC(void)
14102 return CVMX_ADD_IO_SEG(0x0001180058001100ull);
14105 #define CVMX_TIM_MEM_DEBUG1 CVMX_TIM_MEM_DEBUG1_FUNC()
14106 static inline uint64_t CVMX_TIM_MEM_DEBUG1_FUNC(void)
14108 return CVMX_ADD_IO_SEG(0x0001180058001108ull);
14111 #define CVMX_TIM_MEM_DEBUG2 CVMX_TIM_MEM_DEBUG2_FUNC()
14112 static inline uint64_t CVMX_TIM_MEM_DEBUG2_FUNC(void)
14114 return CVMX_ADD_IO_SEG(0x0001180058001110ull);
14117 #define CVMX_TIM_MEM_RING0 CVMX_TIM_MEM_RING0_FUNC()
14118 static inline uint64_t CVMX_TIM_MEM_RING0_FUNC(void)
14120 return CVMX_ADD_IO_SEG(0x0001180058001000ull);
14123 #define CVMX_TIM_MEM_RING1 CVMX_TIM_MEM_RING1_FUNC()
14124 static inline uint64_t CVMX_TIM_MEM_RING1_FUNC(void)
14126 return CVMX_ADD_IO_SEG(0x0001180058001008ull);
14129 #define CVMX_TIM_REG_BIST_RESULT CVMX_TIM_REG_BIST_RESULT_FUNC()
14130 static inline uint64_t CVMX_TIM_REG_BIST_RESULT_FUNC(void)
14132 return CVMX_ADD_IO_SEG(0x0001180058000080ull);
14135 #define CVMX_TIM_REG_ERROR CVMX_TIM_REG_ERROR_FUNC()
14136 static inline uint64_t CVMX_TIM_REG_ERROR_FUNC(void)
14138 return CVMX_ADD_IO_SEG(0x0001180058000088ull);
14141 #define CVMX_TIM_REG_FLAGS CVMX_TIM_REG_FLAGS_FUNC()
14142 static inline uint64_t CVMX_TIM_REG_FLAGS_FUNC(void)
14144 return CVMX_ADD_IO_SEG(0x0001180058000000ull);
14147 #define CVMX_TIM_REG_INT_MASK CVMX_TIM_REG_INT_MASK_FUNC()
14148 static inline uint64_t CVMX_TIM_REG_INT_MASK_FUNC(void)
14150 return CVMX_ADD_IO_SEG(0x0001180058000090ull);
14153 #define CVMX_TIM_REG_READ_IDX CVMX_TIM_REG_READ_IDX_FUNC()
14154 static inline uint64_t CVMX_TIM_REG_READ_IDX_FUNC(void)
14156 return CVMX_ADD_IO_SEG(0x0001180058000008ull);
14159 #define CVMX_TRA_BIST_STATUS CVMX_TRA_BIST_STATUS_FUNC()
14160 static inline uint64_t CVMX_TRA_BIST_STATUS_FUNC(void)
14162 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14163 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14164 cvmx_warn("CVMX_TRA_BIST_STATUS not supported on this chip\n");
14166 return CVMX_ADD_IO_SEG(0x00011800A8000010ull);
14169 #define CVMX_TRA_CTL CVMX_TRA_CTL_FUNC()
14170 static inline uint64_t CVMX_TRA_CTL_FUNC(void)
14172 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14173 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14174 cvmx_warn("CVMX_TRA_CTL not supported on this chip\n");
14176 return CVMX_ADD_IO_SEG(0x00011800A8000000ull);
14179 #define CVMX_TRA_CYCLES_SINCE CVMX_TRA_CYCLES_SINCE_FUNC()
14180 static inline uint64_t CVMX_TRA_CYCLES_SINCE_FUNC(void)
14182 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14183 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14184 cvmx_warn("CVMX_TRA_CYCLES_SINCE not supported on this chip\n");
14186 return CVMX_ADD_IO_SEG(0x00011800A8000018ull);
14189 #define CVMX_TRA_CYCLES_SINCE1 CVMX_TRA_CYCLES_SINCE1_FUNC()
14190 static inline uint64_t CVMX_TRA_CYCLES_SINCE1_FUNC(void)
14192 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14193 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14194 cvmx_warn("CVMX_TRA_CYCLES_SINCE1 not supported on this chip\n");
14196 return CVMX_ADD_IO_SEG(0x00011800A8000028ull);
14199 #define CVMX_TRA_FILT_ADR_ADR CVMX_TRA_FILT_ADR_ADR_FUNC()
14200 static inline uint64_t CVMX_TRA_FILT_ADR_ADR_FUNC(void)
14202 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14203 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14204 cvmx_warn("CVMX_TRA_FILT_ADR_ADR not supported on this chip\n");
14206 return CVMX_ADD_IO_SEG(0x00011800A8000058ull);
14209 #define CVMX_TRA_FILT_ADR_MSK CVMX_TRA_FILT_ADR_MSK_FUNC()
14210 static inline uint64_t CVMX_TRA_FILT_ADR_MSK_FUNC(void)
14212 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14213 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14214 cvmx_warn("CVMX_TRA_FILT_ADR_MSK not supported on this chip\n");
14216 return CVMX_ADD_IO_SEG(0x00011800A8000060ull);
14219 #define CVMX_TRA_FILT_CMD CVMX_TRA_FILT_CMD_FUNC()
14220 static inline uint64_t CVMX_TRA_FILT_CMD_FUNC(void)
14222 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14223 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14224 cvmx_warn("CVMX_TRA_FILT_CMD not supported on this chip\n");
14226 return CVMX_ADD_IO_SEG(0x00011800A8000040ull);
14229 #define CVMX_TRA_FILT_DID CVMX_TRA_FILT_DID_FUNC()
14230 static inline uint64_t CVMX_TRA_FILT_DID_FUNC(void)
14232 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14233 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14234 cvmx_warn("CVMX_TRA_FILT_DID not supported on this chip\n");
14236 return CVMX_ADD_IO_SEG(0x00011800A8000050ull);
14239 #define CVMX_TRA_FILT_SID CVMX_TRA_FILT_SID_FUNC()
14240 static inline uint64_t CVMX_TRA_FILT_SID_FUNC(void)
14242 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14243 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14244 cvmx_warn("CVMX_TRA_FILT_SID not supported on this chip\n");
14246 return CVMX_ADD_IO_SEG(0x00011800A8000048ull);
14249 #define CVMX_TRA_INT_STATUS CVMX_TRA_INT_STATUS_FUNC()
14250 static inline uint64_t CVMX_TRA_INT_STATUS_FUNC(void)
14252 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14253 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14254 cvmx_warn("CVMX_TRA_INT_STATUS not supported on this chip\n");
14256 return CVMX_ADD_IO_SEG(0x00011800A8000008ull);
14259 #define CVMX_TRA_READ_DAT CVMX_TRA_READ_DAT_FUNC()
14260 static inline uint64_t CVMX_TRA_READ_DAT_FUNC(void)
14262 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14263 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14264 cvmx_warn("CVMX_TRA_READ_DAT not supported on this chip\n");
14266 return CVMX_ADD_IO_SEG(0x00011800A8000020ull);
14269 #define CVMX_TRA_TRIG0_ADR_ADR CVMX_TRA_TRIG0_ADR_ADR_FUNC()
14270 static inline uint64_t CVMX_TRA_TRIG0_ADR_ADR_FUNC(void)
14272 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14273 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14274 cvmx_warn("CVMX_TRA_TRIG0_ADR_ADR not supported on this chip\n");
14276 return CVMX_ADD_IO_SEG(0x00011800A8000098ull);
14279 #define CVMX_TRA_TRIG0_ADR_MSK CVMX_TRA_TRIG0_ADR_MSK_FUNC()
14280 static inline uint64_t CVMX_TRA_TRIG0_ADR_MSK_FUNC(void)
14282 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14283 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14284 cvmx_warn("CVMX_TRA_TRIG0_ADR_MSK not supported on this chip\n");
14286 return CVMX_ADD_IO_SEG(0x00011800A80000A0ull);
14289 #define CVMX_TRA_TRIG0_CMD CVMX_TRA_TRIG0_CMD_FUNC()
14290 static inline uint64_t CVMX_TRA_TRIG0_CMD_FUNC(void)
14292 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14293 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14294 cvmx_warn("CVMX_TRA_TRIG0_CMD not supported on this chip\n");
14296 return CVMX_ADD_IO_SEG(0x00011800A8000080ull);
14299 #define CVMX_TRA_TRIG0_DID CVMX_TRA_TRIG0_DID_FUNC()
14300 static inline uint64_t CVMX_TRA_TRIG0_DID_FUNC(void)
14302 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14303 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14304 cvmx_warn("CVMX_TRA_TRIG0_DID not supported on this chip\n");
14306 return CVMX_ADD_IO_SEG(0x00011800A8000090ull);
14309 #define CVMX_TRA_TRIG0_SID CVMX_TRA_TRIG0_SID_FUNC()
14310 static inline uint64_t CVMX_TRA_TRIG0_SID_FUNC(void)
14312 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14313 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14314 cvmx_warn("CVMX_TRA_TRIG0_SID not supported on this chip\n");
14316 return CVMX_ADD_IO_SEG(0x00011800A8000088ull);
14319 #define CVMX_TRA_TRIG1_ADR_ADR CVMX_TRA_TRIG1_ADR_ADR_FUNC()
14320 static inline uint64_t CVMX_TRA_TRIG1_ADR_ADR_FUNC(void)
14322 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14323 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14324 cvmx_warn("CVMX_TRA_TRIG1_ADR_ADR not supported on this chip\n");
14326 return CVMX_ADD_IO_SEG(0x00011800A80000D8ull);
14329 #define CVMX_TRA_TRIG1_ADR_MSK CVMX_TRA_TRIG1_ADR_MSK_FUNC()
14330 static inline uint64_t CVMX_TRA_TRIG1_ADR_MSK_FUNC(void)
14332 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14333 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14334 cvmx_warn("CVMX_TRA_TRIG1_ADR_MSK not supported on this chip\n");
14336 return CVMX_ADD_IO_SEG(0x00011800A80000E0ull);
14339 #define CVMX_TRA_TRIG1_CMD CVMX_TRA_TRIG1_CMD_FUNC()
14340 static inline uint64_t CVMX_TRA_TRIG1_CMD_FUNC(void)
14342 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14343 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14344 cvmx_warn("CVMX_TRA_TRIG1_CMD not supported on this chip\n");
14346 return CVMX_ADD_IO_SEG(0x00011800A80000C0ull);
14349 #define CVMX_TRA_TRIG1_DID CVMX_TRA_TRIG1_DID_FUNC()
14350 static inline uint64_t CVMX_TRA_TRIG1_DID_FUNC(void)
14352 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14353 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14354 cvmx_warn("CVMX_TRA_TRIG1_DID not supported on this chip\n");
14356 return CVMX_ADD_IO_SEG(0x00011800A80000D0ull);
14359 #define CVMX_TRA_TRIG1_SID CVMX_TRA_TRIG1_SID_FUNC()
14360 static inline uint64_t CVMX_TRA_TRIG1_SID_FUNC(void)
14362 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14363 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
14364 cvmx_warn("CVMX_TRA_TRIG1_SID not supported on this chip\n");
14366 return CVMX_ADD_IO_SEG(0x00011800A80000C8ull);
14369 static inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id)
14371 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14373 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14374 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14375 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14376 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14377 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14378 cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n", block_id);
14380 return CVMX_ADD_IO_SEG(0x00016F0010000818ull) + (block_id&1)*0x100000000000ull;
14383 static inline uint64_t CVMX_USBCX_DAINTMSK(unsigned long block_id)
14385 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14387 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14388 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14389 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14390 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14391 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14392 cvmx_warn("CVMX_USBCX_DAINTMSK(%lu) is invalid on this chip\n", block_id);
14394 return CVMX_ADD_IO_SEG(0x00016F001000081Cull) + (block_id&1)*0x100000000000ull;
14397 static inline uint64_t CVMX_USBCX_DCFG(unsigned long block_id)
14399 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14401 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14402 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14403 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14404 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14405 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14406 cvmx_warn("CVMX_USBCX_DCFG(%lu) is invalid on this chip\n", block_id);
14408 return CVMX_ADD_IO_SEG(0x00016F0010000800ull) + (block_id&1)*0x100000000000ull;
14411 static inline uint64_t CVMX_USBCX_DCTL(unsigned long block_id)
14413 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14415 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14416 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14417 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14418 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14419 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14420 cvmx_warn("CVMX_USBCX_DCTL(%lu) is invalid on this chip\n", block_id);
14422 return CVMX_ADD_IO_SEG(0x00016F0010000804ull) + (block_id&1)*0x100000000000ull;
14425 static inline uint64_t CVMX_USBCX_DIEPCTLX(unsigned long offset, unsigned long block_id)
14427 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14429 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14430 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14431 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14432 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14433 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
14434 cvmx_warn("CVMX_USBCX_DIEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14436 return CVMX_ADD_IO_SEG(0x00016F0010000900ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14439 static inline uint64_t CVMX_USBCX_DIEPINTX(unsigned long offset, unsigned long block_id)
14441 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14443 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14444 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14445 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14446 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14447 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
14448 cvmx_warn("CVMX_USBCX_DIEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14450 return CVMX_ADD_IO_SEG(0x00016F0010000908ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14453 static inline uint64_t CVMX_USBCX_DIEPMSK(unsigned long block_id)
14455 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14457 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14458 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14459 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14460 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14461 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14462 cvmx_warn("CVMX_USBCX_DIEPMSK(%lu) is invalid on this chip\n", block_id);
14464 return CVMX_ADD_IO_SEG(0x00016F0010000810ull) + (block_id&1)*0x100000000000ull;
14467 static inline uint64_t CVMX_USBCX_DIEPTSIZX(unsigned long offset, unsigned long block_id)
14469 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14471 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14472 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14473 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14474 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14475 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
14476 cvmx_warn("CVMX_USBCX_DIEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14478 return CVMX_ADD_IO_SEG(0x00016F0010000910ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14481 static inline uint64_t CVMX_USBCX_DOEPCTLX(unsigned long offset, unsigned long block_id)
14483 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14485 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14486 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14487 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14488 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14489 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
14490 cvmx_warn("CVMX_USBCX_DOEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14492 return CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14495 static inline uint64_t CVMX_USBCX_DOEPINTX(unsigned long offset, unsigned long block_id)
14497 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14499 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14500 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14501 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14502 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14503 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
14504 cvmx_warn("CVMX_USBCX_DOEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14506 return CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14509 static inline uint64_t CVMX_USBCX_DOEPMSK(unsigned long block_id)
14511 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14513 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14514 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14515 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14516 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14517 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14518 cvmx_warn("CVMX_USBCX_DOEPMSK(%lu) is invalid on this chip\n", block_id);
14520 return CVMX_ADD_IO_SEG(0x00016F0010000814ull) + (block_id&1)*0x100000000000ull;
14523 static inline uint64_t CVMX_USBCX_DOEPTSIZX(unsigned long offset, unsigned long block_id)
14525 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14527 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14528 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14529 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14530 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
14531 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
14532 cvmx_warn("CVMX_USBCX_DOEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14534 return CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14537 static inline uint64_t CVMX_USBCX_DPTXFSIZX(unsigned long offset, unsigned long block_id)
14539 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14541 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
14542 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
14543 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
14544 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
14545 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id <= 1))))))
14546 cvmx_warn("CVMX_USBCX_DPTXFSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14548 return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((offset&7) + (block_id&1)*0x40000000000ull)*4;
14551 static inline uint64_t CVMX_USBCX_DSTS(unsigned long block_id)
14553 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14555 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14556 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14557 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14558 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14559 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14560 cvmx_warn("CVMX_USBCX_DSTS(%lu) is invalid on this chip\n", block_id);
14562 return CVMX_ADD_IO_SEG(0x00016F0010000808ull) + (block_id&1)*0x100000000000ull;
14565 static inline uint64_t CVMX_USBCX_DTKNQR1(unsigned long block_id)
14567 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14569 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14570 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14571 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14572 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14573 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14574 cvmx_warn("CVMX_USBCX_DTKNQR1(%lu) is invalid on this chip\n", block_id);
14576 return CVMX_ADD_IO_SEG(0x00016F0010000820ull) + (block_id&1)*0x100000000000ull;
14579 static inline uint64_t CVMX_USBCX_DTKNQR2(unsigned long block_id)
14581 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14583 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14584 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14585 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14586 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14587 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14588 cvmx_warn("CVMX_USBCX_DTKNQR2(%lu) is invalid on this chip\n", block_id);
14590 return CVMX_ADD_IO_SEG(0x00016F0010000824ull) + (block_id&1)*0x100000000000ull;
14593 static inline uint64_t CVMX_USBCX_DTKNQR3(unsigned long block_id)
14595 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14597 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14598 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14599 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14600 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14601 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14602 cvmx_warn("CVMX_USBCX_DTKNQR3(%lu) is invalid on this chip\n", block_id);
14604 return CVMX_ADD_IO_SEG(0x00016F0010000830ull) + (block_id&1)*0x100000000000ull;
14607 static inline uint64_t CVMX_USBCX_DTKNQR4(unsigned long block_id)
14609 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14611 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14612 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14613 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14614 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14615 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14616 cvmx_warn("CVMX_USBCX_DTKNQR4(%lu) is invalid on this chip\n", block_id);
14618 return CVMX_ADD_IO_SEG(0x00016F0010000834ull) + (block_id&1)*0x100000000000ull;
14621 static inline uint64_t CVMX_USBCX_GAHBCFG(unsigned long block_id)
14623 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14625 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14626 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14627 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14628 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14629 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14630 cvmx_warn("CVMX_USBCX_GAHBCFG(%lu) is invalid on this chip\n", block_id);
14632 return CVMX_ADD_IO_SEG(0x00016F0010000008ull) + (block_id&1)*0x100000000000ull;
14635 static inline uint64_t CVMX_USBCX_GHWCFG1(unsigned long block_id)
14637 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14639 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14640 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14641 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14642 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14643 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14644 cvmx_warn("CVMX_USBCX_GHWCFG1(%lu) is invalid on this chip\n", block_id);
14646 return CVMX_ADD_IO_SEG(0x00016F0010000044ull) + (block_id&1)*0x100000000000ull;
14649 static inline uint64_t CVMX_USBCX_GHWCFG2(unsigned long block_id)
14651 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14653 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14654 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14655 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14656 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14657 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14658 cvmx_warn("CVMX_USBCX_GHWCFG2(%lu) is invalid on this chip\n", block_id);
14660 return CVMX_ADD_IO_SEG(0x00016F0010000048ull) + (block_id&1)*0x100000000000ull;
14663 static inline uint64_t CVMX_USBCX_GHWCFG3(unsigned long block_id)
14665 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14667 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14668 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14669 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14670 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14671 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14672 cvmx_warn("CVMX_USBCX_GHWCFG3(%lu) is invalid on this chip\n", block_id);
14674 return CVMX_ADD_IO_SEG(0x00016F001000004Cull) + (block_id&1)*0x100000000000ull;
14677 static inline uint64_t CVMX_USBCX_GHWCFG4(unsigned long block_id)
14679 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14681 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14682 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14683 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14685 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14686 cvmx_warn("CVMX_USBCX_GHWCFG4(%lu) is invalid on this chip\n", block_id);
14688 return CVMX_ADD_IO_SEG(0x00016F0010000050ull) + (block_id&1)*0x100000000000ull;
14691 static inline uint64_t CVMX_USBCX_GINTMSK(unsigned long block_id)
14693 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14695 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14696 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14697 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14698 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14699 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14700 cvmx_warn("CVMX_USBCX_GINTMSK(%lu) is invalid on this chip\n", block_id);
14702 return CVMX_ADD_IO_SEG(0x00016F0010000018ull) + (block_id&1)*0x100000000000ull;
14705 static inline uint64_t CVMX_USBCX_GINTSTS(unsigned long block_id)
14707 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14709 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14710 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14711 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14712 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14713 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14714 cvmx_warn("CVMX_USBCX_GINTSTS(%lu) is invalid on this chip\n", block_id);
14716 return CVMX_ADD_IO_SEG(0x00016F0010000014ull) + (block_id&1)*0x100000000000ull;
14719 static inline uint64_t CVMX_USBCX_GNPTXFSIZ(unsigned long block_id)
14721 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14723 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14724 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14725 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14726 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14727 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14728 cvmx_warn("CVMX_USBCX_GNPTXFSIZ(%lu) is invalid on this chip\n", block_id);
14730 return CVMX_ADD_IO_SEG(0x00016F0010000028ull) + (block_id&1)*0x100000000000ull;
14733 static inline uint64_t CVMX_USBCX_GNPTXSTS(unsigned long block_id)
14735 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14737 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14738 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14739 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14740 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14741 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14742 cvmx_warn("CVMX_USBCX_GNPTXSTS(%lu) is invalid on this chip\n", block_id);
14744 return CVMX_ADD_IO_SEG(0x00016F001000002Cull) + (block_id&1)*0x100000000000ull;
14747 static inline uint64_t CVMX_USBCX_GOTGCTL(unsigned long block_id)
14749 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14751 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14752 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14753 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14754 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14755 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14756 cvmx_warn("CVMX_USBCX_GOTGCTL(%lu) is invalid on this chip\n", block_id);
14758 return CVMX_ADD_IO_SEG(0x00016F0010000000ull) + (block_id&1)*0x100000000000ull;
14761 static inline uint64_t CVMX_USBCX_GOTGINT(unsigned long block_id)
14763 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14765 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14766 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14767 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14768 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14769 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14770 cvmx_warn("CVMX_USBCX_GOTGINT(%lu) is invalid on this chip\n", block_id);
14772 return CVMX_ADD_IO_SEG(0x00016F0010000004ull) + (block_id&1)*0x100000000000ull;
14775 static inline uint64_t CVMX_USBCX_GRSTCTL(unsigned long block_id)
14777 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14779 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14780 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14781 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14782 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14783 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14784 cvmx_warn("CVMX_USBCX_GRSTCTL(%lu) is invalid on this chip\n", block_id);
14786 return CVMX_ADD_IO_SEG(0x00016F0010000010ull) + (block_id&1)*0x100000000000ull;
14789 static inline uint64_t CVMX_USBCX_GRXFSIZ(unsigned long block_id)
14791 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14793 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14794 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14795 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14796 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14797 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14798 cvmx_warn("CVMX_USBCX_GRXFSIZ(%lu) is invalid on this chip\n", block_id);
14800 return CVMX_ADD_IO_SEG(0x00016F0010000024ull) + (block_id&1)*0x100000000000ull;
14803 static inline uint64_t CVMX_USBCX_GRXSTSPD(unsigned long block_id)
14805 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14807 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14808 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14809 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14810 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14811 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14812 cvmx_warn("CVMX_USBCX_GRXSTSPD(%lu) is invalid on this chip\n", block_id);
14814 return CVMX_ADD_IO_SEG(0x00016F0010040020ull) + (block_id&1)*0x100000000000ull;
14817 static inline uint64_t CVMX_USBCX_GRXSTSPH(unsigned long block_id)
14819 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14821 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14822 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14823 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14824 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14825 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14826 cvmx_warn("CVMX_USBCX_GRXSTSPH(%lu) is invalid on this chip\n", block_id);
14828 return CVMX_ADD_IO_SEG(0x00016F0010000020ull) + (block_id&1)*0x100000000000ull;
14831 static inline uint64_t CVMX_USBCX_GRXSTSRD(unsigned long block_id)
14833 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14835 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14836 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14837 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14838 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14839 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14840 cvmx_warn("CVMX_USBCX_GRXSTSRD(%lu) is invalid on this chip\n", block_id);
14842 return CVMX_ADD_IO_SEG(0x00016F001004001Cull) + (block_id&1)*0x100000000000ull;
14845 static inline uint64_t CVMX_USBCX_GRXSTSRH(unsigned long block_id)
14847 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14849 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14850 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14851 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14852 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14853 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14854 cvmx_warn("CVMX_USBCX_GRXSTSRH(%lu) is invalid on this chip\n", block_id);
14856 return CVMX_ADD_IO_SEG(0x00016F001000001Cull) + (block_id&1)*0x100000000000ull;
14859 static inline uint64_t CVMX_USBCX_GSNPSID(unsigned long block_id)
14861 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14863 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14864 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14865 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14866 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14867 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14868 cvmx_warn("CVMX_USBCX_GSNPSID(%lu) is invalid on this chip\n", block_id);
14870 return CVMX_ADD_IO_SEG(0x00016F0010000040ull) + (block_id&1)*0x100000000000ull;
14873 static inline uint64_t CVMX_USBCX_GUSBCFG(unsigned long block_id)
14875 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14877 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14878 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14879 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14880 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14881 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14882 cvmx_warn("CVMX_USBCX_GUSBCFG(%lu) is invalid on this chip\n", block_id);
14884 return CVMX_ADD_IO_SEG(0x00016F001000000Cull) + (block_id&1)*0x100000000000ull;
14887 static inline uint64_t CVMX_USBCX_HAINT(unsigned long block_id)
14889 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14891 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14892 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14893 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14894 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14895 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14896 cvmx_warn("CVMX_USBCX_HAINT(%lu) is invalid on this chip\n", block_id);
14898 return CVMX_ADD_IO_SEG(0x00016F0010000414ull) + (block_id&1)*0x100000000000ull;
14901 static inline uint64_t CVMX_USBCX_HAINTMSK(unsigned long block_id)
14903 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14905 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14906 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14907 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14908 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14909 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14910 cvmx_warn("CVMX_USBCX_HAINTMSK(%lu) is invalid on this chip\n", block_id);
14912 return CVMX_ADD_IO_SEG(0x00016F0010000418ull) + (block_id&1)*0x100000000000ull;
14915 static inline uint64_t CVMX_USBCX_HCCHARX(unsigned long offset, unsigned long block_id)
14917 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14919 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14920 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14921 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14922 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14923 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
14924 cvmx_warn("CVMX_USBCX_HCCHARX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14926 return CVMX_ADD_IO_SEG(0x00016F0010000500ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14929 static inline uint64_t CVMX_USBCX_HCFG(unsigned long block_id)
14931 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14933 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
14934 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
14935 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
14936 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
14937 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
14938 cvmx_warn("CVMX_USBCX_HCFG(%lu) is invalid on this chip\n", block_id);
14940 return CVMX_ADD_IO_SEG(0x00016F0010000400ull) + (block_id&1)*0x100000000000ull;
14943 static inline uint64_t CVMX_USBCX_HCINTMSKX(unsigned long offset, unsigned long block_id)
14945 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14947 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14948 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14949 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14950 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14951 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
14952 cvmx_warn("CVMX_USBCX_HCINTMSKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14954 return CVMX_ADD_IO_SEG(0x00016F001000050Cull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14957 static inline uint64_t CVMX_USBCX_HCINTX(unsigned long offset, unsigned long block_id)
14959 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14961 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14962 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14963 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14964 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14965 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
14966 cvmx_warn("CVMX_USBCX_HCINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14968 return CVMX_ADD_IO_SEG(0x00016F0010000508ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14971 static inline uint64_t CVMX_USBCX_HCSPLTX(unsigned long offset, unsigned long block_id)
14973 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14975 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14976 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14977 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14978 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14979 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
14980 cvmx_warn("CVMX_USBCX_HCSPLTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14982 return CVMX_ADD_IO_SEG(0x00016F0010000504ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14985 static inline uint64_t CVMX_USBCX_HCTSIZX(unsigned long offset, unsigned long block_id)
14987 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14989 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14990 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14991 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14992 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
14993 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
14994 cvmx_warn("CVMX_USBCX_HCTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
14996 return CVMX_ADD_IO_SEG(0x00016F0010000510ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
14999 static inline uint64_t CVMX_USBCX_HFIR(unsigned long block_id)
15001 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15003 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15004 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15005 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15006 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15007 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15008 cvmx_warn("CVMX_USBCX_HFIR(%lu) is invalid on this chip\n", block_id);
15010 return CVMX_ADD_IO_SEG(0x00016F0010000404ull) + (block_id&1)*0x100000000000ull;
15013 static inline uint64_t CVMX_USBCX_HFNUM(unsigned long block_id)
15015 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15017 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15018 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15019 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15020 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15021 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15022 cvmx_warn("CVMX_USBCX_HFNUM(%lu) is invalid on this chip\n", block_id);
15024 return CVMX_ADD_IO_SEG(0x00016F0010000408ull) + (block_id&1)*0x100000000000ull;
15027 static inline uint64_t CVMX_USBCX_HPRT(unsigned long block_id)
15029 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15031 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15032 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15033 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15034 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15035 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15036 cvmx_warn("CVMX_USBCX_HPRT(%lu) is invalid on this chip\n", block_id);
15038 return CVMX_ADD_IO_SEG(0x00016F0010000440ull) + (block_id&1)*0x100000000000ull;
15041 static inline uint64_t CVMX_USBCX_HPTXFSIZ(unsigned long block_id)
15043 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15045 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15046 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15047 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15048 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15049 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15050 cvmx_warn("CVMX_USBCX_HPTXFSIZ(%lu) is invalid on this chip\n", block_id);
15052 return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (block_id&1)*0x100000000000ull;
15055 static inline uint64_t CVMX_USBCX_HPTXSTS(unsigned long block_id)
15057 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15059 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15060 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15061 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15062 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15063 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15064 cvmx_warn("CVMX_USBCX_HPTXSTS(%lu) is invalid on this chip\n", block_id);
15066 return CVMX_ADD_IO_SEG(0x00016F0010000410ull) + (block_id&1)*0x100000000000ull;
15069 static inline uint64_t CVMX_USBCX_NPTXDFIFOX(unsigned long offset, unsigned long block_id)
15071 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15073 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
15074 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
15075 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
15076 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
15077 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
15078 cvmx_warn("CVMX_USBCX_NPTXDFIFOX(%lu,%lu) is invalid on this chip\n", offset, block_id);
15080 return CVMX_ADD_IO_SEG(0x00016F0010001000ull) + ((offset&7) + (block_id&1)*0x100000000ull)*4096;
15083 static inline uint64_t CVMX_USBCX_PCGCCTL(unsigned long block_id)
15085 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15087 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15088 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15089 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15090 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15091 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15092 cvmx_warn("CVMX_USBCX_PCGCCTL(%lu) is invalid on this chip\n", block_id);
15094 return CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + (block_id&1)*0x100000000000ull;
15097 static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id)
15099 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15101 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15102 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15103 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15104 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15105 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15106 cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
15108 return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + (block_id&1)*0x10000000ull;
15111 static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id)
15113 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15115 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15116 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15117 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15118 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15119 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15120 cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
15122 return CVMX_ADD_IO_SEG(0x0001180068000010ull) + (block_id&1)*0x10000000ull;
15125 static inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id)
15127 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15129 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15130 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15131 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15132 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15133 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15134 cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
15136 return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + (block_id&1)*0x100000000000ull;
15139 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id)
15141 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15143 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15144 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15145 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15146 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15147 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15148 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id);
15150 return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + (block_id&1)*0x100000000000ull;
15153 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id)
15155 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15157 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15158 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15159 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15160 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15161 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15162 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id);
15164 return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + (block_id&1)*0x100000000000ull;
15167 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id)
15169 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15171 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15172 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15173 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15174 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15175 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15176 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id);
15178 return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + (block_id&1)*0x100000000000ull;
15181 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id)
15183 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15185 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15186 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15187 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15188 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15190 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id);
15192 return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + (block_id&1)*0x100000000000ull;
15195 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id)
15197 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15199 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15200 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15201 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15202 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15203 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15204 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id);
15206 return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + (block_id&1)*0x100000000000ull;
15209 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id)
15211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15213 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15214 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15215 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15216 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15217 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15218 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id);
15220 return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + (block_id&1)*0x100000000000ull;
15223 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id)
15225 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15227 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15228 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15229 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15230 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15231 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15232 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id);
15234 return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + (block_id&1)*0x100000000000ull;
15237 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id)
15239 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15241 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15242 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15243 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15244 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15245 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15246 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id);
15248 return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + (block_id&1)*0x100000000000ull;
15251 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id)
15253 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15255 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15257 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15258 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15259 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15260 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id);
15262 return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + (block_id&1)*0x100000000000ull;
15265 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id)
15267 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15269 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15270 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15271 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15272 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15273 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15274 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id);
15276 return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + (block_id&1)*0x100000000000ull;
15279 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id)
15281 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15283 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15284 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15286 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15287 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15288 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id);
15290 return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + (block_id&1)*0x100000000000ull;
15293 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id)
15295 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15297 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15298 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15299 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15300 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15301 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15302 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id);
15304 return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + (block_id&1)*0x100000000000ull;
15307 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id)
15309 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15311 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15312 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15313 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15314 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15315 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15316 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id);
15318 return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + (block_id&1)*0x100000000000ull;
15321 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id)
15323 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15325 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15326 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15327 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15328 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15329 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15330 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id);
15332 return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + (block_id&1)*0x100000000000ull;
15335 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id)
15337 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15339 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15340 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15341 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15342 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15343 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15344 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id);
15346 return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + (block_id&1)*0x100000000000ull;
15349 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id)
15351 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15353 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15354 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15355 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15356 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15357 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15358 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id);
15360 return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + (block_id&1)*0x100000000000ull;
15363 static inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id)
15365 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15367 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15368 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15369 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15370 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15371 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15372 cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id);
15374 return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + (block_id&1)*0x100000000000ull;
15377 static inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id)
15379 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15381 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15382 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15383 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15384 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15385 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15386 cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id);
15388 return CVMX_ADD_IO_SEG(0x0001180068000008ull) + (block_id&1)*0x10000000ull;
15391 static inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id)
15393 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15395 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15396 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15397 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15398 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15399 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15400 cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id);
15402 return CVMX_ADD_IO_SEG(0x0001180068000000ull) + (block_id&1)*0x10000000ull;
15405 static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id)
15407 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15409 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
15410 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
15411 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
15412 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
15413 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
15414 cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
15416 return CVMX_ADD_IO_SEG(0x0001180068000018ull) + (block_id&1)*0x10000000ull;
15419 #define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC()
15420 static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void)
15422 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15423 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
15424 cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n");
15426 return CVMX_ADD_IO_SEG(0x0001180038000080ull);
15429 #define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC()
15430 static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void)
15432 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15433 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
15434 cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n");
15436 return CVMX_ADD_IO_SEG(0x0001180038000008ull);
15439 #define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC()
15440 static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void)
15442 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15443 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
15444 cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n");
15446 return CVMX_ADD_IO_SEG(0x0001180038000000ull);
15449 #define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC()
15450 static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void)
15452 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15453 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
15454 cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n");
15456 return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
15459 #define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC()
15460 static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void)
15462 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15463 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
15464 cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n");
15466 return CVMX_ADD_IO_SEG(0x0001180038000098ull);
15469 #define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC()
15470 static inline uint64_t CVMX_ZIP_ERROR_FUNC(void)
15472 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15473 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
15474 cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n");
15476 return CVMX_ADD_IO_SEG(0x0001180038000088ull);
15479 #define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC()
15480 static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void)
15482 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15483 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
15484 cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n");
15486 return CVMX_ADD_IO_SEG(0x0001180038000090ull);
15490 #endif /* __CVMX_CSR_ADDRESSES_H__ */